1 //=- llvm/CodeGen/AntiDepBreaker.h - Anti-Dependence Breaking -*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AntiDepBreaker class, which implements
11 // anti-dependence breaking heuristics for post-register-allocation scheduling.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_CODEGEN_ANTIDEPBREAKER_H
16 #define LLVM_LIB_CODEGEN_ANTIDEPBREAKER_H
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/ScheduleDAG.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
28 /// This class works in conjunction with the post-RA scheduler to rename
29 /// registers to break register anti-dependencies (WAR hazards).
30 class LLVM_LIBRARY_VISIBILITY AntiDepBreaker {
32 typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
35 virtual ~AntiDepBreaker();
37 /// Initialize anti-dep breaking for a new basic block.
38 virtual void StartBlock(MachineBasicBlock *BB) =0;
40 /// Identifiy anti-dependencies within a basic-block region and break them by
41 /// renaming registers. Return the number of anti-dependencies broken.
42 virtual unsigned BreakAntiDependencies(const std::vector<SUnit>& SUnits,
43 MachineBasicBlock::iterator Begin,
44 MachineBasicBlock::iterator End,
45 unsigned InsertPosIndex,
46 DbgValueVector &DbgValues) = 0;
48 /// Update liveness information to account for the current
49 /// instruction, which will not be scheduled.
50 virtual void Observe(MachineInstr &MI, unsigned Count,
51 unsigned InsertPosIndex) = 0;
53 /// Finish anti-dep breaking for a basic block.
54 virtual void FinishBlock() =0;
56 /// Update DBG_VALUE if dependency breaker is updating
57 /// other machine instruction to use NewReg.
58 void UpdateDbgValue(MachineInstr &MI, unsigned OldReg, unsigned NewReg) {
59 assert(MI.isDebugValue() && "MI is not DBG_VALUE!");
60 if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == OldReg)
61 MI.getOperand(0).setReg(NewReg);
64 /// Update all DBG_VALUE instructions that may be affected by the dependency
65 /// breaker's update of ParentMI to use NewReg.
66 void UpdateDbgValues(const DbgValueVector &DbgValues, MachineInstr *ParentMI,
67 unsigned OldReg, unsigned NewReg) {
68 // The following code is dependent on the order in which the DbgValues are
69 // constructed in ScheduleDAGInstrs::buildSchedGraph.
70 MachineInstr *PrevDbgMI = nullptr;
71 for (const auto &DV : make_range(DbgValues.crbegin(), DbgValues.crend())) {
72 MachineInstr *PrevMI = DV.second;
73 if ((PrevMI == ParentMI) || (PrevMI == PrevDbgMI)) {
74 MachineInstr *DbgMI = DV.first;
75 UpdateDbgValue(*DbgMI, OldReg, NewReg);
77 } else if (PrevDbgMI) {
78 break; // If no match and already found a DBG_VALUE, we're done.