1 //===-- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains support for writing dwarf debug info into asm files.
12 //===----------------------------------------------------------------------===//
14 #include "DwarfExpression.h"
15 #include "DwarfDebug.h"
16 #include "llvm/ADT/SmallBitVector.h"
17 #include "llvm/CodeGen/AsmPrinter.h"
18 #include "llvm/Support/Dwarf.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/Target/TargetSubtargetInfo.h"
25 void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
26 assert(DwarfReg >= 0 && "invalid negative dwarf register number");
27 assert((LocationKind == Unknown || LocationKind == Register) &&
28 "location description already locked down");
29 LocationKind = Register;
31 emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
33 emitOp(dwarf::DW_OP_regx, Comment);
34 emitUnsigned(DwarfReg);
38 void DwarfExpression::addBReg(int DwarfReg, int Offset) {
39 assert(DwarfReg >= 0 && "invalid negative dwarf register number");
40 assert(LocationKind != Register && "location description already locked down");
42 emitOp(dwarf::DW_OP_breg0 + DwarfReg);
44 emitOp(dwarf::DW_OP_bregx);
45 emitUnsigned(DwarfReg);
50 void DwarfExpression::addFBReg(int Offset) {
51 emitOp(dwarf::DW_OP_fbreg);
55 void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
59 const unsigned SizeOfByte = 8;
60 if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
61 emitOp(dwarf::DW_OP_bit_piece);
62 emitUnsigned(SizeInBits);
63 emitUnsigned(OffsetInBits);
65 emitOp(dwarf::DW_OP_piece);
66 unsigned ByteSize = SizeInBits / SizeOfByte;
67 emitUnsigned(ByteSize);
69 this->OffsetInBits += SizeInBits;
72 void DwarfExpression::addShr(unsigned ShiftBy) {
73 emitOp(dwarf::DW_OP_constu);
74 emitUnsigned(ShiftBy);
75 emitOp(dwarf::DW_OP_shr);
78 void DwarfExpression::addAnd(unsigned Mask) {
79 emitOp(dwarf::DW_OP_constu);
81 emitOp(dwarf::DW_OP_and);
84 bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
85 unsigned MachineReg, unsigned MaxSize) {
86 if (!TRI.isPhysicalRegister(MachineReg)) {
87 if (isFrameRegister(TRI, MachineReg)) {
88 DwarfRegs.push_back({-1, 0, nullptr});
94 int Reg = TRI.getDwarfRegNum(MachineReg, false);
96 // If this is a valid register number, emit it.
98 DwarfRegs.push_back({Reg, 0, nullptr});
102 // Walk up the super-register chain until we find a valid number.
103 // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
104 for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
105 Reg = TRI.getDwarfRegNum(*SR, false);
107 unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
108 unsigned Size = TRI.getSubRegIdxSize(Idx);
109 unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
110 DwarfRegs.push_back({Reg, 0, "super-register"});
111 // Use a DW_OP_bit_piece to describe the sub-register.
112 setSubRegisterPiece(Size, RegOffset);
117 // Otherwise, attempt to find a covering set of sub-register numbers.
118 // For example, Q0 on ARM is a composition of D0+D1.
120 // The size of the register in bits.
121 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
122 unsigned RegSize = TRI.getRegSizeInBits(*RC);
123 // Keep track of the bits in the register we already emitted, so we
124 // can avoid emitting redundant aliasing subregs.
125 SmallBitVector Coverage(RegSize, false);
126 for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
127 unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
128 unsigned Size = TRI.getSubRegIdxSize(Idx);
129 unsigned Offset = TRI.getSubRegIdxOffset(Idx);
130 Reg = TRI.getDwarfRegNum(*SR, false);
132 // Intersection between the bits we already emitted and the bits
133 // covered by this subregister.
134 SmallBitVector Intersection(RegSize, false);
135 Intersection.set(Offset, Offset + Size);
136 Intersection ^= Coverage;
138 // If this sub-register has a DWARF number and we haven't covered
139 // its range, emit a DWARF piece for it.
140 if (Reg >= 0 && Intersection.any()) {
141 // Emit a piece for any gap in the coverage.
143 DwarfRegs.push_back({-1, Offset - CurPos, nullptr});
145 {Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"});
146 if (Offset >= MaxSize)
149 // Mark it as emitted.
150 Coverage.set(Offset, Offset + Size);
151 CurPos = Offset + Size;
158 void DwarfExpression::addStackValue() {
159 if (DwarfVersion >= 4)
160 emitOp(dwarf::DW_OP_stack_value);
163 void DwarfExpression::addSignedConstant(int64_t Value) {
164 assert(LocationKind == Implicit || LocationKind == Unknown);
165 LocationKind = Implicit;
166 emitOp(dwarf::DW_OP_consts);
170 void DwarfExpression::addUnsignedConstant(uint64_t Value) {
171 assert(LocationKind == Implicit || LocationKind == Unknown);
172 LocationKind = Implicit;
173 emitOp(dwarf::DW_OP_constu);
177 void DwarfExpression::addUnsignedConstant(const APInt &Value) {
178 assert(LocationKind == Implicit || LocationKind == Unknown);
179 LocationKind = Implicit;
181 unsigned Size = Value.getBitWidth();
182 const uint64_t *Data = Value.getRawData();
184 // Chop it up into 64-bit pieces, because that's the maximum that
185 // addUnsignedConstant takes.
187 while (Offset < Size) {
188 addUnsignedConstant(*Data++);
189 if (Offset == 0 && Size <= 64)
192 addOpPiece(std::min(Size - Offset, 64u), Offset);
197 bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI,
198 DIExpressionCursor &ExprCursor,
200 unsigned FragmentOffsetInBits) {
201 auto Fragment = ExprCursor.getFragmentInfo();
202 if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) {
203 LocationKind = Unknown;
207 bool HasComplexExpression = false;
208 auto Op = ExprCursor.peek();
209 if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
210 HasComplexExpression = true;
212 // If the register can only be described by a complex expression (i.e.,
213 // multiple subregisters) it doesn't safely compose with another complex
214 // expression. For example, it is not possible to apply a DW_OP_deref
215 // operation to multiple DW_OP_pieces.
216 if (HasComplexExpression && DwarfRegs.size() > 1) {
218 LocationKind = Unknown;
222 // Handle simple register locations.
223 if (LocationKind != Memory && !HasComplexExpression) {
224 for (auto &Reg : DwarfRegs) {
225 if (Reg.DwarfRegNo >= 0)
226 addReg(Reg.DwarfRegNo, Reg.Comment);
227 addOpPiece(Reg.Size);
233 // Don't emit locations that cannot be expressed without DW_OP_stack_value.
234 if (DwarfVersion < 4)
235 if (std::any_of(ExprCursor.begin(), ExprCursor.end(),
236 [](DIExpression::ExprOperand Op) -> bool {
237 return Op.getOp() == dwarf::DW_OP_stack_value;
240 LocationKind = Unknown;
244 assert(DwarfRegs.size() == 1);
245 auto Reg = DwarfRegs[0];
246 bool FBReg = isFrameRegister(TRI, MachineReg);
247 int SignedOffset = 0;
248 assert(Reg.Size == 0 && "subregister has same size as superregister");
250 // Pattern-match combinations for which more efficient representations exist.
251 // [Reg, Offset, DW_OP_plus] --> [DW_OP_breg, Offset].
252 // [Reg, Offset, DW_OP_minus] --> [DW_OP_breg, -Offset].
253 // If Reg is a subregister we need to mask it out before subtracting.
254 if (Op && ((Op->getOp() == dwarf::DW_OP_plus) ||
255 (Op->getOp() == dwarf::DW_OP_minus && !SubRegisterSizeInBits))) {
256 int Offset = Op->getArg(0);
257 SignedOffset = (Op->getOp() == dwarf::DW_OP_plus) ? Offset : -Offset;
261 addFBReg(SignedOffset);
263 addBReg(Reg.DwarfRegNo, SignedOffset);
268 /// Assuming a well-formed expression, match "DW_OP_deref* DW_OP_LLVM_fragment?".
269 static bool isMemoryLocation(DIExpressionCursor ExprCursor) {
271 auto Op = ExprCursor.take();
272 switch (Op->getOp()) {
273 case dwarf::DW_OP_deref:
274 case dwarf::DW_OP_LLVM_fragment:
283 void DwarfExpression::addExpression(DIExpressionCursor &&ExprCursor,
284 unsigned FragmentOffsetInBits) {
285 // If we need to mask out a subregister, do it now, unless the next
286 // operation would emit an OpPiece anyway.
287 auto N = ExprCursor.peek();
288 if (SubRegisterSizeInBits && N && (N->getOp() != dwarf::DW_OP_LLVM_fragment))
292 auto Op = ExprCursor.take();
293 switch (Op->getOp()) {
294 case dwarf::DW_OP_LLVM_fragment: {
295 unsigned SizeInBits = Op->getArg(1);
296 unsigned FragmentOffset = Op->getArg(0);
297 // The fragment offset must have already been adjusted by emitting an
298 // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
300 assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
302 // If addMachineReg already emitted DW_OP_piece operations to represent
303 // a super-register by splicing together sub-registers, subtract the size
304 // of the pieces that was already emitted.
305 SizeInBits -= OffsetInBits - FragmentOffset;
307 // If addMachineReg requested a DW_OP_bit_piece to stencil out a
308 // sub-register that is smaller than the current fragment's size, use it.
309 if (SubRegisterSizeInBits)
310 SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
312 // Emit a DW_OP_stack_value for implicit location descriptions.
313 if (LocationKind == Implicit)
316 // Emit the DW_OP_piece.
317 addOpPiece(SizeInBits, SubRegisterOffsetInBits);
318 setSubRegisterPiece(0, 0);
319 // Reset the location description kind.
320 LocationKind = Unknown;
323 case dwarf::DW_OP_plus:
324 assert(LocationKind != Register);
325 emitOp(dwarf::DW_OP_plus_uconst);
326 emitUnsigned(Op->getArg(0));
328 case dwarf::DW_OP_minus:
329 assert(LocationKind != Register);
330 // There is no DW_OP_minus_uconst.
331 emitOp(dwarf::DW_OP_constu);
332 emitUnsigned(Op->getArg(0));
333 emitOp(dwarf::DW_OP_minus);
335 case dwarf::DW_OP_deref: {
336 assert(LocationKind != Register);
337 if (LocationKind != Memory && isMemoryLocation(ExprCursor))
338 // Turning this into a memory location description makes the deref
340 LocationKind = Memory;
342 emitOp(dwarf::DW_OP_deref);
345 case dwarf::DW_OP_constu:
346 assert(LocationKind != Register);
347 emitOp(dwarf::DW_OP_constu);
348 emitUnsigned(Op->getArg(0));
350 case dwarf::DW_OP_stack_value:
351 LocationKind = Implicit;
353 case dwarf::DW_OP_swap:
354 assert(LocationKind != Register);
355 emitOp(dwarf::DW_OP_swap);
357 case dwarf::DW_OP_xderef:
358 assert(LocationKind != Register);
359 emitOp(dwarf::DW_OP_xderef);
362 llvm_unreachable("unhandled opcode found in expression");
366 if (LocationKind == Implicit)
367 // Turn this into an implicit location description.
371 /// add masking operations to stencil out a subregister.
372 void DwarfExpression::maskSubRegister() {
373 assert(SubRegisterSizeInBits && "no subregister was registered");
374 if (SubRegisterOffsetInBits > 0)
375 addShr(SubRegisterOffsetInBits);
376 uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
381 void DwarfExpression::finalize() {
382 assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
383 // Emit any outstanding DW_OP_piece operations to mask out subregisters.
384 if (SubRegisterSizeInBits == 0)
386 // Don't emit a DW_OP_piece for a subregister at offset 0.
387 if (SubRegisterOffsetInBits == 0)
389 addOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits);
392 void DwarfExpression::addFragmentOffset(const DIExpression *Expr) {
393 if (!Expr || !Expr->isFragment())
396 uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
397 assert(FragmentOffset >= OffsetInBits &&
398 "overlapping or duplicate fragments");
399 if (FragmentOffset > OffsetInBits)
400 addOpPiece(FragmentOffset - OffsetInBits);
401 OffsetInBits = FragmentOffset;