1 //===-- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains support for writing dwarf debug info into asm files.
12 //===----------------------------------------------------------------------===//
14 #include "DwarfExpression.h"
15 #include "DwarfDebug.h"
16 #include "llvm/ADT/SmallBitVector.h"
17 #include "llvm/CodeGen/AsmPrinter.h"
18 #include "llvm/Support/Dwarf.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/Target/TargetSubtargetInfo.h"
25 void DwarfExpression::AddReg(int DwarfReg, const char *Comment) {
26 assert(DwarfReg >= 0 && "invalid negative dwarf register number");
28 EmitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
30 EmitOp(dwarf::DW_OP_regx, Comment);
31 EmitUnsigned(DwarfReg);
35 void DwarfExpression::AddRegIndirect(int DwarfReg, int Offset, bool Deref) {
36 assert(DwarfReg >= 0 && "invalid negative dwarf register number");
38 EmitOp(dwarf::DW_OP_breg0 + DwarfReg);
40 EmitOp(dwarf::DW_OP_bregx);
41 EmitUnsigned(DwarfReg);
45 EmitOp(dwarf::DW_OP_deref);
48 void DwarfExpression::AddOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
49 assert(SizeInBits > 0 && "piece has size zero");
50 const unsigned SizeOfByte = 8;
51 if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
52 EmitOp(dwarf::DW_OP_bit_piece);
53 EmitUnsigned(SizeInBits);
54 EmitUnsigned(OffsetInBits);
56 EmitOp(dwarf::DW_OP_piece);
57 unsigned ByteSize = SizeInBits / SizeOfByte;
58 EmitUnsigned(ByteSize);
62 void DwarfExpression::AddShr(unsigned ShiftBy) {
63 EmitOp(dwarf::DW_OP_constu);
64 EmitUnsigned(ShiftBy);
65 EmitOp(dwarf::DW_OP_shr);
68 bool DwarfExpression::AddMachineRegIndirect(const TargetRegisterInfo &TRI,
69 unsigned MachineReg, int Offset) {
70 if (isFrameRegister(TRI, MachineReg)) {
71 // If variable offset is based in frame register then use fbreg.
72 EmitOp(dwarf::DW_OP_fbreg);
77 int DwarfReg = TRI.getDwarfRegNum(MachineReg, false);
81 AddRegIndirect(DwarfReg, Offset);
85 bool DwarfExpression::AddMachineRegPiece(const TargetRegisterInfo &TRI,
87 unsigned PieceSizeInBits,
88 unsigned PieceOffsetInBits) {
89 if (!TRI.isPhysicalRegister(MachineReg))
92 int Reg = TRI.getDwarfRegNum(MachineReg, false);
94 // If this is a valid register number, emit it.
98 AddOpPiece(PieceSizeInBits, PieceOffsetInBits);
102 // Walk up the super-register chain until we find a valid number.
103 // For example, EAX on x86_64 is a 32-bit piece of RAX with offset 0.
104 for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
105 Reg = TRI.getDwarfRegNum(*SR, false);
107 unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
108 unsigned Size = TRI.getSubRegIdxSize(Idx);
109 unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
110 AddReg(Reg, "super-register");
111 if (PieceOffsetInBits == RegOffset) {
112 AddOpPiece(Size, RegOffset);
114 // If this is part of a variable in a sub-register at a
115 // non-zero offset, we need to manually shift the value into
116 // place, since the DW_OP_piece describes the part of the
117 // variable, not the position of the subregister.
120 AddOpPiece(Size, PieceOffsetInBits);
126 // Otherwise, attempt to find a covering set of sub-register numbers.
127 // For example, Q0 on ARM is a composition of D0+D1.
129 // Keep track of the current position so we can emit the more
130 // efficient DW_OP_piece.
131 unsigned CurPos = PieceOffsetInBits;
132 // The size of the register in bits, assuming 8 bits per byte.
133 unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8;
134 // Keep track of the bits in the register we already emitted, so we
135 // can avoid emitting redundant aliasing subregs.
136 SmallBitVector Coverage(RegSize, false);
137 for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
138 unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
139 unsigned Size = TRI.getSubRegIdxSize(Idx);
140 unsigned Offset = TRI.getSubRegIdxOffset(Idx);
141 Reg = TRI.getDwarfRegNum(*SR, false);
143 // Intersection between the bits we already emitted and the bits
144 // covered by this subregister.
145 SmallBitVector Intersection(RegSize, false);
146 Intersection.set(Offset, Offset + Size);
147 Intersection ^= Coverage;
149 // If this sub-register has a DWARF number and we haven't covered
150 // its range, emit a DWARF piece for it.
151 if (Reg >= 0 && Intersection.any()) {
152 AddReg(Reg, "sub-register");
153 AddOpPiece(Size, Offset == CurPos ? 0 : Offset);
154 CurPos = Offset + Size;
156 // Mark it as emitted.
157 Coverage.set(Offset, Offset + Size);
161 return CurPos > PieceOffsetInBits;
164 void DwarfExpression::AddStackValue() {
165 if (DwarfVersion >= 4)
166 EmitOp(dwarf::DW_OP_stack_value);
169 void DwarfExpression::AddSignedConstant(int64_t Value) {
170 EmitOp(dwarf::DW_OP_consts);
175 void DwarfExpression::AddUnsignedConstant(uint64_t Value) {
176 EmitOp(dwarf::DW_OP_constu);
181 void DwarfExpression::AddUnsignedConstant(const APInt &Value) {
182 unsigned Size = Value.getBitWidth();
183 const uint64_t *Data = Value.getRawData();
185 // Chop it up into 64-bit pieces, because that's the maximum that
186 // AddUnsignedConstant takes.
188 while (Offset < Size) {
189 AddUnsignedConstant(*Data++);
190 if (Offset == 0 && Size <= 64)
192 AddOpPiece(std::min(Size-Offset, 64u), Offset);
197 static unsigned getOffsetOrZero(unsigned OffsetInBits,
198 unsigned PieceOffsetInBits) {
199 if (OffsetInBits == PieceOffsetInBits)
201 assert(OffsetInBits >= PieceOffsetInBits && "overlapping pieces");
205 bool DwarfExpression::AddMachineRegExpression(const TargetRegisterInfo &TRI,
206 const DIExpression *Expr,
208 unsigned PieceOffsetInBits) {
209 auto I = Expr->expr_op_begin();
210 auto E = Expr->expr_op_end();
212 return AddMachineRegPiece(TRI, MachineReg);
214 // Pattern-match combinations for which more efficient representations exist
216 bool ValidReg = false;
217 switch (I->getOp()) {
218 case dwarf::DW_OP_bit_piece: {
219 unsigned OffsetInBits = I->getArg(0);
220 unsigned SizeInBits = I->getArg(1);
221 // Piece always comes at the end of the expression.
222 return AddMachineRegPiece(TRI, MachineReg, SizeInBits,
223 getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
225 case dwarf::DW_OP_plus:
226 case dwarf::DW_OP_minus: {
227 // [DW_OP_reg,Offset,DW_OP_plus, DW_OP_deref] --> [DW_OP_breg, Offset].
228 // [DW_OP_reg,Offset,DW_OP_minus,DW_OP_deref] --> [DW_OP_breg,-Offset].
229 auto N = I.getNext();
230 if (N != E && N->getOp() == dwarf::DW_OP_deref) {
231 unsigned Offset = I->getArg(0);
232 ValidReg = AddMachineRegIndirect(
233 TRI, MachineReg, I->getOp() == dwarf::DW_OP_plus ? Offset : -Offset);
237 ValidReg = AddMachineRegPiece(TRI, MachineReg);
239 case dwarf::DW_OP_deref: {
240 // [DW_OP_reg,DW_OP_deref] --> [DW_OP_breg].
241 ValidReg = AddMachineRegIndirect(TRI, MachineReg);
246 llvm_unreachable("unsupported operand");
252 // Emit remaining elements of the expression.
253 AddExpression(I, E, PieceOffsetInBits);
257 void DwarfExpression::AddExpression(DIExpression::expr_op_iterator I,
258 DIExpression::expr_op_iterator E,
259 unsigned PieceOffsetInBits) {
260 for (; I != E; ++I) {
261 switch (I->getOp()) {
262 case dwarf::DW_OP_bit_piece: {
263 unsigned OffsetInBits = I->getArg(0);
264 unsigned SizeInBits = I->getArg(1);
265 AddOpPiece(SizeInBits, getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
268 case dwarf::DW_OP_plus:
269 EmitOp(dwarf::DW_OP_plus_uconst);
270 EmitUnsigned(I->getArg(0));
272 case dwarf::DW_OP_minus:
273 // There is no OP_minus_uconst.
274 EmitOp(dwarf::DW_OP_constu);
275 EmitUnsigned(I->getArg(0));
276 EmitOp(dwarf::DW_OP_minus);
278 case dwarf::DW_OP_deref:
279 EmitOp(dwarf::DW_OP_deref);
282 llvm_unreachable("unhandled opcode found in expression");