1 //===-- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains support for writing dwarf debug info into asm files.
12 //===----------------------------------------------------------------------===//
14 #include "DwarfExpression.h"
15 #include "DwarfDebug.h"
16 #include "llvm/ADT/SmallBitVector.h"
17 #include "llvm/CodeGen/AsmPrinter.h"
18 #include "llvm/Support/Dwarf.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/Target/TargetSubtargetInfo.h"
25 void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
26 assert(DwarfReg >= 0 && "invalid negative dwarf register number");
28 emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
30 emitOp(dwarf::DW_OP_regx, Comment);
31 emitUnsigned(DwarfReg);
35 void DwarfExpression::addBReg(int DwarfReg, int Offset) {
36 assert(DwarfReg >= 0 && "invalid negative dwarf register number");
38 emitOp(dwarf::DW_OP_breg0 + DwarfReg);
40 emitOp(dwarf::DW_OP_bregx);
41 emitUnsigned(DwarfReg);
46 void DwarfExpression::addFBReg(int Offset) {
47 emitOp(dwarf::DW_OP_fbreg);
51 void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
55 const unsigned SizeOfByte = 8;
56 if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
57 emitOp(dwarf::DW_OP_bit_piece);
58 emitUnsigned(SizeInBits);
59 emitUnsigned(OffsetInBits);
61 emitOp(dwarf::DW_OP_piece);
62 unsigned ByteSize = SizeInBits / SizeOfByte;
63 emitUnsigned(ByteSize);
65 this->OffsetInBits += SizeInBits;
68 void DwarfExpression::addShr(unsigned ShiftBy) {
69 emitOp(dwarf::DW_OP_constu);
70 emitUnsigned(ShiftBy);
71 emitOp(dwarf::DW_OP_shr);
74 void DwarfExpression::addAnd(unsigned Mask) {
75 emitOp(dwarf::DW_OP_constu);
77 emitOp(dwarf::DW_OP_and);
80 bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
81 unsigned MachineReg, unsigned MaxSize) {
82 if (!TRI.isPhysicalRegister(MachineReg)) {
83 if (isFrameRegister(TRI, MachineReg)) {
84 DwarfRegs.push_back({-1, 0, nullptr});
90 int Reg = TRI.getDwarfRegNum(MachineReg, false);
92 // If this is a valid register number, emit it.
94 DwarfRegs.push_back({Reg, 0, nullptr});
98 // Walk up the super-register chain until we find a valid number.
99 // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
100 for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
101 Reg = TRI.getDwarfRegNum(*SR, false);
103 unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
104 unsigned Size = TRI.getSubRegIdxSize(Idx);
105 unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
106 DwarfRegs.push_back({Reg, 0, "super-register"});
107 // Use a DW_OP_bit_piece to describe the sub-register.
108 setSubRegisterPiece(Size, RegOffset);
113 // Otherwise, attempt to find a covering set of sub-register numbers.
114 // For example, Q0 on ARM is a composition of D0+D1.
116 // The size of the register in bits, assuming 8 bits per byte.
117 unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8;
118 // Keep track of the bits in the register we already emitted, so we
119 // can avoid emitting redundant aliasing subregs.
120 SmallBitVector Coverage(RegSize, false);
121 for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
122 unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
123 unsigned Size = TRI.getSubRegIdxSize(Idx);
124 unsigned Offset = TRI.getSubRegIdxOffset(Idx);
125 Reg = TRI.getDwarfRegNum(*SR, false);
127 // Intersection between the bits we already emitted and the bits
128 // covered by this subregister.
129 SmallBitVector Intersection(RegSize, false);
130 Intersection.set(Offset, Offset + Size);
131 Intersection ^= Coverage;
133 // If this sub-register has a DWARF number and we haven't covered
134 // its range, emit a DWARF piece for it.
135 if (Reg >= 0 && Intersection.any()) {
136 // Emit a piece for any gap in the coverage.
138 DwarfRegs.push_back({-1, Offset - CurPos, nullptr});
140 {Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"});
141 if (Offset >= MaxSize)
144 // Mark it as emitted.
145 Coverage.set(Offset, Offset + Size);
146 CurPos = Offset + Size;
153 void DwarfExpression::addStackValue() {
154 if (DwarfVersion >= 4)
155 emitOp(dwarf::DW_OP_stack_value);
158 void DwarfExpression::addSignedConstant(int64_t Value) {
159 emitOp(dwarf::DW_OP_consts);
164 void DwarfExpression::addUnsignedConstant(uint64_t Value) {
165 emitOp(dwarf::DW_OP_constu);
170 void DwarfExpression::addUnsignedConstant(const APInt &Value) {
171 unsigned Size = Value.getBitWidth();
172 const uint64_t *Data = Value.getRawData();
174 // Chop it up into 64-bit pieces, because that's the maximum that
175 // addUnsignedConstant takes.
177 while (Offset < Size) {
178 addUnsignedConstant(*Data++);
179 if (Offset == 0 && Size <= 64)
181 addOpPiece(std::min(Size-Offset, 64u), Offset);
186 bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI,
187 DIExpressionCursor &ExprCursor,
189 unsigned FragmentOffsetInBits) {
190 auto Fragment = ExprCursor.getFragmentInfo();
191 if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U))
194 bool HasComplexExpression = false;
195 auto Op = ExprCursor.peek();
196 if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
197 HasComplexExpression = true;
199 // If the register can only be described by a complex expression (i.e.,
200 // multiple subregisters) it doesn't safely compose with another complex
201 // expression. For example, it is not possible to apply a DW_OP_deref
202 // operation to multiple DW_OP_pieces.
203 if (HasComplexExpression && DwarfRegs.size() > 1) {
208 // Handle simple register locations.
209 if (!HasComplexExpression) {
210 for (auto &Reg : DwarfRegs) {
211 if (Reg.DwarfRegNo >= 0)
212 addReg(Reg.DwarfRegNo, Reg.Comment);
213 addOpPiece(Reg.Size);
219 assert(DwarfRegs.size() == 1);
220 auto Reg = DwarfRegs[0];
221 bool FBReg = isFrameRegister(TRI, MachineReg);
222 assert(Reg.Size == 0 && "subregister has same size as superregister");
224 // Pattern-match combinations for which more efficient representations exist.
225 switch (Op->getOp()) {
230 addReg(Reg.DwarfRegNo, 0);
233 case dwarf::DW_OP_plus:
234 case dwarf::DW_OP_minus: {
235 // [DW_OP_reg,Offset,DW_OP_plus, DW_OP_deref] --> [DW_OP_breg, Offset].
236 // [DW_OP_reg,Offset,DW_OP_minus,DW_OP_deref] --> [DW_OP_breg,-Offset].
237 auto N = ExprCursor.peekNext();
238 if (N && N->getOp() == dwarf::DW_OP_deref) {
239 int Offset = Op->getArg(0);
240 int SignedOffset = (Op->getOp() == dwarf::DW_OP_plus) ? Offset : -Offset;
242 addFBReg(SignedOffset);
244 addBReg(Reg.DwarfRegNo, SignedOffset);
246 ExprCursor.consume(2);
249 addReg(Reg.DwarfRegNo, 0);
252 case dwarf::DW_OP_deref:
253 // [DW_OP_reg,DW_OP_deref] --> [DW_OP_breg].
257 addBReg(Reg.DwarfRegNo, 0);
265 void DwarfExpression::addExpression(DIExpressionCursor &&ExprCursor,
266 unsigned FragmentOffsetInBits) {
268 auto Op = ExprCursor.take();
270 // If we need to mask out a subregister, do it now, unless the next
271 // operation would emit an OpPiece anyway.
272 if (SubRegisterSizeInBits && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
275 switch (Op->getOp()) {
276 case dwarf::DW_OP_LLVM_fragment: {
277 unsigned SizeInBits = Op->getArg(1);
278 unsigned FragmentOffset = Op->getArg(0);
279 // The fragment offset must have already been adjusted by emitting an
280 // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
282 assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
284 // If \a addMachineReg already emitted DW_OP_piece operations to represent
285 // a super-register by splicing together sub-registers, subtract the size
286 // of the pieces that was already emitted.
287 SizeInBits -= OffsetInBits - FragmentOffset;
289 // If \a addMachineReg requested a DW_OP_bit_piece to stencil out a
290 // sub-register that is smaller than the current fragment's size, use it.
291 if (SubRegisterSizeInBits)
292 SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
294 addOpPiece(SizeInBits, SubRegisterOffsetInBits);
295 setSubRegisterPiece(0, 0);
298 case dwarf::DW_OP_plus:
299 emitOp(dwarf::DW_OP_plus_uconst);
300 emitUnsigned(Op->getArg(0));
302 case dwarf::DW_OP_minus:
303 // There is no OP_minus_uconst.
304 emitOp(dwarf::DW_OP_constu);
305 emitUnsigned(Op->getArg(0));
306 emitOp(dwarf::DW_OP_minus);
308 case dwarf::DW_OP_deref:
309 emitOp(dwarf::DW_OP_deref);
311 case dwarf::DW_OP_constu:
312 emitOp(dwarf::DW_OP_constu);
313 emitUnsigned(Op->getArg(0));
315 case dwarf::DW_OP_stack_value:
318 case dwarf::DW_OP_swap:
319 emitOp(dwarf::DW_OP_swap);
321 case dwarf::DW_OP_xderef:
322 emitOp(dwarf::DW_OP_xderef);
325 llvm_unreachable("unhandled opcode found in expression");
330 /// add masking operations to stencil out a subregister.
331 void DwarfExpression::maskSubRegister() {
332 assert(SubRegisterSizeInBits && "no subregister was registered");
333 if (SubRegisterOffsetInBits > 0)
334 addShr(SubRegisterOffsetInBits);
335 uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
340 void DwarfExpression::finalize() {
341 assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
342 // Emit any outstanding DW_OP_piece operations to mask out subregisters.
343 if (SubRegisterSizeInBits == 0)
345 // Don't emit a DW_OP_piece for a subregister at offset 0.
346 if (SubRegisterOffsetInBits == 0)
348 addOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits);
351 void DwarfExpression::addFragmentOffset(const DIExpression *Expr) {
352 if (!Expr || !Expr->isFragment())
355 uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
356 assert(FragmentOffset >= OffsetInBits &&
357 "overlapping or duplicate fragments");
358 if (FragmentOffset > OffsetInBits)
359 addOpPiece(FragmentOffset - OffsetInBits);
360 OffsetInBits = FragmentOffset;