1 //=- llvm/CodeGen/DFAPacketizer.cpp - DFA Packetizer for VLIW -*- C++ -*-=====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This class implements a deterministic finite automaton (DFA) based
10 // packetizing mechanism for VLIW architectures. It provides APIs to
11 // determine whether there exists a legal mapping of instructions to
12 // functional unit assignments in a packet. The DFA is auto-generated from
13 // the target's Schedule.td file.
15 // A DFA consists of 3 major elements: states, inputs, and transitions. For
16 // the packetizing mechanism, the input is the set of instruction classes for
17 // a target. The state models all possible combinations of functional unit
18 // consumption for a given set of instructions in a packet. A transition
19 // models the addition of an instruction to a packet. In the DFA constructed
20 // by this class, if an instruction can be added to a packet, then a valid
21 // transition exists from the corresponding state. Invalid transitions
22 // indicate that the instruction cannot be added to the current packet.
24 //===----------------------------------------------------------------------===//
26 #define DEBUG_TYPE "packets"
28 #include "llvm/CodeGen/DFAPacketizer.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineInstrBundle.h"
31 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
32 #include "llvm/MC/MCInstrItineraries.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Support/CommandLine.h"
38 static cl::opt<unsigned> InstrLimit("dfa-instr-limit", cl::Hidden,
39 cl::init(0), cl::desc("If present, stops packetizing after N instructions"));
40 static unsigned InstrCount = 0;
42 // --------------------------------------------------------------------
43 // Definitions shared between DFAPacketizer.cpp and DFAPacketizerEmitter.cpp
46 DFAInput addDFAFuncUnits(DFAInput Inp, unsigned FuncUnits) {
47 return (Inp << DFA_MAX_RESOURCES) | FuncUnits;
50 /// Return the DFAInput for an instruction class input vector.
51 /// This function is used in both DFAPacketizer.cpp and in
52 /// DFAPacketizerEmitter.cpp.
53 DFAInput getDFAInsnInput(const std::vector<unsigned> &InsnClass) {
54 DFAInput InsnInput = 0;
55 assert((InsnClass.size() <= DFA_MAX_RESTERMS) &&
56 "Exceeded maximum number of DFA terms");
57 for (auto U : InsnClass)
58 InsnInput = addDFAFuncUnits(InsnInput, U);
62 // --------------------------------------------------------------------
64 DFAPacketizer::DFAPacketizer(const InstrItineraryData *I,
65 const DFAStateInput (*SIT)[2],
67 InstrItins(I), CurrentState(0), DFAStateInputTable(SIT),
68 DFAStateEntryTable(SET) {
69 // Make sure DFA types are large enough for the number of terms & resources.
70 static_assert((DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <=
71 (8 * sizeof(DFAInput)),
72 "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAInput");
74 (DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <= (8 * sizeof(DFAStateInput)),
75 "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAStateInput");
79 // Read the DFA transition table and update CachedTable.
81 // Format of the transition tables:
82 // DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid
84 // DFAStateEntryTable[i] = Index of the first entry in DFAStateInputTable
87 void DFAPacketizer::ReadTable(unsigned int state) {
88 unsigned ThisState = DFAStateEntryTable[state];
89 unsigned NextStateInTable = DFAStateEntryTable[state+1];
90 // Early exit in case CachedTable has already contains this
91 // state's transitions.
92 if (CachedTable.count(UnsignPair(state, DFAStateInputTable[ThisState][0])))
95 for (unsigned i = ThisState; i < NextStateInTable; i++)
96 CachedTable[UnsignPair(state, DFAStateInputTable[i][0])] =
97 DFAStateInputTable[i][1];
101 // Return the DFAInput for an instruction class.
102 DFAInput DFAPacketizer::getInsnInput(unsigned InsnClass) {
103 // Note: this logic must match that in DFAPacketizerDefs.h for input vectors.
104 DFAInput InsnInput = 0;
107 for (const InstrStage *IS = InstrItins->beginStage(InsnClass),
108 *IE = InstrItins->endStage(InsnClass); IS != IE; ++IS) {
109 InsnInput = addDFAFuncUnits(InsnInput, IS->getUnits());
110 assert((i++ < DFA_MAX_RESTERMS) && "Exceeded maximum number of DFA inputs");
116 // Return the DFAInput for an instruction class input vector.
117 DFAInput DFAPacketizer::getInsnInput(const std::vector<unsigned> &InsnClass) {
118 return getDFAInsnInput(InsnClass);
122 // Check if the resources occupied by a MCInstrDesc are available in the
124 bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc *MID) {
125 unsigned InsnClass = MID->getSchedClass();
126 DFAInput InsnInput = getInsnInput(InsnClass);
127 UnsignPair StateTrans = UnsignPair(CurrentState, InsnInput);
128 ReadTable(CurrentState);
129 return CachedTable.count(StateTrans) != 0;
133 // Reserve the resources occupied by a MCInstrDesc and change the current
134 // state to reflect that change.
135 void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) {
136 unsigned InsnClass = MID->getSchedClass();
137 DFAInput InsnInput = getInsnInput(InsnClass);
138 UnsignPair StateTrans = UnsignPair(CurrentState, InsnInput);
139 ReadTable(CurrentState);
140 assert(CachedTable.count(StateTrans) != 0);
141 CurrentState = CachedTable[StateTrans];
145 // Check if the resources occupied by a machine instruction are available
146 // in the current state.
147 bool DFAPacketizer::canReserveResources(llvm::MachineInstr &MI) {
148 const llvm::MCInstrDesc &MID = MI.getDesc();
149 return canReserveResources(&MID);
153 // Reserve the resources occupied by a machine instruction and change the
154 // current state to reflect that change.
155 void DFAPacketizer::reserveResources(llvm::MachineInstr &MI) {
156 const llvm::MCInstrDesc &MID = MI.getDesc();
157 reserveResources(&MID);
162 // This class extends ScheduleDAGInstrs and overrides the schedule method
163 // to build the dependence graph.
164 class DefaultVLIWScheduler : public ScheduleDAGInstrs {
167 /// Ordered list of DAG postprocessing steps.
168 std::vector<std::unique_ptr<ScheduleDAGMutation>> Mutations;
170 DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI,
172 // Actual scheduling work.
173 void schedule() override;
175 /// DefaultVLIWScheduler takes ownership of the Mutation object.
176 void addMutation(std::unique_ptr<ScheduleDAGMutation> Mutation) {
177 Mutations.push_back(std::move(Mutation));
180 void postprocessDAG();
185 DefaultVLIWScheduler::DefaultVLIWScheduler(MachineFunction &MF,
186 MachineLoopInfo &MLI,
188 : ScheduleDAGInstrs(MF, &MLI), AA(AA) {
189 CanHandleTerminators = true;
193 /// Apply each ScheduleDAGMutation step in order.
194 void DefaultVLIWScheduler::postprocessDAG() {
195 for (auto &M : Mutations)
200 void DefaultVLIWScheduler::schedule() {
201 // Build the scheduling graph.
207 VLIWPacketizerList::VLIWPacketizerList(MachineFunction &mf,
208 MachineLoopInfo &mli, AliasAnalysis *aa)
209 : MF(mf), TII(mf.getSubtarget().getInstrInfo()), AA(aa) {
210 ResourceTracker = TII->CreateTargetScheduleState(MF.getSubtarget());
211 VLIWScheduler = new DefaultVLIWScheduler(MF, mli, AA);
215 VLIWPacketizerList::~VLIWPacketizerList() {
216 delete VLIWScheduler;
217 delete ResourceTracker;
221 // End the current packet, bundle packet instructions and reset DFA state.
222 void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,
223 MachineBasicBlock::iterator MI) {
225 if (!CurrentPacketMIs.empty()) {
226 dbgs() << "Finalizing packet:\n";
227 for (MachineInstr *MI : CurrentPacketMIs)
228 dbgs() << " * " << *MI;
231 if (CurrentPacketMIs.size() > 1) {
232 MachineInstr &MIFirst = *CurrentPacketMIs.front();
233 finalizeBundle(*MBB, MIFirst.getIterator(), MI.getInstrIterator());
235 CurrentPacketMIs.clear();
236 ResourceTracker->clearResources();
237 DEBUG(dbgs() << "End packet\n");
241 // Bundle machine instructions into packets.
242 void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
243 MachineBasicBlock::iterator BeginItr,
244 MachineBasicBlock::iterator EndItr) {
245 assert(VLIWScheduler && "VLIW Scheduler is not initialized!");
246 VLIWScheduler->startBlock(MBB);
247 VLIWScheduler->enterRegion(MBB, BeginItr, EndItr,
248 std::distance(BeginItr, EndItr));
249 VLIWScheduler->schedule();
252 dbgs() << "Scheduling DAG of the packetize region\n";
253 for (SUnit &SU : VLIWScheduler->SUnits)
254 SU.dumpAll(VLIWScheduler);
257 // Generate MI -> SU map.
259 for (SUnit &SU : VLIWScheduler->SUnits)
260 MIToSUnit[SU.getInstr()] = &SU;
262 bool LimitPresent = InstrLimit.getPosition();
264 // The main packetizer loop.
265 for (; BeginItr != EndItr; ++BeginItr) {
267 if (InstrCount >= InstrLimit) {
273 MachineInstr &MI = *BeginItr;
274 initPacketizerState();
276 // End the current packet if needed.
277 if (isSoloInstruction(MI)) {
282 // Ignore pseudo instructions.
283 if (ignorePseudoInstruction(MI, MBB))
286 SUnit *SUI = MIToSUnit[&MI];
287 assert(SUI && "Missing SUnit Info!");
289 // Ask DFA if machine resource is available for MI.
290 DEBUG(dbgs() << "Checking resources for adding MI to packet " << MI);
292 bool ResourceAvail = ResourceTracker->canReserveResources(MI);
295 dbgs() << " Resources are available for adding MI to packet\n";
297 dbgs() << " Resources NOT available\n";
299 if (ResourceAvail && shouldAddToPacket(MI)) {
300 // Dependency check for MI with instructions in CurrentPacketMIs.
301 for (auto MJ : CurrentPacketMIs) {
302 SUnit *SUJ = MIToSUnit[MJ];
303 assert(SUJ && "Missing SUnit Info!");
305 DEBUG(dbgs() << " Checking against MJ " << *MJ);
306 // Is it legal to packetize SUI and SUJ together.
307 if (!isLegalToPacketizeTogether(SUI, SUJ)) {
308 DEBUG(dbgs() << " Not legal to add MI, try to prune\n");
309 // Allow packetization if dependency can be pruned.
310 if (!isLegalToPruneDependencies(SUI, SUJ)) {
311 // End the packet if dependency cannot be pruned.
312 DEBUG(dbgs() << " Could not prune dependencies for adding MI\n");
316 DEBUG(dbgs() << " Pruned dependence for adding MI\n");
320 DEBUG(if (ResourceAvail)
321 dbgs() << "Resources are available, but instruction should not be "
322 "added to packet\n " << MI);
323 // End the packet if resource is not available, or if the instruction
324 // shoud not be added to the current packet.
328 // Add MI to the current packet.
329 DEBUG(dbgs() << "* Adding MI to packet " << MI << '\n');
330 BeginItr = addToPacket(MI);
331 } // For all instructions in the packetization range.
333 // End any packet left behind.
334 endPacket(MBB, EndItr);
335 VLIWScheduler->exitRegion();
336 VLIWScheduler->finishBlock();
340 // Add a DAG mutation object to the ordered list.
341 void VLIWPacketizerList::addMutation(
342 std::unique_ptr<ScheduleDAGMutation> Mutation) {
343 VLIWScheduler->addMutation(std::move(Mutation));