1 //===- DeadMachineInstructionElim.cpp - Remove dead machine instructions --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is an extremely simple MachineInstr-level dead-code-elimination pass.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/ADT/Statistic.h"
15 #include "llvm/CodeGen/MachineFunctionPass.h"
16 #include "llvm/CodeGen/MachineRegisterInfo.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/TargetSubtargetInfo.h"
19 #include "llvm/Pass.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
25 #define DEBUG_TYPE "dead-mi-elimination"
27 STATISTIC(NumDeletes, "Number of dead instructions deleted");
30 class DeadMachineInstructionElim : public MachineFunctionPass {
31 bool runOnMachineFunction(MachineFunction &MF) override;
33 const TargetRegisterInfo *TRI;
34 const MachineRegisterInfo *MRI;
35 const TargetInstrInfo *TII;
36 BitVector LivePhysRegs;
39 static char ID; // Pass identification, replacement for typeid
40 DeadMachineInstructionElim() : MachineFunctionPass(ID) {
41 initializeDeadMachineInstructionElimPass(*PassRegistry::getPassRegistry());
44 void getAnalysisUsage(AnalysisUsage &AU) const override {
46 MachineFunctionPass::getAnalysisUsage(AU);
50 bool isDead(const MachineInstr *MI) const;
53 char DeadMachineInstructionElim::ID = 0;
54 char &llvm::DeadMachineInstructionElimID = DeadMachineInstructionElim::ID;
56 INITIALIZE_PASS(DeadMachineInstructionElim, DEBUG_TYPE,
57 "Remove dead machine instructions", false, false)
59 bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
60 // Technically speaking inline asm without side effects and no defs can still
61 // be deleted. But there is so much bad inline asm code out there, we should
63 if (MI->isInlineAsm())
66 // Don't delete frame allocation labels.
67 if (MI->getOpcode() == TargetOpcode::LOCAL_ESCAPE)
70 // Don't delete instructions with side effects.
71 bool SawStore = false;
72 if (!MI->isSafeToMove(nullptr, SawStore) && !MI->isPHI())
75 // Examine each operand.
76 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
77 const MachineOperand &MO = MI->getOperand(i);
78 if (MO.isReg() && MO.isDef()) {
79 unsigned Reg = MO.getReg();
80 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
81 // Don't delete live physreg defs, or any reserved register defs.
82 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
85 if (!MRI->use_nodbg_empty(Reg))
86 // This def has a non-debug use. Don't delete the instruction!
92 // If there are no defs with uses, the instruction is dead.
96 bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
97 if (skipFunction(MF.getFunction()))
100 bool AnyChanges = false;
101 MRI = &MF.getRegInfo();
102 TRI = MF.getSubtarget().getRegisterInfo();
103 TII = MF.getSubtarget().getInstrInfo();
105 // Loop over all instructions in all blocks, from bottom to top, so that it's
106 // more likely that chains of dependent but ultimately dead instructions will
108 for (MachineBasicBlock &MBB : make_range(MF.rbegin(), MF.rend())) {
109 // Start out assuming that reserved registers are live out of this block.
110 LivePhysRegs = MRI->getReservedRegs();
112 // Add live-ins from successors to LivePhysRegs. Normally, physregs are not
113 // live across blocks, but some targets (x86) can have flags live out of a
115 for (MachineBasicBlock::succ_iterator S = MBB.succ_begin(),
116 E = MBB.succ_end(); S != E; S++)
117 for (const auto &LI : (*S)->liveins())
118 LivePhysRegs.set(LI.PhysReg);
120 // Now scan the instructions and delete dead ones, tracking physreg
121 // liveness as we go.
122 for (MachineBasicBlock::reverse_iterator MII = MBB.rbegin(),
123 MIE = MBB.rend(); MII != MIE; ) {
124 MachineInstr *MI = &*MII++;
126 // If the instruction is dead, delete it!
128 DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << *MI);
129 // It is possible that some DBG_VALUE instructions refer to this
130 // instruction. They get marked as undef and will be deleted
131 // in the live debug variable analysis.
132 MI->eraseFromParentAndMarkDBGValuesForRemoval();
138 // Record the physreg defs.
139 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
140 const MachineOperand &MO = MI->getOperand(i);
141 if (MO.isReg() && MO.isDef()) {
142 unsigned Reg = MO.getReg();
143 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
144 // Check the subreg set, not the alias set, because a def
145 // of a super-register may still be partially live after
147 for (MCSubRegIterator SR(Reg, TRI,/*IncludeSelf=*/true);
149 LivePhysRegs.reset(*SR);
151 } else if (MO.isRegMask()) {
152 // Register mask of preserved registers. All clobbers are dead.
153 LivePhysRegs.clearBitsNotInMask(MO.getRegMask());
156 // Record the physreg uses, after the defs, in case a physreg is
157 // both defined and used in the same instruction.
158 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
159 const MachineOperand &MO = MI->getOperand(i);
160 if (MO.isReg() && MO.isUse()) {
161 unsigned Reg = MO.getReg();
162 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
163 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
164 LivePhysRegs.set(*AI);
171 LivePhysRegs.clear();