1 //===-- lib/CodeGen/GlobalISel/CallLowering.cpp - Call lowering -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file implements some simple delegations needed for call lowering.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
16 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
17 #include "llvm/CodeGen/MachineOperand.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/TargetLowering.h"
20 #include "llvm/IR/DataLayout.h"
21 #include "llvm/IR/Instructions.h"
22 #include "llvm/IR/Module.h"
26 void CallLowering::anchor() {}
28 bool CallLowering::lowerCall(
29 MachineIRBuilder &MIRBuilder, ImmutableCallSite CS, unsigned ResReg,
30 ArrayRef<unsigned> ArgRegs, std::function<unsigned()> GetCalleeReg) const {
31 auto &DL = CS.getParent()->getParent()->getParent()->getDataLayout();
33 // First step is to marshall all the function's parameters into the correct
34 // physregs and memory locations. Gather the sequence of argument types that
35 // we'll pass to the assigner function.
36 SmallVector<ArgInfo, 8> OrigArgs;
38 unsigned NumFixedArgs = CS.getFunctionType()->getNumParams();
39 for (auto &Arg : CS.args()) {
40 ArgInfo OrigArg{ArgRegs[i], Arg->getType(), ISD::ArgFlagsTy{},
42 setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, CS);
43 // We don't currently support swifterror or swiftself args.
44 if (OrigArg.Flags.isSwiftError() || OrigArg.Flags.isSwiftSelf())
46 OrigArgs.push_back(OrigArg);
50 MachineOperand Callee = MachineOperand::CreateImm(0);
51 if (const Function *F = CS.getCalledFunction())
52 Callee = MachineOperand::CreateGA(F, 0);
54 Callee = MachineOperand::CreateReg(GetCalleeReg(), false);
56 ArgInfo OrigRet{ResReg, CS.getType(), ISD::ArgFlagsTy{}};
57 if (!OrigRet.Ty->isVoidTy())
58 setArgFlags(OrigRet, AttributeList::ReturnIndex, DL, CS);
60 return lowerCall(MIRBuilder, CS.getCallingConv(), Callee, OrigRet, OrigArgs);
63 template <typename FuncInfoTy>
64 void CallLowering::setArgFlags(CallLowering::ArgInfo &Arg, unsigned OpIdx,
66 const FuncInfoTy &FuncInfo) const {
67 const AttributeList &Attrs = FuncInfo.getAttributes();
68 if (Attrs.hasAttribute(OpIdx, Attribute::ZExt))
70 if (Attrs.hasAttribute(OpIdx, Attribute::SExt))
72 if (Attrs.hasAttribute(OpIdx, Attribute::InReg))
74 if (Attrs.hasAttribute(OpIdx, Attribute::StructRet))
76 if (Attrs.hasAttribute(OpIdx, Attribute::SwiftSelf))
77 Arg.Flags.setSwiftSelf();
78 if (Attrs.hasAttribute(OpIdx, Attribute::SwiftError))
79 Arg.Flags.setSwiftError();
80 if (Attrs.hasAttribute(OpIdx, Attribute::ByVal))
82 if (Attrs.hasAttribute(OpIdx, Attribute::InAlloca))
83 Arg.Flags.setInAlloca();
85 if (Arg.Flags.isByVal() || Arg.Flags.isInAlloca()) {
86 Type *ElementTy = cast<PointerType>(Arg.Ty)->getElementType();
87 Arg.Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
88 // For ByVal, alignment should be passed from FE. BE will guess if
89 // this info is not there but there are cases it cannot get right.
91 if (FuncInfo.getParamAlignment(OpIdx - 2))
92 FrameAlign = FuncInfo.getParamAlignment(OpIdx - 2);
94 FrameAlign = getTLI()->getByValTypeAlignment(ElementTy, DL);
95 Arg.Flags.setByValAlign(FrameAlign);
97 if (Attrs.hasAttribute(OpIdx, Attribute::Nest))
99 Arg.Flags.setOrigAlign(DL.getABITypeAlignment(Arg.Ty));
103 CallLowering::setArgFlags<Function>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
104 const DataLayout &DL,
105 const Function &FuncInfo) const;
108 CallLowering::setArgFlags<CallInst>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
109 const DataLayout &DL,
110 const CallInst &FuncInfo) const;
112 bool CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder,
113 ArrayRef<ArgInfo> Args,
114 ValueHandler &Handler) const {
115 MachineFunction &MF = MIRBuilder.getMF();
116 const Function &F = MF.getFunction();
117 const DataLayout &DL = F.getParent()->getDataLayout();
119 SmallVector<CCValAssign, 16> ArgLocs;
120 CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
122 unsigned NumArgs = Args.size();
123 for (unsigned i = 0; i != NumArgs; ++i) {
124 MVT CurVT = MVT::getVT(Args[i].Ty);
125 if (Handler.assignArg(i, CurVT, CurVT, CCValAssign::Full, Args[i], CCInfo))
129 for (unsigned i = 0, e = Args.size(), j = 0; i != e; ++i, ++j) {
130 assert(j < ArgLocs.size() && "Skipped too many arg locs");
132 CCValAssign &VA = ArgLocs[j];
133 assert(VA.getValNo() == i && "Location doesn't correspond to current arg");
135 if (VA.needsCustom()) {
136 j += Handler.assignCustomValue(Args[i], makeArrayRef(ArgLocs).slice(j));
141 Handler.assignValueToReg(Args[i].Reg, VA.getLocReg(), VA);
142 else if (VA.isMemLoc()) {
143 unsigned Size = VA.getValVT() == MVT::iPTR
144 ? DL.getPointerSize()
145 : alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
146 unsigned Offset = VA.getLocMemOffset();
147 MachinePointerInfo MPO;
148 unsigned StackAddr = Handler.getStackAddress(Size, Offset, MPO);
149 Handler.assignValueToAddress(Args[i].Reg, StackAddr, Size, MPO, VA);
151 // FIXME: Support byvals and other weirdness
158 unsigned CallLowering::ValueHandler::extendRegister(unsigned ValReg,
160 LLT LocTy{VA.getLocVT()};
161 switch (VA.getLocInfo()) {
163 case CCValAssign::Full:
164 case CCValAssign::BCvt:
165 // FIXME: bitconverting between vector types may or may not be a
166 // nop in big-endian situations.
168 case CCValAssign::AExt: {
169 auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg);
170 return MIB->getOperand(0).getReg();
172 case CCValAssign::SExt: {
173 unsigned NewReg = MRI.createGenericVirtualRegister(LocTy);
174 MIRBuilder.buildSExt(NewReg, ValReg);
177 case CCValAssign::ZExt: {
178 unsigned NewReg = MRI.createGenericVirtualRegister(LocTy);
179 MIRBuilder.buildZExt(NewReg, ValReg);
183 llvm_unreachable("unable to extend register");
186 void CallLowering::ValueHandler::anchor() {}