1 //===-- llvm/CodeGen/GlobalISel/IRTranslator.cpp - IRTranslator --*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements the IRTranslator class.
11 //===----------------------------------------------------------------------===//
13 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
17 #include "llvm/CodeGen/Analysis.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineModuleInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/TargetPassConfig.h"
23 #include "llvm/IR/Constant.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/IR/GetElementPtrTypeIterator.h"
26 #include "llvm/IR/IntrinsicInst.h"
27 #include "llvm/IR/Type.h"
28 #include "llvm/IR/Value.h"
29 #include "llvm/Target/TargetIntrinsicInfo.h"
30 #include "llvm/Target/TargetLowering.h"
32 #define DEBUG_TYPE "irtranslator"
36 char IRTranslator::ID = 0;
37 INITIALIZE_PASS_BEGIN(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
39 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
40 INITIALIZE_PASS_END(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
43 static void reportTranslationError(const Value &V, const Twine &Message) {
44 std::string ErrStorage;
45 raw_string_ostream Err(ErrStorage);
46 Err << Message << ": " << V << '\n';
47 report_fatal_error(Err.str());
50 IRTranslator::IRTranslator() : MachineFunctionPass(ID), MRI(nullptr) {
51 initializeIRTranslatorPass(*PassRegistry::getPassRegistry());
54 void IRTranslator::getAnalysisUsage(AnalysisUsage &AU) const {
55 AU.addRequired<TargetPassConfig>();
56 MachineFunctionPass::getAnalysisUsage(AU);
60 unsigned IRTranslator::getOrCreateVReg(const Value &Val) {
61 unsigned &ValReg = ValToVReg[&Val];
62 // Check if this is the first time we see Val.
64 // Fill ValRegsSequence with the sequence of registers
65 // we need to concat together to produce the value.
66 assert(Val.getType()->isSized() &&
67 "Don't know how to create an empty vreg");
68 unsigned VReg = MRI->createGenericVirtualRegister(LLT{*Val.getType(), *DL});
71 if (auto CV = dyn_cast<Constant>(&Val)) {
72 bool Success = translate(*CV, VReg);
74 if (!TPC->isGlobalISelAbortEnabled()) {
75 MF->getProperties().set(
76 MachineFunctionProperties::Property::FailedISel);
79 reportTranslationError(Val, "unable to translate constant");
86 int IRTranslator::getOrCreateFrameIndex(const AllocaInst &AI) {
87 if (FrameIndices.find(&AI) != FrameIndices.end())
88 return FrameIndices[&AI];
90 unsigned ElementSize = DL->getTypeStoreSize(AI.getAllocatedType());
92 ElementSize * cast<ConstantInt>(AI.getArraySize())->getZExtValue();
94 // Always allocate at least one byte.
95 Size = std::max(Size, 1u);
97 unsigned Alignment = AI.getAlignment();
99 Alignment = DL->getABITypeAlignment(AI.getAllocatedType());
101 int &FI = FrameIndices[&AI];
102 FI = MF->getFrameInfo().CreateStackObject(Size, Alignment, false, &AI);
106 unsigned IRTranslator::getMemOpAlignment(const Instruction &I) {
107 unsigned Alignment = 0;
108 Type *ValTy = nullptr;
109 if (const StoreInst *SI = dyn_cast<StoreInst>(&I)) {
110 Alignment = SI->getAlignment();
111 ValTy = SI->getValueOperand()->getType();
112 } else if (const LoadInst *LI = dyn_cast<LoadInst>(&I)) {
113 Alignment = LI->getAlignment();
114 ValTy = LI->getType();
115 } else if (!TPC->isGlobalISelAbortEnabled()) {
116 MF->getProperties().set(
117 MachineFunctionProperties::Property::FailedISel);
120 llvm_unreachable("unhandled memory instruction");
122 return Alignment ? Alignment : DL->getABITypeAlignment(ValTy);
125 MachineBasicBlock &IRTranslator::getOrCreateBB(const BasicBlock &BB) {
126 MachineBasicBlock *&MBB = BBToMBB[&BB];
128 MBB = MF->CreateMachineBasicBlock(&BB);
131 if (BB.hasAddressTaken())
132 MBB->setHasAddressTaken();
137 bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U,
138 MachineIRBuilder &MIRBuilder) {
139 // FIXME: handle signed/unsigned wrapping flags.
141 // Get or create a virtual register for each value.
142 // Unless the value is a Constant => loadimm cst?
143 // or inline constant each time?
144 // Creation of a virtual register needs to have a size.
145 unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
146 unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
147 unsigned Res = getOrCreateVReg(U);
148 MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op0).addUse(Op1);
152 bool IRTranslator::translateCompare(const User &U,
153 MachineIRBuilder &MIRBuilder) {
154 const CmpInst *CI = dyn_cast<CmpInst>(&U);
155 unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
156 unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
157 unsigned Res = getOrCreateVReg(U);
158 CmpInst::Predicate Pred =
159 CI ? CI->getPredicate() : static_cast<CmpInst::Predicate>(
160 cast<ConstantExpr>(U).getPredicate());
162 if (CmpInst::isIntPredicate(Pred))
163 MIRBuilder.buildICmp(Pred, Res, Op0, Op1);
165 MIRBuilder.buildFCmp(Pred, Res, Op0, Op1);
170 bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
171 const ReturnInst &RI = cast<ReturnInst>(U);
172 const Value *Ret = RI.getReturnValue();
173 // The target may mess up with the insertion point, but
174 // this is not important as a return is the last instruction
175 // of the block anyway.
176 return CLI->lowerReturn(MIRBuilder, Ret, !Ret ? 0 : getOrCreateVReg(*Ret));
179 bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
180 const BranchInst &BrInst = cast<BranchInst>(U);
182 if (!BrInst.isUnconditional()) {
183 // We want a G_BRCOND to the true BB followed by an unconditional branch.
184 unsigned Tst = getOrCreateVReg(*BrInst.getCondition());
185 const BasicBlock &TrueTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ++));
186 MachineBasicBlock &TrueBB = getOrCreateBB(TrueTgt);
187 MIRBuilder.buildBrCond(Tst, TrueBB);
190 const BasicBlock &BrTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ));
191 MachineBasicBlock &TgtBB = getOrCreateBB(BrTgt);
192 MIRBuilder.buildBr(TgtBB);
195 MachineBasicBlock &CurBB = MIRBuilder.getMBB();
196 for (const BasicBlock *Succ : BrInst.successors())
197 CurBB.addSuccessor(&getOrCreateBB(*Succ));
201 bool IRTranslator::translateSwitch(const User &U,
202 MachineIRBuilder &MIRBuilder) {
203 // For now, just translate as a chain of conditional branches.
204 // FIXME: could we share most of the logic/code in
205 // SelectionDAGBuilder::visitSwitch between SelectionDAG and GlobalISel?
206 // At first sight, it seems most of the logic in there is independent of
207 // SelectionDAG-specifics and a lot of work went in to optimize switch
208 // lowering in there.
210 const SwitchInst &SwInst = cast<SwitchInst>(U);
211 const unsigned SwCondValue = getOrCreateVReg(*SwInst.getCondition());
213 LLT LLTi1 = LLT(*Type::getInt1Ty(U.getContext()), *DL);
214 for (auto &CaseIt : SwInst.cases()) {
215 const unsigned CaseValueReg = getOrCreateVReg(*CaseIt.getCaseValue());
216 const unsigned Tst = MRI->createGenericVirtualRegister(LLTi1);
217 MIRBuilder.buildICmp(CmpInst::ICMP_EQ, Tst, CaseValueReg, SwCondValue);
218 MachineBasicBlock &CurBB = MIRBuilder.getMBB();
219 MachineBasicBlock &TrueBB = getOrCreateBB(*CaseIt.getCaseSuccessor());
221 MIRBuilder.buildBrCond(Tst, TrueBB);
222 CurBB.addSuccessor(&TrueBB);
224 MachineBasicBlock *FalseBB =
225 MF->CreateMachineBasicBlock(SwInst.getParent());
226 MF->push_back(FalseBB);
227 MIRBuilder.buildBr(*FalseBB);
228 CurBB.addSuccessor(FalseBB);
230 MIRBuilder.setMBB(*FalseBB);
232 // handle default case
233 MachineBasicBlock &DefaultBB = getOrCreateBB(*SwInst.getDefaultDest());
234 MIRBuilder.buildBr(DefaultBB);
235 MIRBuilder.getMBB().addSuccessor(&DefaultBB);
240 bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
241 const LoadInst &LI = cast<LoadInst>(U);
243 if (!TPC->isGlobalISelAbortEnabled() && LI.isAtomic())
246 assert(!LI.isAtomic() && "only non-atomic loads are supported at the moment");
247 auto Flags = LI.isVolatile() ? MachineMemOperand::MOVolatile
248 : MachineMemOperand::MONone;
249 Flags |= MachineMemOperand::MOLoad;
251 unsigned Res = getOrCreateVReg(LI);
252 unsigned Addr = getOrCreateVReg(*LI.getPointerOperand());
253 LLT VTy{*LI.getType(), *DL}, PTy{*LI.getPointerOperand()->getType(), *DL};
254 MIRBuilder.buildLoad(
256 *MF->getMachineMemOperand(MachinePointerInfo(LI.getPointerOperand()),
257 Flags, DL->getTypeStoreSize(LI.getType()),
258 getMemOpAlignment(LI)));
262 bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
263 const StoreInst &SI = cast<StoreInst>(U);
265 if (!TPC->isGlobalISelAbortEnabled() && SI.isAtomic())
268 assert(!SI.isAtomic() && "only non-atomic stores supported at the moment");
269 auto Flags = SI.isVolatile() ? MachineMemOperand::MOVolatile
270 : MachineMemOperand::MONone;
271 Flags |= MachineMemOperand::MOStore;
273 unsigned Val = getOrCreateVReg(*SI.getValueOperand());
274 unsigned Addr = getOrCreateVReg(*SI.getPointerOperand());
275 LLT VTy{*SI.getValueOperand()->getType(), *DL},
276 PTy{*SI.getPointerOperand()->getType(), *DL};
278 MIRBuilder.buildStore(
280 *MF->getMachineMemOperand(
281 MachinePointerInfo(SI.getPointerOperand()), Flags,
282 DL->getTypeStoreSize(SI.getValueOperand()->getType()),
283 getMemOpAlignment(SI)));
287 bool IRTranslator::translateExtractValue(const User &U,
288 MachineIRBuilder &MIRBuilder) {
289 const Value *Src = U.getOperand(0);
290 Type *Int32Ty = Type::getInt32Ty(U.getContext());
291 SmallVector<Value *, 1> Indices;
293 // getIndexedOffsetInType is designed for GEPs, so the first index is the
294 // usual array element rather than looking into the actual aggregate.
295 Indices.push_back(ConstantInt::get(Int32Ty, 0));
297 if (const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(&U)) {
298 for (auto Idx : EVI->indices())
299 Indices.push_back(ConstantInt::get(Int32Ty, Idx));
301 for (unsigned i = 1; i < U.getNumOperands(); ++i)
302 Indices.push_back(U.getOperand(i));
305 uint64_t Offset = 8 * DL->getIndexedOffsetInType(Src->getType(), Indices);
307 unsigned Res = getOrCreateVReg(U);
308 MIRBuilder.buildExtract(Res, Offset, getOrCreateVReg(*Src));
313 bool IRTranslator::translateInsertValue(const User &U,
314 MachineIRBuilder &MIRBuilder) {
315 const Value *Src = U.getOperand(0);
316 Type *Int32Ty = Type::getInt32Ty(U.getContext());
317 SmallVector<Value *, 1> Indices;
319 // getIndexedOffsetInType is designed for GEPs, so the first index is the
320 // usual array element rather than looking into the actual aggregate.
321 Indices.push_back(ConstantInt::get(Int32Ty, 0));
323 if (const InsertValueInst *IVI = dyn_cast<InsertValueInst>(&U)) {
324 for (auto Idx : IVI->indices())
325 Indices.push_back(ConstantInt::get(Int32Ty, Idx));
327 for (unsigned i = 2; i < U.getNumOperands(); ++i)
328 Indices.push_back(U.getOperand(i));
331 uint64_t Offset = 8 * DL->getIndexedOffsetInType(Src->getType(), Indices);
333 unsigned Res = getOrCreateVReg(U);
334 const Value &Inserted = *U.getOperand(1);
335 MIRBuilder.buildInsert(Res, getOrCreateVReg(*Src), getOrCreateVReg(Inserted),
341 bool IRTranslator::translateSelect(const User &U,
342 MachineIRBuilder &MIRBuilder) {
343 MIRBuilder.buildSelect(getOrCreateVReg(U), getOrCreateVReg(*U.getOperand(0)),
344 getOrCreateVReg(*U.getOperand(1)),
345 getOrCreateVReg(*U.getOperand(2)));
349 bool IRTranslator::translateBitCast(const User &U,
350 MachineIRBuilder &MIRBuilder) {
351 if (LLT{*U.getOperand(0)->getType(), *DL} == LLT{*U.getType(), *DL}) {
352 unsigned &Reg = ValToVReg[&U];
354 MIRBuilder.buildCopy(Reg, getOrCreateVReg(*U.getOperand(0)));
356 Reg = getOrCreateVReg(*U.getOperand(0));
359 return translateCast(TargetOpcode::G_BITCAST, U, MIRBuilder);
362 bool IRTranslator::translateCast(unsigned Opcode, const User &U,
363 MachineIRBuilder &MIRBuilder) {
364 unsigned Op = getOrCreateVReg(*U.getOperand(0));
365 unsigned Res = getOrCreateVReg(U);
366 MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op);
370 bool IRTranslator::translateGetElementPtr(const User &U,
371 MachineIRBuilder &MIRBuilder) {
372 // FIXME: support vector GEPs.
373 if (U.getType()->isVectorTy())
376 Value &Op0 = *U.getOperand(0);
377 unsigned BaseReg = getOrCreateVReg(Op0);
378 LLT PtrTy{*Op0.getType(), *DL};
379 unsigned PtrSize = DL->getPointerSizeInBits(PtrTy.getAddressSpace());
380 LLT OffsetTy = LLT::scalar(PtrSize);
383 for (gep_type_iterator GTI = gep_type_begin(&U), E = gep_type_end(&U);
385 const Value *Idx = GTI.getOperand();
386 if (StructType *StTy = GTI.getStructTypeOrNull()) {
387 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
388 Offset += DL->getStructLayout(StTy)->getElementOffset(Field);
391 uint64_t ElementSize = DL->getTypeAllocSize(GTI.getIndexedType());
393 // If this is a scalar constant or a splat vector of constants,
394 // handle it quickly.
395 if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
396 Offset += ElementSize * CI->getSExtValue();
401 unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
402 unsigned OffsetReg = MRI->createGenericVirtualRegister(OffsetTy);
403 MIRBuilder.buildConstant(OffsetReg, Offset);
404 MIRBuilder.buildGEP(NewBaseReg, BaseReg, OffsetReg);
406 BaseReg = NewBaseReg;
410 // N = N + Idx * ElementSize;
411 unsigned ElementSizeReg = MRI->createGenericVirtualRegister(OffsetTy);
412 MIRBuilder.buildConstant(ElementSizeReg, ElementSize);
414 unsigned IdxReg = getOrCreateVReg(*Idx);
415 if (MRI->getType(IdxReg) != OffsetTy) {
416 unsigned NewIdxReg = MRI->createGenericVirtualRegister(OffsetTy);
417 MIRBuilder.buildSExtOrTrunc(NewIdxReg, IdxReg);
421 unsigned OffsetReg = MRI->createGenericVirtualRegister(OffsetTy);
422 MIRBuilder.buildMul(OffsetReg, ElementSizeReg, IdxReg);
424 unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
425 MIRBuilder.buildGEP(NewBaseReg, BaseReg, OffsetReg);
426 BaseReg = NewBaseReg;
431 unsigned OffsetReg = MRI->createGenericVirtualRegister(OffsetTy);
432 MIRBuilder.buildConstant(OffsetReg, Offset);
433 MIRBuilder.buildGEP(getOrCreateVReg(U), BaseReg, OffsetReg);
437 MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg);
441 bool IRTranslator::translateMemcpy(const CallInst &CI,
442 MachineIRBuilder &MIRBuilder) {
443 LLT SizeTy{*CI.getArgOperand(2)->getType(), *DL};
444 if (cast<PointerType>(CI.getArgOperand(0)->getType())->getAddressSpace() !=
446 cast<PointerType>(CI.getArgOperand(1)->getType())->getAddressSpace() !=
448 SizeTy.getSizeInBits() != DL->getPointerSizeInBits(0))
451 SmallVector<CallLowering::ArgInfo, 8> Args;
452 for (int i = 0; i < 3; ++i) {
453 const auto &Arg = CI.getArgOperand(i);
454 Args.emplace_back(getOrCreateVReg(*Arg), Arg->getType());
457 MachineOperand Callee = MachineOperand::CreateES("memcpy");
459 return CLI->lowerCall(MIRBuilder, Callee,
460 CallLowering::ArgInfo(0, CI.getType()), Args);
463 void IRTranslator::getStackGuard(unsigned DstReg,
464 MachineIRBuilder &MIRBuilder) {
465 auto MIB = MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD);
468 auto &TLI = *MF->getSubtarget().getTargetLowering();
469 Value *Global = TLI.getSDagStackGuard(*MF->getFunction()->getParent());
473 MachinePointerInfo MPInfo(Global);
474 MachineInstr::mmo_iterator MemRefs = MF->allocateMemRefsArray(1);
475 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant |
476 MachineMemOperand::MODereferenceable;
478 MF->getMachineMemOperand(MPInfo, Flags, DL->getPointerSizeInBits() / 8,
479 DL->getPointerABIAlignment());
480 MIB.setMemRefs(MemRefs, MemRefs + 1);
483 bool IRTranslator::translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
484 MachineIRBuilder &MIRBuilder) {
485 LLT Ty{*CI.getOperand(0)->getType(), *DL};
486 LLT s1 = LLT::scalar(1);
487 unsigned Width = Ty.getSizeInBits();
488 unsigned Res = MRI->createGenericVirtualRegister(Ty);
489 unsigned Overflow = MRI->createGenericVirtualRegister(s1);
490 auto MIB = MIRBuilder.buildInstr(Op)
493 .addUse(getOrCreateVReg(*CI.getOperand(0)))
494 .addUse(getOrCreateVReg(*CI.getOperand(1)));
496 if (Op == TargetOpcode::G_UADDE || Op == TargetOpcode::G_USUBE) {
497 unsigned Zero = MRI->createGenericVirtualRegister(s1);
498 EntryBuilder.buildConstant(Zero, 0);
502 MIRBuilder.buildSequence(getOrCreateVReg(CI), Res, 0, Overflow, Width);
506 bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
507 MachineIRBuilder &MIRBuilder) {
511 case Intrinsic::dbg_declare:
512 case Intrinsic::dbg_value:
513 // FIXME: these obviously need to be supported properly.
514 MF->getProperties().set(
515 MachineFunctionProperties::Property::FailedISel);
517 case Intrinsic::uadd_with_overflow:
518 return translateOverflowIntrinsic(CI, TargetOpcode::G_UADDE, MIRBuilder);
519 case Intrinsic::sadd_with_overflow:
520 return translateOverflowIntrinsic(CI, TargetOpcode::G_SADDO, MIRBuilder);
521 case Intrinsic::usub_with_overflow:
522 return translateOverflowIntrinsic(CI, TargetOpcode::G_USUBE, MIRBuilder);
523 case Intrinsic::ssub_with_overflow:
524 return translateOverflowIntrinsic(CI, TargetOpcode::G_SSUBO, MIRBuilder);
525 case Intrinsic::umul_with_overflow:
526 return translateOverflowIntrinsic(CI, TargetOpcode::G_UMULO, MIRBuilder);
527 case Intrinsic::smul_with_overflow:
528 return translateOverflowIntrinsic(CI, TargetOpcode::G_SMULO, MIRBuilder);
529 case Intrinsic::memcpy:
530 return translateMemcpy(CI, MIRBuilder);
531 case Intrinsic::eh_typeid_for: {
532 GlobalValue *GV = ExtractTypeInfo(CI.getArgOperand(0));
533 unsigned Reg = getOrCreateVReg(CI);
534 unsigned TypeID = MF->getTypeIDFor(GV);
535 MIRBuilder.buildConstant(Reg, TypeID);
538 case Intrinsic::objectsize: {
539 // If we don't know by now, we're never going to know.
540 const ConstantInt *Min = cast<ConstantInt>(CI.getArgOperand(1));
542 MIRBuilder.buildConstant(getOrCreateVReg(CI), Min->isZero() ? -1ULL : 0);
545 case Intrinsic::stackguard:
546 getStackGuard(getOrCreateVReg(CI), MIRBuilder);
548 case Intrinsic::stackprotector: {
549 LLT PtrTy{*CI.getArgOperand(0)->getType(), *DL};
550 unsigned GuardVal = MRI->createGenericVirtualRegister(PtrTy);
551 getStackGuard(GuardVal, MIRBuilder);
553 AllocaInst *Slot = cast<AllocaInst>(CI.getArgOperand(1));
554 MIRBuilder.buildStore(
555 GuardVal, getOrCreateVReg(*Slot),
556 *MF->getMachineMemOperand(
557 MachinePointerInfo::getFixedStack(*MF,
558 getOrCreateFrameIndex(*Slot)),
559 MachineMemOperand::MOStore | MachineMemOperand::MOVolatile,
560 PtrTy.getSizeInBits() / 8, 8));
567 bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
568 const CallInst &CI = cast<CallInst>(U);
569 auto TII = MF->getTarget().getIntrinsicInfo();
570 const Function *F = CI.getCalledFunction();
572 if (!F || !F->isIntrinsic()) {
573 unsigned Res = CI.getType()->isVoidTy() ? 0 : getOrCreateVReg(CI);
574 SmallVector<unsigned, 8> Args;
575 for (auto &Arg: CI.arg_operands())
576 Args.push_back(getOrCreateVReg(*Arg));
578 return CLI->lowerCall(MIRBuilder, CI, Res, Args, [&]() {
579 return getOrCreateVReg(*CI.getCalledValue());
583 Intrinsic::ID ID = F->getIntrinsicID();
584 if (TII && ID == Intrinsic::not_intrinsic)
585 ID = static_cast<Intrinsic::ID>(TII->getIntrinsicID(F));
587 assert(ID != Intrinsic::not_intrinsic && "unknown intrinsic");
589 if (translateKnownIntrinsic(CI, ID, MIRBuilder))
592 unsigned Res = CI.getType()->isVoidTy() ? 0 : getOrCreateVReg(CI);
593 MachineInstrBuilder MIB =
594 MIRBuilder.buildIntrinsic(ID, Res, !CI.doesNotAccessMemory());
596 for (auto &Arg : CI.arg_operands()) {
597 if (ConstantInt *CI = dyn_cast<ConstantInt>(Arg))
598 MIB.addImm(CI->getSExtValue());
600 MIB.addUse(getOrCreateVReg(*Arg));
605 bool IRTranslator::translateInvoke(const User &U,
606 MachineIRBuilder &MIRBuilder) {
607 const InvokeInst &I = cast<InvokeInst>(U);
608 MCContext &Context = MF->getContext();
610 const BasicBlock *ReturnBB = I.getSuccessor(0);
611 const BasicBlock *EHPadBB = I.getSuccessor(1);
613 const Value *Callee(I.getCalledValue());
614 const Function *Fn = dyn_cast<Function>(Callee);
615 if (isa<InlineAsm>(Callee))
618 // FIXME: support invoking patchpoint and statepoint intrinsics.
619 if (Fn && Fn->isIntrinsic())
622 // FIXME: support whatever these are.
623 if (I.countOperandBundlesOfType(LLVMContext::OB_deopt))
626 // FIXME: support Windows exception handling.
627 if (!isa<LandingPadInst>(EHPadBB->front()))
631 // Emit the actual call, bracketed by EH_LABELs so that the MF knows about
632 // the region covered by the try.
633 MCSymbol *BeginSymbol = Context.createTempSymbol();
634 MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(BeginSymbol);
636 unsigned Res = I.getType()->isVoidTy() ? 0 : getOrCreateVReg(I);
637 SmallVector<CallLowering::ArgInfo, 8> Args;
638 for (auto &Arg: I.arg_operands())
639 Args.emplace_back(getOrCreateVReg(*Arg), Arg->getType());
641 if (!CLI->lowerCall(MIRBuilder, MachineOperand::CreateGA(Fn, 0),
642 CallLowering::ArgInfo(Res, I.getType()), Args))
645 MCSymbol *EndSymbol = Context.createTempSymbol();
646 MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(EndSymbol);
648 // FIXME: track probabilities.
649 MachineBasicBlock &EHPadMBB = getOrCreateBB(*EHPadBB),
650 &ReturnMBB = getOrCreateBB(*ReturnBB);
651 MF->addInvoke(&EHPadMBB, BeginSymbol, EndSymbol);
652 MIRBuilder.getMBB().addSuccessor(&ReturnMBB);
653 MIRBuilder.getMBB().addSuccessor(&EHPadMBB);
658 bool IRTranslator::translateLandingPad(const User &U,
659 MachineIRBuilder &MIRBuilder) {
660 const LandingPadInst &LP = cast<LandingPadInst>(U);
662 MachineBasicBlock &MBB = MIRBuilder.getMBB();
663 addLandingPadInfo(LP, MBB);
667 // If there aren't registers to copy the values into (e.g., during SjLj
668 // exceptions), then don't bother.
669 auto &TLI = *MF->getSubtarget().getTargetLowering();
670 const Constant *PersonalityFn = MF->getFunction()->getPersonalityFn();
671 if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
672 TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
675 // If landingpad's return type is token type, we don't create DAG nodes
676 // for its exception pointer and selector value. The extraction of exception
677 // pointer or selector value from token type landingpads is not currently
679 if (LP.getType()->isTokenTy())
682 // Add a label to mark the beginning of the landing pad. Deletion of the
683 // landing pad can thus be detected via the MachineModuleInfo.
684 MIRBuilder.buildInstr(TargetOpcode::EH_LABEL)
685 .addSym(MF->addLandingPad(&MBB));
687 // Mark exception register as live in.
688 SmallVector<unsigned, 2> Regs;
689 SmallVector<uint64_t, 2> Offsets;
690 LLT p0 = LLT::pointer(0, DL->getPointerSizeInBits());
691 if (unsigned Reg = TLI.getExceptionPointerRegister(PersonalityFn)) {
692 unsigned VReg = MRI->createGenericVirtualRegister(p0);
693 MIRBuilder.buildCopy(VReg, Reg);
694 Regs.push_back(VReg);
695 Offsets.push_back(0);
698 if (unsigned Reg = TLI.getExceptionSelectorRegister(PersonalityFn)) {
699 unsigned VReg = MRI->createGenericVirtualRegister(p0);
700 MIRBuilder.buildCopy(VReg, Reg);
701 Regs.push_back(VReg);
702 Offsets.push_back(p0.getSizeInBits());
705 MIRBuilder.buildSequence(getOrCreateVReg(LP), Regs, Offsets);
709 bool IRTranslator::translateStaticAlloca(const AllocaInst &AI,
710 MachineIRBuilder &MIRBuilder) {
711 if (!TPC->isGlobalISelAbortEnabled() && !AI.isStaticAlloca())
714 assert(AI.isStaticAlloca() && "only handle static allocas now");
715 unsigned Res = getOrCreateVReg(AI);
716 int FI = getOrCreateFrameIndex(AI);
717 MIRBuilder.buildFrameIndex(Res, FI);
721 bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) {
722 const PHINode &PI = cast<PHINode>(U);
723 auto MIB = MIRBuilder.buildInstr(TargetOpcode::PHI);
724 MIB.addDef(getOrCreateVReg(PI));
726 PendingPHIs.emplace_back(&PI, MIB.getInstr());
730 void IRTranslator::finishPendingPhis() {
731 for (std::pair<const PHINode *, MachineInstr *> &Phi : PendingPHIs) {
732 const PHINode *PI = Phi.first;
733 MachineInstrBuilder MIB(*MF, Phi.second);
735 // All MachineBasicBlocks exist, add them to the PHI. We assume IRTranslator
736 // won't create extra control flow here, otherwise we need to find the
737 // dominating predecessor here (or perhaps force the weirder IRTranslators
738 // to provide a simple boundary).
739 for (unsigned i = 0; i < PI->getNumIncomingValues(); ++i) {
740 assert(BBToMBB[PI->getIncomingBlock(i)]->isSuccessor(MIB->getParent()) &&
741 "I appear to have misunderstood Machine PHIs");
742 MIB.addUse(getOrCreateVReg(*PI->getIncomingValue(i)));
743 MIB.addMBB(BBToMBB[PI->getIncomingBlock(i)]);
748 bool IRTranslator::translate(const Instruction &Inst) {
749 CurBuilder.setDebugLoc(Inst.getDebugLoc());
750 switch(Inst.getOpcode()) {
751 #define HANDLE_INST(NUM, OPCODE, CLASS) \
752 case Instruction::OPCODE: return translate##OPCODE(Inst, CurBuilder);
753 #include "llvm/IR/Instruction.def"
755 if (!TPC->isGlobalISelAbortEnabled())
757 llvm_unreachable("unknown opcode");
761 bool IRTranslator::translate(const Constant &C, unsigned Reg) {
762 if (auto CI = dyn_cast<ConstantInt>(&C))
763 EntryBuilder.buildConstant(Reg, *CI);
764 else if (auto CF = dyn_cast<ConstantFP>(&C))
765 EntryBuilder.buildFConstant(Reg, *CF);
766 else if (isa<UndefValue>(C))
767 EntryBuilder.buildInstr(TargetOpcode::IMPLICIT_DEF).addDef(Reg);
768 else if (isa<ConstantPointerNull>(C))
769 EntryBuilder.buildConstant(Reg, 0);
770 else if (auto GV = dyn_cast<GlobalValue>(&C))
771 EntryBuilder.buildGlobalValue(Reg, GV);
772 else if (auto CE = dyn_cast<ConstantExpr>(&C)) {
773 switch(CE->getOpcode()) {
774 #define HANDLE_INST(NUM, OPCODE, CLASS) \
775 case Instruction::OPCODE: return translate##OPCODE(*CE, EntryBuilder);
776 #include "llvm/IR/Instruction.def"
778 if (!TPC->isGlobalISelAbortEnabled())
780 llvm_unreachable("unknown opcode");
782 } else if (!TPC->isGlobalISelAbortEnabled())
785 llvm_unreachable("unhandled constant kind");
790 void IRTranslator::finalizeFunction() {
791 // Release the memory used by the different maps we
792 // needed during the translation.
795 FrameIndices.clear();
799 bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
801 const Function &F = *MF->getFunction();
804 CLI = MF->getSubtarget().getCallLowering();
805 CurBuilder.setMF(*MF);
806 EntryBuilder.setMF(*MF);
807 MRI = &MF->getRegInfo();
808 DL = &F.getParent()->getDataLayout();
809 TPC = &getAnalysis<TargetPassConfig>();
811 assert(PendingPHIs.empty() && "stale PHIs");
813 // Setup a separate basic-block for the arguments and constants, falling
814 // through to the IR-level Function's entry block.
815 MachineBasicBlock *EntryBB = MF->CreateMachineBasicBlock();
816 MF->push_back(EntryBB);
817 EntryBB->addSuccessor(&getOrCreateBB(F.front()));
818 EntryBuilder.setMBB(*EntryBB);
820 // Lower the actual args into this basic block.
821 SmallVector<unsigned, 8> VRegArgs;
822 for (const Argument &Arg: F.args())
823 VRegArgs.push_back(getOrCreateVReg(Arg));
824 bool Succeeded = CLI->lowerFormalArguments(EntryBuilder, F, VRegArgs);
826 if (!TPC->isGlobalISelAbortEnabled()) {
827 MF->getProperties().set(
828 MachineFunctionProperties::Property::FailedISel);
832 report_fatal_error("Unable to lower arguments");
835 // And translate the function!
836 for (const BasicBlock &BB: F) {
837 MachineBasicBlock &MBB = getOrCreateBB(BB);
838 // Set the insertion point of all the following translations to
839 // the end of this basic block.
840 CurBuilder.setMBB(MBB);
842 for (const Instruction &Inst: BB) {
843 Succeeded &= translate(Inst);
845 if (TPC->isGlobalISelAbortEnabled())
846 reportTranslationError(Inst, "unable to translate instruction");
847 MF->getProperties().set(
848 MachineFunctionProperties::Property::FailedISel);
857 // Now that the MachineFrameInfo has been configured, no further changes to
858 // the reserved registers are possible.
859 MRI->freezeReservedRegs(*MF);
861 // Merge the argument lowering and constants block with its single
862 // successor, the LLVM-IR entry block. We want the basic block to
864 assert(EntryBB->succ_size() == 1 &&
865 "Custom BB used for lowering should have only one successor");
866 // Get the successor of the current entry block.
867 MachineBasicBlock &NewEntryBB = **EntryBB->succ_begin();
868 assert(NewEntryBB.pred_size() == 1 &&
869 "LLVM-IR entry block has a predecessor!?");
870 // Move all the instruction from the current entry block to the
872 NewEntryBB.splice(NewEntryBB.begin(), EntryBB, EntryBB->begin(),
875 // Update the live-in information for the new entry block.
876 for (const MachineBasicBlock::RegisterMaskPair &LiveIn : EntryBB->liveins())
877 NewEntryBB.addLiveIn(LiveIn);
878 NewEntryBB.sortUniqueLiveIns();
880 // Get rid of the now empty basic block.
881 EntryBB->removeSuccessor(&NewEntryBB);
884 assert(&MF->front() == &NewEntryBB &&
885 "New entry wasn't next in the list of basic block!");