1 //===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements the InstructionSelector class.
11 //===----------------------------------------------------------------------===//
13 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
14 #include "llvm/CodeGen/GlobalISel/Utils.h"
15 #include "llvm/CodeGen/MachineBasicBlock.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineOperand.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/IR/Constants.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Target/TargetRegisterInfo.h"
29 #define DEBUG_TYPE "instructionselector"
33 InstructionSelector::MatcherState::MatcherState(unsigned MaxRenderers)
34 : Renderers(MaxRenderers, nullptr), MIs() {}
36 InstructionSelector::InstructionSelector() = default;
38 bool InstructionSelector::constrainOperandRegToRegClass(
39 MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC,
40 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,
41 const RegisterBankInfo &RBI) const {
42 MachineBasicBlock &MBB = *I.getParent();
43 MachineFunction &MF = *MBB.getParent();
44 MachineRegisterInfo &MRI = MF.getRegInfo();
47 constrainRegToClass(MRI, TII, RBI, I, I.getOperand(OpIdx).getReg(), RC);
50 bool InstructionSelector::constrainSelectedInstRegOperands(
51 MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,
52 const RegisterBankInfo &RBI) const {
53 MachineBasicBlock &MBB = *I.getParent();
54 MachineFunction &MF = *MBB.getParent();
55 MachineRegisterInfo &MRI = MF.getRegInfo();
57 for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
58 MachineOperand &MO = I.getOperand(OpI);
60 // There's nothing to be done on non-register operands.
64 DEBUG(dbgs() << "Converting operand: " << MO << '\n');
65 assert(MO.isReg() && "Unsupported non-reg operand");
67 unsigned Reg = MO.getReg();
68 // Physical registers don't need to be constrained.
69 if (TRI.isPhysicalRegister(Reg))
72 // Register operands with a value of 0 (e.g. predicate operands) don't need
77 // If the operand is a vreg, we should constrain its regclass, and only
78 // insert COPYs if that's impossible.
79 // constrainOperandRegClass does that for us.
80 MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
83 // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
86 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
87 if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
88 I.tieOperands(DefIdx, OpI);
94 bool InstructionSelector::isOperandImmEqual(
95 const MachineOperand &MO, int64_t Value,
96 const MachineRegisterInfo &MRI) const {
97 if (MO.isReg() && MO.getReg())
98 if (auto VRegVal = getConstantVRegVal(MO.getReg(), MRI))
99 return *VRegVal == Value;
103 bool InstructionSelector::isObviouslySafeToFold(MachineInstr &MI) const {
104 return !MI.mayLoadOrStore() && !MI.hasUnmodeledSideEffects() &&
105 MI.implicit_operands().begin() == MI.implicit_operands().end();