1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// \file This file implements the LegalizerHelper class to legalize
11 /// individual instructions and the LegalizeMachineIR wrapper pass for the
12 /// primary legalization.
14 //===----------------------------------------------------------------------===//
16 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
17 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define DEBUG_TYPE "legalizer"
31 LegalizerHelper::LegalizerHelper(MachineFunction &MF)
32 : MRI(MF.getRegInfo()), LI(*MF.getSubtarget().getLegalizerInfo()) {
36 LegalizerHelper::LegalizeResult
37 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
38 DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
40 auto Action = LI.getAction(MI, MRI);
41 switch (std::get<0>(Action)) {
42 case LegalizerInfo::Legal:
43 DEBUG(dbgs() << ".. Already legal\n");
45 case LegalizerInfo::Libcall:
46 DEBUG(dbgs() << ".. Convert to libcall\n");
48 case LegalizerInfo::NarrowScalar:
49 DEBUG(dbgs() << ".. Narrow scalar\n");
50 return narrowScalar(MI, std::get<1>(Action), std::get<2>(Action));
51 case LegalizerInfo::WidenScalar:
52 DEBUG(dbgs() << ".. Widen scalar\n");
53 return widenScalar(MI, std::get<1>(Action), std::get<2>(Action));
54 case LegalizerInfo::Lower:
55 DEBUG(dbgs() << ".. Lower\n");
56 return lower(MI, std::get<1>(Action), std::get<2>(Action));
57 case LegalizerInfo::FewerElements:
58 DEBUG(dbgs() << ".. Reduce number of elements\n");
59 return fewerElementsVector(MI, std::get<1>(Action), std::get<2>(Action));
60 case LegalizerInfo::Custom:
61 DEBUG(dbgs() << ".. Custom legalization\n");
62 return LI.legalizeCustom(MI, MRI, MIRBuilder) ? Legalized
65 DEBUG(dbgs() << ".. Unable to legalize\n");
66 return UnableToLegalize;
70 void LegalizerHelper::extractParts(unsigned Reg, LLT Ty, int NumParts,
71 SmallVectorImpl<unsigned> &VRegs) {
72 for (int i = 0; i < NumParts; ++i)
73 VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
74 MIRBuilder.buildUnmerge(VRegs, Reg);
77 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
79 case TargetOpcode::G_SDIV:
80 assert(Size == 32 && "Unsupported size");
81 return RTLIB::SDIV_I32;
82 case TargetOpcode::G_UDIV:
83 assert(Size == 32 && "Unsupported size");
84 return RTLIB::UDIV_I32;
85 case TargetOpcode::G_SREM:
86 assert(Size == 32 && "Unsupported size");
87 return RTLIB::SREM_I32;
88 case TargetOpcode::G_UREM:
89 assert(Size == 32 && "Unsupported size");
90 return RTLIB::UREM_I32;
91 case TargetOpcode::G_FADD:
92 assert((Size == 32 || Size == 64) && "Unsupported size");
93 return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
94 case TargetOpcode::G_FREM:
95 return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
96 case TargetOpcode::G_FPOW:
97 return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
99 llvm_unreachable("Unknown libcall function");
102 LegalizerHelper::LegalizeResult
103 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
104 const CallLowering::ArgInfo &Result,
105 ArrayRef<CallLowering::ArgInfo> Args) {
106 auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
107 auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
108 const char *Name = TLI.getLibcallName(Libcall);
110 MIRBuilder.getMF().getFrameInfo().setHasCalls(true);
111 if (!CLI.lowerCall(MIRBuilder, TLI.getLibcallCallingConv(Libcall),
112 MachineOperand::CreateES(Name), Result, Args))
113 return LegalizerHelper::UnableToLegalize;
115 return LegalizerHelper::Legalized;
118 static LegalizerHelper::LegalizeResult
119 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
121 auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
122 return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
123 {{MI.getOperand(1).getReg(), OpType},
124 {MI.getOperand(2).getReg(), OpType}});
127 LegalizerHelper::LegalizeResult
128 LegalizerHelper::libcall(MachineInstr &MI) {
129 LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
130 unsigned Size = LLTy.getSizeInBits();
131 auto &Ctx = MIRBuilder.getMF().getFunction()->getContext();
133 MIRBuilder.setInstr(MI);
135 switch (MI.getOpcode()) {
137 return UnableToLegalize;
138 case TargetOpcode::G_SDIV:
139 case TargetOpcode::G_UDIV:
140 case TargetOpcode::G_SREM:
141 case TargetOpcode::G_UREM: {
142 Type *HLTy = Type::getInt32Ty(Ctx);
143 auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
144 if (Status != Legalized)
148 case TargetOpcode::G_FADD:
149 case TargetOpcode::G_FPOW:
150 case TargetOpcode::G_FREM: {
151 Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
152 auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
153 if (Status != Legalized)
159 MI.eraseFromParent();
163 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
166 // FIXME: Don't know how to handle secondary types yet.
167 if (TypeIdx != 0 && MI.getOpcode() != TargetOpcode::G_EXTRACT)
168 return UnableToLegalize;
170 MIRBuilder.setInstr(MI);
172 switch (MI.getOpcode()) {
174 return UnableToLegalize;
175 case TargetOpcode::G_IMPLICIT_DEF: {
176 int NumParts = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() /
177 NarrowTy.getSizeInBits();
179 SmallVector<unsigned, 2> DstRegs;
180 for (int i = 0; i < NumParts; ++i) {
181 unsigned Dst = MRI.createGenericVirtualRegister(NarrowTy);
182 MIRBuilder.buildUndef(Dst);
183 DstRegs.push_back(Dst);
185 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
186 MI.eraseFromParent();
189 case TargetOpcode::G_ADD: {
190 // Expand in terms of carry-setting/consuming G_ADDE instructions.
191 int NumParts = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() /
192 NarrowTy.getSizeInBits();
194 SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
195 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
196 extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
198 unsigned CarryIn = MRI.createGenericVirtualRegister(LLT::scalar(1));
199 MIRBuilder.buildConstant(CarryIn, 0);
201 for (int i = 0; i < NumParts; ++i) {
202 unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
203 unsigned CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
205 MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
206 Src2Regs[i], CarryIn);
208 DstRegs.push_back(DstReg);
211 unsigned DstReg = MI.getOperand(0).getReg();
212 MIRBuilder.buildMerge(DstReg, DstRegs);
213 MI.eraseFromParent();
216 case TargetOpcode::G_EXTRACT: {
218 return UnableToLegalize;
220 int64_t NarrowSize = NarrowTy.getSizeInBits();
222 MRI.getType(MI.getOperand(1).getReg()).getSizeInBits() / NarrowSize;
224 SmallVector<unsigned, 2> SrcRegs, DstRegs;
225 SmallVector<uint64_t, 2> Indexes;
226 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
228 unsigned OpReg = MI.getOperand(0).getReg();
229 int64_t OpStart = MI.getOperand(2).getImm();
230 int64_t OpSize = MRI.getType(OpReg).getSizeInBits();
231 for (int i = 0; i < NumParts; ++i) {
232 unsigned SrcStart = i * NarrowSize;
234 if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
235 // No part of the extract uses this subregister, ignore it.
237 } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
238 // The entire subregister is extracted, forward the value.
239 DstRegs.push_back(SrcRegs[i]);
243 // OpSegStart is where this destination segment would start in OpReg if it
244 // extended infinitely in both directions.
245 int64_t ExtractOffset, SegSize;
246 if (OpStart < SrcStart) {
248 SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
250 ExtractOffset = OpStart - SrcStart;
251 SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
254 unsigned SegReg = SrcRegs[i];
255 if (ExtractOffset != 0 || SegSize != NarrowSize) {
256 // A genuine extract is needed.
257 SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
258 MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
261 DstRegs.push_back(SegReg);
264 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
265 MI.eraseFromParent();
268 case TargetOpcode::G_INSERT: {
270 return UnableToLegalize;
272 int64_t NarrowSize = NarrowTy.getSizeInBits();
274 MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
276 SmallVector<unsigned, 2> SrcRegs, DstRegs;
277 SmallVector<uint64_t, 2> Indexes;
278 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
280 unsigned OpReg = MI.getOperand(2).getReg();
281 int64_t OpStart = MI.getOperand(3).getImm();
282 int64_t OpSize = MRI.getType(OpReg).getSizeInBits();
283 for (int i = 0; i < NumParts; ++i) {
284 unsigned DstStart = i * NarrowSize;
286 if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
287 // No part of the insert affects this subregister, forward the original.
288 DstRegs.push_back(SrcRegs[i]);
290 } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
291 // The entire subregister is defined by this insert, forward the new
293 DstRegs.push_back(OpReg);
297 // OpSegStart is where this destination segment would start in OpReg if it
298 // extended infinitely in both directions.
299 int64_t ExtractOffset, InsertOffset, SegSize;
300 if (OpStart < DstStart) {
302 ExtractOffset = DstStart - OpStart;
303 SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
305 InsertOffset = OpStart - DstStart;
308 std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
311 unsigned SegReg = OpReg;
312 if (ExtractOffset != 0 || SegSize != OpSize) {
313 // A genuine extract is needed.
314 SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
315 MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
318 unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
319 MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
320 DstRegs.push_back(DstReg);
323 assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
324 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
325 MI.eraseFromParent();
328 case TargetOpcode::G_LOAD: {
329 unsigned NarrowSize = NarrowTy.getSizeInBits();
331 MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
332 LLT OffsetTy = LLT::scalar(
333 MRI.getType(MI.getOperand(1).getReg()).getScalarSizeInBits());
335 SmallVector<unsigned, 2> DstRegs;
336 for (int i = 0; i < NumParts; ++i) {
337 unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
339 unsigned Adjustment = i * NarrowSize / 8;
341 MIRBuilder.materializeGEP(SrcReg, MI.getOperand(1).getReg(), OffsetTy,
344 // TODO: This is conservatively correct, but we probably want to split the
345 // memory operands in the future.
346 MIRBuilder.buildLoad(DstReg, SrcReg, **MI.memoperands_begin());
348 DstRegs.push_back(DstReg);
350 unsigned DstReg = MI.getOperand(0).getReg();
351 MIRBuilder.buildMerge(DstReg, DstRegs);
352 MI.eraseFromParent();
355 case TargetOpcode::G_STORE: {
356 unsigned NarrowSize = NarrowTy.getSizeInBits();
358 MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
359 LLT OffsetTy = LLT::scalar(
360 MRI.getType(MI.getOperand(1).getReg()).getScalarSizeInBits());
362 SmallVector<unsigned, 2> SrcRegs;
363 extractParts(MI.getOperand(0).getReg(), NarrowTy, NumParts, SrcRegs);
365 for (int i = 0; i < NumParts; ++i) {
367 unsigned Adjustment = i * NarrowSize / 8;
369 MIRBuilder.materializeGEP(DstReg, MI.getOperand(1).getReg(), OffsetTy,
372 // TODO: This is conservatively correct, but we probably want to split the
373 // memory operands in the future.
374 MIRBuilder.buildStore(SrcRegs[i], DstReg, **MI.memoperands_begin());
376 MI.eraseFromParent();
379 case TargetOpcode::G_CONSTANT: {
380 unsigned NarrowSize = NarrowTy.getSizeInBits();
382 MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
383 const APInt &Cst = MI.getOperand(1).getCImm()->getValue();
384 LLVMContext &Ctx = MIRBuilder.getMF().getFunction()->getContext();
386 SmallVector<unsigned, 2> DstRegs;
387 for (int i = 0; i < NumParts; ++i) {
388 unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
390 ConstantInt::get(Ctx, Cst.lshr(NarrowSize * i).trunc(NarrowSize));
391 MIRBuilder.buildConstant(DstReg, *CI);
392 DstRegs.push_back(DstReg);
394 unsigned DstReg = MI.getOperand(0).getReg();
395 MIRBuilder.buildMerge(DstReg, DstRegs);
396 MI.eraseFromParent();
402 LegalizerHelper::LegalizeResult
403 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
404 MIRBuilder.setInstr(MI);
406 switch (MI.getOpcode()) {
408 return UnableToLegalize;
409 case TargetOpcode::G_ADD:
410 case TargetOpcode::G_AND:
411 case TargetOpcode::G_MUL:
412 case TargetOpcode::G_OR:
413 case TargetOpcode::G_XOR:
414 case TargetOpcode::G_SUB:
415 case TargetOpcode::G_SHL: {
416 // Perform operation at larger width (any extension is fine here, high bits
417 // don't affect the result) and then truncate the result back to the
419 unsigned Src1Ext = MRI.createGenericVirtualRegister(WideTy);
420 unsigned Src2Ext = MRI.createGenericVirtualRegister(WideTy);
421 MIRBuilder.buildAnyExt(Src1Ext, MI.getOperand(1).getReg());
422 MIRBuilder.buildAnyExt(Src2Ext, MI.getOperand(2).getReg());
424 unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
425 MIRBuilder.buildInstr(MI.getOpcode())
430 MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
431 MI.eraseFromParent();
434 case TargetOpcode::G_SDIV:
435 case TargetOpcode::G_UDIV:
436 case TargetOpcode::G_SREM:
437 case TargetOpcode::G_UREM:
438 case TargetOpcode::G_ASHR:
439 case TargetOpcode::G_LSHR: {
440 unsigned ExtOp = MI.getOpcode() == TargetOpcode::G_SDIV ||
441 MI.getOpcode() == TargetOpcode::G_SREM ||
442 MI.getOpcode() == TargetOpcode::G_ASHR
443 ? TargetOpcode::G_SEXT
444 : TargetOpcode::G_ZEXT;
446 unsigned LHSExt = MRI.createGenericVirtualRegister(WideTy);
447 MIRBuilder.buildInstr(ExtOp).addDef(LHSExt).addUse(
448 MI.getOperand(1).getReg());
450 unsigned RHSExt = MRI.createGenericVirtualRegister(WideTy);
451 MIRBuilder.buildInstr(ExtOp).addDef(RHSExt).addUse(
452 MI.getOperand(2).getReg());
454 unsigned ResExt = MRI.createGenericVirtualRegister(WideTy);
455 MIRBuilder.buildInstr(MI.getOpcode())
460 MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), ResExt);
461 MI.eraseFromParent();
464 case TargetOpcode::G_SELECT: {
466 return UnableToLegalize;
468 // Perform operation at larger width (any extension is fine here, high bits
469 // don't affect the result) and then truncate the result back to the
471 unsigned Src1Ext = MRI.createGenericVirtualRegister(WideTy);
472 unsigned Src2Ext = MRI.createGenericVirtualRegister(WideTy);
473 MIRBuilder.buildAnyExt(Src1Ext, MI.getOperand(2).getReg());
474 MIRBuilder.buildAnyExt(Src2Ext, MI.getOperand(3).getReg());
476 unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
477 MIRBuilder.buildInstr(TargetOpcode::G_SELECT)
479 .addReg(MI.getOperand(1).getReg())
483 MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
484 MI.eraseFromParent();
487 case TargetOpcode::G_FPTOSI:
488 case TargetOpcode::G_FPTOUI: {
490 return UnableToLegalize;
492 unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
493 MIRBuilder.buildInstr(MI.getOpcode())
495 .addUse(MI.getOperand(1).getReg());
497 MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
498 MI.eraseFromParent();
501 case TargetOpcode::G_SITOFP:
502 case TargetOpcode::G_UITOFP: {
504 return UnableToLegalize;
506 unsigned Src = MI.getOperand(1).getReg();
507 unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
509 if (MI.getOpcode() == TargetOpcode::G_SITOFP) {
510 MIRBuilder.buildSExt(SrcExt, Src);
512 assert(MI.getOpcode() == TargetOpcode::G_UITOFP && "Unexpected conv op");
513 MIRBuilder.buildZExt(SrcExt, Src);
516 MIRBuilder.buildInstr(MI.getOpcode())
517 .addDef(MI.getOperand(0).getReg())
520 MI.eraseFromParent();
523 case TargetOpcode::G_INSERT: {
525 return UnableToLegalize;
527 unsigned Src = MI.getOperand(1).getReg();
528 unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
529 MIRBuilder.buildAnyExt(SrcExt, Src);
531 unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
532 auto MIB = MIRBuilder.buildInsert(DstExt, SrcExt, MI.getOperand(2).getReg(),
533 MI.getOperand(3).getImm());
534 for (unsigned OpNum = 4; OpNum < MI.getNumOperands(); OpNum += 2) {
535 MIB.addReg(MI.getOperand(OpNum).getReg());
536 MIB.addImm(MI.getOperand(OpNum + 1).getImm());
539 MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
540 MI.eraseFromParent();
543 case TargetOpcode::G_LOAD: {
544 assert(alignTo(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(), 8) ==
545 WideTy.getSizeInBits() &&
546 "illegal to increase number of bytes loaded");
548 unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
549 MIRBuilder.buildLoad(DstExt, MI.getOperand(1).getReg(),
550 **MI.memoperands_begin());
551 MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
552 MI.eraseFromParent();
555 case TargetOpcode::G_STORE: {
556 if (MRI.getType(MI.getOperand(0).getReg()) != LLT::scalar(1) ||
557 WideTy != LLT::scalar(8))
558 return UnableToLegalize;
560 auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
561 auto Content = TLI.getBooleanContents(false, false);
563 unsigned ExtOp = TargetOpcode::G_ANYEXT;
564 if (Content == TargetLoweringBase::ZeroOrOneBooleanContent)
565 ExtOp = TargetOpcode::G_ZEXT;
566 else if (Content == TargetLoweringBase::ZeroOrNegativeOneBooleanContent)
567 ExtOp = TargetOpcode::G_SEXT;
569 ExtOp = TargetOpcode::G_ANYEXT;
571 unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
572 MIRBuilder.buildInstr(ExtOp).addDef(SrcExt).addUse(
573 MI.getOperand(0).getReg());
574 MIRBuilder.buildStore(SrcExt, MI.getOperand(1).getReg(),
575 **MI.memoperands_begin());
576 MI.eraseFromParent();
579 case TargetOpcode::G_CONSTANT: {
580 unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
581 MIRBuilder.buildConstant(DstExt, *MI.getOperand(1).getCImm());
582 MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
583 MI.eraseFromParent();
586 case TargetOpcode::G_FCONSTANT: {
587 unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
588 MIRBuilder.buildFConstant(DstExt, *MI.getOperand(1).getFPImm());
589 MIRBuilder.buildFPTrunc(MI.getOperand(0).getReg(), DstExt);
590 MI.eraseFromParent();
593 case TargetOpcode::G_BRCOND: {
594 unsigned TstExt = MRI.createGenericVirtualRegister(WideTy);
595 MIRBuilder.buildAnyExt(TstExt, MI.getOperand(0).getReg());
596 MIRBuilder.buildBrCond(TstExt, *MI.getOperand(1).getMBB());
597 MI.eraseFromParent();
600 case TargetOpcode::G_ICMP: {
601 assert(TypeIdx == 1 && "unable to legalize predicate");
602 bool IsSigned = CmpInst::isSigned(
603 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()));
604 unsigned Op0Ext = MRI.createGenericVirtualRegister(WideTy);
605 unsigned Op1Ext = MRI.createGenericVirtualRegister(WideTy);
607 MIRBuilder.buildSExt(Op0Ext, MI.getOperand(2).getReg());
608 MIRBuilder.buildSExt(Op1Ext, MI.getOperand(3).getReg());
610 MIRBuilder.buildZExt(Op0Ext, MI.getOperand(2).getReg());
611 MIRBuilder.buildZExt(Op1Ext, MI.getOperand(3).getReg());
613 MIRBuilder.buildICmp(
614 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()),
615 MI.getOperand(0).getReg(), Op0Ext, Op1Ext);
616 MI.eraseFromParent();
619 case TargetOpcode::G_GEP: {
620 assert(TypeIdx == 1 && "unable to legalize pointer of GEP");
621 unsigned OffsetExt = MRI.createGenericVirtualRegister(WideTy);
622 MIRBuilder.buildSExt(OffsetExt, MI.getOperand(2).getReg());
623 MI.getOperand(2).setReg(OffsetExt);
629 LegalizerHelper::LegalizeResult
630 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
631 using namespace TargetOpcode;
632 MIRBuilder.setInstr(MI);
634 switch(MI.getOpcode()) {
636 return UnableToLegalize;
637 case TargetOpcode::G_SREM:
638 case TargetOpcode::G_UREM: {
639 unsigned QuotReg = MRI.createGenericVirtualRegister(Ty);
640 MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
642 .addUse(MI.getOperand(1).getReg())
643 .addUse(MI.getOperand(2).getReg());
645 unsigned ProdReg = MRI.createGenericVirtualRegister(Ty);
646 MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
647 MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
649 MI.eraseFromParent();
652 case TargetOpcode::G_SMULO:
653 case TargetOpcode::G_UMULO: {
654 // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
656 unsigned Res = MI.getOperand(0).getReg();
657 unsigned Overflow = MI.getOperand(1).getReg();
658 unsigned LHS = MI.getOperand(2).getReg();
659 unsigned RHS = MI.getOperand(3).getReg();
661 MIRBuilder.buildMul(Res, LHS, RHS);
663 unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
664 ? TargetOpcode::G_SMULH
665 : TargetOpcode::G_UMULH;
667 unsigned HiPart = MRI.createGenericVirtualRegister(Ty);
668 MIRBuilder.buildInstr(Opcode)
673 unsigned Zero = MRI.createGenericVirtualRegister(Ty);
674 MIRBuilder.buildConstant(Zero, 0);
675 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
676 MI.eraseFromParent();
679 case TargetOpcode::G_FNEG: {
680 // TODO: Handle vector types once we are able to
683 return UnableToLegalize;
684 unsigned Res = MI.getOperand(0).getReg();
686 LLVMContext &Ctx = MIRBuilder.getMF().getFunction()->getContext();
687 switch (Ty.getSizeInBits()) {
689 ZeroTy = Type::getHalfTy(Ctx);
692 ZeroTy = Type::getFloatTy(Ctx);
695 ZeroTy = Type::getDoubleTy(Ctx);
698 llvm_unreachable("unexpected floating-point type");
700 ConstantFP &ZeroForNegation =
701 *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
702 unsigned Zero = MRI.createGenericVirtualRegister(Ty);
703 MIRBuilder.buildFConstant(Zero, ZeroForNegation);
704 MIRBuilder.buildInstr(TargetOpcode::G_FSUB)
707 .addUse(MI.getOperand(1).getReg());
708 MI.eraseFromParent();
711 case TargetOpcode::G_FSUB: {
712 // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
713 // First, check if G_FNEG is marked as Lower. If so, we may
714 // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
715 if (LI.getAction({G_FNEG, Ty}).first == LegalizerInfo::Lower)
716 return UnableToLegalize;
717 unsigned Res = MI.getOperand(0).getReg();
718 unsigned LHS = MI.getOperand(1).getReg();
719 unsigned RHS = MI.getOperand(2).getReg();
720 unsigned Neg = MRI.createGenericVirtualRegister(Ty);
721 MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
722 MIRBuilder.buildInstr(TargetOpcode::G_FADD)
726 MI.eraseFromParent();
732 LegalizerHelper::LegalizeResult
733 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
735 // FIXME: Don't know how to handle secondary types yet.
737 return UnableToLegalize;
738 switch (MI.getOpcode()) {
740 return UnableToLegalize;
741 case TargetOpcode::G_ADD: {
742 unsigned NarrowSize = NarrowTy.getSizeInBits();
743 unsigned DstReg = MI.getOperand(0).getReg();
744 int NumParts = MRI.getType(DstReg).getSizeInBits() / NarrowSize;
746 MIRBuilder.setInstr(MI);
748 SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
749 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
750 extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
752 for (int i = 0; i < NumParts; ++i) {
753 unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
754 MIRBuilder.buildAdd(DstReg, Src1Regs[i], Src2Regs[i]);
755 DstRegs.push_back(DstReg);
758 MIRBuilder.buildMerge(DstReg, DstRegs);
759 MI.eraseFromParent();