1 //===- llvm/CodeGen/GlobalISel/RegisterBank.cpp - Register Bank --*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements the RegisterBank class.
11 //===----------------------------------------------------------------------===//
13 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
14 #include "llvm/Target/TargetRegisterInfo.h"
16 #define DEBUG_TYPE "registerbank"
20 const unsigned RegisterBank::InvalidID = UINT_MAX;
22 RegisterBank::RegisterBank(unsigned ID, const char *Name, unsigned Size,
23 const uint32_t *CoveredClasses)
24 : ID(ID), Name(Name), Size(Size) {
25 ContainedRegClasses.resize(200);
26 ContainedRegClasses.setBitsInMask(CoveredClasses);
29 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const {
30 assert(isValid() && "Invalid register bank");
31 for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) {
32 const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
36 // Verify that the register bank covers all the sub classes of the
39 // Use a different (slow in that case) method than
40 // RegisterBankInfo to find the subclasses of RC, to make sure
41 // both agree on the covers.
42 for (unsigned SubRCId = 0; SubRCId != End; ++SubRCId) {
43 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId);
45 if (!RC.hasSubClassEq(&SubRC))
48 // Verify that the Size of the register bank is big enough to cover
49 // all the register classes it covers.
50 assert((getSize() >= SubRC.getSize() * 8) &&
51 "Size is not big enough for all the subclasses!");
52 assert(covers(SubRC) && "Not all subclasses are covered");
58 bool RegisterBank::covers(const TargetRegisterClass &RC) const {
59 assert(isValid() && "RB hasn't been initialized yet");
60 return ContainedRegClasses.test(RC.getID());
63 bool RegisterBank::isValid() const {
64 return ID != InvalidID && Name != nullptr && Size != 0 &&
65 // A register bank that does not cover anything is useless.
66 !ContainedRegClasses.empty();
69 bool RegisterBank::operator==(const RegisterBank &OtherRB) const {
70 // There must be only one instance of a given register bank alive
71 // for the whole compilation.
72 // The RegisterBankInfo is supposed to enforce that.
73 assert((OtherRB.getID() != getID() || &OtherRB == this) &&
74 "ID does not uniquely identify a RegisterBank");
75 return &OtherRB == this;
78 LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const {
79 print(dbgs(), /* IsForDebug */ true, TRI);
82 void RegisterBank::print(raw_ostream &OS, bool IsForDebug,
83 const TargetRegisterInfo *TRI) const {
87 OS << "(ID:" << getID() << ", Size:" << getSize() << ")\n"
88 << "isValid:" << isValid() << '\n'
89 << "Number of Covered register classes: " << ContainedRegClasses.count()
91 // Print all the subclasses if we can.
92 // This register classes may not be properly initialized yet.
93 if (!TRI || ContainedRegClasses.empty())
95 assert(ContainedRegClasses.size() == TRI->getNumRegClasses() &&
96 "TRI does not match the initialization process?");
98 OS << "Covered register classes:\n";
99 for (unsigned RCId = 0, End = TRI->getNumRegClasses(); RCId != End; ++RCId) {
100 const TargetRegisterClass &RC = *TRI->getRegClass(RCId);
107 OS << TRI->getRegClassName(&RC);