1 //===- llvm/CodeGen/GlobalISel/RegisterBankInfo.cpp --------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements the RegisterBankInfo class.
11 //===----------------------------------------------------------------------===//
13 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/ADT/iterator_range.h"
18 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/TargetOpcodes.h"
23 #include "llvm/CodeGen/TargetRegisterInfo.h"
24 #include "llvm/CodeGen/TargetSubtargetInfo.h"
25 #include "llvm/IR/Type.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/raw_ostream.h"
29 #include <algorithm> // For std::max.
31 #define DEBUG_TYPE "registerbankinfo"
35 STATISTIC(NumPartialMappingsCreated,
36 "Number of partial mappings dynamically created");
37 STATISTIC(NumPartialMappingsAccessed,
38 "Number of partial mappings dynamically accessed");
39 STATISTIC(NumValueMappingsCreated,
40 "Number of value mappings dynamically created");
41 STATISTIC(NumValueMappingsAccessed,
42 "Number of value mappings dynamically accessed");
43 STATISTIC(NumOperandsMappingsCreated,
44 "Number of operands mappings dynamically created");
45 STATISTIC(NumOperandsMappingsAccessed,
46 "Number of operands mappings dynamically accessed");
47 STATISTIC(NumInstructionMappingsCreated,
48 "Number of instruction mappings dynamically created");
49 STATISTIC(NumInstructionMappingsAccessed,
50 "Number of instruction mappings dynamically accessed");
52 const unsigned RegisterBankInfo::DefaultMappingID = UINT_MAX;
53 const unsigned RegisterBankInfo::InvalidMappingID = UINT_MAX - 1;
55 //------------------------------------------------------------------------------
56 // RegisterBankInfo implementation.
57 //------------------------------------------------------------------------------
58 RegisterBankInfo::RegisterBankInfo(RegisterBank **RegBanks,
60 : RegBanks(RegBanks), NumRegBanks(NumRegBanks) {
62 for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
63 assert(RegBanks[Idx] != nullptr && "Invalid RegisterBank");
64 assert(RegBanks[Idx]->isValid() && "RegisterBank should be valid");
69 bool RegisterBankInfo::verify(const TargetRegisterInfo &TRI) const {
71 for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
72 const RegisterBank &RegBank = getRegBank(Idx);
73 assert(Idx == RegBank.getID() &&
74 "ID does not match the index in the array");
75 DEBUG(dbgs() << "Verify " << RegBank << '\n');
76 assert(RegBank.verify(TRI) && "RegBank is invalid");
83 RegisterBankInfo::getRegBank(unsigned Reg, const MachineRegisterInfo &MRI,
84 const TargetRegisterInfo &TRI) const {
85 if (TargetRegisterInfo::isPhysicalRegister(Reg))
86 return &getRegBankFromRegClass(getMinimalPhysRegClass(Reg, TRI));
88 assert(Reg && "NoRegister does not have a register bank");
89 const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
90 if (auto *RB = RegClassOrBank.dyn_cast<const RegisterBank *>())
92 if (auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>())
93 return &getRegBankFromRegClass(*RC);
97 const TargetRegisterClass &
98 RegisterBankInfo::getMinimalPhysRegClass(unsigned Reg,
99 const TargetRegisterInfo &TRI) const {
100 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
101 "Reg must be a physreg");
102 const auto &RegRCIt = PhysRegMinimalRCs.find(Reg);
103 if (RegRCIt != PhysRegMinimalRCs.end())
104 return *RegRCIt->second;
105 const TargetRegisterClass *PhysRC = TRI.getMinimalPhysRegClass(Reg);
106 PhysRegMinimalRCs[Reg] = PhysRC;
110 const RegisterBank *RegisterBankInfo::getRegBankFromConstraints(
111 const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII,
112 const TargetRegisterInfo &TRI) const {
113 // The mapping of the registers may be available via the
114 // register class constraints.
115 const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, &TRI);
120 const RegisterBank &RegBank = getRegBankFromRegClass(*RC);
121 // Sanity check that the target properly implemented getRegBankFromRegClass.
122 assert(RegBank.covers(*RC) &&
123 "The mapping of the register bank does not make sense");
127 const TargetRegisterClass *RegisterBankInfo::constrainGenericRegister(
128 unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI) {
130 // If the register already has a class, fallback to MRI::constrainRegClass.
131 auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
132 if (RegClassOrBank.is<const TargetRegisterClass *>())
133 return MRI.constrainRegClass(Reg, &RC);
135 const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
136 // Otherwise, all we can do is ensure the bank covers the class, and set it.
137 if (RB && !RB->covers(RC))
140 // If nothing was set or the class is simply compatible, set it.
141 MRI.setRegClass(Reg, &RC);
145 /// Check whether or not \p MI should be treated like a copy
146 /// for the mappings.
147 /// Copy like instruction are special for mapping because
148 /// they don't have actual register constraints. Moreover,
149 /// they sometimes have register classes assigned and we can
150 /// just use that instead of failing to provide a generic mapping.
151 static bool isCopyLike(const MachineInstr &MI) {
152 return MI.isCopy() || MI.isPHI() ||
153 MI.getOpcode() == TargetOpcode::REG_SEQUENCE;
156 const RegisterBankInfo::InstructionMapping &
157 RegisterBankInfo::getInstrMappingImpl(const MachineInstr &MI) const {
158 // For copies we want to walk over the operands and try to find one
159 // that has a register bank since the instruction itself will not get
160 // us any constraint.
161 bool IsCopyLike = isCopyLike(MI);
162 // For copy like instruction, only the mapping of the definition
163 // is important. The rest is not constrained.
164 unsigned NumOperandsForMapping = IsCopyLike ? 1 : MI.getNumOperands();
166 const MachineFunction &MF = *MI.getMF();
167 const TargetSubtargetInfo &STI = MF.getSubtarget();
168 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
169 const MachineRegisterInfo &MRI = MF.getRegInfo();
170 // We may need to query the instruction encoding to guess the mapping.
171 const TargetInstrInfo &TII = *STI.getInstrInfo();
173 // Before doing anything complicated check if the mapping is not
174 // directly available.
175 bool CompleteMapping = true;
177 SmallVector<const ValueMapping *, 8> OperandsMapping(NumOperandsForMapping);
178 for (unsigned OpIdx = 0, EndIdx = MI.getNumOperands(); OpIdx != EndIdx;
180 const MachineOperand &MO = MI.getOperand(OpIdx);
183 unsigned Reg = MO.getReg();
186 // The register bank of Reg is just a side effect of the current
187 // excution and in particular, there is no reason to believe this
188 // is the best default mapping for the current instruction. Keep
189 // it as an alternative register bank if we cannot figure out
191 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI);
192 // For copy-like instruction, we want to reuse the register bank
193 // that is already set on Reg, if any, since those instructions do
194 // not have any constraints.
195 const RegisterBank *CurRegBank = IsCopyLike ? AltRegBank : nullptr;
197 // If this is a target specific instruction, we can deduce
198 // the register bank from the encoding constraints.
199 CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, TRI);
201 // All our attempts failed, give up.
202 CompleteMapping = false;
205 // MI does not carry enough information to guess the mapping.
206 return getInvalidInstructionMapping();
210 const ValueMapping *ValMapping =
211 &getValueMapping(0, getSizeInBits(Reg, MRI, TRI), *CurRegBank);
213 OperandsMapping[0] = ValMapping;
214 CompleteMapping = true;
217 OperandsMapping[OpIdx] = ValMapping;
220 if (IsCopyLike && !CompleteMapping)
221 // No way to deduce the type from what we have.
222 return getInvalidInstructionMapping();
224 assert(CompleteMapping && "Setting an uncomplete mapping");
225 return getInstructionMapping(
226 DefaultMappingID, /*Cost*/ 1,
227 /*OperandsMapping*/ getOperandsMapping(OperandsMapping),
228 NumOperandsForMapping);
231 /// Hashing function for PartialMapping.
232 static hash_code hashPartialMapping(unsigned StartIdx, unsigned Length,
233 const RegisterBank *RegBank) {
234 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0);
237 /// Overloaded version of hash_value for a PartialMapping.
239 llvm::hash_value(const RegisterBankInfo::PartialMapping &PartMapping) {
240 return hashPartialMapping(PartMapping.StartIdx, PartMapping.Length,
241 PartMapping.RegBank);
244 const RegisterBankInfo::PartialMapping &
245 RegisterBankInfo::getPartialMapping(unsigned StartIdx, unsigned Length,
246 const RegisterBank &RegBank) const {
247 ++NumPartialMappingsAccessed;
249 hash_code Hash = hashPartialMapping(StartIdx, Length, &RegBank);
250 const auto &It = MapOfPartialMappings.find(Hash);
251 if (It != MapOfPartialMappings.end())
254 ++NumPartialMappingsCreated;
256 auto &PartMapping = MapOfPartialMappings[Hash];
257 PartMapping = llvm::make_unique<PartialMapping>(StartIdx, Length, RegBank);
261 const RegisterBankInfo::ValueMapping &
262 RegisterBankInfo::getValueMapping(unsigned StartIdx, unsigned Length,
263 const RegisterBank &RegBank) const {
264 return getValueMapping(&getPartialMapping(StartIdx, Length, RegBank), 1);
268 hashValueMapping(const RegisterBankInfo::PartialMapping *BreakDown,
269 unsigned NumBreakDowns) {
270 if (LLVM_LIKELY(NumBreakDowns == 1))
271 return hash_value(*BreakDown);
272 SmallVector<size_t, 8> Hashes(NumBreakDowns);
273 for (unsigned Idx = 0; Idx != NumBreakDowns; ++Idx)
274 Hashes.push_back(hash_value(BreakDown[Idx]));
275 return hash_combine_range(Hashes.begin(), Hashes.end());
278 const RegisterBankInfo::ValueMapping &
279 RegisterBankInfo::getValueMapping(const PartialMapping *BreakDown,
280 unsigned NumBreakDowns) const {
281 ++NumValueMappingsAccessed;
283 hash_code Hash = hashValueMapping(BreakDown, NumBreakDowns);
284 const auto &It = MapOfValueMappings.find(Hash);
285 if (It != MapOfValueMappings.end())
288 ++NumValueMappingsCreated;
290 auto &ValMapping = MapOfValueMappings[Hash];
291 ValMapping = llvm::make_unique<ValueMapping>(BreakDown, NumBreakDowns);
295 template <typename Iterator>
296 const RegisterBankInfo::ValueMapping *
297 RegisterBankInfo::getOperandsMapping(Iterator Begin, Iterator End) const {
299 ++NumOperandsMappingsAccessed;
301 // The addresses of the value mapping are unique.
302 // Therefore, we can use them directly to hash the operand mapping.
303 hash_code Hash = hash_combine_range(Begin, End);
304 auto &Res = MapOfOperandsMappings[Hash];
308 ++NumOperandsMappingsCreated;
310 // Create the array of ValueMapping.
311 // Note: this array will not hash to this instance of operands
312 // mapping, because we use the pointer of the ValueMapping
313 // to hash and we expect them to uniquely identify an instance
315 Res = llvm::make_unique<ValueMapping[]>(std::distance(Begin, End));
317 for (Iterator It = Begin; It != End; ++It, ++Idx) {
318 const ValueMapping *ValMap = *It;
326 const RegisterBankInfo::ValueMapping *RegisterBankInfo::getOperandsMapping(
327 const SmallVectorImpl<const RegisterBankInfo::ValueMapping *> &OpdsMapping)
329 return getOperandsMapping(OpdsMapping.begin(), OpdsMapping.end());
332 const RegisterBankInfo::ValueMapping *RegisterBankInfo::getOperandsMapping(
333 std::initializer_list<const RegisterBankInfo::ValueMapping *> OpdsMapping)
335 return getOperandsMapping(OpdsMapping.begin(), OpdsMapping.end());
339 hashInstructionMapping(unsigned ID, unsigned Cost,
340 const RegisterBankInfo::ValueMapping *OperandsMapping,
341 unsigned NumOperands) {
342 return hash_combine(ID, Cost, OperandsMapping, NumOperands);
345 const RegisterBankInfo::InstructionMapping &
346 RegisterBankInfo::getInstructionMappingImpl(
347 bool IsInvalid, unsigned ID, unsigned Cost,
348 const RegisterBankInfo::ValueMapping *OperandsMapping,
349 unsigned NumOperands) const {
350 assert(((IsInvalid && ID == InvalidMappingID && Cost == 0 &&
351 OperandsMapping == nullptr && NumOperands == 0) ||
353 "Mismatch argument for invalid input");
354 ++NumInstructionMappingsAccessed;
357 hashInstructionMapping(ID, Cost, OperandsMapping, NumOperands);
358 const auto &It = MapOfInstructionMappings.find(Hash);
359 if (It != MapOfInstructionMappings.end())
362 ++NumInstructionMappingsCreated;
364 auto &InstrMapping = MapOfInstructionMappings[Hash];
366 InstrMapping = llvm::make_unique<InstructionMapping>();
368 InstrMapping = llvm::make_unique<InstructionMapping>(
369 ID, Cost, OperandsMapping, NumOperands);
370 return *InstrMapping;
373 const RegisterBankInfo::InstructionMapping &
374 RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
375 const RegisterBankInfo::InstructionMapping &Mapping = getInstrMappingImpl(MI);
376 if (Mapping.isValid())
378 llvm_unreachable("The target must implement this");
381 RegisterBankInfo::InstructionMappings
382 RegisterBankInfo::getInstrPossibleMappings(const MachineInstr &MI) const {
383 InstructionMappings PossibleMappings;
384 // Put the default mapping first.
385 PossibleMappings.push_back(&getInstrMapping(MI));
386 // Then the alternative mapping, if any.
387 InstructionMappings AltMappings = getInstrAlternativeMappings(MI);
388 for (const InstructionMapping *AltMapping : AltMappings)
389 PossibleMappings.push_back(AltMapping);
391 for (const InstructionMapping *Mapping : PossibleMappings)
392 assert(Mapping->verify(MI) && "Mapping is invalid");
394 return PossibleMappings;
397 RegisterBankInfo::InstructionMappings
398 RegisterBankInfo::getInstrAlternativeMappings(const MachineInstr &MI) const {
399 // No alternative for MI.
400 return InstructionMappings();
403 void RegisterBankInfo::applyDefaultMapping(const OperandsMapper &OpdMapper) {
404 MachineInstr &MI = OpdMapper.getMI();
405 MachineRegisterInfo &MRI = OpdMapper.getMRI();
406 DEBUG(dbgs() << "Applying default-like mapping\n");
407 for (unsigned OpIdx = 0,
408 EndIdx = OpdMapper.getInstrMapping().getNumOperands();
409 OpIdx != EndIdx; ++OpIdx) {
410 DEBUG(dbgs() << "OpIdx " << OpIdx);
411 MachineOperand &MO = MI.getOperand(OpIdx);
413 DEBUG(dbgs() << " is not a register, nothing to be done\n");
417 DEBUG(dbgs() << " is %%noreg, nothing to be done\n");
420 assert(OpdMapper.getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns !=
423 assert(OpdMapper.getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns ==
425 "This mapping is too complex for this function");
426 iterator_range<SmallVectorImpl<unsigned>::const_iterator> NewRegs =
427 OpdMapper.getVRegs(OpIdx);
428 if (NewRegs.begin() == NewRegs.end()) {
429 DEBUG(dbgs() << " has not been repaired, nothing to be done\n");
432 unsigned OrigReg = MO.getReg();
433 unsigned NewReg = *NewRegs.begin();
434 DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr));
436 DEBUG(dbgs() << " with " << printReg(NewReg, nullptr));
438 // The OperandsMapper creates plain scalar, we may have to fix that.
439 // Check if the types match and if not, fix that.
440 LLT OrigTy = MRI.getType(OrigReg);
441 LLT NewTy = MRI.getType(NewReg);
442 if (OrigTy != NewTy) {
443 // The default mapping is not supposed to change the size of
444 // the storage. However, right now we don't necessarily bump all
445 // the types to storage size. For instance, we can consider
446 // s16 G_AND legal whereas the storage size is going to be 32.
447 assert(OrigTy.getSizeInBits() <= NewTy.getSizeInBits() &&
448 "Types with difference size cannot be handled by the default "
450 DEBUG(dbgs() << "\nChange type of new opd from " << NewTy << " to "
452 MRI.setType(NewReg, OrigTy);
454 DEBUG(dbgs() << '\n');
458 unsigned RegisterBankInfo::getSizeInBits(unsigned Reg,
459 const MachineRegisterInfo &MRI,
460 const TargetRegisterInfo &TRI) const {
461 const TargetRegisterClass *RC = nullptr;
462 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
463 // The size is not directly available for physical registers.
464 // Instead, we need to access a register class that contains Reg and
465 // get the size of that register class.
466 RC = &getMinimalPhysRegClass(Reg, TRI);
468 LLT Ty = MRI.getType(Reg);
469 unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0;
470 // If Reg is not a generic register, query the register class to
474 // Since Reg is not a generic register, it must have a register class.
475 RC = MRI.getRegClass(Reg);
477 assert(RC && "Unable to deduce the register class");
478 return TRI.getRegSizeInBits(*RC);
481 //------------------------------------------------------------------------------
482 // Helper classes implementation.
483 //------------------------------------------------------------------------------
484 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
485 LLVM_DUMP_METHOD void RegisterBankInfo::PartialMapping::dump() const {
491 bool RegisterBankInfo::PartialMapping::verify() const {
492 assert(RegBank && "Register bank not set");
493 assert(Length && "Empty mapping");
494 assert((StartIdx <= getHighBitIdx()) && "Overflow, switch to APInt?");
495 // Check if the minimum width fits into RegBank.
496 assert(RegBank->getSize() >= Length && "Register bank too small for Mask");
500 void RegisterBankInfo::PartialMapping::print(raw_ostream &OS) const {
501 OS << "[" << StartIdx << ", " << getHighBitIdx() << "], RegBank = ";
508 bool RegisterBankInfo::ValueMapping::verify(unsigned MeaningfulBitWidth) const {
509 assert(NumBreakDowns && "Value mapped nowhere?!");
510 unsigned OrigValueBitWidth = 0;
511 for (const RegisterBankInfo::PartialMapping &PartMap : *this) {
512 // Check that each register bank is big enough to hold the partial value:
513 // this check is done by PartialMapping::verify
514 assert(PartMap.verify() && "Partial mapping is invalid");
515 // The original value should completely be mapped.
516 // Thus the maximum accessed index + 1 is the size of the original value.
518 std::max(OrigValueBitWidth, PartMap.getHighBitIdx() + 1);
520 assert(OrigValueBitWidth >= MeaningfulBitWidth &&
521 "Meaningful bits not covered by the mapping");
522 APInt ValueMask(OrigValueBitWidth, 0);
523 for (const RegisterBankInfo::PartialMapping &PartMap : *this) {
524 // Check that the union of the partial mappings covers the whole value,
526 // The high bit is exclusive in the APInt API, thus getHighBitIdx + 1.
527 APInt PartMapMask = APInt::getBitsSet(OrigValueBitWidth, PartMap.StartIdx,
528 PartMap.getHighBitIdx() + 1);
529 ValueMask ^= PartMapMask;
530 assert((ValueMask & PartMapMask) == PartMapMask &&
531 "Some partial mappings overlap");
533 assert(ValueMask.isAllOnesValue() && "Value is not fully mapped");
537 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
538 LLVM_DUMP_METHOD void RegisterBankInfo::ValueMapping::dump() const {
544 void RegisterBankInfo::ValueMapping::print(raw_ostream &OS) const {
545 OS << "#BreakDown: " << NumBreakDowns << " ";
547 for (const PartialMapping &PartMap : *this) {
550 OS << '[' << PartMap << ']';
555 bool RegisterBankInfo::InstructionMapping::verify(
556 const MachineInstr &MI) const {
557 // Check that all the register operands are properly mapped.
558 // Check the constructor invariant.
559 // For PHI, we only care about mapping the definition.
560 assert(NumOperands == (isCopyLike(MI) ? 1 : MI.getNumOperands()) &&
561 "NumOperands must match, see constructor");
562 assert(MI.getParent() && MI.getMF() &&
563 "MI must be connected to a MachineFunction");
564 const MachineFunction &MF = *MI.getMF();
565 const RegisterBankInfo *RBI = MF.getSubtarget().getRegBankInfo();
568 for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
569 const MachineOperand &MO = MI.getOperand(Idx);
571 assert(!getOperandMapping(Idx).isValid() &&
572 "We should not care about non-reg mapping");
575 unsigned Reg = MO.getReg();
578 assert(getOperandMapping(Idx).isValid() &&
579 "We must have a mapping for reg operands");
580 const RegisterBankInfo::ValueMapping &MOMapping = getOperandMapping(Idx);
582 // Register size in bits.
583 // This size must match what the mapping expects.
584 assert(MOMapping.verify(RBI->getSizeInBits(
585 Reg, MF.getRegInfo(), *MF.getSubtarget().getRegisterInfo())) &&
586 "Value mapping is invalid");
591 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
592 LLVM_DUMP_METHOD void RegisterBankInfo::InstructionMapping::dump() const {
598 void RegisterBankInfo::InstructionMapping::print(raw_ostream &OS) const {
599 OS << "ID: " << getID() << " Cost: " << getCost() << " Mapping: ";
601 for (unsigned OpIdx = 0; OpIdx != NumOperands; ++OpIdx) {
602 const ValueMapping &ValMapping = getOperandMapping(OpIdx);
605 OS << "{ Idx: " << OpIdx << " Map: " << ValMapping << '}';
609 const int RegisterBankInfo::OperandsMapper::DontKnowIdx = -1;
611 RegisterBankInfo::OperandsMapper::OperandsMapper(
612 MachineInstr &MI, const InstructionMapping &InstrMapping,
613 MachineRegisterInfo &MRI)
614 : MRI(MRI), MI(MI), InstrMapping(InstrMapping) {
615 unsigned NumOpds = InstrMapping.getNumOperands();
616 OpToNewVRegIdx.resize(NumOpds, OperandsMapper::DontKnowIdx);
617 assert(InstrMapping.verify(MI) && "Invalid mapping for MI");
620 iterator_range<SmallVectorImpl<unsigned>::iterator>
621 RegisterBankInfo::OperandsMapper::getVRegsMem(unsigned OpIdx) {
622 assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
623 unsigned NumPartialVal =
624 getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns;
625 int StartIdx = OpToNewVRegIdx[OpIdx];
627 if (StartIdx == OperandsMapper::DontKnowIdx) {
628 // This is the first time we try to access OpIdx.
629 // Create the cells that will hold all the partial values at the
630 // end of the list of NewVReg.
631 StartIdx = NewVRegs.size();
632 OpToNewVRegIdx[OpIdx] = StartIdx;
633 for (unsigned i = 0; i < NumPartialVal; ++i)
634 NewVRegs.push_back(0);
636 SmallVectorImpl<unsigned>::iterator End =
637 getNewVRegsEnd(StartIdx, NumPartialVal);
639 return make_range(&NewVRegs[StartIdx], End);
642 SmallVectorImpl<unsigned>::const_iterator
643 RegisterBankInfo::OperandsMapper::getNewVRegsEnd(unsigned StartIdx,
644 unsigned NumVal) const {
645 return const_cast<OperandsMapper *>(this)->getNewVRegsEnd(StartIdx, NumVal);
647 SmallVectorImpl<unsigned>::iterator
648 RegisterBankInfo::OperandsMapper::getNewVRegsEnd(unsigned StartIdx,
650 assert((NewVRegs.size() == StartIdx + NumVal ||
651 NewVRegs.size() > StartIdx + NumVal) &&
652 "NewVRegs too small to contain all the partial mapping");
653 return NewVRegs.size() <= StartIdx + NumVal ? NewVRegs.end()
654 : &NewVRegs[StartIdx + NumVal];
657 void RegisterBankInfo::OperandsMapper::createVRegs(unsigned OpIdx) {
658 assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
659 iterator_range<SmallVectorImpl<unsigned>::iterator> NewVRegsForOpIdx =
661 const ValueMapping &ValMapping = getInstrMapping().getOperandMapping(OpIdx);
662 const PartialMapping *PartMap = ValMapping.begin();
663 for (unsigned &NewVReg : NewVRegsForOpIdx) {
664 assert(PartMap != ValMapping.end() && "Out-of-bound access");
665 assert(NewVReg == 0 && "Register has already been created");
666 // The new registers are always bound to scalar with the right size.
667 // The actual type has to be set when the target does the mapping
668 // of the instruction.
669 // The rationale is that this generic code cannot guess how the
670 // target plans to split the input type.
671 NewVReg = MRI.createGenericVirtualRegister(LLT::scalar(PartMap->Length));
672 MRI.setRegBank(NewVReg, *PartMap->RegBank);
677 void RegisterBankInfo::OperandsMapper::setVRegs(unsigned OpIdx,
678 unsigned PartialMapIdx,
680 assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
681 assert(getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns >
683 "Out-of-bound access for partial mapping");
684 // Make sure the memory is initialized for that operand.
685 (void)getVRegsMem(OpIdx);
686 assert(NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] == 0 &&
687 "This value is already set");
688 NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] = NewVReg;
691 iterator_range<SmallVectorImpl<unsigned>::const_iterator>
692 RegisterBankInfo::OperandsMapper::getVRegs(unsigned OpIdx,
693 bool ForDebug) const {
695 assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
696 int StartIdx = OpToNewVRegIdx[OpIdx];
698 if (StartIdx == OperandsMapper::DontKnowIdx)
699 return make_range(NewVRegs.end(), NewVRegs.end());
701 unsigned PartMapSize =
702 getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns;
703 SmallVectorImpl<unsigned>::const_iterator End =
704 getNewVRegsEnd(StartIdx, PartMapSize);
705 iterator_range<SmallVectorImpl<unsigned>::const_iterator> Res =
706 make_range(&NewVRegs[StartIdx], End);
708 for (unsigned VReg : Res)
709 assert((VReg || ForDebug) && "Some registers are uninitialized");
714 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
715 LLVM_DUMP_METHOD void RegisterBankInfo::OperandsMapper::dump() const {
721 void RegisterBankInfo::OperandsMapper::print(raw_ostream &OS,
722 bool ForDebug) const {
723 unsigned NumOpds = getInstrMapping().getNumOperands();
725 OS << "Mapping for " << getMI() << "\nwith " << getInstrMapping() << '\n';
726 // Print out the internal state of the index table.
727 OS << "Populated indices (CellNumber, IndexInNewVRegs): ";
729 for (unsigned Idx = 0; Idx != NumOpds; ++Idx) {
730 if (OpToNewVRegIdx[Idx] != DontKnowIdx) {
733 OS << '(' << Idx << ", " << OpToNewVRegIdx[Idx] << ')';
739 OS << "Mapping ID: " << getInstrMapping().getID() << ' ';
741 OS << "Operand Mapping: ";
742 // If we have a function, we can pretty print the name of the registers.
743 // Otherwise we will print the raw numbers.
744 const TargetRegisterInfo *TRI =
745 getMI().getParent() && getMI().getMF()
746 ? getMI().getMF()->getSubtarget().getRegisterInfo()
749 for (unsigned Idx = 0; Idx != NumOpds; ++Idx) {
750 if (OpToNewVRegIdx[Idx] == DontKnowIdx)
755 OS << '(' << printReg(getMI().getOperand(Idx).getReg(), TRI) << ", [";
756 bool IsFirstNewVReg = true;
757 for (unsigned VReg : getVRegs(Idx)) {
760 IsFirstNewVReg = false;
761 OS << printReg(VReg, TRI);