1 //===- llvm/CodeGen/GlobalISel/RegisterBankInfo.cpp --------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements the RegisterBankInfo class.
11 //===----------------------------------------------------------------------===//
13 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/ADT/iterator_range.h"
18 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/IR/Type.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Target/TargetOpcodes.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Target/TargetSubtargetInfo.h"
30 #include <algorithm> // For std::max.
32 #define DEBUG_TYPE "registerbankinfo"
36 STATISTIC(NumPartialMappingsCreated,
37 "Number of partial mappings dynamically created");
38 STATISTIC(NumPartialMappingsAccessed,
39 "Number of partial mappings dynamically accessed");
40 STATISTIC(NumValueMappingsCreated,
41 "Number of value mappings dynamically created");
42 STATISTIC(NumValueMappingsAccessed,
43 "Number of value mappings dynamically accessed");
44 STATISTIC(NumOperandsMappingsCreated,
45 "Number of operands mappings dynamically created");
46 STATISTIC(NumOperandsMappingsAccessed,
47 "Number of operands mappings dynamically accessed");
49 const unsigned RegisterBankInfo::DefaultMappingID = UINT_MAX;
50 const unsigned RegisterBankInfo::InvalidMappingID = UINT_MAX - 1;
52 //------------------------------------------------------------------------------
53 // RegisterBankInfo implementation.
54 //------------------------------------------------------------------------------
55 RegisterBankInfo::RegisterBankInfo(RegisterBank **RegBanks,
57 : RegBanks(RegBanks), NumRegBanks(NumRegBanks) {
59 for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
60 assert(RegBanks[Idx] != nullptr && "Invalid RegisterBank");
61 assert(RegBanks[Idx]->isValid() && "RegisterBank should be valid");
66 bool RegisterBankInfo::verify(const TargetRegisterInfo &TRI) const {
68 for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
69 const RegisterBank &RegBank = getRegBank(Idx);
70 assert(Idx == RegBank.getID() &&
71 "ID does not match the index in the array");
72 DEBUG(dbgs() << "Verify " << RegBank << '\n');
73 assert(RegBank.verify(TRI) && "RegBank is invalid");
80 RegisterBankInfo::getRegBank(unsigned Reg, const MachineRegisterInfo &MRI,
81 const TargetRegisterInfo &TRI) const {
82 if (TargetRegisterInfo::isPhysicalRegister(Reg))
83 return &getRegBankFromRegClass(*TRI.getMinimalPhysRegClass(Reg));
85 assert(Reg && "NoRegister does not have a register bank");
86 const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
87 if (auto *RB = RegClassOrBank.dyn_cast<const RegisterBank *>())
89 if (auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>())
90 return &getRegBankFromRegClass(*RC);
94 const RegisterBank *RegisterBankInfo::getRegBankFromConstraints(
95 const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII,
96 const TargetRegisterInfo &TRI) const {
97 // The mapping of the registers may be available via the
98 // register class constraints.
99 const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, &TRI);
104 const RegisterBank &RegBank = getRegBankFromRegClass(*RC);
105 // Sanity check that the target properly implemented getRegBankFromRegClass.
106 assert(RegBank.covers(*RC) &&
107 "The mapping of the register bank does not make sense");
111 const TargetRegisterClass *RegisterBankInfo::constrainGenericRegister(
112 unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI) {
114 // If the register already has a class, fallback to MRI::constrainRegClass.
115 auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
116 if (RegClassOrBank.is<const TargetRegisterClass *>())
117 return MRI.constrainRegClass(Reg, &RC);
119 const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
120 // Otherwise, all we can do is ensure the bank covers the class, and set it.
121 if (RB && !RB->covers(RC))
124 // If nothing was set or the class is simply compatible, set it.
125 MRI.setRegClass(Reg, &RC);
129 /// Check whether or not \p MI should be treated like a copy
130 /// for the mappings.
131 /// Copy like instruction are special for mapping because
132 /// they don't have actual register constraints. Moreover,
133 /// they sometimes have register classes assigned and we can
134 /// just use that instead of failing to provide a generic mapping.
135 static bool isCopyLike(const MachineInstr &MI) {
136 return MI.isCopy() || MI.isPHI() ||
137 MI.getOpcode() == TargetOpcode::REG_SEQUENCE;
140 RegisterBankInfo::InstructionMapping
141 RegisterBankInfo::getInstrMappingImpl(const MachineInstr &MI) const {
142 // For copies we want to walk over the operands and try to find one
143 // that has a register bank since the instruction itself will not get
144 // us any constraint.
145 bool IsCopyLike = isCopyLike(MI);
146 // For copy like instruction, only the mapping of the definition
147 // is important. The rest is not constrained.
148 unsigned NumOperandsForMapping = IsCopyLike ? 1 : MI.getNumOperands();
150 RegisterBankInfo::InstructionMapping Mapping(DefaultMappingID, /*Cost*/ 1,
151 /*OperandsMapping*/ nullptr,
152 NumOperandsForMapping);
153 const MachineFunction &MF = *MI.getParent()->getParent();
154 const TargetSubtargetInfo &STI = MF.getSubtarget();
155 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
156 const MachineRegisterInfo &MRI = MF.getRegInfo();
157 // We may need to query the instruction encoding to guess the mapping.
158 const TargetInstrInfo &TII = *STI.getInstrInfo();
160 // Before doing anything complicated check if the mapping is not
161 // directly available.
162 bool CompleteMapping = true;
164 SmallVector<const ValueMapping *, 8> OperandsMapping(NumOperandsForMapping);
165 for (unsigned OpIdx = 0, EndIdx = MI.getNumOperands(); OpIdx != EndIdx;
167 const MachineOperand &MO = MI.getOperand(OpIdx);
170 unsigned Reg = MO.getReg();
173 // The register bank of Reg is just a side effect of the current
174 // excution and in particular, there is no reason to believe this
175 // is the best default mapping for the current instruction. Keep
176 // it as an alternative register bank if we cannot figure out
178 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI);
179 // For copy-like instruction, we want to reuse the register bank
180 // that is already set on Reg, if any, since those instructions do
181 // not have any constraints.
182 const RegisterBank *CurRegBank = IsCopyLike ? AltRegBank : nullptr;
184 // If this is a target specific instruction, we can deduce
185 // the register bank from the encoding constraints.
186 CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, TRI);
188 // All our attempts failed, give up.
189 CompleteMapping = false;
192 // MI does not carry enough information to guess the mapping.
193 return InstructionMapping();
197 const ValueMapping *ValMapping =
198 &getValueMapping(0, getSizeInBits(Reg, MRI, TRI), *CurRegBank);
200 OperandsMapping[0] = ValMapping;
201 CompleteMapping = true;
204 OperandsMapping[OpIdx] = ValMapping;
207 if (IsCopyLike && !CompleteMapping)
208 // No way to deduce the type from what we have.
209 return InstructionMapping();
211 assert(CompleteMapping && "Setting an uncomplete mapping");
212 Mapping.setOperandsMapping(getOperandsMapping(OperandsMapping));
216 /// Hashing function for PartialMapping.
217 static hash_code hashPartialMapping(unsigned StartIdx, unsigned Length,
218 const RegisterBank *RegBank) {
219 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0);
222 /// Overloaded version of hash_value for a PartialMapping.
224 llvm::hash_value(const RegisterBankInfo::PartialMapping &PartMapping) {
225 return hashPartialMapping(PartMapping.StartIdx, PartMapping.Length,
226 PartMapping.RegBank);
229 const RegisterBankInfo::PartialMapping &
230 RegisterBankInfo::getPartialMapping(unsigned StartIdx, unsigned Length,
231 const RegisterBank &RegBank) const {
232 ++NumPartialMappingsAccessed;
234 hash_code Hash = hashPartialMapping(StartIdx, Length, &RegBank);
235 const auto &It = MapOfPartialMappings.find(Hash);
236 if (It != MapOfPartialMappings.end())
239 ++NumPartialMappingsCreated;
241 auto &PartMapping = MapOfPartialMappings[Hash];
242 PartMapping = llvm::make_unique<PartialMapping>(StartIdx, Length, RegBank);
246 const RegisterBankInfo::ValueMapping &
247 RegisterBankInfo::getValueMapping(unsigned StartIdx, unsigned Length,
248 const RegisterBank &RegBank) const {
249 return getValueMapping(&getPartialMapping(StartIdx, Length, RegBank), 1);
253 hashValueMapping(const RegisterBankInfo::PartialMapping *BreakDown,
254 unsigned NumBreakDowns) {
255 if (LLVM_LIKELY(NumBreakDowns == 1))
256 return hash_value(*BreakDown);
257 SmallVector<size_t, 8> Hashes(NumBreakDowns);
258 for (unsigned Idx = 0; Idx != NumBreakDowns; ++Idx)
259 Hashes.push_back(hash_value(BreakDown[Idx]));
260 return hash_combine_range(Hashes.begin(), Hashes.end());
263 const RegisterBankInfo::ValueMapping &
264 RegisterBankInfo::getValueMapping(const PartialMapping *BreakDown,
265 unsigned NumBreakDowns) const {
266 ++NumValueMappingsAccessed;
268 hash_code Hash = hashValueMapping(BreakDown, NumBreakDowns);
269 const auto &It = MapOfValueMappings.find(Hash);
270 if (It != MapOfValueMappings.end())
273 ++NumValueMappingsCreated;
275 auto &ValMapping = MapOfValueMappings[Hash];
276 ValMapping = llvm::make_unique<ValueMapping>(BreakDown, NumBreakDowns);
280 template <typename Iterator>
281 const RegisterBankInfo::ValueMapping *
282 RegisterBankInfo::getOperandsMapping(Iterator Begin, Iterator End) const {
284 ++NumOperandsMappingsAccessed;
286 // The addresses of the value mapping are unique.
287 // Therefore, we can use them directly to hash the operand mapping.
288 hash_code Hash = hash_combine_range(Begin, End);
289 auto &Res = MapOfOperandsMappings[Hash];
293 ++NumOperandsMappingsCreated;
295 // Create the array of ValueMapping.
296 // Note: this array will not hash to this instance of operands
297 // mapping, because we use the pointer of the ValueMapping
298 // to hash and we expect them to uniquely identify an instance
300 Res = llvm::make_unique<ValueMapping[]>(std::distance(Begin, End));
302 for (Iterator It = Begin; It != End; ++It, ++Idx) {
303 const ValueMapping *ValMap = *It;
311 const RegisterBankInfo::ValueMapping *RegisterBankInfo::getOperandsMapping(
312 const SmallVectorImpl<const RegisterBankInfo::ValueMapping *> &OpdsMapping)
314 return getOperandsMapping(OpdsMapping.begin(), OpdsMapping.end());
317 const RegisterBankInfo::ValueMapping *RegisterBankInfo::getOperandsMapping(
318 std::initializer_list<const RegisterBankInfo::ValueMapping *> OpdsMapping)
320 return getOperandsMapping(OpdsMapping.begin(), OpdsMapping.end());
323 RegisterBankInfo::InstructionMapping
324 RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
325 RegisterBankInfo::InstructionMapping Mapping = getInstrMappingImpl(MI);
326 if (Mapping.isValid())
328 llvm_unreachable("The target must implement this");
331 RegisterBankInfo::InstructionMappings
332 RegisterBankInfo::getInstrPossibleMappings(const MachineInstr &MI) const {
333 InstructionMappings PossibleMappings;
334 // Put the default mapping first.
335 PossibleMappings.push_back(getInstrMapping(MI));
336 // Then the alternative mapping, if any.
337 InstructionMappings AltMappings = getInstrAlternativeMappings(MI);
338 for (InstructionMapping &AltMapping : AltMappings)
339 PossibleMappings.emplace_back(std::move(AltMapping));
341 for (const InstructionMapping &Mapping : PossibleMappings)
342 assert(Mapping.verify(MI) && "Mapping is invalid");
344 return PossibleMappings;
347 RegisterBankInfo::InstructionMappings
348 RegisterBankInfo::getInstrAlternativeMappings(const MachineInstr &MI) const {
349 // No alternative for MI.
350 return InstructionMappings();
353 void RegisterBankInfo::applyDefaultMapping(const OperandsMapper &OpdMapper) {
354 MachineInstr &MI = OpdMapper.getMI();
355 MachineRegisterInfo &MRI = OpdMapper.getMRI();
356 DEBUG(dbgs() << "Applying default-like mapping\n");
357 for (unsigned OpIdx = 0,
358 EndIdx = OpdMapper.getInstrMapping().getNumOperands();
359 OpIdx != EndIdx; ++OpIdx) {
360 DEBUG(dbgs() << "OpIdx " << OpIdx);
361 MachineOperand &MO = MI.getOperand(OpIdx);
363 DEBUG(dbgs() << " is not a register, nothing to be done\n");
367 DEBUG(dbgs() << " is %%noreg, nothing to be done\n");
370 assert(OpdMapper.getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns !=
373 assert(OpdMapper.getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns ==
375 "This mapping is too complex for this function");
376 iterator_range<SmallVectorImpl<unsigned>::const_iterator> NewRegs =
377 OpdMapper.getVRegs(OpIdx);
378 if (NewRegs.begin() == NewRegs.end()) {
379 DEBUG(dbgs() << " has not been repaired, nothing to be done\n");
382 unsigned OrigReg = MO.getReg();
383 unsigned NewReg = *NewRegs.begin();
384 DEBUG(dbgs() << " changed, replace " << PrintReg(OrigReg, nullptr));
386 DEBUG(dbgs() << " with " << PrintReg(NewReg, nullptr));
388 // The OperandsMapper creates plain scalar, we may have to fix that.
389 // Check if the types match and if not, fix that.
390 LLT OrigTy = MRI.getType(OrigReg);
391 LLT NewTy = MRI.getType(NewReg);
392 if (OrigTy != NewTy) {
393 assert(OrigTy.getSizeInBits() == NewTy.getSizeInBits() &&
394 "Types with difference size cannot be handled by the default "
396 DEBUG(dbgs() << "\nChange type of new opd from " << NewTy << " to "
398 MRI.setType(NewReg, OrigTy);
400 DEBUG(dbgs() << '\n');
404 unsigned RegisterBankInfo::getSizeInBits(unsigned Reg,
405 const MachineRegisterInfo &MRI,
406 const TargetRegisterInfo &TRI) {
407 const TargetRegisterClass *RC = nullptr;
408 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
409 // The size is not directly available for physical registers.
410 // Instead, we need to access a register class that contains Reg and
411 // get the size of that register class.
412 RC = TRI.getMinimalPhysRegClass(Reg);
414 LLT Ty = MRI.getType(Reg);
415 unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0;
416 // If Reg is not a generic register, query the register class to
420 // Since Reg is not a generic register, it must have a register class.
421 RC = MRI.getRegClass(Reg);
423 assert(RC && "Unable to deduce the register class");
424 return RC->getSize() * 8;
427 //------------------------------------------------------------------------------
428 // Helper classes implementation.
429 //------------------------------------------------------------------------------
430 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
431 LLVM_DUMP_METHOD void RegisterBankInfo::PartialMapping::dump() const {
437 bool RegisterBankInfo::PartialMapping::verify() const {
438 assert(RegBank && "Register bank not set");
439 assert(Length && "Empty mapping");
440 assert((StartIdx <= getHighBitIdx()) && "Overflow, switch to APInt?");
441 // Check if the minimum width fits into RegBank.
442 assert(RegBank->getSize() >= Length && "Register bank too small for Mask");
446 void RegisterBankInfo::PartialMapping::print(raw_ostream &OS) const {
447 OS << "[" << StartIdx << ", " << getHighBitIdx() << "], RegBank = ";
454 bool RegisterBankInfo::ValueMapping::verify(unsigned MeaningfulBitWidth) const {
455 assert(NumBreakDowns && "Value mapped nowhere?!");
456 unsigned OrigValueBitWidth = 0;
457 for (const RegisterBankInfo::PartialMapping &PartMap : *this) {
458 // Check that each register bank is big enough to hold the partial value:
459 // this check is done by PartialMapping::verify
460 assert(PartMap.verify() && "Partial mapping is invalid");
461 // The original value should completely be mapped.
462 // Thus the maximum accessed index + 1 is the size of the original value.
464 std::max(OrigValueBitWidth, PartMap.getHighBitIdx() + 1);
466 assert(OrigValueBitWidth >= MeaningfulBitWidth &&
467 "Meaningful bits not covered by the mapping");
468 APInt ValueMask(OrigValueBitWidth, 0);
469 for (const RegisterBankInfo::PartialMapping &PartMap : *this) {
470 // Check that the union of the partial mappings covers the whole value,
472 // The high bit is exclusive in the APInt API, thus getHighBitIdx + 1.
473 APInt PartMapMask = APInt::getBitsSet(OrigValueBitWidth, PartMap.StartIdx,
474 PartMap.getHighBitIdx() + 1);
475 ValueMask ^= PartMapMask;
476 assert((ValueMask & PartMapMask) == PartMapMask &&
477 "Some partial mappings overlap");
479 assert(ValueMask.isAllOnesValue() && "Value is not fully mapped");
483 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
484 LLVM_DUMP_METHOD void RegisterBankInfo::ValueMapping::dump() const {
490 void RegisterBankInfo::ValueMapping::print(raw_ostream &OS) const {
491 OS << "#BreakDown: " << NumBreakDowns << " ";
493 for (const PartialMapping &PartMap : *this) {
496 OS << '[' << PartMap << ']';
501 bool RegisterBankInfo::InstructionMapping::verify(
502 const MachineInstr &MI) const {
503 // Check that all the register operands are properly mapped.
504 // Check the constructor invariant.
505 // For PHI, we only care about mapping the definition.
506 assert(NumOperands == (isCopyLike(MI) ? 1 : MI.getNumOperands()) &&
507 "NumOperands must match, see constructor");
508 assert(MI.getParent() && MI.getParent()->getParent() &&
509 "MI must be connected to a MachineFunction");
510 const MachineFunction &MF = *MI.getParent()->getParent();
513 for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
514 const MachineOperand &MO = MI.getOperand(Idx);
516 assert(!getOperandMapping(Idx).isValid() &&
517 "We should not care about non-reg mapping");
520 unsigned Reg = MO.getReg();
523 assert(getOperandMapping(Idx).isValid() &&
524 "We must have a mapping for reg operands");
525 const RegisterBankInfo::ValueMapping &MOMapping = getOperandMapping(Idx);
527 // Register size in bits.
528 // This size must match what the mapping expects.
529 assert(MOMapping.verify(getSizeInBits(
530 Reg, MF.getRegInfo(), *MF.getSubtarget().getRegisterInfo())) &&
531 "Value mapping is invalid");
536 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
537 LLVM_DUMP_METHOD void RegisterBankInfo::InstructionMapping::dump() const {
543 void RegisterBankInfo::InstructionMapping::print(raw_ostream &OS) const {
544 OS << "ID: " << getID() << " Cost: " << getCost() << " Mapping: ";
546 for (unsigned OpIdx = 0; OpIdx != NumOperands; ++OpIdx) {
547 const ValueMapping &ValMapping = getOperandMapping(OpIdx);
550 OS << "{ Idx: " << OpIdx << " Map: " << ValMapping << '}';
554 const int RegisterBankInfo::OperandsMapper::DontKnowIdx = -1;
556 RegisterBankInfo::OperandsMapper::OperandsMapper(
557 MachineInstr &MI, const InstructionMapping &InstrMapping,
558 MachineRegisterInfo &MRI)
559 : MRI(MRI), MI(MI), InstrMapping(InstrMapping) {
560 unsigned NumOpds = InstrMapping.getNumOperands();
561 OpToNewVRegIdx.resize(NumOpds, OperandsMapper::DontKnowIdx);
562 assert(InstrMapping.verify(MI) && "Invalid mapping for MI");
565 iterator_range<SmallVectorImpl<unsigned>::iterator>
566 RegisterBankInfo::OperandsMapper::getVRegsMem(unsigned OpIdx) {
567 assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
568 unsigned NumPartialVal =
569 getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns;
570 int StartIdx = OpToNewVRegIdx[OpIdx];
572 if (StartIdx == OperandsMapper::DontKnowIdx) {
573 // This is the first time we try to access OpIdx.
574 // Create the cells that will hold all the partial values at the
575 // end of the list of NewVReg.
576 StartIdx = NewVRegs.size();
577 OpToNewVRegIdx[OpIdx] = StartIdx;
578 for (unsigned i = 0; i < NumPartialVal; ++i)
579 NewVRegs.push_back(0);
581 SmallVectorImpl<unsigned>::iterator End =
582 getNewVRegsEnd(StartIdx, NumPartialVal);
584 return make_range(&NewVRegs[StartIdx], End);
587 SmallVectorImpl<unsigned>::const_iterator
588 RegisterBankInfo::OperandsMapper::getNewVRegsEnd(unsigned StartIdx,
589 unsigned NumVal) const {
590 return const_cast<OperandsMapper *>(this)->getNewVRegsEnd(StartIdx, NumVal);
592 SmallVectorImpl<unsigned>::iterator
593 RegisterBankInfo::OperandsMapper::getNewVRegsEnd(unsigned StartIdx,
595 assert((NewVRegs.size() == StartIdx + NumVal ||
596 NewVRegs.size() > StartIdx + NumVal) &&
597 "NewVRegs too small to contain all the partial mapping");
598 return NewVRegs.size() <= StartIdx + NumVal ? NewVRegs.end()
599 : &NewVRegs[StartIdx + NumVal];
602 void RegisterBankInfo::OperandsMapper::createVRegs(unsigned OpIdx) {
603 assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
604 iterator_range<SmallVectorImpl<unsigned>::iterator> NewVRegsForOpIdx =
606 const ValueMapping &ValMapping = getInstrMapping().getOperandMapping(OpIdx);
607 const PartialMapping *PartMap = ValMapping.begin();
608 for (unsigned &NewVReg : NewVRegsForOpIdx) {
609 assert(PartMap != ValMapping.end() && "Out-of-bound access");
610 assert(NewVReg == 0 && "Register has already been created");
611 // The new registers are always bound to scalar with the right size.
612 // The actual type has to be set when the target does the mapping
613 // of the instruction.
614 // The rationale is that this generic code cannot guess how the
615 // target plans to split the input type.
616 NewVReg = MRI.createGenericVirtualRegister(LLT::scalar(PartMap->Length));
617 MRI.setRegBank(NewVReg, *PartMap->RegBank);
622 void RegisterBankInfo::OperandsMapper::setVRegs(unsigned OpIdx,
623 unsigned PartialMapIdx,
625 assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
626 assert(getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns >
628 "Out-of-bound access for partial mapping");
629 // Make sure the memory is initialized for that operand.
630 (void)getVRegsMem(OpIdx);
631 assert(NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] == 0 &&
632 "This value is already set");
633 NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] = NewVReg;
636 iterator_range<SmallVectorImpl<unsigned>::const_iterator>
637 RegisterBankInfo::OperandsMapper::getVRegs(unsigned OpIdx,
638 bool ForDebug) const {
640 assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
641 int StartIdx = OpToNewVRegIdx[OpIdx];
643 if (StartIdx == OperandsMapper::DontKnowIdx)
644 return make_range(NewVRegs.end(), NewVRegs.end());
646 unsigned PartMapSize =
647 getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns;
648 SmallVectorImpl<unsigned>::const_iterator End =
649 getNewVRegsEnd(StartIdx, PartMapSize);
650 iterator_range<SmallVectorImpl<unsigned>::const_iterator> Res =
651 make_range(&NewVRegs[StartIdx], End);
653 for (unsigned VReg : Res)
654 assert((VReg || ForDebug) && "Some registers are uninitialized");
659 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
660 LLVM_DUMP_METHOD void RegisterBankInfo::OperandsMapper::dump() const {
666 void RegisterBankInfo::OperandsMapper::print(raw_ostream &OS,
667 bool ForDebug) const {
668 unsigned NumOpds = getInstrMapping().getNumOperands();
670 OS << "Mapping for " << getMI() << "\nwith " << getInstrMapping() << '\n';
671 // Print out the internal state of the index table.
672 OS << "Populated indices (CellNumber, IndexInNewVRegs): ";
674 for (unsigned Idx = 0; Idx != NumOpds; ++Idx) {
675 if (OpToNewVRegIdx[Idx] != DontKnowIdx) {
678 OS << '(' << Idx << ", " << OpToNewVRegIdx[Idx] << ')';
684 OS << "Mapping ID: " << getInstrMapping().getID() << ' ';
686 OS << "Operand Mapping: ";
687 // If we have a function, we can pretty print the name of the registers.
688 // Otherwise we will print the raw numbers.
689 const TargetRegisterInfo *TRI =
690 getMI().getParent() && getMI().getParent()->getParent()
691 ? getMI().getParent()->getParent()->getSubtarget().getRegisterInfo()
694 for (unsigned Idx = 0; Idx != NumOpds; ++Idx) {
695 if (OpToNewVRegIdx[Idx] == DontKnowIdx)
700 OS << '(' << PrintReg(getMI().getOperand(Idx).getReg(), TRI) << ", [";
701 bool IsFirstNewVReg = true;
702 for (unsigned VReg : getVRegs(Idx)) {
705 IsFirstNewVReg = false;
706 OS << PrintReg(VReg, TRI);