1 //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 /// \file This file implements the utility functions used by the GlobalISel
11 //===----------------------------------------------------------------------===//
13 #include "llvm/CodeGen/GlobalISel/Utils.h"
14 #include "llvm/ADT/Twine.h"
15 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
16 #include "llvm/CodeGen/MachineInstr.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetPassConfig.h"
21 #include "llvm/IR/Constants.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
25 #define DEBUG_TYPE "globalisel-utils"
29 unsigned llvm::constrainRegToClass(MachineRegisterInfo &MRI,
30 const TargetInstrInfo &TII,
31 const RegisterBankInfo &RBI,
32 MachineInstr &InsertPt, unsigned Reg,
33 const TargetRegisterClass &RegClass) {
34 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) {
35 unsigned NewReg = MRI.createVirtualRegister(&RegClass);
36 BuildMI(*InsertPt.getParent(), InsertPt, InsertPt.getDebugLoc(),
37 TII.get(TargetOpcode::COPY), NewReg)
46 unsigned llvm::constrainOperandRegClass(
47 const MachineFunction &MF, const TargetRegisterInfo &TRI,
48 MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
49 const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
50 unsigned Reg, unsigned OpIdx) {
51 // Assume physical registers are properly constrained.
52 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
53 "PhysReg not implemented");
55 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
56 return constrainRegToClass(MRI, TII, RBI, InsertPt, Reg, *RegClass);
59 bool llvm::isTriviallyDead(const MachineInstr &MI,
60 const MachineRegisterInfo &MRI) {
61 // If we can move an instruction, we can remove it. Otherwise, it has
62 // a side-effect of some sort.
63 bool SawStore = false;
64 if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore))
67 // Instructions without side-effects are dead iff they only define dead vregs.
68 for (auto &MO : MI.operands()) {
69 if (!MO.isReg() || !MO.isDef())
72 unsigned Reg = MO.getReg();
73 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
74 !MRI.use_nodbg_empty(Reg))
80 void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
81 MachineOptimizationRemarkEmitter &MORE,
82 MachineOptimizationRemarkMissed &R) {
83 MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
85 // Print the function name explicitly if we don't have a debug location (which
86 // makes the diagnostic less useful) or if we're going to emit a raw error.
87 if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
88 R << (" (in function: " + MF.getName() + ")").str();
90 if (TPC.isGlobalISelAbortEnabled())
91 report_fatal_error(R.getMsg());
96 void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
97 MachineOptimizationRemarkEmitter &MORE,
98 const char *PassName, StringRef Msg,
99 const MachineInstr &MI) {
100 MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
101 MI.getDebugLoc(), MI.getParent());
102 R << Msg << ": " << ore::MNV("Inst", MI);
103 reportGISelFailure(MF, TPC, MORE, R);
106 Optional<int64_t> llvm::getConstantVRegVal(unsigned VReg,
107 const MachineRegisterInfo &MRI) {
108 MachineInstr *MI = MRI.getVRegDef(VReg);
109 if (MI->getOpcode() != TargetOpcode::G_CONSTANT)
112 if (MI->getOperand(1).isImm())
113 return MI->getOperand(1).getImm();
115 if (MI->getOperand(1).isCImm() &&
116 MI->getOperand(1).getCImm()->getBitWidth() <= 64)
117 return MI->getOperand(1).getCImm()->getSExtValue();
122 const llvm::ConstantFP* llvm::getConstantFPVRegVal(unsigned VReg,
123 const MachineRegisterInfo &MRI) {
124 MachineInstr *MI = MRI.getVRegDef(VReg);
125 if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
127 return MI->getOperand(1).getFPImm();