1 //===-------- InlineSpiller.cpp - Insert spills and restores inline -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // The inline spiller modifies the machine function directly instead of
11 // inserting spills and restores in VirtRegMap.
13 //===----------------------------------------------------------------------===//
17 #include "llvm/ADT/MapVector.h"
18 #include "llvm/ADT/SetVector.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/ADT/TinyPtrVector.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
23 #include "llvm/CodeGen/LiveRangeEdit.h"
24 #include "llvm/CodeGen/LiveStackAnalysis.h"
25 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
26 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
27 #include "llvm/CodeGen/MachineDominators.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineInstrBundle.h"
32 #include "llvm/CodeGen/MachineLoopInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/VirtRegMap.h"
35 #include "llvm/IR/DebugInfo.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetInstrInfo.h"
43 #define DEBUG_TYPE "regalloc"
45 STATISTIC(NumSpilledRanges, "Number of spilled live ranges");
46 STATISTIC(NumSnippets, "Number of spilled snippets");
47 STATISTIC(NumSpills, "Number of spills inserted");
48 STATISTIC(NumSpillsRemoved, "Number of spills removed");
49 STATISTIC(NumReloads, "Number of reloads inserted");
50 STATISTIC(NumReloadsRemoved, "Number of reloads removed");
51 STATISTIC(NumFolded, "Number of folded stack accesses");
52 STATISTIC(NumFoldedLoads, "Number of folded loads");
53 STATISTIC(NumRemats, "Number of rematerialized defs for spilling");
55 static cl::opt<bool> DisableHoisting("disable-spill-hoist", cl::Hidden,
56 cl::desc("Disable inline spill hoisting"));
59 class HoistSpillHelper : private LiveRangeEdit::Delegate {
64 MachineDominatorTree &MDT;
65 MachineLoopInfo &Loops;
67 MachineFrameInfo &MFI;
68 MachineRegisterInfo &MRI;
69 const TargetInstrInfo &TII;
70 const TargetRegisterInfo &TRI;
71 const MachineBlockFrequencyInfo &MBFI;
73 InsertPointAnalysis IPA;
75 // Map from StackSlot to its original register.
76 DenseMap<int, unsigned> StackSlotToReg;
77 // Map from pair of (StackSlot and Original VNI) to a set of spills which
78 // have the same stackslot and have equal values defined by Original VNI.
79 // These spills are mergeable and are hoist candiates.
80 typedef MapVector<std::pair<int, VNInfo *>, SmallPtrSet<MachineInstr *, 16>>
82 MergeableSpillsMap MergeableSpills;
84 /// This is the map from original register to a set containing all its
85 /// siblings. To hoist a spill to another BB, we need to find out a live
86 /// sibling there and use it as the source of the new spill.
87 DenseMap<unsigned, SmallSetVector<unsigned, 16>> Virt2SiblingsMap;
89 bool isSpillCandBB(unsigned OrigReg, VNInfo &OrigVNI, MachineBasicBlock &BB,
92 void rmRedundantSpills(
93 SmallPtrSet<MachineInstr *, 16> &Spills,
94 SmallVectorImpl<MachineInstr *> &SpillsToRm,
95 DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill);
98 MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills,
99 SmallVectorImpl<MachineDomTreeNode *> &Orders,
100 SmallVectorImpl<MachineInstr *> &SpillsToRm,
101 DenseMap<MachineDomTreeNode *, unsigned> &SpillsToKeep,
102 DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill);
104 void runHoistSpills(unsigned OrigReg, VNInfo &OrigVNI,
105 SmallPtrSet<MachineInstr *, 16> &Spills,
106 SmallVectorImpl<MachineInstr *> &SpillsToRm,
107 DenseMap<MachineBasicBlock *, unsigned> &SpillsToIns);
110 HoistSpillHelper(MachineFunctionPass &pass, MachineFunction &mf,
112 : MF(mf), LIS(pass.getAnalysis<LiveIntervals>()),
113 LSS(pass.getAnalysis<LiveStacks>()),
114 AA(&pass.getAnalysis<AAResultsWrapperPass>().getAAResults()),
115 MDT(pass.getAnalysis<MachineDominatorTree>()),
116 Loops(pass.getAnalysis<MachineLoopInfo>()), VRM(vrm),
117 MFI(mf.getFrameInfo()), MRI(mf.getRegInfo()),
118 TII(*mf.getSubtarget().getInstrInfo()),
119 TRI(*mf.getSubtarget().getRegisterInfo()),
120 MBFI(pass.getAnalysis<MachineBlockFrequencyInfo>()),
121 IPA(LIS, mf.getNumBlockIDs()) {}
123 void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
125 bool rmFromMergeableSpills(MachineInstr &Spill, int StackSlot);
126 void hoistAllSpills();
127 void LRE_DidCloneVirtReg(unsigned, unsigned) override;
130 class InlineSpiller : public Spiller {
135 MachineDominatorTree &MDT;
136 MachineLoopInfo &Loops;
138 MachineFrameInfo &MFI;
139 MachineRegisterInfo &MRI;
140 const TargetInstrInfo &TII;
141 const TargetRegisterInfo &TRI;
142 const MachineBlockFrequencyInfo &MBFI;
144 // Variables that are valid during spill(), but used by multiple methods.
146 LiveInterval *StackInt;
150 // All registers to spill to StackSlot, including the main register.
151 SmallVector<unsigned, 8> RegsToSpill;
153 // All COPY instructions to/from snippets.
154 // They are ignored since both operands refer to the same stack slot.
155 SmallPtrSet<MachineInstr*, 8> SnippetCopies;
157 // Values that failed to remat at some point.
158 SmallPtrSet<VNInfo*, 8> UsedValues;
160 // Dead defs generated during spilling.
161 SmallVector<MachineInstr*, 8> DeadDefs;
163 // Object records spills information and does the hoisting.
164 HoistSpillHelper HSpiller;
166 ~InlineSpiller() override {}
169 InlineSpiller(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm)
170 : MF(mf), LIS(pass.getAnalysis<LiveIntervals>()),
171 LSS(pass.getAnalysis<LiveStacks>()),
172 AA(&pass.getAnalysis<AAResultsWrapperPass>().getAAResults()),
173 MDT(pass.getAnalysis<MachineDominatorTree>()),
174 Loops(pass.getAnalysis<MachineLoopInfo>()), VRM(vrm),
175 MFI(mf.getFrameInfo()), MRI(mf.getRegInfo()),
176 TII(*mf.getSubtarget().getInstrInfo()),
177 TRI(*mf.getSubtarget().getRegisterInfo()),
178 MBFI(pass.getAnalysis<MachineBlockFrequencyInfo>()),
179 HSpiller(pass, mf, vrm) {}
181 void spill(LiveRangeEdit &) override;
182 void postOptimization() override;
185 bool isSnippet(const LiveInterval &SnipLI);
186 void collectRegsToSpill();
188 bool isRegToSpill(unsigned Reg) { return is_contained(RegsToSpill, Reg); }
190 bool isSibling(unsigned Reg);
191 bool hoistSpillInsideBB(LiveInterval &SpillLI, MachineInstr &CopyMI);
192 void eliminateRedundantSpills(LiveInterval &LI, VNInfo *VNI);
194 void markValueUsed(LiveInterval*, VNInfo*);
195 bool reMaterializeFor(LiveInterval &, MachineInstr &MI);
196 void reMaterializeAll();
198 bool coalesceStackAccess(MachineInstr *MI, unsigned Reg);
199 bool foldMemoryOperand(ArrayRef<std::pair<MachineInstr*, unsigned> >,
200 MachineInstr *LoadMI = nullptr);
201 void insertReload(unsigned VReg, SlotIndex, MachineBasicBlock::iterator MI);
202 void insertSpill(unsigned VReg, bool isKill, MachineBasicBlock::iterator MI);
204 void spillAroundUses(unsigned Reg);
211 Spiller::~Spiller() { }
212 void Spiller::anchor() { }
214 Spiller *createInlineSpiller(MachineFunctionPass &pass,
217 return new InlineSpiller(pass, mf, vrm);
222 //===----------------------------------------------------------------------===//
224 //===----------------------------------------------------------------------===//
226 // When spilling a virtual register, we also spill any snippets it is connected
227 // to. The snippets are small live ranges that only have a single real use,
228 // leftovers from live range splitting. Spilling them enables memory operand
229 // folding or tightens the live range around the single use.
231 // This minimizes register pressure and maximizes the store-to-load distance for
232 // spill slots which can be important in tight loops.
234 /// isFullCopyOf - If MI is a COPY to or from Reg, return the other register,
235 /// otherwise return 0.
236 static unsigned isFullCopyOf(const MachineInstr &MI, unsigned Reg) {
237 if (!MI.isFullCopy())
239 if (MI.getOperand(0).getReg() == Reg)
240 return MI.getOperand(1).getReg();
241 if (MI.getOperand(1).getReg() == Reg)
242 return MI.getOperand(0).getReg();
246 /// isSnippet - Identify if a live interval is a snippet that should be spilled.
247 /// It is assumed that SnipLI is a virtual register with the same original as
249 bool InlineSpiller::isSnippet(const LiveInterval &SnipLI) {
250 unsigned Reg = Edit->getReg();
252 // A snippet is a tiny live range with only a single instruction using it
253 // besides copies to/from Reg or spills/fills. We accept:
255 // %snip = COPY %Reg / FILL fi#
257 // %Reg = COPY %snip / SPILL %snip, fi#
259 if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI))
262 MachineInstr *UseMI = nullptr;
264 // Check that all uses satisfy our criteria.
265 for (MachineRegisterInfo::reg_instr_nodbg_iterator
266 RI = MRI.reg_instr_nodbg_begin(SnipLI.reg),
267 E = MRI.reg_instr_nodbg_end(); RI != E; ) {
268 MachineInstr &MI = *RI++;
270 // Allow copies to/from Reg.
271 if (isFullCopyOf(MI, Reg))
274 // Allow stack slot loads.
276 if (SnipLI.reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot)
279 // Allow stack slot stores.
280 if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot)
283 // Allow a single additional instruction.
284 if (UseMI && &MI != UseMI)
291 /// collectRegsToSpill - Collect live range snippets that only have a single
293 void InlineSpiller::collectRegsToSpill() {
294 unsigned Reg = Edit->getReg();
296 // Main register always spills.
297 RegsToSpill.assign(1, Reg);
298 SnippetCopies.clear();
300 // Snippets all have the same original, so there can't be any for an original
305 for (MachineRegisterInfo::reg_instr_iterator
306 RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end(); RI != E; ) {
307 MachineInstr &MI = *RI++;
308 unsigned SnipReg = isFullCopyOf(MI, Reg);
309 if (!isSibling(SnipReg))
311 LiveInterval &SnipLI = LIS.getInterval(SnipReg);
312 if (!isSnippet(SnipLI))
314 SnippetCopies.insert(&MI);
315 if (isRegToSpill(SnipReg))
317 RegsToSpill.push_back(SnipReg);
318 DEBUG(dbgs() << "\talso spill snippet " << SnipLI << '\n');
323 bool InlineSpiller::isSibling(unsigned Reg) {
324 return TargetRegisterInfo::isVirtualRegister(Reg) &&
325 VRM.getOriginal(Reg) == Original;
328 /// It is beneficial to spill to earlier place in the same BB in case
330 /// There is an alternative def earlier in the same MBB.
331 /// Hoist the spill as far as possible in SpillMBB. This can ease
332 /// register pressure:
338 /// Hoisting the spill of s to immediately after the def removes the
339 /// interference between x and y:
345 /// This hoist only helps when the copy kills its source.
347 bool InlineSpiller::hoistSpillInsideBB(LiveInterval &SpillLI,
348 MachineInstr &CopyMI) {
349 SlotIndex Idx = LIS.getInstructionIndex(CopyMI);
351 VNInfo *VNI = SpillLI.getVNInfoAt(Idx.getRegSlot());
352 assert(VNI && VNI->def == Idx.getRegSlot() && "Not defined by copy");
355 unsigned SrcReg = CopyMI.getOperand(1).getReg();
356 LiveInterval &SrcLI = LIS.getInterval(SrcReg);
357 VNInfo *SrcVNI = SrcLI.getVNInfoAt(Idx);
358 LiveQueryResult SrcQ = SrcLI.Query(Idx);
359 MachineBasicBlock *DefMBB = LIS.getMBBFromIndex(SrcVNI->def);
360 if (DefMBB != CopyMI.getParent() || !SrcQ.isKill())
363 // Conservatively extend the stack slot range to the range of the original
364 // value. We may be able to do better with stack slot coloring by being more
366 assert(StackInt && "No stack slot assigned yet.");
367 LiveInterval &OrigLI = LIS.getInterval(Original);
368 VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
369 StackInt->MergeValueInAsValue(OrigLI, OrigVNI, StackInt->getValNumInfo(0));
370 DEBUG(dbgs() << "\tmerged orig valno " << OrigVNI->id << ": "
371 << *StackInt << '\n');
373 // We are going to spill SrcVNI immediately after its def, so clear out
374 // any later spills of the same value.
375 eliminateRedundantSpills(SrcLI, SrcVNI);
377 MachineBasicBlock *MBB = LIS.getMBBFromIndex(SrcVNI->def);
378 MachineBasicBlock::iterator MII;
379 if (SrcVNI->isPHIDef())
380 MII = MBB->SkipPHIsLabelsAndDebug(MBB->begin());
382 MachineInstr *DefMI = LIS.getInstructionFromIndex(SrcVNI->def);
383 assert(DefMI && "Defining instruction disappeared");
387 // Insert spill without kill flag immediately after def.
388 TII.storeRegToStackSlot(*MBB, MII, SrcReg, false, StackSlot,
389 MRI.getRegClass(SrcReg), &TRI);
390 --MII; // Point to store instruction.
391 LIS.InsertMachineInstrInMaps(*MII);
392 DEBUG(dbgs() << "\thoisted: " << SrcVNI->def << '\t' << *MII);
394 HSpiller.addToMergeableSpills(*MII, StackSlot, Original);
399 /// eliminateRedundantSpills - SLI:VNI is known to be on the stack. Remove any
400 /// redundant spills of this value in SLI.reg and sibling copies.
401 void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
402 assert(VNI && "Missing value");
403 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
404 WorkList.push_back(std::make_pair(&SLI, VNI));
405 assert(StackInt && "No stack slot assigned yet.");
409 std::tie(LI, VNI) = WorkList.pop_back_val();
410 unsigned Reg = LI->reg;
411 DEBUG(dbgs() << "Checking redundant spills for "
412 << VNI->id << '@' << VNI->def << " in " << *LI << '\n');
414 // Regs to spill are taken care of.
415 if (isRegToSpill(Reg))
418 // Add all of VNI's live range to StackInt.
419 StackInt->MergeValueInAsValue(*LI, VNI, StackInt->getValNumInfo(0));
420 DEBUG(dbgs() << "Merged to stack int: " << *StackInt << '\n');
422 // Find all spills and copies of VNI.
423 for (MachineRegisterInfo::use_instr_nodbg_iterator
424 UI = MRI.use_instr_nodbg_begin(Reg), E = MRI.use_instr_nodbg_end();
426 MachineInstr &MI = *UI++;
427 if (!MI.isCopy() && !MI.mayStore())
429 SlotIndex Idx = LIS.getInstructionIndex(MI);
430 if (LI->getVNInfoAt(Idx) != VNI)
433 // Follow sibling copies down the dominator tree.
434 if (unsigned DstReg = isFullCopyOf(MI, Reg)) {
435 if (isSibling(DstReg)) {
436 LiveInterval &DstLI = LIS.getInterval(DstReg);
437 VNInfo *DstVNI = DstLI.getVNInfoAt(Idx.getRegSlot());
438 assert(DstVNI && "Missing defined value");
439 assert(DstVNI->def == Idx.getRegSlot() && "Wrong copy def slot");
440 WorkList.push_back(std::make_pair(&DstLI, DstVNI));
447 if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) {
448 DEBUG(dbgs() << "Redundant spill " << Idx << '\t' << MI);
449 // eliminateDeadDefs won't normally remove stores, so switch opcode.
450 MI.setDesc(TII.get(TargetOpcode::KILL));
451 DeadDefs.push_back(&MI);
453 if (HSpiller.rmFromMergeableSpills(MI, StackSlot))
457 } while (!WorkList.empty());
461 //===----------------------------------------------------------------------===//
463 //===----------------------------------------------------------------------===//
465 /// markValueUsed - Remember that VNI failed to rematerialize, so its defining
466 /// instruction cannot be eliminated. See through snippet copies
467 void InlineSpiller::markValueUsed(LiveInterval *LI, VNInfo *VNI) {
468 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
469 WorkList.push_back(std::make_pair(LI, VNI));
471 std::tie(LI, VNI) = WorkList.pop_back_val();
472 if (!UsedValues.insert(VNI).second)
475 if (VNI->isPHIDef()) {
476 MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
477 for (MachineBasicBlock *P : MBB->predecessors()) {
478 VNInfo *PVNI = LI->getVNInfoBefore(LIS.getMBBEndIdx(P));
480 WorkList.push_back(std::make_pair(LI, PVNI));
485 // Follow snippet copies.
486 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
487 if (!SnippetCopies.count(MI))
489 LiveInterval &SnipLI = LIS.getInterval(MI->getOperand(1).getReg());
490 assert(isRegToSpill(SnipLI.reg) && "Unexpected register in copy");
491 VNInfo *SnipVNI = SnipLI.getVNInfoAt(VNI->def.getRegSlot(true));
492 assert(SnipVNI && "Snippet undefined before copy");
493 WorkList.push_back(std::make_pair(&SnipLI, SnipVNI));
494 } while (!WorkList.empty());
497 /// reMaterializeFor - Attempt to rematerialize before MI instead of reloading.
498 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) {
500 // Analyze instruction
501 SmallVector<std::pair<MachineInstr *, unsigned>, 8> Ops;
502 MIBundleOperands::VirtRegInfo RI =
503 MIBundleOperands(MI).analyzeVirtReg(VirtReg.reg, &Ops);
508 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true);
509 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
512 DEBUG(dbgs() << "\tadding <undef> flags: ");
513 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
514 MachineOperand &MO = MI.getOperand(i);
515 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
518 DEBUG(dbgs() << UseIdx << '\t' << MI);
522 if (SnippetCopies.count(&MI))
525 LiveInterval &OrigLI = LIS.getInterval(Original);
526 VNInfo *OrigVNI = OrigLI.getVNInfoAt(UseIdx);
527 LiveRangeEdit::Remat RM(ParentVNI);
528 RM.OrigMI = LIS.getInstructionFromIndex(OrigVNI->def);
530 if (!Edit->canRematerializeAt(RM, OrigVNI, UseIdx, false)) {
531 markValueUsed(&VirtReg, ParentVNI);
532 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << MI);
536 // If the instruction also writes VirtReg.reg, it had better not require the
537 // same register for uses and defs.
539 markValueUsed(&VirtReg, ParentVNI);
540 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << MI);
544 // Before rematerializing into a register for a single instruction, try to
545 // fold a load into the instruction. That avoids allocating a new register.
546 if (RM.OrigMI->canFoldAsLoad() &&
547 foldMemoryOperand(Ops, RM.OrigMI)) {
548 Edit->markRematerialized(RM.ParentVNI);
553 // Allocate a new register for the remat.
554 unsigned NewVReg = Edit->createFrom(Original);
556 // Finally we can rematerialize OrigMI before MI.
558 Edit->rematerializeAt(*MI.getParent(), MI, NewVReg, RM, TRI);
560 // We take the DebugLoc from MI, since OrigMI may be attributed to a
561 // different source location.
562 auto *NewMI = LIS.getInstructionFromIndex(DefIdx);
563 NewMI->setDebugLoc(MI.getDebugLoc());
566 DEBUG(dbgs() << "\tremat: " << DefIdx << '\t'
567 << *LIS.getInstructionFromIndex(DefIdx));
570 for (const auto &OpPair : Ops) {
571 MachineOperand &MO = OpPair.first->getOperand(OpPair.second);
572 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
577 DEBUG(dbgs() << "\t " << UseIdx << '\t' << MI << '\n');
583 /// reMaterializeAll - Try to rematerialize as many uses as possible,
584 /// and trim the live ranges after.
585 void InlineSpiller::reMaterializeAll() {
586 if (!Edit->anyRematerializable(AA))
591 // Try to remat before all uses of snippets.
592 bool anyRemat = false;
593 for (unsigned Reg : RegsToSpill) {
594 LiveInterval &LI = LIS.getInterval(Reg);
595 for (MachineRegisterInfo::reg_bundle_iterator
596 RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end();
598 MachineInstr &MI = *RegI++;
600 // Debug values are not allowed to affect codegen.
601 if (MI.isDebugValue())
604 anyRemat |= reMaterializeFor(LI, MI);
610 // Remove any values that were completely rematted.
611 for (unsigned Reg : RegsToSpill) {
612 LiveInterval &LI = LIS.getInterval(Reg);
613 for (LiveInterval::vni_iterator I = LI.vni_begin(), E = LI.vni_end();
616 if (VNI->isUnused() || VNI->isPHIDef() || UsedValues.count(VNI))
618 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
619 MI->addRegisterDead(Reg, &TRI);
620 if (!MI->allDefsAreDead())
622 DEBUG(dbgs() << "All defs dead: " << *MI);
623 DeadDefs.push_back(MI);
627 // Eliminate dead code after remat. Note that some snippet copies may be
629 if (DeadDefs.empty())
631 DEBUG(dbgs() << "Remat created " << DeadDefs.size() << " dead defs.\n");
632 Edit->eliminateDeadDefs(DeadDefs, RegsToSpill, AA);
634 // LiveRangeEdit::eliminateDeadDef is used to remove dead define instructions
635 // after rematerialization. To remove a VNI for a vreg from its LiveInterval,
636 // LiveIntervals::removeVRegDefAt is used. However, after non-PHI VNIs are all
637 // removed, PHI VNI are still left in the LiveInterval.
638 // So to get rid of unused reg, we need to check whether it has non-dbg
639 // reference instead of whether it has non-empty interval.
640 unsigned ResultPos = 0;
641 for (unsigned Reg : RegsToSpill) {
642 if (MRI.reg_nodbg_empty(Reg)) {
643 Edit->eraseVirtReg(Reg);
647 assert(LIS.hasInterval(Reg) &&
648 (!LIS.getInterval(Reg).empty() || !MRI.reg_nodbg_empty(Reg)) &&
649 "Empty and not used live-range?!");
651 RegsToSpill[ResultPos++] = Reg;
653 RegsToSpill.erase(RegsToSpill.begin() + ResultPos, RegsToSpill.end());
654 DEBUG(dbgs() << RegsToSpill.size() << " registers to spill after remat.\n");
658 //===----------------------------------------------------------------------===//
660 //===----------------------------------------------------------------------===//
662 /// If MI is a load or store of StackSlot, it can be removed.
663 bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) {
665 unsigned InstrReg = TII.isLoadFromStackSlot(*MI, FI);
666 bool IsLoad = InstrReg;
668 InstrReg = TII.isStoreToStackSlot(*MI, FI);
670 // We have a stack access. Is it the right register and slot?
671 if (InstrReg != Reg || FI != StackSlot)
675 HSpiller.rmFromMergeableSpills(*MI, StackSlot);
677 DEBUG(dbgs() << "Coalescing stack access: " << *MI);
678 LIS.RemoveMachineInstrFromMaps(*MI);
679 MI->eraseFromParent();
692 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
694 // Dump the range of instructions from B to E with their slot indexes.
695 static void dumpMachineInstrRangeWithSlotIndex(MachineBasicBlock::iterator B,
696 MachineBasicBlock::iterator E,
697 LiveIntervals const &LIS,
698 const char *const header,
700 char NextLine = '\n';
701 char SlotIndent = '\t';
703 if (std::next(B) == E) {
708 dbgs() << '\t' << header << ": " << NextLine;
710 for (MachineBasicBlock::iterator I = B; I != E; ++I) {
711 SlotIndex Idx = LIS.getInstructionIndex(*I).getRegSlot();
713 // If a register was passed in and this instruction has it as a
714 // destination that is marked as an early clobber, print the
715 // early-clobber slot index.
717 MachineOperand *MO = I->findRegisterDefOperand(VReg);
718 if (MO && MO->isEarlyClobber())
719 Idx = Idx.getRegSlot(true);
722 dbgs() << SlotIndent << Idx << '\t' << *I;
727 /// foldMemoryOperand - Try folding stack slot references in Ops into their
730 /// @param Ops Operand indices from analyzeVirtReg().
731 /// @param LoadMI Load instruction to use instead of stack slot when non-null.
732 /// @return True on success.
734 foldMemoryOperand(ArrayRef<std::pair<MachineInstr*, unsigned> > Ops,
735 MachineInstr *LoadMI) {
738 // Don't attempt folding in bundles.
739 MachineInstr *MI = Ops.front().first;
740 if (Ops.back().first != MI || MI->isBundled())
743 bool WasCopy = MI->isCopy();
746 // Spill subregs if the target allows it.
747 // We always want to spill subregs for stackmap/patchpoint pseudos.
748 bool SpillSubRegs = TII.isSubregFoldable() ||
749 MI->getOpcode() == TargetOpcode::STATEPOINT ||
750 MI->getOpcode() == TargetOpcode::PATCHPOINT ||
751 MI->getOpcode() == TargetOpcode::STACKMAP;
753 // TargetInstrInfo::foldMemoryOperand only expects explicit, non-tied
755 SmallVector<unsigned, 8> FoldOps;
756 for (const auto &OpPair : Ops) {
757 unsigned Idx = OpPair.second;
758 assert(MI == OpPair.first && "Instruction conflict during operand folding");
759 MachineOperand &MO = MI->getOperand(Idx);
760 if (MO.isImplicit()) {
761 ImpReg = MO.getReg();
765 if (!SpillSubRegs && MO.getSubReg())
767 // We cannot fold a load instruction into a def.
768 if (LoadMI && MO.isDef())
770 // Tied use operands should not be passed to foldMemoryOperand.
771 if (!MI->isRegTiedToDefOperand(Idx))
772 FoldOps.push_back(Idx);
775 // If we only have implicit uses, we won't be able to fold that.
776 // Moreover, TargetInstrInfo::foldMemoryOperand will assert if we try!
780 MachineInstrSpan MIS(MI);
782 MachineInstr *FoldMI =
783 LoadMI ? TII.foldMemoryOperand(*MI, FoldOps, *LoadMI, &LIS)
784 : TII.foldMemoryOperand(*MI, FoldOps, StackSlot, &LIS);
788 // Remove LIS for any dead defs in the original MI not in FoldMI.
789 for (MIBundleOperands MO(*MI); MO.isValid(); ++MO) {
792 unsigned Reg = MO->getReg();
793 if (!Reg || TargetRegisterInfo::isVirtualRegister(Reg) ||
794 MRI.isReserved(Reg)) {
797 // Skip non-Defs, including undef uses and internal reads.
800 MIBundleOperands::PhysRegInfo RI =
801 MIBundleOperands(*FoldMI).analyzePhysReg(Reg, &TRI);
804 // FoldMI does not define this physreg. Remove the LI segment.
805 assert(MO->isDead() && "Cannot fold physreg def");
806 SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
807 LIS.removePhysRegDefAt(Reg, Idx);
811 if (TII.isStoreToStackSlot(*MI, FI) &&
812 HSpiller.rmFromMergeableSpills(*MI, FI))
814 LIS.ReplaceMachineInstrInMaps(*MI, *FoldMI);
815 MI->eraseFromParent();
817 // Insert any new instructions other than FoldMI into the LIS maps.
818 assert(!MIS.empty() && "Unexpected empty span of instructions!");
819 for (MachineInstr &MI : MIS)
821 LIS.InsertMachineInstrInMaps(MI);
823 // TII.foldMemoryOperand may have left some implicit operands on the
824 // instruction. Strip them.
826 for (unsigned i = FoldMI->getNumOperands(); i; --i) {
827 MachineOperand &MO = FoldMI->getOperand(i - 1);
828 if (!MO.isReg() || !MO.isImplicit())
830 if (MO.getReg() == ImpReg)
831 FoldMI->RemoveOperand(i - 1);
834 DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MIS.end(), LIS,
839 else if (Ops.front().second == 0) {
841 HSpiller.addToMergeableSpills(*FoldMI, StackSlot, Original);
847 void InlineSpiller::insertReload(unsigned NewVReg,
849 MachineBasicBlock::iterator MI) {
850 MachineBasicBlock &MBB = *MI->getParent();
852 MachineInstrSpan MIS(MI);
853 TII.loadRegFromStackSlot(MBB, MI, NewVReg, StackSlot,
854 MRI.getRegClass(NewVReg), &TRI);
856 LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MI);
858 DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MI, LIS, "reload",
863 /// Check if \p Def fully defines a VReg with an undefined value.
864 /// If that's the case, that means the value of VReg is actually
866 static bool isFullUndefDef(const MachineInstr &Def) {
867 if (!Def.isImplicitDef())
869 assert(Def.getNumOperands() == 1 &&
870 "Implicit def with more than one definition");
871 // We can say that the VReg defined by Def is undef, only if it is
872 // fully defined by Def. Otherwise, some of the lanes may not be
873 // undef and the value of the VReg matters.
874 return !Def.getOperand(0).getSubReg();
877 /// insertSpill - Insert a spill of NewVReg after MI.
878 void InlineSpiller::insertSpill(unsigned NewVReg, bool isKill,
879 MachineBasicBlock::iterator MI) {
880 MachineBasicBlock &MBB = *MI->getParent();
882 MachineInstrSpan MIS(MI);
883 bool IsRealSpill = true;
884 if (isFullUndefDef(*MI)) {
885 // Don't spill undef value.
886 // Anything works for undef, in particular keeping the memory
887 // uninitialized is a viable option and it saves code size and
889 BuildMI(MBB, std::next(MI), MI->getDebugLoc(), TII.get(TargetOpcode::KILL))
890 .addReg(NewVReg, getKillRegState(isKill));
893 TII.storeRegToStackSlot(MBB, std::next(MI), NewVReg, isKill, StackSlot,
894 MRI.getRegClass(NewVReg), &TRI);
896 LIS.InsertMachineInstrRangeInMaps(std::next(MI), MIS.end());
898 DEBUG(dumpMachineInstrRangeWithSlotIndex(std::next(MI), MIS.end(), LIS,
902 HSpiller.addToMergeableSpills(*std::next(MI), StackSlot, Original);
905 /// spillAroundUses - insert spill code around each use of Reg.
906 void InlineSpiller::spillAroundUses(unsigned Reg) {
907 DEBUG(dbgs() << "spillAroundUses " << PrintReg(Reg) << '\n');
908 LiveInterval &OldLI = LIS.getInterval(Reg);
910 // Iterate over instructions using Reg.
911 for (MachineRegisterInfo::reg_bundle_iterator
912 RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end();
914 MachineInstr *MI = &*(RegI++);
916 // Debug values are not allowed to affect codegen.
917 if (MI->isDebugValue()) {
918 // Modify DBG_VALUE now that the value is in a spill slot.
919 MachineBasicBlock *MBB = MI->getParent();
920 DEBUG(dbgs() << "Modifying debug info due to spill:\t" << *MI);
921 buildDbgValueForSpill(*MBB, MI, *MI, StackSlot);
926 // Ignore copies to/from snippets. We'll delete them.
927 if (SnippetCopies.count(MI))
930 // Stack slot accesses may coalesce away.
931 if (coalesceStackAccess(MI, Reg))
934 // Analyze instruction.
935 SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops;
936 MIBundleOperands::VirtRegInfo RI =
937 MIBundleOperands(*MI).analyzeVirtReg(Reg, &Ops);
939 // Find the slot index where this instruction reads and writes OldLI.
940 // This is usually the def slot, except for tied early clobbers.
941 SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
942 if (VNInfo *VNI = OldLI.getVNInfoAt(Idx.getRegSlot(true)))
943 if (SlotIndex::isSameInstr(Idx, VNI->def))
946 // Check for a sibling copy.
947 unsigned SibReg = isFullCopyOf(*MI, Reg);
948 if (SibReg && isSibling(SibReg)) {
949 // This may actually be a copy between snippets.
950 if (isRegToSpill(SibReg)) {
951 DEBUG(dbgs() << "Found new snippet copy: " << *MI);
952 SnippetCopies.insert(MI);
956 if (hoistSpillInsideBB(OldLI, *MI)) {
957 // This COPY is now dead, the value is already in the stack slot.
958 MI->getOperand(0).setIsDead();
959 DeadDefs.push_back(MI);
963 // This is a reload for a sib-reg copy. Drop spills downstream.
964 LiveInterval &SibLI = LIS.getInterval(SibReg);
965 eliminateRedundantSpills(SibLI, SibLI.getVNInfoAt(Idx));
966 // The COPY will fold to a reload below.
970 // Attempt to fold memory ops.
971 if (foldMemoryOperand(Ops))
974 // Create a new virtual register for spill/fill.
975 // FIXME: Infer regclass from instruction alone.
976 unsigned NewVReg = Edit->createFrom(Reg);
979 insertReload(NewVReg, Idx, MI);
981 // Rewrite instruction operands.
982 bool hasLiveDef = false;
983 for (const auto &OpPair : Ops) {
984 MachineOperand &MO = OpPair.first->getOperand(OpPair.second);
987 if (!OpPair.first->isRegTiedToDefOperand(OpPair.second))
994 DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI << '\n');
996 // FIXME: Use a second vreg if instruction has no tied ops.
999 insertSpill(NewVReg, true, MI);
1003 /// spillAll - Spill all registers remaining after rematerialization.
1004 void InlineSpiller::spillAll() {
1005 // Update LiveStacks now that we are committed to spilling.
1006 if (StackSlot == VirtRegMap::NO_STACK_SLOT) {
1007 StackSlot = VRM.assignVirt2StackSlot(Original);
1008 StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original));
1009 StackInt->getNextValue(SlotIndex(), LSS.getVNInfoAllocator());
1011 StackInt = &LSS.getInterval(StackSlot);
1013 if (Original != Edit->getReg())
1014 VRM.assignVirt2StackSlot(Edit->getReg(), StackSlot);
1016 assert(StackInt->getNumValNums() == 1 && "Bad stack interval values");
1017 for (unsigned Reg : RegsToSpill)
1018 StackInt->MergeSegmentsInAsValue(LIS.getInterval(Reg),
1019 StackInt->getValNumInfo(0));
1020 DEBUG(dbgs() << "Merged spilled regs: " << *StackInt << '\n');
1022 // Spill around uses of all RegsToSpill.
1023 for (unsigned Reg : RegsToSpill)
1024 spillAroundUses(Reg);
1026 // Hoisted spills may cause dead code.
1027 if (!DeadDefs.empty()) {
1028 DEBUG(dbgs() << "Eliminating " << DeadDefs.size() << " dead defs\n");
1029 Edit->eliminateDeadDefs(DeadDefs, RegsToSpill, AA);
1032 // Finally delete the SnippetCopies.
1033 for (unsigned Reg : RegsToSpill) {
1034 for (MachineRegisterInfo::reg_instr_iterator
1035 RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end();
1037 MachineInstr &MI = *(RI++);
1038 assert(SnippetCopies.count(&MI) && "Remaining use wasn't a snippet copy");
1039 // FIXME: Do this with a LiveRangeEdit callback.
1040 LIS.RemoveMachineInstrFromMaps(MI);
1041 MI.eraseFromParent();
1045 // Delete all spilled registers.
1046 for (unsigned Reg : RegsToSpill)
1047 Edit->eraseVirtReg(Reg);
1050 void InlineSpiller::spill(LiveRangeEdit &edit) {
1053 assert(!TargetRegisterInfo::isStackSlot(edit.getReg())
1054 && "Trying to spill a stack slot.");
1055 // Share a stack slot among all descendants of Original.
1056 Original = VRM.getOriginal(edit.getReg());
1057 StackSlot = VRM.getStackSlot(Original);
1060 DEBUG(dbgs() << "Inline spilling "
1061 << TRI.getRegClassName(MRI.getRegClass(edit.getReg()))
1062 << ':' << edit.getParent()
1063 << "\nFrom original " << PrintReg(Original) << '\n');
1064 assert(edit.getParent().isSpillable() &&
1065 "Attempting to spill already spilled value.");
1066 assert(DeadDefs.empty() && "Previous spill didn't remove dead defs");
1068 collectRegsToSpill();
1071 // Remat may handle everything.
1072 if (!RegsToSpill.empty())
1075 Edit->calculateRegClassAndHint(MF, Loops, MBFI);
1078 /// Optimizations after all the reg selections and spills are done.
1080 void InlineSpiller::postOptimization() { HSpiller.hoistAllSpills(); }
1082 /// When a spill is inserted, add the spill to MergeableSpills map.
1084 void HoistSpillHelper::addToMergeableSpills(MachineInstr &Spill, int StackSlot,
1085 unsigned Original) {
1086 StackSlotToReg[StackSlot] = Original;
1087 SlotIndex Idx = LIS.getInstructionIndex(Spill);
1088 VNInfo *OrigVNI = LIS.getInterval(Original).getVNInfoAt(Idx.getRegSlot());
1089 std::pair<int, VNInfo *> MIdx = std::make_pair(StackSlot, OrigVNI);
1090 MergeableSpills[MIdx].insert(&Spill);
1093 /// When a spill is removed, remove the spill from MergeableSpills map.
1094 /// Return true if the spill is removed successfully.
1096 bool HoistSpillHelper::rmFromMergeableSpills(MachineInstr &Spill,
1098 int Original = StackSlotToReg[StackSlot];
1101 SlotIndex Idx = LIS.getInstructionIndex(Spill);
1102 VNInfo *OrigVNI = LIS.getInterval(Original).getVNInfoAt(Idx.getRegSlot());
1103 std::pair<int, VNInfo *> MIdx = std::make_pair(StackSlot, OrigVNI);
1104 return MergeableSpills[MIdx].erase(&Spill);
1107 /// Check BB to see if it is a possible target BB to place a hoisted spill,
1108 /// i.e., there should be a living sibling of OrigReg at the insert point.
1110 bool HoistSpillHelper::isSpillCandBB(unsigned OrigReg, VNInfo &OrigVNI,
1111 MachineBasicBlock &BB, unsigned &LiveReg) {
1113 LiveInterval &OrigLI = LIS.getInterval(OrigReg);
1114 MachineBasicBlock::iterator MI = IPA.getLastInsertPointIter(OrigLI, BB);
1116 Idx = LIS.getInstructionIndex(*MI);
1118 Idx = LIS.getMBBEndIdx(&BB).getPrevSlot();
1119 SmallSetVector<unsigned, 16> &Siblings = Virt2SiblingsMap[OrigReg];
1120 assert((LIS.getInterval(OrigReg)).getVNInfoAt(Idx) == &OrigVNI &&
1123 for (auto const SibReg : Siblings) {
1124 LiveInterval &LI = LIS.getInterval(SibReg);
1125 VNInfo *VNI = LI.getVNInfoAt(Idx);
1134 /// Remove redundant spills in the same BB. Save those redundant spills in
1135 /// SpillsToRm, and save the spill to keep and its BB in SpillBBToSpill map.
1137 void HoistSpillHelper::rmRedundantSpills(
1138 SmallPtrSet<MachineInstr *, 16> &Spills,
1139 SmallVectorImpl<MachineInstr *> &SpillsToRm,
1140 DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill) {
1141 // For each spill saw, check SpillBBToSpill[] and see if its BB already has
1142 // another spill inside. If a BB contains more than one spill, only keep the
1143 // earlier spill with smaller SlotIndex.
1144 for (const auto CurrentSpill : Spills) {
1145 MachineBasicBlock *Block = CurrentSpill->getParent();
1146 MachineDomTreeNode *Node = MDT.getBase().getNode(Block);
1147 MachineInstr *PrevSpill = SpillBBToSpill[Node];
1149 SlotIndex PIdx = LIS.getInstructionIndex(*PrevSpill);
1150 SlotIndex CIdx = LIS.getInstructionIndex(*CurrentSpill);
1151 MachineInstr *SpillToRm = (CIdx > PIdx) ? CurrentSpill : PrevSpill;
1152 MachineInstr *SpillToKeep = (CIdx > PIdx) ? PrevSpill : CurrentSpill;
1153 SpillsToRm.push_back(SpillToRm);
1154 SpillBBToSpill[MDT.getBase().getNode(Block)] = SpillToKeep;
1156 SpillBBToSpill[MDT.getBase().getNode(Block)] = CurrentSpill;
1159 for (const auto SpillToRm : SpillsToRm)
1160 Spills.erase(SpillToRm);
1163 /// Starting from \p Root find a top-down traversal order of the dominator
1164 /// tree to visit all basic blocks containing the elements of \p Spills.
1165 /// Redundant spills will be found and put into \p SpillsToRm at the same
1166 /// time. \p SpillBBToSpill will be populated as part of the process and
1167 /// maps a basic block to the first store occurring in the basic block.
1168 /// \post SpillsToRm.union(Spills\@post) == Spills\@pre
1170 void HoistSpillHelper::getVisitOrders(
1171 MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills,
1172 SmallVectorImpl<MachineDomTreeNode *> &Orders,
1173 SmallVectorImpl<MachineInstr *> &SpillsToRm,
1174 DenseMap<MachineDomTreeNode *, unsigned> &SpillsToKeep,
1175 DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill) {
1176 // The set contains all the possible BB nodes to which we may hoist
1178 SmallPtrSet<MachineDomTreeNode *, 8> WorkSet;
1179 // Save the BB nodes on the path from the first BB node containing
1180 // non-redundant spill to the Root node.
1181 SmallPtrSet<MachineDomTreeNode *, 8> NodesOnPath;
1182 // All the spills to be hoisted must originate from a single def instruction
1183 // to the OrigReg. It means the def instruction should dominate all the spills
1184 // to be hoisted. We choose the BB where the def instruction is located as
1186 MachineDomTreeNode *RootIDomNode = MDT[Root]->getIDom();
1187 // For every node on the dominator tree with spill, walk up on the dominator
1188 // tree towards the Root node until it is reached. If there is other node
1189 // containing spill in the middle of the path, the previous spill saw will
1190 // be redundant and the node containing it will be removed. All the nodes on
1191 // the path starting from the first node with non-redundant spill to the Root
1192 // node will be added to the WorkSet, which will contain all the possible
1193 // locations where spills may be hoisted to after the loop below is done.
1194 for (const auto Spill : Spills) {
1195 MachineBasicBlock *Block = Spill->getParent();
1196 MachineDomTreeNode *Node = MDT[Block];
1197 MachineInstr *SpillToRm = nullptr;
1198 while (Node != RootIDomNode) {
1199 // If Node dominates Block, and it already contains a spill, the spill in
1200 // Block will be redundant.
1201 if (Node != MDT[Block] && SpillBBToSpill[Node]) {
1202 SpillToRm = SpillBBToSpill[MDT[Block]];
1204 /// If we see the Node already in WorkSet, the path from the Node to
1205 /// the Root node must already be traversed by another spill.
1206 /// Then no need to repeat.
1207 } else if (WorkSet.count(Node)) {
1210 NodesOnPath.insert(Node);
1212 Node = Node->getIDom();
1215 SpillsToRm.push_back(SpillToRm);
1217 // Add a BB containing the original spills to SpillsToKeep -- i.e.,
1218 // set the initial status before hoisting start. The value of BBs
1219 // containing original spills is set to 0, in order to descriminate
1220 // with BBs containing hoisted spills which will be inserted to
1221 // SpillsToKeep later during hoisting.
1222 SpillsToKeep[MDT[Block]] = 0;
1223 WorkSet.insert(NodesOnPath.begin(), NodesOnPath.end());
1225 NodesOnPath.clear();
1228 // Sort the nodes in WorkSet in top-down order and save the nodes
1229 // in Orders. Orders will be used for hoisting in runHoistSpills.
1231 Orders.push_back(MDT.getBase().getNode(Root));
1233 MachineDomTreeNode *Node = Orders[idx++];
1234 const std::vector<MachineDomTreeNode *> &Children = Node->getChildren();
1235 unsigned NumChildren = Children.size();
1236 for (unsigned i = 0; i != NumChildren; ++i) {
1237 MachineDomTreeNode *Child = Children[i];
1238 if (WorkSet.count(Child))
1239 Orders.push_back(Child);
1241 } while (idx != Orders.size());
1242 assert(Orders.size() == WorkSet.size() &&
1243 "Orders have different size with WorkSet");
1246 DEBUG(dbgs() << "Orders size is " << Orders.size() << "\n");
1247 SmallVector<MachineDomTreeNode *, 32>::reverse_iterator RIt = Orders.rbegin();
1248 for (; RIt != Orders.rend(); RIt++)
1249 DEBUG(dbgs() << "BB" << (*RIt)->getBlock()->getNumber() << ",");
1250 DEBUG(dbgs() << "\n");
1254 /// Try to hoist spills according to BB hotness. The spills to removed will
1255 /// be saved in \p SpillsToRm. The spills to be inserted will be saved in
1258 void HoistSpillHelper::runHoistSpills(
1259 unsigned OrigReg, VNInfo &OrigVNI, SmallPtrSet<MachineInstr *, 16> &Spills,
1260 SmallVectorImpl<MachineInstr *> &SpillsToRm,
1261 DenseMap<MachineBasicBlock *, unsigned> &SpillsToIns) {
1262 // Visit order of dominator tree nodes.
1263 SmallVector<MachineDomTreeNode *, 32> Orders;
1264 // SpillsToKeep contains all the nodes where spills are to be inserted
1265 // during hoisting. If the spill to be inserted is an original spill
1266 // (not a hoisted one), the value of the map entry is 0. If the spill
1267 // is a hoisted spill, the value of the map entry is the VReg to be used
1268 // as the source of the spill.
1269 DenseMap<MachineDomTreeNode *, unsigned> SpillsToKeep;
1270 // Map from BB to the first spill inside of it.
1271 DenseMap<MachineDomTreeNode *, MachineInstr *> SpillBBToSpill;
1273 rmRedundantSpills(Spills, SpillsToRm, SpillBBToSpill);
1275 MachineBasicBlock *Root = LIS.getMBBFromIndex(OrigVNI.def);
1276 getVisitOrders(Root, Spills, Orders, SpillsToRm, SpillsToKeep,
1279 // SpillsInSubTreeMap keeps the map from a dom tree node to a pair of
1280 // nodes set and the cost of all the spills inside those nodes.
1281 // The nodes set are the locations where spills are to be inserted
1282 // in the subtree of current node.
1283 typedef std::pair<SmallPtrSet<MachineDomTreeNode *, 16>, BlockFrequency>
1285 DenseMap<MachineDomTreeNode *, NodesCostPair> SpillsInSubTreeMap;
1286 // Iterate Orders set in reverse order, which will be a bottom-up order
1287 // in the dominator tree. Once we visit a dom tree node, we know its
1288 // children have already been visited and the spill locations in the
1289 // subtrees of all the children have been determined.
1290 SmallVector<MachineDomTreeNode *, 32>::reverse_iterator RIt = Orders.rbegin();
1291 for (; RIt != Orders.rend(); RIt++) {
1292 MachineBasicBlock *Block = (*RIt)->getBlock();
1294 // If Block contains an original spill, simply continue.
1295 if (SpillsToKeep.find(*RIt) != SpillsToKeep.end() && !SpillsToKeep[*RIt]) {
1296 SpillsInSubTreeMap[*RIt].first.insert(*RIt);
1297 // SpillsInSubTreeMap[*RIt].second contains the cost of spill.
1298 SpillsInSubTreeMap[*RIt].second = MBFI.getBlockFreq(Block);
1302 // Collect spills in subtree of current node (*RIt) to
1303 // SpillsInSubTreeMap[*RIt].first.
1304 const std::vector<MachineDomTreeNode *> &Children = (*RIt)->getChildren();
1305 unsigned NumChildren = Children.size();
1306 for (unsigned i = 0; i != NumChildren; ++i) {
1307 MachineDomTreeNode *Child = Children[i];
1308 if (SpillsInSubTreeMap.find(Child) == SpillsInSubTreeMap.end())
1310 // The stmt "SpillsInSubTree = SpillsInSubTreeMap[*RIt].first" below
1311 // should be placed before getting the begin and end iterators of
1312 // SpillsInSubTreeMap[Child].first, or else the iterators may be
1313 // invalidated when SpillsInSubTreeMap[*RIt] is seen the first time
1314 // and the map grows and then the original buckets in the map are moved.
1315 SmallPtrSet<MachineDomTreeNode *, 16> &SpillsInSubTree =
1316 SpillsInSubTreeMap[*RIt].first;
1317 BlockFrequency &SubTreeCost = SpillsInSubTreeMap[*RIt].second;
1318 SubTreeCost += SpillsInSubTreeMap[Child].second;
1319 auto BI = SpillsInSubTreeMap[Child].first.begin();
1320 auto EI = SpillsInSubTreeMap[Child].first.end();
1321 SpillsInSubTree.insert(BI, EI);
1322 SpillsInSubTreeMap.erase(Child);
1325 SmallPtrSet<MachineDomTreeNode *, 16> &SpillsInSubTree =
1326 SpillsInSubTreeMap[*RIt].first;
1327 BlockFrequency &SubTreeCost = SpillsInSubTreeMap[*RIt].second;
1328 // No spills in subtree, simply continue.
1329 if (SpillsInSubTree.empty())
1332 // Check whether Block is a possible candidate to insert spill.
1333 unsigned LiveReg = 0;
1334 if (!isSpillCandBB(OrigReg, OrigVNI, *Block, LiveReg))
1337 // If there are multiple spills that could be merged, bias a little
1338 // to hoist the spill.
1339 BranchProbability MarginProb = (SpillsInSubTree.size() > 1)
1340 ? BranchProbability(9, 10)
1341 : BranchProbability(1, 1);
1342 if (SubTreeCost > MBFI.getBlockFreq(Block) * MarginProb) {
1343 // Hoist: Move spills to current Block.
1344 for (const auto SpillBB : SpillsInSubTree) {
1345 // When SpillBB is a BB contains original spill, insert the spill
1347 if (SpillsToKeep.find(SpillBB) != SpillsToKeep.end() &&
1348 !SpillsToKeep[SpillBB]) {
1349 MachineInstr *SpillToRm = SpillBBToSpill[SpillBB];
1350 SpillsToRm.push_back(SpillToRm);
1352 // SpillBB will not contain spill anymore, remove it from SpillsToKeep.
1353 SpillsToKeep.erase(SpillBB);
1355 // Current Block is the BB containing the new hoisted spill. Add it to
1356 // SpillsToKeep. LiveReg is the source of the new spill.
1357 SpillsToKeep[*RIt] = LiveReg;
1359 dbgs() << "spills in BB: ";
1360 for (const auto Rspill : SpillsInSubTree)
1361 dbgs() << Rspill->getBlock()->getNumber() << " ";
1362 dbgs() << "were promoted to BB" << (*RIt)->getBlock()->getNumber()
1365 SpillsInSubTree.clear();
1366 SpillsInSubTree.insert(*RIt);
1367 SubTreeCost = MBFI.getBlockFreq(Block);
1370 // For spills in SpillsToKeep with LiveReg set (i.e., not original spill),
1371 // save them to SpillsToIns.
1372 for (const auto Ent : SpillsToKeep) {
1374 SpillsToIns[Ent.first->getBlock()] = Ent.second;
1378 /// For spills with equal values, remove redundant spills and hoist those left
1379 /// to less hot spots.
1381 /// Spills with equal values will be collected into the same set in
1382 /// MergeableSpills when spill is inserted. These equal spills are originated
1383 /// from the same defining instruction and are dominated by the instruction.
1384 /// Before hoisting all the equal spills, redundant spills inside in the same
1385 /// BB are first marked to be deleted. Then starting from the spills left, walk
1386 /// up on the dominator tree towards the Root node where the define instruction
1387 /// is located, mark the dominated spills to be deleted along the way and
1388 /// collect the BB nodes on the path from non-dominated spills to the define
1389 /// instruction into a WorkSet. The nodes in WorkSet are the candidate places
1390 /// where we are considering to hoist the spills. We iterate the WorkSet in
1391 /// bottom-up order, and for each node, we will decide whether to hoist spills
1392 /// inside its subtree to that node. In this way, we can get benefit locally
1393 /// even if hoisting all the equal spills to one cold place is impossible.
1395 void HoistSpillHelper::hoistAllSpills() {
1396 SmallVector<unsigned, 4> NewVRegs;
1397 LiveRangeEdit Edit(nullptr, NewVRegs, MF, LIS, &VRM, this);
1399 // Save the mapping between stackslot and its original reg.
1400 DenseMap<int, unsigned> SlotToOrigReg;
1401 for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
1402 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1403 int Slot = VRM.getStackSlot(Reg);
1404 if (Slot != VirtRegMap::NO_STACK_SLOT)
1405 SlotToOrigReg[Slot] = VRM.getOriginal(Reg);
1406 unsigned Original = VRM.getPreSplitReg(Reg);
1407 if (!MRI.def_empty(Reg))
1408 Virt2SiblingsMap[Original].insert(Reg);
1411 // Each entry in MergeableSpills contains a spill set with equal values.
1412 for (auto &Ent : MergeableSpills) {
1413 int Slot = Ent.first.first;
1414 unsigned OrigReg = SlotToOrigReg[Slot];
1415 LiveInterval &OrigLI = LIS.getInterval(OrigReg);
1416 VNInfo *OrigVNI = Ent.first.second;
1417 SmallPtrSet<MachineInstr *, 16> &EqValSpills = Ent.second;
1418 if (Ent.second.empty())
1422 dbgs() << "\nFor Slot" << Slot << " and VN" << OrigVNI->id << ":\n"
1423 << "Equal spills in BB: ";
1424 for (const auto spill : EqValSpills)
1425 dbgs() << spill->getParent()->getNumber() << " ";
1429 // SpillsToRm is the spill set to be removed from EqValSpills.
1430 SmallVector<MachineInstr *, 16> SpillsToRm;
1431 // SpillsToIns is the spill set to be newly inserted after hoisting.
1432 DenseMap<MachineBasicBlock *, unsigned> SpillsToIns;
1434 runHoistSpills(OrigReg, *OrigVNI, EqValSpills, SpillsToRm, SpillsToIns);
1437 dbgs() << "Finally inserted spills in BB: ";
1438 for (const auto Ispill : SpillsToIns)
1439 dbgs() << Ispill.first->getNumber() << " ";
1440 dbgs() << "\nFinally removed spills in BB: ";
1441 for (const auto Rspill : SpillsToRm)
1442 dbgs() << Rspill->getParent()->getNumber() << " ";
1446 // Stack live range update.
1447 LiveInterval &StackIntvl = LSS.getInterval(Slot);
1448 if (!SpillsToIns.empty() || !SpillsToRm.empty())
1449 StackIntvl.MergeValueInAsValue(OrigLI, OrigVNI,
1450 StackIntvl.getValNumInfo(0));
1452 // Insert hoisted spills.
1453 for (auto const Insert : SpillsToIns) {
1454 MachineBasicBlock *BB = Insert.first;
1455 unsigned LiveReg = Insert.second;
1456 MachineBasicBlock::iterator MI = IPA.getLastInsertPointIter(OrigLI, *BB);
1457 TII.storeRegToStackSlot(*BB, MI, LiveReg, false, Slot,
1458 MRI.getRegClass(LiveReg), &TRI);
1459 LIS.InsertMachineInstrRangeInMaps(std::prev(MI), MI);
1463 // Remove redundant spills or change them to dead instructions.
1464 NumSpills -= SpillsToRm.size();
1465 for (auto const RMEnt : SpillsToRm) {
1466 RMEnt->setDesc(TII.get(TargetOpcode::KILL));
1467 for (unsigned i = RMEnt->getNumOperands(); i; --i) {
1468 MachineOperand &MO = RMEnt->getOperand(i - 1);
1469 if (MO.isReg() && MO.isImplicit() && MO.isDef() && !MO.isDead())
1470 RMEnt->RemoveOperand(i - 1);
1473 Edit.eliminateDeadDefs(SpillsToRm, None, AA);
1477 /// For VirtReg clone, the \p New register should have the same physreg or
1478 /// stackslot as the \p old register.
1479 void HoistSpillHelper::LRE_DidCloneVirtReg(unsigned New, unsigned Old) {
1480 if (VRM.hasPhys(Old))
1481 VRM.assignVirt2Phys(New, VRM.getPhys(Old));
1482 else if (VRM.getStackSlot(Old) != VirtRegMap::NO_STACK_SLOT)
1483 VRM.assignVirt2StackSlot(New, VRM.getStackSlot(Old));
1485 llvm_unreachable("VReg should be assigned either physreg or stackslot");