1 //===--------------------- InterleavedAccessPass.cpp ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the Interleaved Access pass, which identifies
11 // interleaved memory accesses and transforms them into target specific
14 // An interleaved load reads data from memory into several vectors, with
15 // DE-interleaving the data on a factor. An interleaved store writes several
16 // vectors to memory with RE-interleaving the data on a factor.
18 // As interleaved accesses are difficult to identified in CodeGen (mainly
19 // because the VECTOR_SHUFFLE DAG node is quite different from the shufflevector
20 // IR), we identify and transform them to intrinsics in this pass so the
21 // intrinsics can be easily matched into target specific instructions later in
24 // E.g. An interleaved load (Factor = 2):
25 // %wide.vec = load <8 x i32>, <8 x i32>* %ptr
26 // %v0 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <0, 2, 4, 6>
27 // %v1 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <1, 3, 5, 7>
29 // It could be transformed into a ld2 intrinsic in AArch64 backend or a vld2
30 // intrinsic in ARM backend.
32 // In X86, this can be further optimized into a set of target
33 // specific loads followed by an optimized sequence of shuffles.
35 // E.g. An interleaved store (Factor = 3):
36 // %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1,
37 // <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
38 // store <12 x i32> %i.vec, <12 x i32>* %ptr
40 // It could be transformed into a st3 intrinsic in AArch64 backend or a vst3
41 // intrinsic in ARM backend.
43 // Similarly, a set of interleaved stores can be transformed into an optimized
44 // sequence of shuffles followed by a set of target specific stores for X86.
45 //===----------------------------------------------------------------------===//
47 #include "llvm/CodeGen/Passes.h"
48 #include "llvm/CodeGen/TargetPassConfig.h"
49 #include "llvm/IR/Dominators.h"
50 #include "llvm/IR/InstIterator.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetLowering.h"
55 #include "llvm/Target/TargetSubtargetInfo.h"
59 #define DEBUG_TYPE "interleaved-access"
61 static cl::opt<bool> LowerInterleavedAccesses(
62 "lower-interleaved-accesses",
63 cl::desc("Enable lowering interleaved accesses to intrinsics"),
64 cl::init(true), cl::Hidden);
68 class InterleavedAccess : public FunctionPass {
72 InterleavedAccess() : FunctionPass(ID), DT(nullptr), TLI(nullptr) {
73 initializeInterleavedAccessPass(*PassRegistry::getPassRegistry());
76 StringRef getPassName() const override { return "Interleaved Access Pass"; }
78 bool runOnFunction(Function &F) override;
80 void getAnalysisUsage(AnalysisUsage &AU) const override {
81 AU.addRequired<DominatorTreeWrapperPass>();
82 AU.addPreserved<DominatorTreeWrapperPass>();
87 const TargetLowering *TLI;
89 /// The maximum supported interleave factor.
92 /// \brief Transform an interleaved load into target specific intrinsics.
93 bool lowerInterleavedLoad(LoadInst *LI,
94 SmallVector<Instruction *, 32> &DeadInsts);
96 /// \brief Transform an interleaved store into target specific intrinsics.
97 bool lowerInterleavedStore(StoreInst *SI,
98 SmallVector<Instruction *, 32> &DeadInsts);
100 /// \brief Returns true if the uses of an interleaved load by the
101 /// extractelement instructions in \p Extracts can be replaced by uses of the
102 /// shufflevector instructions in \p Shuffles instead. If so, the necessary
103 /// replacements are also performed.
104 bool tryReplaceExtracts(ArrayRef<ExtractElementInst *> Extracts,
105 ArrayRef<ShuffleVectorInst *> Shuffles);
107 } // end anonymous namespace.
109 char InterleavedAccess::ID = 0;
110 INITIALIZE_PASS_BEGIN(InterleavedAccess, DEBUG_TYPE,
111 "Lower interleaved memory accesses to target specific intrinsics", false,
113 INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
114 INITIALIZE_PASS_END(InterleavedAccess, DEBUG_TYPE,
115 "Lower interleaved memory accesses to target specific intrinsics", false,
118 FunctionPass *llvm::createInterleavedAccessPass() {
119 return new InterleavedAccess();
122 /// \brief Check if the mask is a DE-interleave mask of the given factor
124 /// <Index, Index+Factor, ..., Index+(NumElts-1)*Factor>
125 static bool isDeInterleaveMaskOfFactor(ArrayRef<int> Mask, unsigned Factor,
127 // Check all potential start indices from 0 to (Factor - 1).
128 for (Index = 0; Index < Factor; Index++) {
131 // Check that elements are in ascending order by Factor. Ignore undef
133 for (; i < Mask.size(); i++)
134 if (Mask[i] >= 0 && static_cast<unsigned>(Mask[i]) != Index + i * Factor)
137 if (i == Mask.size())
144 /// \brief Check if the mask is a DE-interleave mask for an interleaved load.
146 /// E.g. DE-interleave masks (Factor = 2) could be:
147 /// <0, 2, 4, 6> (mask of index 0 to extract even elements)
148 /// <1, 3, 5, 7> (mask of index 1 to extract odd elements)
149 static bool isDeInterleaveMask(ArrayRef<int> Mask, unsigned &Factor,
150 unsigned &Index, unsigned MaxFactor) {
154 // Check potential Factors.
155 for (Factor = 2; Factor <= MaxFactor; Factor++)
156 if (isDeInterleaveMaskOfFactor(Mask, Factor, Index))
162 /// \brief Check if the mask can be used in an interleaved store.
164 /// It checks for a more general pattern than the RE-interleave mask.
165 /// I.e. <x, y, ... z, x+1, y+1, ...z+1, x+2, y+2, ...z+2, ...>
166 /// E.g. For a Factor of 2 (LaneLen=4): <4, 32, 5, 33, 6, 34, 7, 35>
167 /// E.g. For a Factor of 3 (LaneLen=4): <4, 32, 16, 5, 33, 17, 6, 34, 18, 7, 35, 19>
168 /// E.g. For a Factor of 4 (LaneLen=2): <8, 2, 12, 4, 9, 3, 13, 5>
170 /// The particular case of an RE-interleave mask is:
171 /// I.e. <0, LaneLen, ... , LaneLen*(Factor - 1), 1, LaneLen + 1, ...>
172 /// E.g. For a Factor of 2 (LaneLen=4): <0, 4, 1, 5, 2, 6, 3, 7>
173 static bool isReInterleaveMask(ArrayRef<int> Mask, unsigned &Factor,
174 unsigned MaxFactor, unsigned OpNumElts) {
175 unsigned NumElts = Mask.size();
179 // Check potential Factors.
180 for (Factor = 2; Factor <= MaxFactor; Factor++) {
181 if (NumElts % Factor)
184 unsigned LaneLen = NumElts / Factor;
185 if (!isPowerOf2_32(LaneLen))
188 // Check whether each element matches the general interleaved rule.
189 // Ignore undef elements, as long as the defined elements match the rule.
190 // Outer loop processes all factors (x, y, z in the above example)
192 for (; I < Factor; I++) {
193 unsigned SavedLaneValue;
194 unsigned SavedNoUndefs = 0;
196 // Inner loop processes consecutive accesses (x, x+1... in the example)
197 for (J = 0; J < LaneLen - 1; J++) {
198 // Lane computes x's position in the Mask
199 unsigned Lane = J * Factor + I;
200 unsigned NextLane = Lane + Factor;
201 int LaneValue = Mask[Lane];
202 int NextLaneValue = Mask[NextLane];
204 // If both are defined, values must be sequential
205 if (LaneValue >= 0 && NextLaneValue >= 0 &&
206 LaneValue + 1 != NextLaneValue)
209 // If the next value is undef, save the current one as reference
210 if (LaneValue >= 0 && NextLaneValue < 0) {
211 SavedLaneValue = LaneValue;
215 // Undefs are allowed, but defined elements must still be consecutive:
216 // i.e.: x,..., undef,..., x + 2,..., undef,..., undef,..., x + 5, ....
217 // Verify this by storing the last non-undef followed by an undef
218 // Check that following non-undef masks are incremented with the
219 // corresponding distance.
220 if (SavedNoUndefs > 0 && LaneValue < 0) {
222 if (NextLaneValue >= 0 &&
223 SavedLaneValue + SavedNoUndefs != (unsigned)NextLaneValue)
233 // Check that the start of the I range (J=0) is greater than 0
235 } else if (Mask[(LaneLen - 1) * Factor + I] >= 0) {
236 // StartMask defined by the last value in lane
237 StartMask = Mask[(LaneLen - 1) * Factor + I] - J;
238 } else if (SavedNoUndefs > 0) {
239 // StartMask defined by some non-zero value in the j loop
240 StartMask = SavedLaneValue - (LaneLen - 1 - SavedNoUndefs);
242 // else StartMask remains set to 0, i.e. all elements are undefs
246 // We must stay within the vectors; This case can happen with undefs.
247 if (StartMask + LaneLen > OpNumElts*2)
251 // Found an interleaved mask of current factor.
259 bool InterleavedAccess::lowerInterleavedLoad(
260 LoadInst *LI, SmallVector<Instruction *, 32> &DeadInsts) {
264 SmallVector<ShuffleVectorInst *, 4> Shuffles;
265 SmallVector<ExtractElementInst *, 4> Extracts;
267 // Check if all users of this load are shufflevectors. If we encounter any
268 // users that are extractelement instructions, we save them to later check if
269 // they can be modifed to extract from one of the shufflevectors instead of
271 for (auto UI = LI->user_begin(), E = LI->user_end(); UI != E; UI++) {
272 auto *Extract = dyn_cast<ExtractElementInst>(*UI);
273 if (Extract && isa<ConstantInt>(Extract->getIndexOperand())) {
274 Extracts.push_back(Extract);
277 ShuffleVectorInst *SVI = dyn_cast<ShuffleVectorInst>(*UI);
278 if (!SVI || !isa<UndefValue>(SVI->getOperand(1)))
281 Shuffles.push_back(SVI);
284 if (Shuffles.empty())
287 unsigned Factor, Index;
289 // Check if the first shufflevector is DE-interleave shuffle.
290 if (!isDeInterleaveMask(Shuffles[0]->getShuffleMask(), Factor, Index,
294 // Holds the corresponding index for each DE-interleave shuffle.
295 SmallVector<unsigned, 4> Indices;
296 Indices.push_back(Index);
298 Type *VecTy = Shuffles[0]->getType();
300 // Check if other shufflevectors are also DE-interleaved of the same type
301 // and factor as the first shufflevector.
302 for (unsigned i = 1; i < Shuffles.size(); i++) {
303 if (Shuffles[i]->getType() != VecTy)
306 if (!isDeInterleaveMaskOfFactor(Shuffles[i]->getShuffleMask(), Factor,
310 Indices.push_back(Index);
313 // Try and modify users of the load that are extractelement instructions to
314 // use the shufflevector instructions instead of the load.
315 if (!tryReplaceExtracts(Extracts, Shuffles))
318 DEBUG(dbgs() << "IA: Found an interleaved load: " << *LI << "\n");
320 // Try to create target specific intrinsics to replace the load and shuffles.
321 if (!TLI->lowerInterleavedLoad(LI, Shuffles, Indices, Factor))
324 for (auto SVI : Shuffles)
325 DeadInsts.push_back(SVI);
327 DeadInsts.push_back(LI);
331 bool InterleavedAccess::tryReplaceExtracts(
332 ArrayRef<ExtractElementInst *> Extracts,
333 ArrayRef<ShuffleVectorInst *> Shuffles) {
335 // If there aren't any extractelement instructions to modify, there's nothing
337 if (Extracts.empty())
340 // Maps extractelement instructions to vector-index pairs. The extractlement
341 // instructions will be modified to use the new vector and index operands.
342 DenseMap<ExtractElementInst *, std::pair<Value *, int>> ReplacementMap;
344 for (auto *Extract : Extracts) {
346 // The vector index that is extracted.
347 auto *IndexOperand = cast<ConstantInt>(Extract->getIndexOperand());
348 auto Index = IndexOperand->getSExtValue();
350 // Look for a suitable shufflevector instruction. The goal is to modify the
351 // extractelement instruction (which uses an interleaved load) to use one
352 // of the shufflevector instructions instead of the load.
353 for (auto *Shuffle : Shuffles) {
355 // If the shufflevector instruction doesn't dominate the extract, we
356 // can't create a use of it.
357 if (!DT->dominates(Shuffle, Extract))
360 // Inspect the indices of the shufflevector instruction. If the shuffle
361 // selects the same index that is extracted, we can modify the
362 // extractelement instruction.
363 SmallVector<int, 4> Indices;
364 Shuffle->getShuffleMask(Indices);
365 for (unsigned I = 0; I < Indices.size(); ++I)
366 if (Indices[I] == Index) {
367 assert(Extract->getOperand(0) == Shuffle->getOperand(0) &&
368 "Vector operations do not match");
369 ReplacementMap[Extract] = std::make_pair(Shuffle, I);
373 // If we found a suitable shufflevector instruction, stop looking.
374 if (ReplacementMap.count(Extract))
378 // If we did not find a suitable shufflevector instruction, the
379 // extractelement instruction cannot be modified, so we must give up.
380 if (!ReplacementMap.count(Extract))
384 // Finally, perform the replacements.
385 IRBuilder<> Builder(Extracts[0]->getContext());
386 for (auto &Replacement : ReplacementMap) {
387 auto *Extract = Replacement.first;
388 auto *Vector = Replacement.second.first;
389 auto Index = Replacement.second.second;
390 Builder.SetInsertPoint(Extract);
391 Extract->replaceAllUsesWith(Builder.CreateExtractElement(Vector, Index));
392 Extract->eraseFromParent();
398 bool InterleavedAccess::lowerInterleavedStore(
399 StoreInst *SI, SmallVector<Instruction *, 32> &DeadInsts) {
403 ShuffleVectorInst *SVI = dyn_cast<ShuffleVectorInst>(SI->getValueOperand());
404 if (!SVI || !SVI->hasOneUse())
407 // Check if the shufflevector is RE-interleave shuffle.
409 unsigned OpNumElts = SVI->getOperand(0)->getType()->getVectorNumElements();
410 if (!isReInterleaveMask(SVI->getShuffleMask(), Factor, MaxFactor, OpNumElts))
413 DEBUG(dbgs() << "IA: Found an interleaved store: " << *SI << "\n");
415 // Try to create target specific intrinsics to replace the store and shuffle.
416 if (!TLI->lowerInterleavedStore(SI, SVI, Factor))
419 // Already have a new target specific interleaved store. Erase the old store.
420 DeadInsts.push_back(SI);
421 DeadInsts.push_back(SVI);
425 bool InterleavedAccess::runOnFunction(Function &F) {
426 auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
427 if (!TPC || !LowerInterleavedAccesses)
430 DEBUG(dbgs() << "*** " << getPassName() << ": " << F.getName() << "\n");
432 DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
433 auto &TM = TPC->getTM<TargetMachine>();
434 TLI = TM.getSubtargetImpl(F)->getTargetLowering();
435 MaxFactor = TLI->getMaxSupportedInterleaveFactor();
437 // Holds dead instructions that will be erased later.
438 SmallVector<Instruction *, 32> DeadInsts;
439 bool Changed = false;
441 for (auto &I : instructions(F)) {
442 if (LoadInst *LI = dyn_cast<LoadInst>(&I))
443 Changed |= lowerInterleavedLoad(LI, DeadInsts);
445 if (StoreInst *SI = dyn_cast<StoreInst>(&I))
446 Changed |= lowerInterleavedStore(SI, DeadInsts);
449 for (auto I : DeadInsts)
450 I->eraseFromParent();