1 //===--- LivePhysRegs.cpp - Live Physical Register Set --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LivePhysRegs utility for tracking liveness of
11 // physical registers across machine instructions in forward or backward order.
12 // A more detailed description can be found in the corresponding header file.
14 //===----------------------------------------------------------------------===//
16 #include "llvm/CodeGen/LivePhysRegs.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBundle.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
26 /// \brief Remove all registers from the set that get clobbered by the register
28 /// The clobbers set will be the list of live registers clobbered
30 void LivePhysRegs::removeRegsInMask(const MachineOperand &MO,
31 SmallVectorImpl<std::pair<unsigned, const MachineOperand*>> *Clobbers) {
32 SparseSet<unsigned>::iterator LRI = LiveRegs.begin();
33 while (LRI != LiveRegs.end()) {
34 if (MO.clobbersPhysReg(*LRI)) {
36 Clobbers->push_back(std::make_pair(*LRI, &MO));
37 LRI = LiveRegs.erase(LRI);
43 /// Remove defined registers and regmask kills from the set.
44 void LivePhysRegs::removeDefs(const MachineInstr &MI) {
45 for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
49 unsigned Reg = O->getReg();
50 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
53 } else if (O->isRegMask())
58 /// Add uses to the set.
59 void LivePhysRegs::addUses(const MachineInstr &MI) {
60 for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
61 if (!O->isReg() || !O->readsReg())
63 unsigned Reg = O->getReg();
64 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
70 /// Simulates liveness when stepping backwards over an instruction(bundle):
71 /// Remove Defs, add uses. This is the recommended way of calculating liveness.
72 void LivePhysRegs::stepBackward(const MachineInstr &MI) {
73 // Remove defined registers and regmask kills from the set.
76 // Add uses to the set.
80 /// Simulates liveness when stepping forward over an instruction(bundle): Remove
81 /// killed-uses, add defs. This is the not recommended way, because it depends
82 /// on accurate kill flags. If possible use stepBackward() instead of this
84 void LivePhysRegs::stepForward(const MachineInstr &MI,
85 SmallVectorImpl<std::pair<unsigned, const MachineOperand*>> &Clobbers) {
86 // Remove killed registers from the set.
87 for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
89 unsigned Reg = O->getReg();
90 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
93 // Note, dead defs are still recorded. The caller should decide how to
95 Clobbers.push_back(std::make_pair(Reg, &*O));
102 } else if (O->isRegMask())
103 removeRegsInMask(*O, &Clobbers);
106 // Add defs to the set.
107 for (auto Reg : Clobbers) {
108 // Skip dead defs. They shouldn't be added to the set.
109 if (Reg.second->isReg() && Reg.second->isDead())
115 /// Prin the currently live registers to OS.
116 void LivePhysRegs::print(raw_ostream &OS) const {
117 OS << "Live Registers:";
119 OS << " (uninitialized)\n";
128 for (const_iterator I = begin(), E = end(); I != E; ++I)
129 OS << " " << printReg(*I, TRI);
133 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
134 LLVM_DUMP_METHOD void LivePhysRegs::dump() const {
135 dbgs() << " " << *this;
139 bool LivePhysRegs::available(const MachineRegisterInfo &MRI,
140 unsigned Reg) const {
141 if (LiveRegs.count(Reg))
143 if (MRI.isReserved(Reg))
145 for (MCRegAliasIterator R(Reg, TRI, false); R.isValid(); ++R) {
146 if (LiveRegs.count(*R))
152 /// Add live-in registers of basic block \p MBB to \p LiveRegs.
153 void LivePhysRegs::addBlockLiveIns(const MachineBasicBlock &MBB) {
154 for (const auto &LI : MBB.liveins()) {
155 unsigned Reg = LI.PhysReg;
156 LaneBitmask Mask = LI.LaneMask;
157 MCSubRegIndexIterator S(Reg, TRI);
158 assert(Mask.any() && "Invalid livein mask");
159 if (Mask.all() || !S.isValid()) {
163 for (; S.isValid(); ++S) {
164 unsigned SI = S.getSubRegIndex();
165 if ((Mask & TRI->getSubRegIndexLaneMask(SI)).any())
166 addReg(S.getSubReg());
171 /// Adds all callee saved registers to \p LiveRegs.
172 static void addCalleeSavedRegs(LivePhysRegs &LiveRegs,
173 const MachineFunction &MF) {
174 const MachineRegisterInfo &MRI = MF.getRegInfo();
175 for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR; ++CSR)
176 LiveRegs.addReg(*CSR);
179 void LivePhysRegs::addPristines(const MachineFunction &MF) {
180 const MachineFrameInfo &MFI = MF.getFrameInfo();
181 if (!MFI.isCalleeSavedInfoValid())
183 /// This function will usually be called on an empty object, handle this
184 /// as a special case.
186 /// Add all callee saved regs, then remove the ones that are saved and
188 addCalleeSavedRegs(*this, MF);
189 /// Remove the ones that are not saved/restored; they are pristine.
190 for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
191 removeReg(Info.getReg());
194 /// If a callee-saved register that is not pristine is already present
195 /// in the set, we should make sure that it stays in it. Precompute the
196 /// set of pristine registers in a separate object.
197 /// Add all callee saved regs, then remove the ones that are saved+restored.
198 LivePhysRegs Pristine(*TRI);
199 addCalleeSavedRegs(Pristine, MF);
200 /// Remove the ones that are not saved/restored; they are pristine.
201 for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
202 Pristine.removeReg(Info.getReg());
203 for (MCPhysReg R : Pristine)
207 void LivePhysRegs::addLiveOutsNoPristines(const MachineBasicBlock &MBB) {
208 if (!MBB.succ_empty()) {
209 // To get the live-outs we simply merge the live-ins of all successors.
210 for (const MachineBasicBlock *Succ : MBB.successors())
211 addBlockLiveIns(*Succ);
212 } else if (MBB.isReturnBlock()) {
213 // For the return block: Add all callee saved registers that are saved and
214 // restored (somewhere); This does not include callee saved registers that
215 // are unused and hence not saved and restored; they are called pristine.
216 const MachineFunction &MF = *MBB.getParent();
217 const MachineFrameInfo &MFI = MF.getFrameInfo();
218 if (MFI.isCalleeSavedInfoValid()) {
219 for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
220 if (Info.isRestored())
221 addReg(Info.getReg());
226 void LivePhysRegs::addLiveOuts(const MachineBasicBlock &MBB) {
227 const MachineFunction &MF = *MBB.getParent();
228 if (!MBB.succ_empty()) {
230 addLiveOutsNoPristines(MBB);
231 } else if (MBB.isReturnBlock()) {
232 // For the return block: Add all callee saved registers.
233 const MachineFrameInfo &MFI = MF.getFrameInfo();
234 if (MFI.isCalleeSavedInfoValid())
235 addCalleeSavedRegs(*this, MF);
239 void LivePhysRegs::addLiveIns(const MachineBasicBlock &MBB) {
240 const MachineFunction &MF = *MBB.getParent();
242 addBlockLiveIns(MBB);
245 void llvm::computeLiveIns(LivePhysRegs &LiveRegs,
246 const MachineBasicBlock &MBB) {
247 const MachineFunction &MF = *MBB.getParent();
248 const MachineRegisterInfo &MRI = MF.getRegInfo();
249 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
251 LiveRegs.addLiveOutsNoPristines(MBB);
252 for (const MachineInstr &MI : make_range(MBB.rbegin(), MBB.rend()))
253 LiveRegs.stepBackward(MI);
256 void llvm::addLiveIns(MachineBasicBlock &MBB, const LivePhysRegs &LiveRegs) {
257 assert(MBB.livein_empty() && "Expected empty live-in list");
258 const MachineFunction &MF = *MBB.getParent();
259 const MachineRegisterInfo &MRI = MF.getRegInfo();
260 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
261 for (MCPhysReg Reg : LiveRegs) {
262 if (MRI.isReserved(Reg))
264 // Skip the register if we are about to add one of its super registers.
265 bool ContainsSuperReg = false;
266 for (MCSuperRegIterator SReg(Reg, &TRI); SReg.isValid(); ++SReg) {
267 if (LiveRegs.contains(*SReg) && !MRI.isReserved(*SReg)) {
268 ContainsSuperReg = true;
272 if (ContainsSuperReg)
278 void llvm::recomputeLivenessFlags(MachineBasicBlock &MBB) {
279 const MachineFunction &MF = *MBB.getParent();
280 const MachineRegisterInfo &MRI = MF.getRegInfo();
281 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
283 // We walk through the block backwards and start with the live outs.
284 LivePhysRegs LiveRegs;
286 LiveRegs.addLiveOutsNoPristines(MBB);
288 for (MachineInstr &MI : make_range(MBB.rbegin(), MBB.rend())) {
289 // Recompute dead flags.
290 for (MIBundleOperands MO(MI); MO.isValid(); ++MO) {
291 if (!MO->isReg() || !MO->isDef() || MO->isDebug())
294 unsigned Reg = MO->getReg();
297 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
299 bool IsNotLive = LiveRegs.available(MRI, Reg);
300 MO->setIsDead(IsNotLive);
303 // Step backward over defs.
304 LiveRegs.removeDefs(MI);
306 // Recompute kill flags.
307 for (MIBundleOperands MO(MI); MO.isValid(); ++MO) {
308 if (!MO->isReg() || !MO->readsReg() || MO->isDebug())
311 unsigned Reg = MO->getReg();
314 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
316 bool IsNotLive = LiveRegs.available(MRI, Reg);
317 MO->setIsKill(IsNotLive);
320 // Complete the stepbackward.
321 LiveRegs.addUses(MI);
325 void llvm::computeAndAddLiveIns(LivePhysRegs &LiveRegs,
326 MachineBasicBlock &MBB) {
327 computeLiveIns(LiveRegs, MBB);
328 addLiveIns(MBB, LiveRegs);