1 //===-- LiveRangeShrink.cpp - Move instructions to shrink live range ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 ///===---------------------------------------------------------------------===//
11 /// This pass moves instructions close to the definition of its operands to
12 /// shrink live range of the def instruction. The code motion is limited within
13 /// the basic block. The moved instruction should have 1 def, and more than one
14 /// uses, all of which are the only use of the def.
16 ///===---------------------------------------------------------------------===//
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/Support/Debug.h"
23 #define DEBUG_TYPE "lrshrink"
25 STATISTIC(NumInstrsHoistedToShrinkLiveRange,
26 "Number of insructions hoisted to shrink live range.");
31 class LiveRangeShrink : public MachineFunctionPass {
35 LiveRangeShrink() : MachineFunctionPass(ID) {
36 initializeLiveRangeShrinkPass(*PassRegistry::getPassRegistry());
39 void getAnalysisUsage(AnalysisUsage &AU) const override {
41 MachineFunctionPass::getAnalysisUsage(AU);
44 StringRef getPassName() const override { return "Live Range Shrink"; }
46 bool runOnMachineFunction(MachineFunction &MF) override;
48 } // End anonymous namespace.
50 char LiveRangeShrink::ID = 0;
51 char &llvm::LiveRangeShrinkID = LiveRangeShrink::ID;
53 INITIALIZE_PASS(LiveRangeShrink, "lrshrink", "Live Range Shrink Pass", false,
56 typedef DenseMap<MachineInstr *, unsigned> InstOrderMap;
58 /// Returns \p New if it's dominated by \p Old, otherwise return \p Old.
59 /// \p M maintains a map from instruction to its dominating order that satisfies
60 /// M[A] > M[B] guarantees that A is dominated by B.
61 /// If \p New is not in \p M, return \p Old. Otherwise if \p Old is null, return
63 MachineInstr *FindDominatedInstruction(MachineInstr &New, MachineInstr *Old,
64 const InstOrderMap &M) {
65 auto NewIter = M.find(&New);
66 if (NewIter == M.end())
70 unsigned OrderOld = M.find(Old)->second;
71 unsigned OrderNew = NewIter->second;
72 if (OrderOld != OrderNew)
73 return OrderOld < OrderNew ? &New : Old;
74 // OrderOld == OrderNew, we need to iterate down from Old to see if it
75 // can reach New, if yes, New is dominated by Old.
76 for (MachineInstr *I = Old->getNextNode(); M.find(I)->second == OrderNew;
83 /// Builds Instruction to its dominating order number map \p M by traversing
84 /// from instruction \p Start.
85 void BuildInstOrderMap(MachineBasicBlock::iterator Start, InstOrderMap &M) {
88 for (MachineInstr &I : make_range(Start, Start->getParent()->end()))
91 } // end anonymous namespace
93 bool LiveRangeShrink::runOnMachineFunction(MachineFunction &MF) {
94 if (skipFunction(*MF.getFunction()))
97 MachineRegisterInfo &MRI = MF.getRegInfo();
99 DEBUG(dbgs() << "**** Analysing " << MF.getName() << '\n');
102 // Map from register to instruction order (value of IOM) where the
103 // register is used last. When moving instructions up, we need to
104 // make sure all its defs (including dead def) will not cross its
105 // last use when moving up.
106 DenseMap<unsigned, unsigned> UseMap;
108 for (MachineBasicBlock &MBB : MF) {
111 bool SawStore = false;
112 BuildInstOrderMap(MBB.begin(), IOM);
115 for (MachineBasicBlock::iterator Next = MBB.begin(); Next != MBB.end();) {
116 MachineInstr &MI = *Next;
118 if (MI.isPHI() || MI.isDebugValue())
123 unsigned CurrentOrder = IOM[&MI];
124 unsigned Barrier = 0;
125 for (const MachineOperand &MO : MI.operands()) {
126 if (!MO.isReg() || MO.isDebug())
129 UseMap[MO.getReg()] = CurrentOrder;
130 else if (MO.isDead() && UseMap.count(MO.getReg()))
131 // Barrier is the last instruction where MO get used. MI should not
132 // be moved above Barrier.
133 Barrier = std::max(Barrier, UseMap[MO.getReg()]);
136 if (!MI.isSafeToMove(nullptr, SawStore)) {
137 // If MI has side effects, it should become a barrier for code motion.
138 // IOM is rebuild from the next instruction to prevent later
139 // instructions from being moved before this MI.
140 if (MI.hasUnmodeledSideEffects() && Next != MBB.end()) {
141 BuildInstOrderMap(Next, IOM);
147 const MachineOperand *DefMO = nullptr;
148 MachineInstr *Insert = nullptr;
150 // Number of live-ranges that will be shortened. We do not count
151 // live-ranges that are defined by a COPY as it could be coalesced later.
152 unsigned NumEligibleUse = 0;
154 for (const MachineOperand &MO : MI.operands()) {
155 if (!MO.isReg() || MO.isDead() || MO.isDebug())
157 unsigned Reg = MO.getReg();
158 // Do not move the instruction if it def/uses a physical register,
159 // unless it is a constant physical register.
160 if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
161 !MRI.isConstantPhysReg(Reg)) {
166 // Do not move if there is more than one def.
172 } else if (MRI.hasOneNonDBGUse(Reg) && MRI.hasOneDef(Reg)) {
173 MachineInstr &DefInstr = *MRI.def_instr_begin(Reg);
174 if (!DefInstr.isCopy())
176 Insert = FindDominatedInstruction(DefInstr, Insert, IOM);
182 // Move the instruction when # of shrunk live range > 1.
183 if (DefMO && Insert && NumEligibleUse > 1 && Barrier <= IOM[Insert]) {
184 MachineBasicBlock::iterator I = std::next(Insert->getIterator());
185 // Skip all the PHI and debug instructions.
186 while (I != MBB.end() && (I->isPHI() || I->isDebugValue()))
188 if (I == MI.getIterator())
191 // Update the dominator order to be the same as the insertion point.
192 // We do this to maintain a non-decreasing order without need to update
193 // all instruction orders after the insertion point.
194 unsigned NewOrder = IOM[&*I];
196 NumInstrsHoistedToShrinkLiveRange++;
198 // Find MI's debug value following MI.
199 MachineBasicBlock::iterator EndIter = std::next(MI.getIterator());
200 if (MI.getOperand(0).isReg())
201 for (; EndIter != MBB.end() && EndIter->isDebugValue() &&
202 EndIter->getOperand(0).isReg() &&
203 EndIter->getOperand(0).getReg() == MI.getOperand(0).getReg();
205 IOM[&*EndIter] = NewOrder;
206 MBB.splice(I, &MBB, MI.getIterator(), EndIter);