1 //===-------------- MIRCanonicalizer.cpp - MIR Canonicalizer --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // The purpose of this pass is to employ a canonical code transformation so
11 // that code compiled with slightly different IR passes can be diffed more
12 // effectively than otherwise. This is done by renaming vregs in a given
13 // LiveRange in a canonical way. This pass also does a pseudo-scheduling to
14 // move defs closer to their use inorder to reduce diffs caused by slightly
15 // different schedules.
19 // llc -o - -run-pass mir-canonicalizer example.mir
21 // Reorders instructions canonically.
22 // Renames virtual register operands canonically.
23 // Strips certain MIR artifacts (optionally).
25 //===----------------------------------------------------------------------===//
27 #include "llvm/ADT/PostOrderIterator.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/Support/raw_ostream.h"
40 extern char &MIRCanonicalizerID;
43 #define DEBUG_TYPE "mir-canonicalizer"
45 static cl::opt<unsigned>
46 CanonicalizeFunctionNumber("canon-nth-function", cl::Hidden, cl::init(~0u),
48 cl::desc("Function number to canonicalize."));
50 static cl::opt<unsigned> CanonicalizeBasicBlockNumber(
51 "canon-nth-basicblock", cl::Hidden, cl::init(~0u), cl::value_desc("N"),
52 cl::desc("BasicBlock number to canonicalize."));
56 class MIRCanonicalizer : public MachineFunctionPass {
59 MIRCanonicalizer() : MachineFunctionPass(ID) {}
61 StringRef getPassName() const override {
62 return "Rename register operands in a canonical ordering.";
65 void getAnalysisUsage(AnalysisUsage &AU) const override {
67 MachineFunctionPass::getAnalysisUsage(AU);
70 bool runOnMachineFunction(MachineFunction &MF) override;
73 } // end anonymous namespace
75 enum VRType { RSE_Reg = 0, RSE_FrameIndex, RSE_NewCandidate };
81 TypedVReg(unsigned reg) : type(RSE_Reg), reg(reg) {}
82 TypedVReg(VRType type) : type(type), reg(~0U) {
83 assert(type != RSE_Reg && "Expected a non-register type.");
86 bool isReg() const { return type == RSE_Reg; }
87 bool isFrameIndex() const { return type == RSE_FrameIndex; }
88 bool isCandidate() const { return type == RSE_NewCandidate; }
90 VRType getType() const { return type; }
91 unsigned getReg() const {
92 assert(this->isReg() && "Expected a virtual or physical register.");
97 char MIRCanonicalizer::ID;
99 char &llvm::MIRCanonicalizerID = MIRCanonicalizer::ID;
101 INITIALIZE_PASS_BEGIN(MIRCanonicalizer, "mir-canonicalizer",
102 "Rename Register Operands Canonically", false, false)
104 INITIALIZE_PASS_END(MIRCanonicalizer, "mir-canonicalizer",
105 "Rename Register Operands Canonically", false, false)
107 static std::vector<MachineBasicBlock *> GetRPOList(MachineFunction &MF) {
108 ReversePostOrderTraversal<MachineBasicBlock *> RPOT(&*MF.begin());
109 std::vector<MachineBasicBlock *> RPOList;
110 for (auto MBB : RPOT) {
111 RPOList.push_back(MBB);
118 rescheduleLexographically(std::vector<MachineInstr *> instructions,
119 MachineBasicBlock *MBB,
120 std::function<MachineBasicBlock::iterator()> getPos) {
122 bool Changed = false;
123 using StringInstrPair = std::pair<std::string, MachineInstr *>;
124 std::vector<StringInstrPair> StringInstrMap;
126 for (auto *II : instructions) {
128 raw_string_ostream OS(S);
132 // Trim the assignment, or start from the begining in the case of a store.
133 const size_t i = S.find("=");
134 StringInstrMap.push_back({(i == std::string::npos) ? S : S.substr(i), II});
137 llvm::sort(StringInstrMap,
138 [](const StringInstrPair &a, const StringInstrPair &b) -> bool {
139 return (a.first < b.first);
142 for (auto &II : StringInstrMap) {
145 dbgs() << "Splicing ";
147 dbgs() << " right before: ";
152 MBB->splice(getPos(), MBB, II.second);
158 static bool rescheduleCanonically(unsigned &PseudoIdempotentInstCount,
159 MachineBasicBlock *MBB) {
161 bool Changed = false;
163 // Calculates the distance of MI from the begining of its parent BB.
164 auto getInstrIdx = [](const MachineInstr &MI) {
166 for (auto &CurMI : *MI.getParent()) {
174 // Pre-Populate vector of instructions to reschedule so that we don't
175 // clobber the iterator.
176 std::vector<MachineInstr *> Instructions;
177 for (auto &MI : *MBB) {
178 Instructions.push_back(&MI);
181 std::map<MachineInstr *, std::vector<MachineInstr *>> MultiUsers;
182 std::vector<MachineInstr *> PseudoIdempotentInstructions;
183 std::vector<unsigned> PhysRegDefs;
184 for (auto *II : Instructions) {
185 for (unsigned i = 1; i < II->getNumOperands(); i++) {
186 MachineOperand &MO = II->getOperand(i);
190 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
196 PhysRegDefs.push_back(MO.getReg());
200 for (auto *II : Instructions) {
201 if (II->getNumOperands() == 0)
203 if (II->mayLoadOrStore())
206 MachineOperand &MO = II->getOperand(0);
207 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
212 bool IsPseudoIdempotent = true;
213 for (unsigned i = 1; i < II->getNumOperands(); i++) {
215 if (II->getOperand(i).isImm()) {
219 if (II->getOperand(i).isReg()) {
220 if (!TargetRegisterInfo::isVirtualRegister(II->getOperand(i).getReg()))
221 if (llvm::find(PhysRegDefs, II->getOperand(i).getReg()) ==
227 IsPseudoIdempotent = false;
231 if (IsPseudoIdempotent) {
232 PseudoIdempotentInstructions.push_back(II);
236 LLVM_DEBUG(dbgs() << "Operand " << 0 << " of "; II->dump(); MO.dump(););
238 MachineInstr *Def = II;
239 unsigned Distance = ~0U;
240 MachineInstr *UseToBringDefCloserTo = nullptr;
241 MachineRegisterInfo *MRI = &MBB->getParent()->getRegInfo();
242 for (auto &UO : MRI->use_nodbg_operands(MO.getReg())) {
243 MachineInstr *UseInst = UO.getParent();
245 const unsigned DefLoc = getInstrIdx(*Def);
246 const unsigned UseLoc = getInstrIdx(*UseInst);
247 const unsigned Delta = (UseLoc - DefLoc);
249 if (UseInst->getParent() != Def->getParent())
251 if (DefLoc >= UseLoc)
254 if (Delta < Distance) {
256 UseToBringDefCloserTo = UseInst;
260 const auto BBE = MBB->instr_end();
261 MachineBasicBlock::iterator DefI = BBE;
262 MachineBasicBlock::iterator UseI = BBE;
264 for (auto BBI = MBB->instr_begin(); BBI != BBE; ++BBI) {
266 if (DefI != BBE && UseI != BBE)
274 if (&*BBI == UseToBringDefCloserTo) {
280 if (DefI == BBE || UseI == BBE)
284 dbgs() << "Splicing ";
286 dbgs() << " right before: ";
290 MultiUsers[UseToBringDefCloserTo].push_back(Def);
292 MBB->splice(UseI, MBB, DefI);
295 // Sort the defs for users of multiple defs lexographically.
296 for (const auto &E : MultiUsers) {
299 std::find_if(MBB->instr_begin(), MBB->instr_end(),
300 [&](MachineInstr &MI) -> bool { return &MI == E.first; });
302 if (UseI == MBB->instr_end())
306 dbgs() << "Rescheduling Multi-Use Instructions Lexographically.";);
307 Changed |= rescheduleLexographically(
308 E.second, MBB, [&]() -> MachineBasicBlock::iterator { return UseI; });
311 PseudoIdempotentInstCount = PseudoIdempotentInstructions.size();
313 dbgs() << "Rescheduling Idempotent Instructions Lexographically.";);
314 Changed |= rescheduleLexographically(
315 PseudoIdempotentInstructions, MBB,
316 [&]() -> MachineBasicBlock::iterator { return MBB->begin(); });
321 static bool propagateLocalCopies(MachineBasicBlock *MBB) {
322 bool Changed = false;
323 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
325 std::vector<MachineInstr *> Copies;
326 for (MachineInstr &MI : MBB->instrs()) {
328 Copies.push_back(&MI);
331 for (MachineInstr *MI : Copies) {
333 if (!MI->getOperand(0).isReg())
335 if (!MI->getOperand(1).isReg())
338 const unsigned Dst = MI->getOperand(0).getReg();
339 const unsigned Src = MI->getOperand(1).getReg();
341 if (!TargetRegisterInfo::isVirtualRegister(Dst))
343 if (!TargetRegisterInfo::isVirtualRegister(Src))
345 if (MRI.getRegClass(Dst) != MRI.getRegClass(Src))
348 for (auto UI = MRI.use_begin(Dst); UI != MRI.use_end(); ++UI) {
349 MachineOperand *MO = &*UI;
354 MI->eraseFromParent();
360 /// Here we find our candidates. What makes an interesting candidate?
361 /// An candidate for a canonicalization tree root is normally any kind of
362 /// instruction that causes side effects such as a store to memory or a copy to
363 /// a physical register or a return instruction. We use these as an expression
364 /// tree root that we walk inorder to build a canonical walk which should result
365 /// in canoncal vreg renaming.
366 static std::vector<MachineInstr *> populateCandidates(MachineBasicBlock *MBB) {
367 std::vector<MachineInstr *> Candidates;
368 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
370 for (auto II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
371 MachineInstr *MI = &*II;
373 bool DoesMISideEffect = false;
375 if (MI->getNumOperands() > 0 && MI->getOperand(0).isReg()) {
376 const unsigned Dst = MI->getOperand(0).getReg();
377 DoesMISideEffect |= !TargetRegisterInfo::isVirtualRegister(Dst);
379 for (auto UI = MRI.use_begin(Dst); UI != MRI.use_end(); ++UI) {
380 if (DoesMISideEffect)
382 DoesMISideEffect |= (UI->getParent()->getParent() != MI->getParent());
386 if (!MI->mayStore() && !MI->isBranch() && !DoesMISideEffect)
389 LLVM_DEBUG(dbgs() << "Found Candidate: "; MI->dump(););
390 Candidates.push_back(MI);
396 static void doCandidateWalk(std::vector<TypedVReg> &VRegs,
397 std::queue<TypedVReg> &RegQueue,
398 std::vector<MachineInstr *> &VisitedMIs,
399 const MachineBasicBlock *MBB) {
401 const MachineFunction &MF = *MBB->getParent();
402 const MachineRegisterInfo &MRI = MF.getRegInfo();
404 while (!RegQueue.empty()) {
406 auto TReg = RegQueue.front();
409 if (TReg.isFrameIndex()) {
410 LLVM_DEBUG(dbgs() << "Popping frame index.\n";);
411 VRegs.push_back(TypedVReg(RSE_FrameIndex));
415 assert(TReg.isReg() && "Expected vreg or physreg.");
416 unsigned Reg = TReg.getReg();
418 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
420 dbgs() << "Popping vreg ";
421 MRI.def_begin(Reg)->dump();
425 if (!llvm::any_of(VRegs, [&](const TypedVReg &TR) {
426 return TR.isReg() && TR.getReg() == Reg;
428 VRegs.push_back(TypedVReg(Reg));
431 LLVM_DEBUG(dbgs() << "Popping physreg.\n";);
432 VRegs.push_back(TypedVReg(Reg));
436 for (auto RI = MRI.def_begin(Reg), RE = MRI.def_end(); RI != RE; ++RI) {
437 MachineInstr *Def = RI->getParent();
439 if (Def->getParent() != MBB)
442 if (llvm::any_of(VisitedMIs,
443 [&](const MachineInstr *VMI) { return Def == VMI; })) {
448 dbgs() << "\n========================\n";
449 dbgs() << "Visited MI: ";
451 dbgs() << "BB Name: " << Def->getParent()->getName() << "\n";
452 dbgs() << "\n========================\n";
454 VisitedMIs.push_back(Def);
455 for (unsigned I = 1, E = Def->getNumOperands(); I != E; ++I) {
457 MachineOperand &MO = Def->getOperand(I);
459 LLVM_DEBUG(dbgs() << "Pushing frame index.\n";);
460 RegQueue.push(TypedVReg(RSE_FrameIndex));
465 RegQueue.push(TypedVReg(MO.getReg()));
472 class NamedVRegCursor {
473 MachineRegisterInfo &MRI;
474 unsigned virtualVRegNumber;
477 NamedVRegCursor(MachineRegisterInfo &MRI) : MRI(MRI) {
478 unsigned VRegGapIndex = 0;
479 const unsigned VR_GAP = (++VRegGapIndex * 1000);
481 unsigned I = MRI.createIncompleteVirtualRegister();
482 const unsigned E = (((I + VR_GAP) / VR_GAP) + 1) * VR_GAP;
484 virtualVRegNumber = E;
488 unsigned VRegGapIndex = 1;
489 const unsigned VR_GAP = (++VRegGapIndex * 1000);
491 unsigned I = virtualVRegNumber;
492 const unsigned E = (((I + VR_GAP) / VR_GAP) + 1) * VR_GAP;
494 virtualVRegNumber = E;
497 unsigned getVirtualVReg() const { return virtualVRegNumber; }
499 unsigned incrementVirtualVReg(unsigned incr = 1) {
500 virtualVRegNumber += incr;
501 return virtualVRegNumber;
504 unsigned createVirtualRegister(const TargetRegisterClass *RC) {
506 raw_string_ostream OS(S);
507 OS << "namedVReg" << (virtualVRegNumber & ~0x80000000);
511 return MRI.createVirtualRegister(RC, OS.str());
516 static std::map<unsigned, unsigned>
517 GetVRegRenameMap(const std::vector<TypedVReg> &VRegs,
518 const std::vector<unsigned> &renamedInOtherBB,
519 MachineRegisterInfo &MRI, NamedVRegCursor &NVC) {
520 std::map<unsigned, unsigned> VRegRenameMap;
521 bool FirstCandidate = true;
523 for (auto &vreg : VRegs) {
524 if (vreg.isFrameIndex()) {
525 // We skip one vreg for any frame index because there is a good chance
526 // (especially when comparing SelectionDAG to GlobalISel generated MIR)
527 // that in the other file we are just getting an incoming vreg that comes
528 // from a copy from a frame index. So it's safe to skip by one.
529 unsigned LastRenameReg = NVC.incrementVirtualVReg();
531 LLVM_DEBUG(dbgs() << "Skipping rename for FI " << LastRenameReg << "\n";);
533 } else if (vreg.isCandidate()) {
535 // After the first candidate, for every subsequent candidate, we skip mod
536 // 10 registers so that the candidates are more likely to start at the
537 // same vreg number making it more likely that the canonical walk from the
538 // candidate insruction. We don't need to skip from the first candidate of
539 // the BasicBlock because we already skip ahead several vregs for each BB.
540 unsigned LastRenameReg = NVC.getVirtualVReg();
542 NVC.incrementVirtualVReg(LastRenameReg % 10);
543 FirstCandidate = false;
545 } else if (!TargetRegisterInfo::isVirtualRegister(vreg.getReg())) {
546 unsigned LastRenameReg = NVC.incrementVirtualVReg();
549 dbgs() << "Skipping rename for Phys Reg " << LastRenameReg << "\n";
554 auto Reg = vreg.getReg();
555 if (llvm::find(renamedInOtherBB, Reg) != renamedInOtherBB.end()) {
556 LLVM_DEBUG(dbgs() << "Vreg " << Reg
557 << " already renamed in other BB.\n";);
561 auto Rename = NVC.createVirtualRegister(MRI.getRegClass(Reg));
563 if (VRegRenameMap.find(Reg) == VRegRenameMap.end()) {
564 LLVM_DEBUG(dbgs() << "Mapping vreg ";);
565 if (MRI.reg_begin(Reg) != MRI.reg_end()) {
566 LLVM_DEBUG(auto foo = &*MRI.reg_begin(Reg); foo->dump(););
568 LLVM_DEBUG(dbgs() << Reg;);
570 LLVM_DEBUG(dbgs() << " to ";);
571 if (MRI.reg_begin(Rename) != MRI.reg_end()) {
572 LLVM_DEBUG(auto foo = &*MRI.reg_begin(Rename); foo->dump(););
574 LLVM_DEBUG(dbgs() << Rename;);
576 LLVM_DEBUG(dbgs() << "\n";);
578 VRegRenameMap.insert(std::pair<unsigned, unsigned>(Reg, Rename));
582 return VRegRenameMap;
585 static bool doVRegRenaming(std::vector<unsigned> &RenamedInOtherBB,
586 const std::map<unsigned, unsigned> &VRegRenameMap,
587 MachineRegisterInfo &MRI) {
588 bool Changed = false;
589 for (auto I = VRegRenameMap.begin(), E = VRegRenameMap.end(); I != E; ++I) {
591 auto VReg = I->first;
592 auto Rename = I->second;
594 RenamedInOtherBB.push_back(Rename);
596 std::vector<MachineOperand *> RenameMOs;
597 for (auto &MO : MRI.reg_operands(VReg)) {
598 RenameMOs.push_back(&MO);
601 for (auto *MO : RenameMOs) {
606 MO->setIsKill(false);
613 static bool doDefKillClear(MachineBasicBlock *MBB) {
614 bool Changed = false;
616 for (auto &MI : *MBB) {
617 for (auto &MO : MI.operands()) {
620 if (!MO.isDef() && MO.isKill()) {
625 if (MO.isDef() && MO.isDead()) {
635 static bool runOnBasicBlock(MachineBasicBlock *MBB,
636 std::vector<StringRef> &bbNames,
637 std::vector<unsigned> &renamedInOtherBB,
638 unsigned &basicBlockNum, unsigned &VRegGapIndex,
639 NamedVRegCursor &NVC) {
641 if (CanonicalizeBasicBlockNumber != ~0U) {
642 if (CanonicalizeBasicBlockNumber != basicBlockNum++)
644 LLVM_DEBUG(dbgs() << "\n Canonicalizing BasicBlock " << MBB->getName()
648 if (llvm::find(bbNames, MBB->getName()) != bbNames.end()) {
650 dbgs() << "Found potentially duplicate BasicBlocks: " << MBB->getName()
657 dbgs() << "\n\n NEW BASIC BLOCK: " << MBB->getName() << " \n\n";
658 dbgs() << "\n\n================================================\n\n";
661 bool Changed = false;
662 MachineFunction &MF = *MBB->getParent();
663 MachineRegisterInfo &MRI = MF.getRegInfo();
665 bbNames.push_back(MBB->getName());
666 LLVM_DEBUG(dbgs() << "\n\n NEW BASIC BLOCK: " << MBB->getName() << "\n\n";);
668 LLVM_DEBUG(dbgs() << "MBB Before Canonical Copy Propagation:\n";
670 Changed |= propagateLocalCopies(MBB);
671 LLVM_DEBUG(dbgs() << "MBB After Canonical Copy Propagation:\n"; MBB->dump(););
673 LLVM_DEBUG(dbgs() << "MBB Before Scheduling:\n"; MBB->dump(););
674 unsigned IdempotentInstCount = 0;
675 Changed |= rescheduleCanonically(IdempotentInstCount, MBB);
676 LLVM_DEBUG(dbgs() << "MBB After Scheduling:\n"; MBB->dump(););
678 std::vector<MachineInstr *> Candidates = populateCandidates(MBB);
679 std::vector<MachineInstr *> VisitedMIs;
680 llvm::copy(Candidates, std::back_inserter(VisitedMIs));
682 std::vector<TypedVReg> VRegs;
683 for (auto candidate : Candidates) {
684 VRegs.push_back(TypedVReg(RSE_NewCandidate));
686 std::queue<TypedVReg> RegQueue;
688 // Here we walk the vreg operands of a non-root node along our walk.
689 // The root nodes are the original candidates (stores normally).
690 // These are normally not the root nodes (except for the case of copies to
691 // physical registers).
692 for (unsigned i = 1; i < candidate->getNumOperands(); i++) {
693 if (candidate->mayStore() || candidate->isBranch())
696 MachineOperand &MO = candidate->getOperand(i);
697 if (!(MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())))
700 LLVM_DEBUG(dbgs() << "Enqueue register"; MO.dump(); dbgs() << "\n";);
701 RegQueue.push(TypedVReg(MO.getReg()));
704 // Here we walk the root candidates. We start from the 0th operand because
705 // the root is normally a store to a vreg.
706 for (unsigned i = 0; i < candidate->getNumOperands(); i++) {
708 if (!candidate->mayStore() && !candidate->isBranch())
711 MachineOperand &MO = candidate->getOperand(i);
713 // TODO: Do we want to only add vregs here?
714 if (!MO.isReg() && !MO.isFI())
717 LLVM_DEBUG(dbgs() << "Enqueue Reg/FI"; MO.dump(); dbgs() << "\n";);
719 RegQueue.push(MO.isReg() ? TypedVReg(MO.getReg())
720 : TypedVReg(RSE_FrameIndex));
723 doCandidateWalk(VRegs, RegQueue, VisitedMIs, MBB);
726 // If we have populated no vregs to rename then bail.
727 // The rest of this function does the vreg remaping.
728 if (VRegs.size() == 0)
731 auto VRegRenameMap = GetVRegRenameMap(VRegs, renamedInOtherBB, MRI, NVC);
732 Changed |= doVRegRenaming(renamedInOtherBB, VRegRenameMap, MRI);
734 // Here we renumber the def vregs for the idempotent instructions from the top
735 // of the MachineBasicBlock so that they are named in the order that we sorted
736 // them alphabetically. Eventually we wont need SkipVRegs because we will use
737 // named vregs instead.
740 auto MII = MBB->begin();
741 for (unsigned i = 0; i < IdempotentInstCount && MII != MBB->end(); ++i) {
742 MachineInstr &MI = *MII++;
744 unsigned vRegToRename = MI.getOperand(0).getReg();
745 auto Rename = NVC.createVirtualRegister(MRI.getRegClass(vRegToRename));
747 std::vector<MachineOperand *> RenameMOs;
748 for (auto &MO : MRI.reg_operands(vRegToRename)) {
749 RenameMOs.push_back(&MO);
752 for (auto *MO : RenameMOs) {
757 Changed |= doDefKillClear(MBB);
759 LLVM_DEBUG(dbgs() << "Updated MachineBasicBlock:\n"; MBB->dump();
762 dbgs() << "\n\n================================================\n\n");
766 bool MIRCanonicalizer::runOnMachineFunction(MachineFunction &MF) {
768 static unsigned functionNum = 0;
769 if (CanonicalizeFunctionNumber != ~0U) {
770 if (CanonicalizeFunctionNumber != functionNum++)
772 LLVM_DEBUG(dbgs() << "\n Canonicalizing Function " << MF.getName()
776 // we need a valid vreg to create a vreg type for skipping all those
777 // stray vreg numbers so reach alignment/canonical vreg values.
778 std::vector<MachineBasicBlock *> RPOList = GetRPOList(MF);
781 dbgs() << "\n\n NEW MACHINE FUNCTION: " << MF.getName() << " \n\n";
782 dbgs() << "\n\n================================================\n\n";
783 dbgs() << "Total Basic Blocks: " << RPOList.size() << "\n";
785 : RPOList) { dbgs() << MBB->getName() << "\n"; } dbgs()
786 << "\n\n================================================\n\n";);
788 std::vector<StringRef> BBNames;
789 std::vector<unsigned> RenamedInOtherBB;
794 bool Changed = false;
796 MachineRegisterInfo &MRI = MF.getRegInfo();
797 NamedVRegCursor NVC(MRI);
798 for (auto MBB : RPOList)
800 runOnBasicBlock(MBB, BBNames, RenamedInOtherBB, BBNum, GapIdx, NVC);