1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/MIRPrinter.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallBitVector.h"
19 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
20 #include "llvm/CodeGen/MIRYamlMapping.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/BasicBlock.h"
28 #include "llvm/IR/Constants.h"
29 #include "llvm/IR/DebugInfo.h"
30 #include "llvm/IR/IRPrintingPasses.h"
31 #include "llvm/IR/Instructions.h"
32 #include "llvm/IR/Intrinsics.h"
33 #include "llvm/IR/Module.h"
34 #include "llvm/IR/ModuleSlotTracker.h"
35 #include "llvm/MC/MCSymbol.h"
36 #include "llvm/Support/Format.h"
37 #include "llvm/Support/MemoryBuffer.h"
38 #include "llvm/Support/Options.h"
39 #include "llvm/Support/YAMLTraits.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetIntrinsicInfo.h"
43 #include "llvm/Target/TargetSubtargetInfo.h"
47 static cl::opt<bool> SimplifyMIR("simplify-mir",
48 cl::desc("Leave out unnecessary information when printing MIR"));
52 /// This structure describes how to print out stack object references.
53 struct FrameIndexOperand {
58 FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
59 : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
61 /// Return an ordinary stack object reference.
62 static FrameIndexOperand create(StringRef Name, unsigned ID) {
63 return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
66 /// Return a fixed stack object reference.
67 static FrameIndexOperand createFixed(unsigned ID) {
68 return FrameIndexOperand("", ID, /*IsFixed=*/true);
72 } // end anonymous namespace
76 /// This class prints out the machine functions using the MIR serialization
80 DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
81 /// Maps from stack object indices to operand indices which will be used when
82 /// printing frame index machine operands.
83 DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
86 MIRPrinter(raw_ostream &OS) : OS(OS) {}
88 void print(const MachineFunction &MF);
90 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
91 const TargetRegisterInfo *TRI);
92 void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
93 const MachineFrameInfo &MFI);
94 void convert(yaml::MachineFunction &MF,
95 const MachineConstantPool &ConstantPool);
96 void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
97 const MachineJumpTableInfo &JTI);
98 void convertStackObjects(yaml::MachineFunction &YMF,
99 const MachineFunction &MF, ModuleSlotTracker &MST);
102 void initRegisterMaskIds(const MachineFunction &MF);
105 /// This class prints out the machine instructions using the MIR serialization
109 ModuleSlotTracker &MST;
110 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
111 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
113 bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
114 bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
117 MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
118 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
119 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
120 : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
121 StackObjectOperandMapping(StackObjectOperandMapping) {}
123 void print(const MachineBasicBlock &MBB);
125 void print(const MachineInstr &MI);
126 void printMBBReference(const MachineBasicBlock &MBB);
127 void printIRBlockReference(const BasicBlock &BB);
128 void printIRValueReference(const Value &V);
129 void printStackObjectReference(int FrameIndex);
130 void printOffset(int64_t Offset);
131 void printTargetFlags(const MachineOperand &Op);
132 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
133 unsigned I, bool ShouldPrintRegisterTies,
134 LLT TypeToPrint, bool IsDef = false);
135 void print(const MachineMemOperand &Op);
137 void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
140 } // end namespace llvm
145 /// This struct serializes the LLVM IR module.
146 template <> struct BlockScalarTraits<Module> {
147 static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
148 Mod.print(OS, nullptr);
150 static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
151 llvm_unreachable("LLVM Module is supposed to be parsed separately");
156 } // end namespace yaml
157 } // end namespace llvm
159 static void printReg(unsigned Reg, raw_ostream &OS,
160 const TargetRegisterInfo *TRI) {
161 // TODO: Print Stack Slots.
164 else if (TargetRegisterInfo::isVirtualRegister(Reg))
165 OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
166 else if (Reg < TRI->getNumRegs())
167 OS << '%' << StringRef(TRI->getName(Reg)).lower();
169 llvm_unreachable("Can't print this kind of register yet");
172 static void printReg(unsigned Reg, yaml::StringValue &Dest,
173 const TargetRegisterInfo *TRI) {
174 raw_string_ostream OS(Dest.Value);
175 printReg(Reg, OS, TRI);
178 void MIRPrinter::print(const MachineFunction &MF) {
179 initRegisterMaskIds(MF);
181 yaml::MachineFunction YamlMF;
182 YamlMF.Name = MF.getName();
183 YamlMF.Alignment = MF.getAlignment();
184 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
186 YamlMF.Legalized = MF.getProperties().hasProperty(
187 MachineFunctionProperties::Property::Legalized);
188 YamlMF.RegBankSelected = MF.getProperties().hasProperty(
189 MachineFunctionProperties::Property::RegBankSelected);
190 YamlMF.Selected = MF.getProperties().hasProperty(
191 MachineFunctionProperties::Property::Selected);
193 convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
194 ModuleSlotTracker MST(MF.getFunction()->getParent());
195 MST.incorporateFunction(*MF.getFunction());
196 convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
197 convertStackObjects(YamlMF, MF, MST);
198 if (const auto *ConstantPool = MF.getConstantPool())
199 convert(YamlMF, *ConstantPool);
200 if (const auto *JumpTableInfo = MF.getJumpTableInfo())
201 convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
202 raw_string_ostream StrOS(YamlMF.Body.Value.Value);
203 bool IsNewlineNeeded = false;
204 for (const auto &MBB : MF) {
207 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
209 IsNewlineNeeded = true;
212 yaml::Output Out(OS);
216 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
217 const TargetRegisterInfo *TRI) {
218 assert(RegMask && "Can't print an empty register mask");
219 OS << StringRef("CustomRegMask(");
221 bool IsRegInRegMaskFound = false;
222 for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
223 // Check whether the register is asserted in regmask.
224 if (RegMask[I / 32] & (1u << (I % 32))) {
225 if (IsRegInRegMaskFound)
227 printReg(I, OS, TRI);
228 IsRegInRegMaskFound = true;
235 void MIRPrinter::convert(yaml::MachineFunction &MF,
236 const MachineRegisterInfo &RegInfo,
237 const TargetRegisterInfo *TRI) {
238 MF.TracksRegLiveness = RegInfo.tracksLiveness();
240 // Print the virtual register definitions.
241 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
242 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
243 yaml::VirtualRegisterDefinition VReg;
245 if (RegInfo.getRegClassOrNull(Reg))
247 StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
248 else if (RegInfo.getRegBankOrNull(Reg))
249 VReg.Class = StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
251 VReg.Class = std::string("_");
252 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
253 "Generic registers must have a valid type");
255 unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
257 printReg(PreferredReg, VReg.PreferredRegister, TRI);
258 MF.VirtualRegisters.push_back(VReg);
261 // Print the live ins.
262 for (auto I = RegInfo.livein_begin(), E = RegInfo.livein_end(); I != E; ++I) {
263 yaml::MachineFunctionLiveIn LiveIn;
264 printReg(I->first, LiveIn.Register, TRI);
266 printReg(I->second, LiveIn.VirtualRegister, TRI);
267 MF.LiveIns.push_back(LiveIn);
270 // Prints the callee saved registers.
271 if (RegInfo.isUpdatedCSRsInitialized()) {
272 const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
273 std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
274 for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
275 yaml::FlowStringValue Reg;
276 printReg(*I, Reg, TRI);
277 CalleeSavedRegisters.push_back(Reg);
279 MF.CalleeSavedRegisters = CalleeSavedRegisters;
283 void MIRPrinter::convert(ModuleSlotTracker &MST,
284 yaml::MachineFrameInfo &YamlMFI,
285 const MachineFrameInfo &MFI) {
286 YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
287 YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
288 YamlMFI.HasStackMap = MFI.hasStackMap();
289 YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
290 YamlMFI.StackSize = MFI.getStackSize();
291 YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
292 YamlMFI.MaxAlignment = MFI.getMaxAlignment();
293 YamlMFI.AdjustsStack = MFI.adjustsStack();
294 YamlMFI.HasCalls = MFI.hasCalls();
295 YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
296 ? MFI.getMaxCallFrameSize() : ~0u;
297 YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
298 YamlMFI.HasVAStart = MFI.hasVAStart();
299 YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
300 if (MFI.getSavePoint()) {
301 raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
302 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
303 .printMBBReference(*MFI.getSavePoint());
305 if (MFI.getRestorePoint()) {
306 raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
307 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
308 .printMBBReference(*MFI.getRestorePoint());
312 void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
313 const MachineFunction &MF,
314 ModuleSlotTracker &MST) {
315 const MachineFrameInfo &MFI = MF.getFrameInfo();
316 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
317 // Process fixed stack objects.
319 for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
320 if (MFI.isDeadObjectIndex(I))
323 yaml::FixedMachineStackObject YamlObject;
325 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
326 ? yaml::FixedMachineStackObject::SpillSlot
327 : yaml::FixedMachineStackObject::DefaultType;
328 YamlObject.Offset = MFI.getObjectOffset(I);
329 YamlObject.Size = MFI.getObjectSize(I);
330 YamlObject.Alignment = MFI.getObjectAlignment(I);
331 YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
332 YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
333 YMF.FixedStackObjects.push_back(YamlObject);
334 StackObjectOperandMapping.insert(
335 std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
338 // Process ordinary stack objects.
340 for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
341 if (MFI.isDeadObjectIndex(I))
344 yaml::MachineStackObject YamlObject;
346 if (const auto *Alloca = MFI.getObjectAllocation(I))
347 YamlObject.Name.Value =
348 Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
349 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
350 ? yaml::MachineStackObject::SpillSlot
351 : MFI.isVariableSizedObjectIndex(I)
352 ? yaml::MachineStackObject::VariableSized
353 : yaml::MachineStackObject::DefaultType;
354 YamlObject.Offset = MFI.getObjectOffset(I);
355 YamlObject.Size = MFI.getObjectSize(I);
356 YamlObject.Alignment = MFI.getObjectAlignment(I);
358 YMF.StackObjects.push_back(YamlObject);
359 StackObjectOperandMapping.insert(std::make_pair(
360 I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
363 for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
364 yaml::StringValue Reg;
365 printReg(CSInfo.getReg(), Reg, TRI);
366 auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
367 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
368 "Invalid stack object index");
369 const FrameIndexOperand &StackObject = StackObjectInfo->second;
370 if (StackObject.IsFixed)
371 YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
373 YMF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
375 for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
376 auto LocalObject = MFI.getLocalFrameObjectMap(I);
377 auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
378 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
379 "Invalid stack object index");
380 const FrameIndexOperand &StackObject = StackObjectInfo->second;
381 assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
382 YMF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
385 // Print the stack object references in the frame information class after
386 // converting the stack objects.
387 if (MFI.hasStackProtectorIndex()) {
388 raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
389 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
390 .printStackObjectReference(MFI.getStackProtectorIndex());
393 // Print the debug variable information.
394 for (const MachineFunction::VariableDbgInfo &DebugVar :
395 MF.getVariableDbgInfo()) {
396 auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
397 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
398 "Invalid stack object index");
399 const FrameIndexOperand &StackObject = StackObjectInfo->second;
400 assert(!StackObject.IsFixed && "Expected a non-fixed stack object");
401 auto &Object = YMF.StackObjects[StackObject.ID];
403 raw_string_ostream StrOS(Object.DebugVar.Value);
404 DebugVar.Var->printAsOperand(StrOS, MST);
407 raw_string_ostream StrOS(Object.DebugExpr.Value);
408 DebugVar.Expr->printAsOperand(StrOS, MST);
411 raw_string_ostream StrOS(Object.DebugLoc.Value);
412 DebugVar.Loc->printAsOperand(StrOS, MST);
417 void MIRPrinter::convert(yaml::MachineFunction &MF,
418 const MachineConstantPool &ConstantPool) {
420 for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
421 // TODO: Serialize target specific constant pool entries.
422 if (Constant.isMachineConstantPoolEntry())
423 llvm_unreachable("Can't print target specific constant pool entries yet");
425 yaml::MachineConstantPoolValue YamlConstant;
427 raw_string_ostream StrOS(Str);
428 Constant.Val.ConstVal->printAsOperand(StrOS);
429 YamlConstant.ID = ID++;
430 YamlConstant.Value = StrOS.str();
431 YamlConstant.Alignment = Constant.getAlignment();
432 MF.Constants.push_back(YamlConstant);
436 void MIRPrinter::convert(ModuleSlotTracker &MST,
437 yaml::MachineJumpTable &YamlJTI,
438 const MachineJumpTableInfo &JTI) {
439 YamlJTI.Kind = JTI.getEntryKind();
441 for (const auto &Table : JTI.getJumpTables()) {
443 yaml::MachineJumpTable::Entry Entry;
445 for (const auto *MBB : Table.MBBs) {
446 raw_string_ostream StrOS(Str);
447 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
448 .printMBBReference(*MBB);
449 Entry.Blocks.push_back(StrOS.str());
452 YamlJTI.Entries.push_back(Entry);
456 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
457 const auto *TRI = MF.getSubtarget().getRegisterInfo();
459 for (const uint32_t *Mask : TRI->getRegMasks())
460 RegisterMaskIds.insert(std::make_pair(Mask, I++));
463 void llvm::guessSuccessors(const MachineBasicBlock &MBB,
464 SmallVectorImpl<MachineBasicBlock*> &Result,
465 bool &IsFallthrough) {
466 SmallPtrSet<MachineBasicBlock*,8> Seen;
468 for (const MachineInstr &MI : MBB) {
471 for (const MachineOperand &MO : MI.operands()) {
474 MachineBasicBlock *Succ = MO.getMBB();
475 auto RP = Seen.insert(Succ);
477 Result.push_back(Succ);
480 MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
481 IsFallthrough = I == MBB.end() || !I->isBarrier();
485 MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
486 if (MBB.succ_size() <= 1)
488 if (!MBB.hasSuccessorProbabilities())
491 SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(),
493 BranchProbability::normalizeProbabilities(Normalized.begin(),
495 SmallVector<BranchProbability,8> Equal(Normalized.size());
496 BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end());
498 return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
501 bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
502 SmallVector<MachineBasicBlock*,8> GuessedSuccs;
503 bool GuessedFallthrough;
504 guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
505 if (GuessedFallthrough) {
506 const MachineFunction &MF = *MBB.getParent();
507 MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
508 if (NextI != MF.end()) {
509 MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI);
510 if (!is_contained(GuessedSuccs, Next))
511 GuessedSuccs.push_back(Next);
514 if (GuessedSuccs.size() != MBB.succ_size())
516 return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
520 void MIPrinter::print(const MachineBasicBlock &MBB) {
521 assert(MBB.getNumber() >= 0 && "Invalid MBB number");
522 OS << "bb." << MBB.getNumber();
523 bool HasAttributes = false;
524 if (const auto *BB = MBB.getBasicBlock()) {
526 OS << "." << BB->getName();
528 HasAttributes = true;
530 int Slot = MST.getLocalSlot(BB);
532 OS << "<ir-block badref>";
534 OS << (Twine("%ir-block.") + Twine(Slot)).str();
537 if (MBB.hasAddressTaken()) {
538 OS << (HasAttributes ? ", " : " (");
539 OS << "address-taken";
540 HasAttributes = true;
543 OS << (HasAttributes ? ", " : " (");
545 HasAttributes = true;
547 if (MBB.getAlignment()) {
548 OS << (HasAttributes ? ", " : " (");
549 OS << "align " << MBB.getAlignment();
550 HasAttributes = true;
556 bool HasLineAttributes = false;
557 // Print the successors
558 bool canPredictProbs = canPredictBranchProbabilities(MBB);
559 if (!MBB.succ_empty() && (!SimplifyMIR || !canPredictProbs ||
560 !canPredictSuccessors(MBB))) {
561 OS.indent(2) << "successors: ";
562 for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
563 if (I != MBB.succ_begin())
565 printMBBReference(**I);
566 if (!SimplifyMIR || !canPredictProbs)
568 << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
572 HasLineAttributes = true;
575 // Print the live in registers.
576 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
577 if (MRI.tracksLiveness() && !MBB.livein_empty()) {
578 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
579 OS.indent(2) << "liveins: ";
581 for (const auto &LI : MBB.liveins()) {
585 printReg(LI.PhysReg, OS, &TRI);
586 if (!LI.LaneMask.all())
587 OS << ":0x" << PrintLaneMask(LI.LaneMask);
590 HasLineAttributes = true;
593 if (HasLineAttributes)
595 bool IsInBundle = false;
596 for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
597 const MachineInstr &MI = *I;
598 if (IsInBundle && !MI.isInsideBundle()) {
599 OS.indent(2) << "}\n";
602 OS.indent(IsInBundle ? 4 : 2);
604 if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
611 OS.indent(2) << "}\n";
614 /// Return true when an instruction has tied register that can't be determined
615 /// by the instruction's descriptor.
616 static bool hasComplexRegisterTies(const MachineInstr &MI) {
617 const MCInstrDesc &MCID = MI.getDesc();
618 for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I) {
619 const auto &Operand = MI.getOperand(I);
620 if (!Operand.isReg() || Operand.isDef())
621 // Ignore the defined registers as MCID marks only the uses as tied.
623 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
624 int TiedIdx = Operand.isTied() ? int(MI.findTiedOperandIdx(I)) : -1;
625 if (ExpectedTiedIdx != TiedIdx)
631 static LLT getTypeToPrint(const MachineInstr &MI, unsigned OpIdx,
632 SmallBitVector &PrintedTypes,
633 const MachineRegisterInfo &MRI) {
634 const MachineOperand &Op = MI.getOperand(OpIdx);
638 if (MI.isVariadic() || OpIdx >= MI.getNumExplicitOperands())
639 return MRI.getType(Op.getReg());
641 auto &OpInfo = MI.getDesc().OpInfo[OpIdx];
642 if (!OpInfo.isGenericType())
643 return MRI.getType(Op.getReg());
645 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
648 PrintedTypes.set(OpInfo.getGenericTypeIndex());
649 return MRI.getType(Op.getReg());
652 void MIPrinter::print(const MachineInstr &MI) {
653 const auto *MF = MI.getParent()->getParent();
654 const auto &MRI = MF->getRegInfo();
655 const auto &SubTarget = MF->getSubtarget();
656 const auto *TRI = SubTarget.getRegisterInfo();
657 assert(TRI && "Expected target register info");
658 const auto *TII = SubTarget.getInstrInfo();
659 assert(TII && "Expected target instruction info");
660 if (MI.isCFIInstruction())
661 assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
663 SmallBitVector PrintedTypes(8);
664 bool ShouldPrintRegisterTies = hasComplexRegisterTies(MI);
665 unsigned I = 0, E = MI.getNumOperands();
666 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
667 !MI.getOperand(I).isImplicit();
671 print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies,
672 getTypeToPrint(MI, I, PrintedTypes, MRI),
678 if (MI.getFlag(MachineInstr::FrameSetup))
679 OS << "frame-setup ";
680 OS << TII->getName(MI.getOpcode());
684 bool NeedComma = false;
688 print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies,
689 getTypeToPrint(MI, I, PrintedTypes, MRI));
693 if (MI.getDebugLoc()) {
696 OS << " debug-location ";
697 MI.getDebugLoc()->printAsOperand(OS, MST);
700 if (!MI.memoperands_empty()) {
702 bool NeedComma = false;
703 for (const auto *Op : MI.memoperands()) {
712 void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
713 OS << "%bb." << MBB.getNumber();
714 if (const auto *BB = MBB.getBasicBlock()) {
716 OS << '.' << BB->getName();
720 static void printIRSlotNumber(raw_ostream &OS, int Slot) {
727 void MIPrinter::printIRBlockReference(const BasicBlock &BB) {
730 printLLVMNameWithoutPrefix(OS, BB.getName());
733 const Function *F = BB.getParent();
735 if (F == MST.getCurrentFunction()) {
736 Slot = MST.getLocalSlot(&BB);
738 ModuleSlotTracker CustomMST(F->getParent(),
739 /*ShouldInitializeAllMetadata=*/false);
740 CustomMST.incorporateFunction(*F);
741 Slot = CustomMST.getLocalSlot(&BB);
743 printIRSlotNumber(OS, Slot);
746 void MIPrinter::printIRValueReference(const Value &V) {
747 if (isa<GlobalValue>(V)) {
748 V.printAsOperand(OS, /*PrintType=*/false, MST);
751 if (isa<Constant>(V)) {
752 // Machine memory operands can load/store to/from constant value pointers.
754 V.printAsOperand(OS, /*PrintType=*/true, MST);
760 printLLVMNameWithoutPrefix(OS, V.getName());
763 printIRSlotNumber(OS, MST.getLocalSlot(&V));
766 void MIPrinter::printStackObjectReference(int FrameIndex) {
767 auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
768 assert(ObjectInfo != StackObjectOperandMapping.end() &&
769 "Invalid frame index");
770 const FrameIndexOperand &Operand = ObjectInfo->second;
771 if (Operand.IsFixed) {
772 OS << "%fixed-stack." << Operand.ID;
775 OS << "%stack." << Operand.ID;
776 if (!Operand.Name.empty())
777 OS << '.' << Operand.Name;
780 void MIPrinter::printOffset(int64_t Offset) {
784 OS << " - " << -Offset;
787 OS << " + " << Offset;
790 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
791 auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
792 for (const auto &I : Flags) {
800 void MIPrinter::printTargetFlags(const MachineOperand &Op) {
801 if (!Op.getTargetFlags())
804 Op.getParent()->getParent()->getParent()->getSubtarget().getInstrInfo();
805 assert(TII && "expected instruction info");
806 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
807 OS << "target-flags(";
808 const bool HasDirectFlags = Flags.first;
809 const bool HasBitmaskFlags = Flags.second;
810 if (!HasDirectFlags && !HasBitmaskFlags) {
814 if (HasDirectFlags) {
815 if (const auto *Name = getTargetFlagName(TII, Flags.first))
818 OS << "<unknown target flag>";
820 if (!HasBitmaskFlags) {
824 bool IsCommaNeeded = HasDirectFlags;
825 unsigned BitMask = Flags.second;
826 auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
827 for (const auto &Mask : BitMasks) {
828 // Check if the flag's bitmask has the bits of the current mask set.
829 if ((BitMask & Mask.first) == Mask.first) {
832 IsCommaNeeded = true;
834 // Clear the bits which were serialized from the flag's bitmask.
835 BitMask &= ~(Mask.first);
839 // When the resulting flag's bitmask isn't zero, we know that we didn't
840 // serialize all of the bit flags.
843 OS << "<unknown bitmask target flag>";
848 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
849 const auto *TII = MF.getSubtarget().getInstrInfo();
850 assert(TII && "expected instruction info");
851 auto Indices = TII->getSerializableTargetIndices();
852 for (const auto &I : Indices) {
853 if (I.first == Index) {
860 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
861 unsigned I, bool ShouldPrintRegisterTies, LLT TypeToPrint,
863 printTargetFlags(Op);
864 switch (Op.getType()) {
865 case MachineOperand::MO_Register:
867 OS << (Op.isDef() ? "implicit-def " : "implicit ");
868 else if (!IsDef && Op.isDef())
869 // Print the 'def' flag only when the operand is defined after '='.
871 if (Op.isInternalRead())
879 if (Op.isEarlyClobber())
880 OS << "early-clobber ";
883 printReg(Op.getReg(), OS, TRI);
884 // Print the sub register.
885 if (Op.getSubReg() != 0)
886 OS << '.' << TRI->getSubRegIndexName(Op.getSubReg());
887 if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef())
888 OS << "(tied-def " << Op.getParent()->findTiedOperandIdx(I) << ")";
889 if (TypeToPrint.isValid())
890 OS << '(' << TypeToPrint << ')';
892 case MachineOperand::MO_Immediate:
895 case MachineOperand::MO_CImmediate:
896 Op.getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
898 case MachineOperand::MO_FPImmediate:
899 Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
901 case MachineOperand::MO_MachineBasicBlock:
902 printMBBReference(*Op.getMBB());
904 case MachineOperand::MO_FrameIndex:
905 printStackObjectReference(Op.getIndex());
907 case MachineOperand::MO_ConstantPoolIndex:
908 OS << "%const." << Op.getIndex();
909 printOffset(Op.getOffset());
911 case MachineOperand::MO_TargetIndex: {
912 OS << "target-index(";
913 if (const auto *Name = getTargetIndexName(
914 *Op.getParent()->getParent()->getParent(), Op.getIndex()))
919 printOffset(Op.getOffset());
922 case MachineOperand::MO_JumpTableIndex:
923 OS << "%jump-table." << Op.getIndex();
925 case MachineOperand::MO_ExternalSymbol:
927 printLLVMNameWithoutPrefix(OS, Op.getSymbolName());
928 printOffset(Op.getOffset());
930 case MachineOperand::MO_GlobalAddress:
931 Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
932 printOffset(Op.getOffset());
934 case MachineOperand::MO_BlockAddress:
935 OS << "blockaddress(";
936 Op.getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
939 printIRBlockReference(*Op.getBlockAddress()->getBasicBlock());
941 printOffset(Op.getOffset());
943 case MachineOperand::MO_RegisterMask: {
944 auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
945 if (RegMaskInfo != RegisterMaskIds.end())
946 OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
948 printCustomRegMask(Op.getRegMask(), OS, TRI);
951 case MachineOperand::MO_RegisterLiveOut: {
952 const uint32_t *RegMask = Op.getRegLiveOut();
954 bool IsCommaNeeded = false;
955 for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
956 if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
959 printReg(Reg, OS, TRI);
960 IsCommaNeeded = true;
966 case MachineOperand::MO_Metadata:
967 Op.getMetadata()->printAsOperand(OS, MST);
969 case MachineOperand::MO_MCSymbol:
970 OS << "<mcsymbol " << *Op.getMCSymbol() << ">";
972 case MachineOperand::MO_CFIIndex: {
973 const MachineFunction &MF = *Op.getParent()->getParent()->getParent();
974 print(MF.getFrameInstructions()[Op.getCFIIndex()], TRI);
977 case MachineOperand::MO_IntrinsicID: {
978 Intrinsic::ID ID = Op.getIntrinsicID();
979 if (ID < Intrinsic::num_intrinsics)
980 OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
982 const MachineFunction &MF = *Op.getParent()->getParent()->getParent();
983 const TargetIntrinsicInfo *TII = MF.getTarget().getIntrinsicInfo();
984 OS << "intrinsic(@" << TII->getName(ID) << ')';
988 case MachineOperand::MO_Predicate: {
989 auto Pred = static_cast<CmpInst::Predicate>(Op.getPredicate());
990 OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
991 << CmpInst::getPredicateName(Pred) << ')';
997 void MIPrinter::print(const MachineMemOperand &Op) {
999 // TODO: Print operand's target specific flags.
1000 if (Op.isVolatile())
1002 if (Op.isNonTemporal())
1003 OS << "non-temporal ";
1004 if (Op.isDereferenceable())
1005 OS << "dereferenceable ";
1006 if (Op.isInvariant())
1011 assert(Op.isStore() && "Non load machine operand must be a store");
1015 if (Op.getSynchScope() == SynchronizationScope::SingleThread)
1016 OS << "singlethread ";
1018 if (Op.getOrdering() != AtomicOrdering::NotAtomic)
1019 OS << toIRString(Op.getOrdering()) << ' ';
1020 if (Op.getFailureOrdering() != AtomicOrdering::NotAtomic)
1021 OS << toIRString(Op.getFailureOrdering()) << ' ';
1024 if (const Value *Val = Op.getValue()) {
1025 OS << (Op.isLoad() ? " from " : " into ");
1026 printIRValueReference(*Val);
1027 } else if (const PseudoSourceValue *PVal = Op.getPseudoValue()) {
1028 OS << (Op.isLoad() ? " from " : " into ");
1029 assert(PVal && "Expected a pseudo source value");
1030 switch (PVal->kind()) {
1031 case PseudoSourceValue::Stack:
1034 case PseudoSourceValue::GOT:
1037 case PseudoSourceValue::JumpTable:
1040 case PseudoSourceValue::ConstantPool:
1041 OS << "constant-pool";
1043 case PseudoSourceValue::FixedStack:
1044 printStackObjectReference(
1045 cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex());
1047 case PseudoSourceValue::GlobalValueCallEntry:
1048 OS << "call-entry ";
1049 cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1050 OS, /*PrintType=*/false, MST);
1052 case PseudoSourceValue::ExternalSymbolCallEntry:
1053 OS << "call-entry $";
1054 printLLVMNameWithoutPrefix(
1055 OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1057 case PseudoSourceValue::TargetCustom:
1058 llvm_unreachable("TargetCustom pseudo source values are not supported");
1062 printOffset(Op.getOffset());
1063 if (Op.getBaseAlignment() != Op.getSize())
1064 OS << ", align " << Op.getBaseAlignment();
1065 auto AAInfo = Op.getAAInfo();
1068 AAInfo.TBAA->printAsOperand(OS, MST);
1071 OS << ", !alias.scope ";
1072 AAInfo.Scope->printAsOperand(OS, MST);
1074 if (AAInfo.NoAlias) {
1075 OS << ", !noalias ";
1076 AAInfo.NoAlias->printAsOperand(OS, MST);
1078 if (Op.getRanges()) {
1080 Op.getRanges()->printAsOperand(OS, MST);
1085 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
1086 const TargetRegisterInfo *TRI) {
1087 int Reg = TRI->getLLVMRegNum(DwarfReg, true);
1092 printReg(Reg, OS, TRI);
1095 void MIPrinter::print(const MCCFIInstruction &CFI,
1096 const TargetRegisterInfo *TRI) {
1097 switch (CFI.getOperation()) {
1098 case MCCFIInstruction::OpSameValue:
1099 OS << "same_value ";
1101 OS << "<mcsymbol> ";
1102 printCFIRegister(CFI.getRegister(), OS, TRI);
1104 case MCCFIInstruction::OpOffset:
1107 OS << "<mcsymbol> ";
1108 printCFIRegister(CFI.getRegister(), OS, TRI);
1109 OS << ", " << CFI.getOffset();
1111 case MCCFIInstruction::OpDefCfaRegister:
1112 OS << "def_cfa_register ";
1114 OS << "<mcsymbol> ";
1115 printCFIRegister(CFI.getRegister(), OS, TRI);
1117 case MCCFIInstruction::OpDefCfaOffset:
1118 OS << "def_cfa_offset ";
1120 OS << "<mcsymbol> ";
1121 OS << CFI.getOffset();
1123 case MCCFIInstruction::OpDefCfa:
1126 OS << "<mcsymbol> ";
1127 printCFIRegister(CFI.getRegister(), OS, TRI);
1128 OS << ", " << CFI.getOffset();
1131 // TODO: Print the other CFI Operations.
1132 OS << "<unserializable cfi operation>";
1137 void llvm::printMIR(raw_ostream &OS, const Module &M) {
1138 yaml::Output Out(OS);
1139 Out << const_cast<Module &>(M);
1142 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
1143 MIRPrinter Printer(OS);