1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/MIRPrinter.h"
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/ADT/None.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallBitVector.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Twine.h"
24 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
25 #include "llvm/CodeGen/MIRYamlMapping.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineMemOperand.h"
33 #include "llvm/CodeGen/MachineOperand.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/PseudoSourceValue.h"
36 #include "llvm/CodeGen/TargetInstrInfo.h"
37 #include "llvm/CodeGen/TargetRegisterInfo.h"
38 #include "llvm/CodeGen/TargetSubtargetInfo.h"
39 #include "llvm/IR/BasicBlock.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DebugLoc.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalValue.h"
45 #include "llvm/IR/IRPrintingPasses.h"
46 #include "llvm/IR/InstrTypes.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/Module.h"
50 #include "llvm/IR/ModuleSlotTracker.h"
51 #include "llvm/IR/Value.h"
52 #include "llvm/MC/LaneBitmask.h"
53 #include "llvm/MC/MCDwarf.h"
54 #include "llvm/MC/MCSymbol.h"
55 #include "llvm/Support/AtomicOrdering.h"
56 #include "llvm/Support/BranchProbability.h"
57 #include "llvm/Support/Casting.h"
58 #include "llvm/Support/CommandLine.h"
59 #include "llvm/Support/ErrorHandling.h"
60 #include "llvm/Support/Format.h"
61 #include "llvm/Support/LowLevelTypeImpl.h"
62 #include "llvm/Support/YAMLTraits.h"
63 #include "llvm/Support/raw_ostream.h"
64 #include "llvm/Target/TargetIntrinsicInfo.h"
65 #include "llvm/Target/TargetMachine.h"
77 static cl::opt<bool> SimplifyMIR(
78 "simplify-mir", cl::Hidden,
79 cl::desc("Leave out unnecessary information when printing MIR"));
83 /// This structure describes how to print out stack object references.
84 struct FrameIndexOperand {
89 FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
90 : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
92 /// Return an ordinary stack object reference.
93 static FrameIndexOperand create(StringRef Name, unsigned ID) {
94 return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
97 /// Return a fixed stack object reference.
98 static FrameIndexOperand createFixed(unsigned ID) {
99 return FrameIndexOperand("", ID, /*IsFixed=*/true);
103 } // end anonymous namespace
107 /// This class prints out the machine functions using the MIR serialization
111 DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
112 /// Maps from stack object indices to operand indices which will be used when
113 /// printing frame index machine operands.
114 DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
117 MIRPrinter(raw_ostream &OS) : OS(OS) {}
119 void print(const MachineFunction &MF);
121 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
122 const TargetRegisterInfo *TRI);
123 void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
124 const MachineFrameInfo &MFI);
125 void convert(yaml::MachineFunction &MF,
126 const MachineConstantPool &ConstantPool);
127 void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
128 const MachineJumpTableInfo &JTI);
129 void convertStackObjects(yaml::MachineFunction &YMF,
130 const MachineFunction &MF, ModuleSlotTracker &MST);
133 void initRegisterMaskIds(const MachineFunction &MF);
136 /// This class prints out the machine instructions using the MIR serialization
140 ModuleSlotTracker &MST;
141 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
142 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
143 /// Synchronization scope names registered with LLVMContext.
144 SmallVector<StringRef, 8> SSNs;
146 bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
147 bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
150 MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
151 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
152 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
153 : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
154 StackObjectOperandMapping(StackObjectOperandMapping) {}
156 void print(const MachineBasicBlock &MBB);
158 void print(const MachineInstr &MI);
159 void printStackObjectReference(int FrameIndex);
160 void print(const MachineInstr &MI, unsigned OpIdx,
161 const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
162 LLT TypeToPrint, bool PrintDef = true);
165 } // end namespace llvm
170 /// This struct serializes the LLVM IR module.
171 template <> struct BlockScalarTraits<Module> {
172 static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
173 Mod.print(OS, nullptr);
176 static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
177 llvm_unreachable("LLVM Module is supposed to be parsed separately");
182 } // end namespace yaml
183 } // end namespace llvm
185 static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
186 const TargetRegisterInfo *TRI) {
187 raw_string_ostream OS(Dest.Value);
188 OS << printReg(Reg, TRI);
191 void MIRPrinter::print(const MachineFunction &MF) {
192 initRegisterMaskIds(MF);
194 yaml::MachineFunction YamlMF;
195 YamlMF.Name = MF.getName();
196 YamlMF.Alignment = MF.getAlignment();
197 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
199 YamlMF.Legalized = MF.getProperties().hasProperty(
200 MachineFunctionProperties::Property::Legalized);
201 YamlMF.RegBankSelected = MF.getProperties().hasProperty(
202 MachineFunctionProperties::Property::RegBankSelected);
203 YamlMF.Selected = MF.getProperties().hasProperty(
204 MachineFunctionProperties::Property::Selected);
205 YamlMF.FailedISel = MF.getProperties().hasProperty(
206 MachineFunctionProperties::Property::FailedISel);
208 convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
209 ModuleSlotTracker MST(MF.getFunction().getParent());
210 MST.incorporateFunction(MF.getFunction());
211 convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
212 convertStackObjects(YamlMF, MF, MST);
213 if (const auto *ConstantPool = MF.getConstantPool())
214 convert(YamlMF, *ConstantPool);
215 if (const auto *JumpTableInfo = MF.getJumpTableInfo())
216 convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
217 raw_string_ostream StrOS(YamlMF.Body.Value.Value);
218 bool IsNewlineNeeded = false;
219 for (const auto &MBB : MF) {
222 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
224 IsNewlineNeeded = true;
227 yaml::Output Out(OS);
229 Out.setWriteDefaultValues(true);
233 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
234 const TargetRegisterInfo *TRI) {
235 assert(RegMask && "Can't print an empty register mask");
236 OS << StringRef("CustomRegMask(");
238 bool IsRegInRegMaskFound = false;
239 for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
240 // Check whether the register is asserted in regmask.
241 if (RegMask[I / 32] & (1u << (I % 32))) {
242 if (IsRegInRegMaskFound)
244 OS << printReg(I, TRI);
245 IsRegInRegMaskFound = true;
252 static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest,
253 const MachineRegisterInfo &RegInfo,
254 const TargetRegisterInfo *TRI) {
255 raw_string_ostream OS(Dest.Value);
256 OS << printRegClassOrBank(Reg, RegInfo, TRI);
259 template <typename T>
261 printStackObjectDbgInfo(const MachineFunction::VariableDbgInfo &DebugVar,
262 T &Object, ModuleSlotTracker &MST) {
263 std::array<std::string *, 3> Outputs{{&Object.DebugVar.Value,
264 &Object.DebugExpr.Value,
265 &Object.DebugLoc.Value}};
266 std::array<const Metadata *, 3> Metas{{DebugVar.Var,
269 for (unsigned i = 0; i < 3; ++i) {
270 raw_string_ostream StrOS(*Outputs[i]);
271 Metas[i]->printAsOperand(StrOS, MST);
275 void MIRPrinter::convert(yaml::MachineFunction &MF,
276 const MachineRegisterInfo &RegInfo,
277 const TargetRegisterInfo *TRI) {
278 MF.TracksRegLiveness = RegInfo.tracksLiveness();
280 // Print the virtual register definitions.
281 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
282 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
283 yaml::VirtualRegisterDefinition VReg;
285 if (RegInfo.getVRegName(Reg) != "")
287 ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
288 unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
290 printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
291 MF.VirtualRegisters.push_back(VReg);
294 // Print the live ins.
295 for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
296 yaml::MachineFunctionLiveIn LiveIn;
297 printRegMIR(LI.first, LiveIn.Register, TRI);
299 printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
300 MF.LiveIns.push_back(LiveIn);
303 // Prints the callee saved registers.
304 if (RegInfo.isUpdatedCSRsInitialized()) {
305 const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
306 std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
307 for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
308 yaml::FlowStringValue Reg;
309 printRegMIR(*I, Reg, TRI);
310 CalleeSavedRegisters.push_back(Reg);
312 MF.CalleeSavedRegisters = CalleeSavedRegisters;
316 void MIRPrinter::convert(ModuleSlotTracker &MST,
317 yaml::MachineFrameInfo &YamlMFI,
318 const MachineFrameInfo &MFI) {
319 YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
320 YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
321 YamlMFI.HasStackMap = MFI.hasStackMap();
322 YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
323 YamlMFI.StackSize = MFI.getStackSize();
324 YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
325 YamlMFI.MaxAlignment = MFI.getMaxAlignment();
326 YamlMFI.AdjustsStack = MFI.adjustsStack();
327 YamlMFI.HasCalls = MFI.hasCalls();
328 YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
329 ? MFI.getMaxCallFrameSize() : ~0u;
330 YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
331 YamlMFI.HasVAStart = MFI.hasVAStart();
332 YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
333 YamlMFI.LocalFrameSize = MFI.getLocalFrameSize();
334 if (MFI.getSavePoint()) {
335 raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
336 StrOS << printMBBReference(*MFI.getSavePoint());
338 if (MFI.getRestorePoint()) {
339 raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
340 StrOS << printMBBReference(*MFI.getRestorePoint());
344 void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
345 const MachineFunction &MF,
346 ModuleSlotTracker &MST) {
347 const MachineFrameInfo &MFI = MF.getFrameInfo();
348 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
349 // Process fixed stack objects.
351 for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
352 if (MFI.isDeadObjectIndex(I))
355 yaml::FixedMachineStackObject YamlObject;
357 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
358 ? yaml::FixedMachineStackObject::SpillSlot
359 : yaml::FixedMachineStackObject::DefaultType;
360 YamlObject.Offset = MFI.getObjectOffset(I);
361 YamlObject.Size = MFI.getObjectSize(I);
362 YamlObject.Alignment = MFI.getObjectAlignment(I);
363 YamlObject.StackID = MFI.getStackID(I);
364 YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
365 YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
366 YMF.FixedStackObjects.push_back(YamlObject);
367 StackObjectOperandMapping.insert(
368 std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
371 // Process ordinary stack objects.
373 for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
374 if (MFI.isDeadObjectIndex(I))
377 yaml::MachineStackObject YamlObject;
379 if (const auto *Alloca = MFI.getObjectAllocation(I))
380 YamlObject.Name.Value =
381 Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
382 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
383 ? yaml::MachineStackObject::SpillSlot
384 : MFI.isVariableSizedObjectIndex(I)
385 ? yaml::MachineStackObject::VariableSized
386 : yaml::MachineStackObject::DefaultType;
387 YamlObject.Offset = MFI.getObjectOffset(I);
388 YamlObject.Size = MFI.getObjectSize(I);
389 YamlObject.Alignment = MFI.getObjectAlignment(I);
390 YamlObject.StackID = MFI.getStackID(I);
392 YMF.StackObjects.push_back(YamlObject);
393 StackObjectOperandMapping.insert(std::make_pair(
394 I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
397 for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
398 yaml::StringValue Reg;
399 printRegMIR(CSInfo.getReg(), Reg, TRI);
400 auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
401 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
402 "Invalid stack object index");
403 const FrameIndexOperand &StackObject = StackObjectInfo->second;
404 if (StackObject.IsFixed) {
405 YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
406 YMF.FixedStackObjects[StackObject.ID].CalleeSavedRestored =
409 YMF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
410 YMF.StackObjects[StackObject.ID].CalleeSavedRestored =
414 for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
415 auto LocalObject = MFI.getLocalFrameObjectMap(I);
416 auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
417 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
418 "Invalid stack object index");
419 const FrameIndexOperand &StackObject = StackObjectInfo->second;
420 assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
421 YMF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
424 // Print the stack object references in the frame information class after
425 // converting the stack objects.
426 if (MFI.hasStackProtectorIndex()) {
427 raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
428 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
429 .printStackObjectReference(MFI.getStackProtectorIndex());
432 // Print the debug variable information.
433 for (const MachineFunction::VariableDbgInfo &DebugVar :
434 MF.getVariableDbgInfo()) {
435 auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
436 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
437 "Invalid stack object index");
438 const FrameIndexOperand &StackObject = StackObjectInfo->second;
439 if (StackObject.IsFixed) {
440 auto &Object = YMF.FixedStackObjects[StackObject.ID];
441 printStackObjectDbgInfo(DebugVar, Object, MST);
443 auto &Object = YMF.StackObjects[StackObject.ID];
444 printStackObjectDbgInfo(DebugVar, Object, MST);
449 void MIRPrinter::convert(yaml::MachineFunction &MF,
450 const MachineConstantPool &ConstantPool) {
452 for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
454 raw_string_ostream StrOS(Str);
455 if (Constant.isMachineConstantPoolEntry()) {
456 Constant.Val.MachineCPVal->print(StrOS);
458 Constant.Val.ConstVal->printAsOperand(StrOS);
461 yaml::MachineConstantPoolValue YamlConstant;
462 YamlConstant.ID = ID++;
463 YamlConstant.Value = StrOS.str();
464 YamlConstant.Alignment = Constant.getAlignment();
465 YamlConstant.IsTargetSpecific = Constant.isMachineConstantPoolEntry();
467 MF.Constants.push_back(YamlConstant);
471 void MIRPrinter::convert(ModuleSlotTracker &MST,
472 yaml::MachineJumpTable &YamlJTI,
473 const MachineJumpTableInfo &JTI) {
474 YamlJTI.Kind = JTI.getEntryKind();
476 for (const auto &Table : JTI.getJumpTables()) {
478 yaml::MachineJumpTable::Entry Entry;
480 for (const auto *MBB : Table.MBBs) {
481 raw_string_ostream StrOS(Str);
482 StrOS << printMBBReference(*MBB);
483 Entry.Blocks.push_back(StrOS.str());
486 YamlJTI.Entries.push_back(Entry);
490 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
491 const auto *TRI = MF.getSubtarget().getRegisterInfo();
493 for (const uint32_t *Mask : TRI->getRegMasks())
494 RegisterMaskIds.insert(std::make_pair(Mask, I++));
497 void llvm::guessSuccessors(const MachineBasicBlock &MBB,
498 SmallVectorImpl<MachineBasicBlock*> &Result,
499 bool &IsFallthrough) {
500 SmallPtrSet<MachineBasicBlock*,8> Seen;
502 for (const MachineInstr &MI : MBB) {
505 for (const MachineOperand &MO : MI.operands()) {
508 MachineBasicBlock *Succ = MO.getMBB();
509 auto RP = Seen.insert(Succ);
511 Result.push_back(Succ);
514 MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
515 IsFallthrough = I == MBB.end() || !I->isBarrier();
519 MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
520 if (MBB.succ_size() <= 1)
522 if (!MBB.hasSuccessorProbabilities())
525 SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(),
527 BranchProbability::normalizeProbabilities(Normalized.begin(),
529 SmallVector<BranchProbability,8> Equal(Normalized.size());
530 BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end());
532 return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
535 bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
536 SmallVector<MachineBasicBlock*,8> GuessedSuccs;
537 bool GuessedFallthrough;
538 guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
539 if (GuessedFallthrough) {
540 const MachineFunction &MF = *MBB.getParent();
541 MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
542 if (NextI != MF.end()) {
543 MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI);
544 if (!is_contained(GuessedSuccs, Next))
545 GuessedSuccs.push_back(Next);
548 if (GuessedSuccs.size() != MBB.succ_size())
550 return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
553 void MIPrinter::print(const MachineBasicBlock &MBB) {
554 assert(MBB.getNumber() >= 0 && "Invalid MBB number");
555 OS << "bb." << MBB.getNumber();
556 bool HasAttributes = false;
557 if (const auto *BB = MBB.getBasicBlock()) {
559 OS << "." << BB->getName();
561 HasAttributes = true;
563 int Slot = MST.getLocalSlot(BB);
565 OS << "<ir-block badref>";
567 OS << (Twine("%ir-block.") + Twine(Slot)).str();
570 if (MBB.hasAddressTaken()) {
571 OS << (HasAttributes ? ", " : " (");
572 OS << "address-taken";
573 HasAttributes = true;
576 OS << (HasAttributes ? ", " : " (");
578 HasAttributes = true;
580 if (MBB.getAlignment()) {
581 OS << (HasAttributes ? ", " : " (");
582 OS << "align " << MBB.getAlignment();
583 HasAttributes = true;
589 bool HasLineAttributes = false;
590 // Print the successors
591 bool canPredictProbs = canPredictBranchProbabilities(MBB);
592 // Even if the list of successors is empty, if we cannot guess it,
593 // we need to print it to tell the parser that the list is empty.
594 // This is needed, because MI model unreachable as empty blocks
595 // with an empty successor list. If the parser would see that
596 // without the successor list, it would guess the code would
598 if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs ||
599 !canPredictSuccessors(MBB)) {
600 OS.indent(2) << "successors: ";
601 for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
602 if (I != MBB.succ_begin())
604 OS << printMBBReference(**I);
605 if (!SimplifyMIR || !canPredictProbs)
607 << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
611 HasLineAttributes = true;
614 // Print the live in registers.
615 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
616 if (MRI.tracksLiveness() && !MBB.livein_empty()) {
617 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
618 OS.indent(2) << "liveins: ";
620 for (const auto &LI : MBB.liveins()) {
624 OS << printReg(LI.PhysReg, &TRI);
625 if (!LI.LaneMask.all())
626 OS << ":0x" << PrintLaneMask(LI.LaneMask);
629 HasLineAttributes = true;
632 if (HasLineAttributes)
634 bool IsInBundle = false;
635 for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
636 const MachineInstr &MI = *I;
637 if (IsInBundle && !MI.isInsideBundle()) {
638 OS.indent(2) << "}\n";
641 OS.indent(IsInBundle ? 4 : 2);
643 if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
650 OS.indent(2) << "}\n";
653 void MIPrinter::print(const MachineInstr &MI) {
654 const auto *MF = MI.getMF();
655 const auto &MRI = MF->getRegInfo();
656 const auto &SubTarget = MF->getSubtarget();
657 const auto *TRI = SubTarget.getRegisterInfo();
658 assert(TRI && "Expected target register info");
659 const auto *TII = SubTarget.getInstrInfo();
660 assert(TII && "Expected target instruction info");
661 if (MI.isCFIInstruction())
662 assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
664 SmallBitVector PrintedTypes(8);
665 bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies();
666 unsigned I = 0, E = MI.getNumOperands();
667 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
668 !MI.getOperand(I).isImplicit();
672 print(MI, I, TRI, ShouldPrintRegisterTies,
673 MI.getTypeToPrint(I, PrintedTypes, MRI),
679 if (MI.getFlag(MachineInstr::FrameSetup))
680 OS << "frame-setup ";
681 if (MI.getFlag(MachineInstr::FrameDestroy))
682 OS << "frame-destroy ";
683 if (MI.getFlag(MachineInstr::FmNoNans))
685 if (MI.getFlag(MachineInstr::FmNoInfs))
687 if (MI.getFlag(MachineInstr::FmNsz))
689 if (MI.getFlag(MachineInstr::FmArcp))
691 if (MI.getFlag(MachineInstr::FmContract))
693 if (MI.getFlag(MachineInstr::FmAfn))
695 if (MI.getFlag(MachineInstr::FmReassoc))
698 OS << TII->getName(MI.getOpcode());
702 bool NeedComma = false;
706 print(MI, I, TRI, ShouldPrintRegisterTies,
707 MI.getTypeToPrint(I, PrintedTypes, MRI));
711 if (const DebugLoc &DL = MI.getDebugLoc()) {
714 OS << " debug-location ";
715 DL->printAsOperand(OS, MST);
718 if (!MI.memoperands_empty()) {
720 const LLVMContext &Context = MF->getFunction().getContext();
721 const MachineFrameInfo &MFI = MF->getFrameInfo();
722 bool NeedComma = false;
723 for (const auto *Op : MI.memoperands()) {
726 Op->print(OS, MST, SSNs, Context, &MFI, TII);
732 void MIPrinter::printStackObjectReference(int FrameIndex) {
733 auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
734 assert(ObjectInfo != StackObjectOperandMapping.end() &&
735 "Invalid frame index");
736 const FrameIndexOperand &Operand = ObjectInfo->second;
737 MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed,
741 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
742 const TargetRegisterInfo *TRI,
743 bool ShouldPrintRegisterTies, LLT TypeToPrint,
745 const MachineOperand &Op = MI.getOperand(OpIdx);
746 switch (Op.getType()) {
747 case MachineOperand::MO_Immediate:
748 if (MI.isOperandSubregIdx(OpIdx)) {
749 MachineOperand::printTargetFlags(OS, Op);
750 MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI);
754 case MachineOperand::MO_Register:
755 case MachineOperand::MO_CImmediate:
756 case MachineOperand::MO_FPImmediate:
757 case MachineOperand::MO_MachineBasicBlock:
758 case MachineOperand::MO_ConstantPoolIndex:
759 case MachineOperand::MO_TargetIndex:
760 case MachineOperand::MO_JumpTableIndex:
761 case MachineOperand::MO_ExternalSymbol:
762 case MachineOperand::MO_GlobalAddress:
763 case MachineOperand::MO_RegisterLiveOut:
764 case MachineOperand::MO_Metadata:
765 case MachineOperand::MO_MCSymbol:
766 case MachineOperand::MO_CFIIndex:
767 case MachineOperand::MO_IntrinsicID:
768 case MachineOperand::MO_Predicate:
769 case MachineOperand::MO_BlockAddress: {
770 unsigned TiedOperandIdx = 0;
771 if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
772 TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
773 const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
774 Op.print(OS, MST, TypeToPrint, PrintDef, /*IsStandalone=*/false,
775 ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII);
778 case MachineOperand::MO_FrameIndex:
779 printStackObjectReference(Op.getIndex());
781 case MachineOperand::MO_RegisterMask: {
782 auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
783 if (RegMaskInfo != RegisterMaskIds.end())
784 OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
786 printCustomRegMask(Op.getRegMask(), OS, TRI);
792 void llvm::printMIR(raw_ostream &OS, const Module &M) {
793 yaml::Output Out(OS);
794 Out << const_cast<Module &>(M);
797 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
798 MIRPrinter Printer(OS);