1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
13 //===----------------------------------------------------------------------===//
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
18 #include "llvm/CodeGen/MIRYamlMapping.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/IR/BasicBlock.h"
26 #include "llvm/IR/Constants.h"
27 #include "llvm/IR/DebugInfo.h"
28 #include "llvm/IR/IRPrintingPasses.h"
29 #include "llvm/IR/Instructions.h"
30 #include "llvm/IR/Module.h"
31 #include "llvm/IR/ModuleSlotTracker.h"
32 #include "llvm/MC/MCSymbol.h"
33 #include "llvm/Support/MemoryBuffer.h"
34 #include "llvm/Support/YAMLTraits.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetSubtargetInfo.h"
43 /// This structure describes how to print out stack object references.
44 struct FrameIndexOperand {
49 FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
50 : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
52 /// Return an ordinary stack object reference.
53 static FrameIndexOperand create(StringRef Name, unsigned ID) {
54 return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
57 /// Return a fixed stack object reference.
58 static FrameIndexOperand createFixed(unsigned ID) {
59 return FrameIndexOperand("", ID, /*IsFixed=*/true);
63 } // end anonymous namespace
67 /// This class prints out the machine functions using the MIR serialization
71 DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
72 /// Maps from stack object indices to operand indices which will be used when
73 /// printing frame index machine operands.
74 DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
77 MIRPrinter(raw_ostream &OS) : OS(OS) {}
79 void print(const MachineFunction &MF);
81 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
82 const TargetRegisterInfo *TRI);
83 void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
84 const MachineFrameInfo &MFI);
85 void convert(yaml::MachineFunction &MF,
86 const MachineConstantPool &ConstantPool);
87 void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
88 const MachineJumpTableInfo &JTI);
89 void convertStackObjects(yaml::MachineFunction &MF,
90 const MachineFrameInfo &MFI, MachineModuleInfo &MMI,
91 ModuleSlotTracker &MST,
92 const TargetRegisterInfo *TRI);
95 void initRegisterMaskIds(const MachineFunction &MF);
98 /// This class prints out the machine instructions using the MIR serialization
102 ModuleSlotTracker &MST;
103 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
104 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
107 MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
108 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
109 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
110 : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
111 StackObjectOperandMapping(StackObjectOperandMapping) {}
113 void print(const MachineBasicBlock &MBB);
115 void print(const MachineInstr &MI);
116 void printMBBReference(const MachineBasicBlock &MBB);
117 void printIRBlockReference(const BasicBlock &BB);
118 void printIRValueReference(const Value &V);
119 void printStackObjectReference(int FrameIndex);
120 void printOffset(int64_t Offset);
121 void printTargetFlags(const MachineOperand &Op);
122 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
123 unsigned I, bool ShouldPrintRegisterTies,
124 const MachineRegisterInfo *MRI = nullptr, bool IsDef = false);
125 void print(const MachineMemOperand &Op);
127 void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
130 } // end namespace llvm
135 /// This struct serializes the LLVM IR module.
136 template <> struct BlockScalarTraits<Module> {
137 static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
138 Mod.print(OS, nullptr);
140 static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
141 llvm_unreachable("LLVM Module is supposed to be parsed separately");
146 } // end namespace yaml
147 } // end namespace llvm
149 static void printReg(unsigned Reg, raw_ostream &OS,
150 const TargetRegisterInfo *TRI) {
151 // TODO: Print Stack Slots.
154 else if (TargetRegisterInfo::isVirtualRegister(Reg))
155 OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
156 else if (Reg < TRI->getNumRegs())
157 OS << '%' << StringRef(TRI->getName(Reg)).lower();
159 llvm_unreachable("Can't print this kind of register yet");
162 static void printReg(unsigned Reg, yaml::StringValue &Dest,
163 const TargetRegisterInfo *TRI) {
164 raw_string_ostream OS(Dest.Value);
165 printReg(Reg, OS, TRI);
168 void MIRPrinter::print(const MachineFunction &MF) {
169 initRegisterMaskIds(MF);
171 yaml::MachineFunction YamlMF;
172 YamlMF.Name = MF.getName();
173 YamlMF.Alignment = MF.getAlignment();
174 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
175 YamlMF.HasInlineAsm = MF.hasInlineAsm();
176 YamlMF.AllVRegsAllocated = MF.getProperties().hasProperty(
177 MachineFunctionProperties::Property::AllVRegsAllocated);
179 convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
180 ModuleSlotTracker MST(MF.getFunction()->getParent());
181 MST.incorporateFunction(*MF.getFunction());
182 convert(MST, YamlMF.FrameInfo, *MF.getFrameInfo());
183 convertStackObjects(YamlMF, *MF.getFrameInfo(), MF.getMMI(), MST,
184 MF.getSubtarget().getRegisterInfo());
185 if (const auto *ConstantPool = MF.getConstantPool())
186 convert(YamlMF, *ConstantPool);
187 if (const auto *JumpTableInfo = MF.getJumpTableInfo())
188 convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
189 raw_string_ostream StrOS(YamlMF.Body.Value.Value);
190 bool IsNewlineNeeded = false;
191 for (const auto &MBB : MF) {
194 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
196 IsNewlineNeeded = true;
199 yaml::Output Out(OS);
203 void MIRPrinter::convert(yaml::MachineFunction &MF,
204 const MachineRegisterInfo &RegInfo,
205 const TargetRegisterInfo *TRI) {
206 MF.IsSSA = RegInfo.isSSA();
207 MF.TracksRegLiveness = RegInfo.tracksLiveness();
208 MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
210 // Print the virtual register definitions.
211 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
212 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
213 yaml::VirtualRegisterDefinition VReg;
215 if (RegInfo.getRegClassOrNull(Reg))
217 StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
218 else if (RegInfo.getRegBankOrNull(Reg))
219 VReg.Class = StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
221 VReg.Class = std::string("_");
222 assert(RegInfo.getSize(Reg) && "Generic registers must have a size");
224 unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
226 printReg(PreferredReg, VReg.PreferredRegister, TRI);
227 MF.VirtualRegisters.push_back(VReg);
230 // Print the live ins.
231 for (auto I = RegInfo.livein_begin(), E = RegInfo.livein_end(); I != E; ++I) {
232 yaml::MachineFunctionLiveIn LiveIn;
233 printReg(I->first, LiveIn.Register, TRI);
235 printReg(I->second, LiveIn.VirtualRegister, TRI);
236 MF.LiveIns.push_back(LiveIn);
238 // The used physical register mask is printed as an inverted callee saved
240 const BitVector &UsedPhysRegMask = RegInfo.getUsedPhysRegsMask();
241 if (UsedPhysRegMask.none())
243 std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
244 for (unsigned I = 0, E = UsedPhysRegMask.size(); I != E; ++I) {
245 if (!UsedPhysRegMask[I]) {
246 yaml::FlowStringValue Reg;
247 printReg(I, Reg, TRI);
248 CalleeSavedRegisters.push_back(Reg);
251 MF.CalleeSavedRegisters = CalleeSavedRegisters;
254 void MIRPrinter::convert(ModuleSlotTracker &MST,
255 yaml::MachineFrameInfo &YamlMFI,
256 const MachineFrameInfo &MFI) {
257 YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
258 YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
259 YamlMFI.HasStackMap = MFI.hasStackMap();
260 YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
261 YamlMFI.StackSize = MFI.getStackSize();
262 YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
263 YamlMFI.MaxAlignment = MFI.getMaxAlignment();
264 YamlMFI.AdjustsStack = MFI.adjustsStack();
265 YamlMFI.HasCalls = MFI.hasCalls();
266 YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize();
267 YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
268 YamlMFI.HasVAStart = MFI.hasVAStart();
269 YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
270 if (MFI.getSavePoint()) {
271 raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
272 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
273 .printMBBReference(*MFI.getSavePoint());
275 if (MFI.getRestorePoint()) {
276 raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
277 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
278 .printMBBReference(*MFI.getRestorePoint());
282 void MIRPrinter::convertStackObjects(yaml::MachineFunction &MF,
283 const MachineFrameInfo &MFI,
284 MachineModuleInfo &MMI,
285 ModuleSlotTracker &MST,
286 const TargetRegisterInfo *TRI) {
287 // Process fixed stack objects.
289 for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
290 if (MFI.isDeadObjectIndex(I))
293 yaml::FixedMachineStackObject YamlObject;
295 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
296 ? yaml::FixedMachineStackObject::SpillSlot
297 : yaml::FixedMachineStackObject::DefaultType;
298 YamlObject.Offset = MFI.getObjectOffset(I);
299 YamlObject.Size = MFI.getObjectSize(I);
300 YamlObject.Alignment = MFI.getObjectAlignment(I);
301 YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
302 YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
303 MF.FixedStackObjects.push_back(YamlObject);
304 StackObjectOperandMapping.insert(
305 std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
308 // Process ordinary stack objects.
310 for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
311 if (MFI.isDeadObjectIndex(I))
314 yaml::MachineStackObject YamlObject;
316 if (const auto *Alloca = MFI.getObjectAllocation(I))
317 YamlObject.Name.Value =
318 Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
319 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
320 ? yaml::MachineStackObject::SpillSlot
321 : MFI.isVariableSizedObjectIndex(I)
322 ? yaml::MachineStackObject::VariableSized
323 : yaml::MachineStackObject::DefaultType;
324 YamlObject.Offset = MFI.getObjectOffset(I);
325 YamlObject.Size = MFI.getObjectSize(I);
326 YamlObject.Alignment = MFI.getObjectAlignment(I);
328 MF.StackObjects.push_back(YamlObject);
329 StackObjectOperandMapping.insert(std::make_pair(
330 I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
333 for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
334 yaml::StringValue Reg;
335 printReg(CSInfo.getReg(), Reg, TRI);
336 auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
337 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
338 "Invalid stack object index");
339 const FrameIndexOperand &StackObject = StackObjectInfo->second;
340 if (StackObject.IsFixed)
341 MF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
343 MF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
345 for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
346 auto LocalObject = MFI.getLocalFrameObjectMap(I);
347 auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
348 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
349 "Invalid stack object index");
350 const FrameIndexOperand &StackObject = StackObjectInfo->second;
351 assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
352 MF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
355 // Print the stack object references in the frame information class after
356 // converting the stack objects.
357 if (MFI.hasStackProtectorIndex()) {
358 raw_string_ostream StrOS(MF.FrameInfo.StackProtector.Value);
359 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
360 .printStackObjectReference(MFI.getStackProtectorIndex());
363 // Print the debug variable information.
364 for (MachineModuleInfo::VariableDbgInfo &DebugVar :
365 MMI.getVariableDbgInfo()) {
366 auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
367 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
368 "Invalid stack object index");
369 const FrameIndexOperand &StackObject = StackObjectInfo->second;
370 assert(!StackObject.IsFixed && "Expected a non-fixed stack object");
371 auto &Object = MF.StackObjects[StackObject.ID];
373 raw_string_ostream StrOS(Object.DebugVar.Value);
374 DebugVar.Var->printAsOperand(StrOS, MST);
377 raw_string_ostream StrOS(Object.DebugExpr.Value);
378 DebugVar.Expr->printAsOperand(StrOS, MST);
381 raw_string_ostream StrOS(Object.DebugLoc.Value);
382 DebugVar.Loc->printAsOperand(StrOS, MST);
387 void MIRPrinter::convert(yaml::MachineFunction &MF,
388 const MachineConstantPool &ConstantPool) {
390 for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
391 // TODO: Serialize target specific constant pool entries.
392 if (Constant.isMachineConstantPoolEntry())
393 llvm_unreachable("Can't print target specific constant pool entries yet");
395 yaml::MachineConstantPoolValue YamlConstant;
397 raw_string_ostream StrOS(Str);
398 Constant.Val.ConstVal->printAsOperand(StrOS);
399 YamlConstant.ID = ID++;
400 YamlConstant.Value = StrOS.str();
401 YamlConstant.Alignment = Constant.getAlignment();
402 MF.Constants.push_back(YamlConstant);
406 void MIRPrinter::convert(ModuleSlotTracker &MST,
407 yaml::MachineJumpTable &YamlJTI,
408 const MachineJumpTableInfo &JTI) {
409 YamlJTI.Kind = JTI.getEntryKind();
411 for (const auto &Table : JTI.getJumpTables()) {
413 yaml::MachineJumpTable::Entry Entry;
415 for (const auto *MBB : Table.MBBs) {
416 raw_string_ostream StrOS(Str);
417 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
418 .printMBBReference(*MBB);
419 Entry.Blocks.push_back(StrOS.str());
422 YamlJTI.Entries.push_back(Entry);
426 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
427 const auto *TRI = MF.getSubtarget().getRegisterInfo();
429 for (const uint32_t *Mask : TRI->getRegMasks())
430 RegisterMaskIds.insert(std::make_pair(Mask, I++));
433 void MIPrinter::print(const MachineBasicBlock &MBB) {
434 assert(MBB.getNumber() >= 0 && "Invalid MBB number");
435 OS << "bb." << MBB.getNumber();
436 bool HasAttributes = false;
437 if (const auto *BB = MBB.getBasicBlock()) {
439 OS << "." << BB->getName();
441 HasAttributes = true;
443 int Slot = MST.getLocalSlot(BB);
445 OS << "<ir-block badref>";
447 OS << (Twine("%ir-block.") + Twine(Slot)).str();
450 if (MBB.hasAddressTaken()) {
451 OS << (HasAttributes ? ", " : " (");
452 OS << "address-taken";
453 HasAttributes = true;
456 OS << (HasAttributes ? ", " : " (");
458 HasAttributes = true;
460 if (MBB.getAlignment()) {
461 OS << (HasAttributes ? ", " : " (");
462 OS << "align " << MBB.getAlignment();
463 HasAttributes = true;
469 bool HasLineAttributes = false;
470 // Print the successors
471 if (!MBB.succ_empty()) {
472 OS.indent(2) << "successors: ";
473 for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
474 if (I != MBB.succ_begin())
476 printMBBReference(**I);
477 if (MBB.hasSuccessorProbabilities())
478 OS << '(' << MBB.getSuccProbability(I) << ')';
481 HasLineAttributes = true;
484 // Print the live in registers.
485 const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo();
486 assert(TRI && "Expected target register info");
487 if (!MBB.livein_empty()) {
488 OS.indent(2) << "liveins: ";
490 for (const auto &LI : MBB.liveins()) {
494 printReg(LI.PhysReg, OS, TRI);
495 if (LI.LaneMask != ~0u)
496 OS << ':' << PrintLaneMask(LI.LaneMask);
499 HasLineAttributes = true;
502 if (HasLineAttributes)
504 bool IsInBundle = false;
505 for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
506 const MachineInstr &MI = *I;
507 if (IsInBundle && !MI.isInsideBundle()) {
508 OS.indent(2) << "}\n";
511 OS.indent(IsInBundle ? 4 : 2);
513 if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
520 OS.indent(2) << "}\n";
523 /// Return true when an instruction has tied register that can't be determined
524 /// by the instruction's descriptor.
525 static bool hasComplexRegisterTies(const MachineInstr &MI) {
526 const MCInstrDesc &MCID = MI.getDesc();
527 for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I) {
528 const auto &Operand = MI.getOperand(I);
529 if (!Operand.isReg() || Operand.isDef())
530 // Ignore the defined registers as MCID marks only the uses as tied.
532 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
533 int TiedIdx = Operand.isTied() ? int(MI.findTiedOperandIdx(I)) : -1;
534 if (ExpectedTiedIdx != TiedIdx)
540 void MIPrinter::print(const MachineInstr &MI) {
541 const auto *MF = MI.getParent()->getParent();
542 const auto &MRI = MF->getRegInfo();
543 const auto &SubTarget = MF->getSubtarget();
544 const auto *TRI = SubTarget.getRegisterInfo();
545 assert(TRI && "Expected target register info");
546 const auto *TII = SubTarget.getInstrInfo();
547 assert(TII && "Expected target instruction info");
548 if (MI.isCFIInstruction())
549 assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
551 bool ShouldPrintRegisterTies = hasComplexRegisterTies(MI);
552 unsigned I = 0, E = MI.getNumOperands();
553 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
554 !MI.getOperand(I).isImplicit();
558 print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies, &MRI,
564 if (MI.getFlag(MachineInstr::FrameSetup))
565 OS << "frame-setup ";
566 OS << TII->getName(MI.getOpcode());
567 if (isPreISelGenericOpcode(MI.getOpcode())) {
568 assert(MI.getType() && "Generic instructions must have a type");
570 MI.getType()->print(OS, /*IsForDebug*/ false, /*NoDetails*/ true);
575 bool NeedComma = false;
579 print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies);
583 if (MI.getDebugLoc()) {
586 OS << " debug-location ";
587 MI.getDebugLoc()->printAsOperand(OS, MST);
590 if (!MI.memoperands_empty()) {
592 bool NeedComma = false;
593 for (const auto *Op : MI.memoperands()) {
602 void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
603 OS << "%bb." << MBB.getNumber();
604 if (const auto *BB = MBB.getBasicBlock()) {
606 OS << '.' << BB->getName();
610 static void printIRSlotNumber(raw_ostream &OS, int Slot) {
617 void MIPrinter::printIRBlockReference(const BasicBlock &BB) {
620 printLLVMNameWithoutPrefix(OS, BB.getName());
623 const Function *F = BB.getParent();
625 if (F == MST.getCurrentFunction()) {
626 Slot = MST.getLocalSlot(&BB);
628 ModuleSlotTracker CustomMST(F->getParent(),
629 /*ShouldInitializeAllMetadata=*/false);
630 CustomMST.incorporateFunction(*F);
631 Slot = CustomMST.getLocalSlot(&BB);
633 printIRSlotNumber(OS, Slot);
636 void MIPrinter::printIRValueReference(const Value &V) {
637 if (isa<GlobalValue>(V)) {
638 V.printAsOperand(OS, /*PrintType=*/false, MST);
641 if (isa<Constant>(V)) {
642 // Machine memory operands can load/store to/from constant value pointers.
644 V.printAsOperand(OS, /*PrintType=*/true, MST);
650 printLLVMNameWithoutPrefix(OS, V.getName());
653 printIRSlotNumber(OS, MST.getLocalSlot(&V));
656 void MIPrinter::printStackObjectReference(int FrameIndex) {
657 auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
658 assert(ObjectInfo != StackObjectOperandMapping.end() &&
659 "Invalid frame index");
660 const FrameIndexOperand &Operand = ObjectInfo->second;
661 if (Operand.IsFixed) {
662 OS << "%fixed-stack." << Operand.ID;
665 OS << "%stack." << Operand.ID;
666 if (!Operand.Name.empty())
667 OS << '.' << Operand.Name;
670 void MIPrinter::printOffset(int64_t Offset) {
674 OS << " - " << -Offset;
677 OS << " + " << Offset;
680 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
681 auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
682 for (const auto &I : Flags) {
690 void MIPrinter::printTargetFlags(const MachineOperand &Op) {
691 if (!Op.getTargetFlags())
694 Op.getParent()->getParent()->getParent()->getSubtarget().getInstrInfo();
695 assert(TII && "expected instruction info");
696 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
697 OS << "target-flags(";
698 const bool HasDirectFlags = Flags.first;
699 const bool HasBitmaskFlags = Flags.second;
700 if (!HasDirectFlags && !HasBitmaskFlags) {
704 if (HasDirectFlags) {
705 if (const auto *Name = getTargetFlagName(TII, Flags.first))
708 OS << "<unknown target flag>";
710 if (!HasBitmaskFlags) {
714 bool IsCommaNeeded = HasDirectFlags;
715 unsigned BitMask = Flags.second;
716 auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
717 for (const auto &Mask : BitMasks) {
718 // Check if the flag's bitmask has the bits of the current mask set.
719 if ((BitMask & Mask.first) == Mask.first) {
722 IsCommaNeeded = true;
724 // Clear the bits which were serialized from the flag's bitmask.
725 BitMask &= ~(Mask.first);
729 // When the resulting flag's bitmask isn't zero, we know that we didn't
730 // serialize all of the bit flags.
733 OS << "<unknown bitmask target flag>";
738 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
739 const auto *TII = MF.getSubtarget().getInstrInfo();
740 assert(TII && "expected instruction info");
741 auto Indices = TII->getSerializableTargetIndices();
742 for (const auto &I : Indices) {
743 if (I.first == Index) {
750 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
751 unsigned I, bool ShouldPrintRegisterTies,
752 const MachineRegisterInfo *MRI, bool IsDef) {
753 printTargetFlags(Op);
754 switch (Op.getType()) {
755 case MachineOperand::MO_Register:
757 OS << (Op.isDef() ? "implicit-def " : "implicit ");
758 else if (!IsDef && Op.isDef())
759 // Print the 'def' flag only when the operand is defined after '='.
761 if (Op.isInternalRead())
769 if (Op.isEarlyClobber())
770 OS << "early-clobber ";
773 printReg(Op.getReg(), OS, TRI);
774 // Print the sub register.
775 if (Op.getSubReg() != 0)
776 OS << ':' << TRI->getSubRegIndexName(Op.getSubReg());
777 if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef())
778 OS << "(tied-def " << Op.getParent()->findTiedOperandIdx(I) << ")";
779 assert((!IsDef || MRI) && "for IsDef, MRI must be provided");
780 if (IsDef && MRI->getSize(Op.getReg()))
781 OS << '(' << MRI->getSize(Op.getReg()) << ')';
783 case MachineOperand::MO_Immediate:
786 case MachineOperand::MO_CImmediate:
787 Op.getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
789 case MachineOperand::MO_FPImmediate:
790 Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
792 case MachineOperand::MO_MachineBasicBlock:
793 printMBBReference(*Op.getMBB());
795 case MachineOperand::MO_FrameIndex:
796 printStackObjectReference(Op.getIndex());
798 case MachineOperand::MO_ConstantPoolIndex:
799 OS << "%const." << Op.getIndex();
800 printOffset(Op.getOffset());
802 case MachineOperand::MO_TargetIndex: {
803 OS << "target-index(";
804 if (const auto *Name = getTargetIndexName(
805 *Op.getParent()->getParent()->getParent(), Op.getIndex()))
810 printOffset(Op.getOffset());
813 case MachineOperand::MO_JumpTableIndex:
814 OS << "%jump-table." << Op.getIndex();
816 case MachineOperand::MO_ExternalSymbol:
818 printLLVMNameWithoutPrefix(OS, Op.getSymbolName());
819 printOffset(Op.getOffset());
821 case MachineOperand::MO_GlobalAddress:
822 Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
823 printOffset(Op.getOffset());
825 case MachineOperand::MO_BlockAddress:
826 OS << "blockaddress(";
827 Op.getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
830 printIRBlockReference(*Op.getBlockAddress()->getBasicBlock());
832 printOffset(Op.getOffset());
834 case MachineOperand::MO_RegisterMask: {
835 auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
836 if (RegMaskInfo != RegisterMaskIds.end())
837 OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
839 llvm_unreachable("Can't print this machine register mask yet.");
842 case MachineOperand::MO_RegisterLiveOut: {
843 const uint32_t *RegMask = Op.getRegLiveOut();
845 bool IsCommaNeeded = false;
846 for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
847 if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
850 printReg(Reg, OS, TRI);
851 IsCommaNeeded = true;
857 case MachineOperand::MO_Metadata:
858 Op.getMetadata()->printAsOperand(OS, MST);
860 case MachineOperand::MO_MCSymbol:
861 OS << "<mcsymbol " << *Op.getMCSymbol() << ">";
863 case MachineOperand::MO_CFIIndex: {
864 const auto &MMI = Op.getParent()->getParent()->getParent()->getMMI();
865 print(MMI.getFrameInstructions()[Op.getCFIIndex()], TRI);
871 void MIPrinter::print(const MachineMemOperand &Op) {
873 // TODO: Print operand's target specific flags.
876 if (Op.isNonTemporal())
877 OS << "non-temporal ";
878 if (Op.isInvariant())
883 assert(Op.isStore() && "Non load machine operand must be a store");
887 if (const Value *Val = Op.getValue()) {
888 OS << (Op.isLoad() ? " from " : " into ");
889 printIRValueReference(*Val);
890 } else if (const PseudoSourceValue *PVal = Op.getPseudoValue()) {
891 OS << (Op.isLoad() ? " from " : " into ");
892 assert(PVal && "Expected a pseudo source value");
893 switch (PVal->kind()) {
894 case PseudoSourceValue::Stack:
897 case PseudoSourceValue::GOT:
900 case PseudoSourceValue::JumpTable:
903 case PseudoSourceValue::ConstantPool:
904 OS << "constant-pool";
906 case PseudoSourceValue::FixedStack:
907 printStackObjectReference(
908 cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex());
910 case PseudoSourceValue::GlobalValueCallEntry:
912 cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
913 OS, /*PrintType=*/false, MST);
915 case PseudoSourceValue::ExternalSymbolCallEntry:
916 OS << "call-entry $";
917 printLLVMNameWithoutPrefix(
918 OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
922 printOffset(Op.getOffset());
923 if (Op.getBaseAlignment() != Op.getSize())
924 OS << ", align " << Op.getBaseAlignment();
925 auto AAInfo = Op.getAAInfo();
928 AAInfo.TBAA->printAsOperand(OS, MST);
931 OS << ", !alias.scope ";
932 AAInfo.Scope->printAsOperand(OS, MST);
934 if (AAInfo.NoAlias) {
936 AAInfo.NoAlias->printAsOperand(OS, MST);
938 if (Op.getRanges()) {
940 Op.getRanges()->printAsOperand(OS, MST);
945 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
946 const TargetRegisterInfo *TRI) {
947 int Reg = TRI->getLLVMRegNum(DwarfReg, true);
952 printReg(Reg, OS, TRI);
955 void MIPrinter::print(const MCCFIInstruction &CFI,
956 const TargetRegisterInfo *TRI) {
957 switch (CFI.getOperation()) {
958 case MCCFIInstruction::OpSameValue:
959 OS << ".cfi_same_value ";
962 printCFIRegister(CFI.getRegister(), OS, TRI);
964 case MCCFIInstruction::OpOffset:
965 OS << ".cfi_offset ";
968 printCFIRegister(CFI.getRegister(), OS, TRI);
969 OS << ", " << CFI.getOffset();
971 case MCCFIInstruction::OpDefCfaRegister:
972 OS << ".cfi_def_cfa_register ";
975 printCFIRegister(CFI.getRegister(), OS, TRI);
977 case MCCFIInstruction::OpDefCfaOffset:
978 OS << ".cfi_def_cfa_offset ";
981 OS << CFI.getOffset();
983 case MCCFIInstruction::OpDefCfa:
984 OS << ".cfi_def_cfa ";
987 printCFIRegister(CFI.getRegister(), OS, TRI);
988 OS << ", " << CFI.getOffset();
991 // TODO: Print the other CFI Operations.
992 OS << "<unserializable cfi operation>";
997 void llvm::printMIR(raw_ostream &OS, const Module &M) {
998 yaml::Output Out(OS);
999 Out << const_cast<Module &>(M);
1002 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
1003 MIRPrinter Printer(OS);