1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/ADT/DenseMap.h"
16 #include "llvm/ADT/None.h"
17 #include "llvm/ADT/SmallBitVector.h"
18 #include "llvm/ADT/SmallPtrSet.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringRef.h"
22 #include "llvm/ADT/Twine.h"
23 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
24 #include "llvm/CodeGen/MachineBasicBlock.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstr.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineOperand.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/MIRPrinter.h"
34 #include "llvm/CodeGen/MIRYamlMapping.h"
35 #include "llvm/CodeGen/PseudoSourceValue.h"
36 #include "llvm/IR/BasicBlock.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DebugInfo.h"
39 #include "llvm/IR/DebugLoc.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalValue.h"
42 #include "llvm/IR/InstrTypes.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/IR/IRPrintingPasses.h"
46 #include "llvm/IR/Module.h"
47 #include "llvm/IR/ModuleSlotTracker.h"
48 #include "llvm/IR/Value.h"
49 #include "llvm/MC/LaneBitmask.h"
50 #include "llvm/MC/MCDwarf.h"
51 #include "llvm/MC/MCSymbol.h"
52 #include "llvm/Support/AtomicOrdering.h"
53 #include "llvm/Support/BranchProbability.h"
54 #include "llvm/Support/Casting.h"
55 #include "llvm/Support/CommandLine.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/Format.h"
58 #include "llvm/Support/LowLevelTypeImpl.h"
59 #include "llvm/Support/raw_ostream.h"
60 #include "llvm/Support/YAMLTraits.h"
61 #include "llvm/Target/TargetInstrInfo.h"
62 #include "llvm/Target/TargetIntrinsicInfo.h"
63 #include "llvm/Target/TargetMachine.h"
64 #include "llvm/Target/TargetRegisterInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
77 static cl::opt<bool> SimplifyMIR("simplify-mir",
78 cl::desc("Leave out unnecessary information when printing MIR"));
82 /// This structure describes how to print out stack object references.
83 struct FrameIndexOperand {
88 FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
89 : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
91 /// Return an ordinary stack object reference.
92 static FrameIndexOperand create(StringRef Name, unsigned ID) {
93 return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
96 /// Return a fixed stack object reference.
97 static FrameIndexOperand createFixed(unsigned ID) {
98 return FrameIndexOperand("", ID, /*IsFixed=*/true);
102 } // end anonymous namespace
106 /// This class prints out the machine functions using the MIR serialization
110 DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
111 /// Maps from stack object indices to operand indices which will be used when
112 /// printing frame index machine operands.
113 DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
116 MIRPrinter(raw_ostream &OS) : OS(OS) {}
118 void print(const MachineFunction &MF);
120 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
121 const TargetRegisterInfo *TRI);
122 void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
123 const MachineFrameInfo &MFI);
124 void convert(yaml::MachineFunction &MF,
125 const MachineConstantPool &ConstantPool);
126 void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
127 const MachineJumpTableInfo &JTI);
128 void convertStackObjects(yaml::MachineFunction &YMF,
129 const MachineFunction &MF, ModuleSlotTracker &MST);
132 void initRegisterMaskIds(const MachineFunction &MF);
135 /// This class prints out the machine instructions using the MIR serialization
139 ModuleSlotTracker &MST;
140 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
141 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
143 bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
144 bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
147 MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
148 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
149 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
150 : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
151 StackObjectOperandMapping(StackObjectOperandMapping) {}
153 void print(const MachineBasicBlock &MBB);
155 void print(const MachineInstr &MI);
156 void printMBBReference(const MachineBasicBlock &MBB);
157 void printIRBlockReference(const BasicBlock &BB);
158 void printIRValueReference(const Value &V);
159 void printStackObjectReference(int FrameIndex);
160 void printOffset(int64_t Offset);
161 void printTargetFlags(const MachineOperand &Op);
162 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
163 unsigned I, bool ShouldPrintRegisterTies,
164 LLT TypeToPrint, bool IsDef = false);
165 void print(const MachineMemOperand &Op);
167 void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
170 } // end namespace llvm
175 /// This struct serializes the LLVM IR module.
176 template <> struct BlockScalarTraits<Module> {
177 static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
178 Mod.print(OS, nullptr);
181 static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
182 llvm_unreachable("LLVM Module is supposed to be parsed separately");
187 } // end namespace yaml
188 } // end namespace llvm
190 static void printReg(unsigned Reg, raw_ostream &OS,
191 const TargetRegisterInfo *TRI) {
192 // TODO: Print Stack Slots.
195 else if (TargetRegisterInfo::isVirtualRegister(Reg))
196 OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
197 else if (Reg < TRI->getNumRegs())
198 OS << '%' << StringRef(TRI->getName(Reg)).lower();
200 llvm_unreachable("Can't print this kind of register yet");
203 static void printReg(unsigned Reg, yaml::StringValue &Dest,
204 const TargetRegisterInfo *TRI) {
205 raw_string_ostream OS(Dest.Value);
206 printReg(Reg, OS, TRI);
209 void MIRPrinter::print(const MachineFunction &MF) {
210 initRegisterMaskIds(MF);
212 yaml::MachineFunction YamlMF;
213 YamlMF.Name = MF.getName();
214 YamlMF.Alignment = MF.getAlignment();
215 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
217 YamlMF.Legalized = MF.getProperties().hasProperty(
218 MachineFunctionProperties::Property::Legalized);
219 YamlMF.RegBankSelected = MF.getProperties().hasProperty(
220 MachineFunctionProperties::Property::RegBankSelected);
221 YamlMF.Selected = MF.getProperties().hasProperty(
222 MachineFunctionProperties::Property::Selected);
224 convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
225 ModuleSlotTracker MST(MF.getFunction()->getParent());
226 MST.incorporateFunction(*MF.getFunction());
227 convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
228 convertStackObjects(YamlMF, MF, MST);
229 if (const auto *ConstantPool = MF.getConstantPool())
230 convert(YamlMF, *ConstantPool);
231 if (const auto *JumpTableInfo = MF.getJumpTableInfo())
232 convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
233 raw_string_ostream StrOS(YamlMF.Body.Value.Value);
234 bool IsNewlineNeeded = false;
235 for (const auto &MBB : MF) {
238 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
240 IsNewlineNeeded = true;
243 yaml::Output Out(OS);
245 Out.setWriteDefaultValues(true);
249 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
250 const TargetRegisterInfo *TRI) {
251 assert(RegMask && "Can't print an empty register mask");
252 OS << StringRef("CustomRegMask(");
254 bool IsRegInRegMaskFound = false;
255 for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
256 // Check whether the register is asserted in regmask.
257 if (RegMask[I / 32] & (1u << (I % 32))) {
258 if (IsRegInRegMaskFound)
260 printReg(I, OS, TRI);
261 IsRegInRegMaskFound = true;
268 void MIRPrinter::convert(yaml::MachineFunction &MF,
269 const MachineRegisterInfo &RegInfo,
270 const TargetRegisterInfo *TRI) {
271 MF.TracksRegLiveness = RegInfo.tracksLiveness();
273 // Print the virtual register definitions.
274 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
275 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
276 yaml::VirtualRegisterDefinition VReg;
278 if (RegInfo.getRegClassOrNull(Reg))
280 StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
281 else if (RegInfo.getRegBankOrNull(Reg))
282 VReg.Class = StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
284 VReg.Class = std::string("_");
285 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
286 "Generic registers must have a valid type");
288 unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
290 printReg(PreferredReg, VReg.PreferredRegister, TRI);
291 MF.VirtualRegisters.push_back(VReg);
294 // Print the live ins.
295 for (auto I = RegInfo.livein_begin(), E = RegInfo.livein_end(); I != E; ++I) {
296 yaml::MachineFunctionLiveIn LiveIn;
297 printReg(I->first, LiveIn.Register, TRI);
299 printReg(I->second, LiveIn.VirtualRegister, TRI);
300 MF.LiveIns.push_back(LiveIn);
303 // Prints the callee saved registers.
304 if (RegInfo.isUpdatedCSRsInitialized()) {
305 const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
306 std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
307 for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
308 yaml::FlowStringValue Reg;
309 printReg(*I, Reg, TRI);
310 CalleeSavedRegisters.push_back(Reg);
312 MF.CalleeSavedRegisters = CalleeSavedRegisters;
316 void MIRPrinter::convert(ModuleSlotTracker &MST,
317 yaml::MachineFrameInfo &YamlMFI,
318 const MachineFrameInfo &MFI) {
319 YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
320 YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
321 YamlMFI.HasStackMap = MFI.hasStackMap();
322 YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
323 YamlMFI.StackSize = MFI.getStackSize();
324 YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
325 YamlMFI.MaxAlignment = MFI.getMaxAlignment();
326 YamlMFI.AdjustsStack = MFI.adjustsStack();
327 YamlMFI.HasCalls = MFI.hasCalls();
328 YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
329 ? MFI.getMaxCallFrameSize() : ~0u;
330 YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
331 YamlMFI.HasVAStart = MFI.hasVAStart();
332 YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
333 if (MFI.getSavePoint()) {
334 raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
335 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
336 .printMBBReference(*MFI.getSavePoint());
338 if (MFI.getRestorePoint()) {
339 raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
340 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
341 .printMBBReference(*MFI.getRestorePoint());
345 void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
346 const MachineFunction &MF,
347 ModuleSlotTracker &MST) {
348 const MachineFrameInfo &MFI = MF.getFrameInfo();
349 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
350 // Process fixed stack objects.
352 for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
353 if (MFI.isDeadObjectIndex(I))
356 yaml::FixedMachineStackObject YamlObject;
358 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
359 ? yaml::FixedMachineStackObject::SpillSlot
360 : yaml::FixedMachineStackObject::DefaultType;
361 YamlObject.Offset = MFI.getObjectOffset(I);
362 YamlObject.Size = MFI.getObjectSize(I);
363 YamlObject.Alignment = MFI.getObjectAlignment(I);
364 YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
365 YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
366 YMF.FixedStackObjects.push_back(YamlObject);
367 StackObjectOperandMapping.insert(
368 std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
371 // Process ordinary stack objects.
373 for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
374 if (MFI.isDeadObjectIndex(I))
377 yaml::MachineStackObject YamlObject;
379 if (const auto *Alloca = MFI.getObjectAllocation(I))
380 YamlObject.Name.Value =
381 Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
382 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
383 ? yaml::MachineStackObject::SpillSlot
384 : MFI.isVariableSizedObjectIndex(I)
385 ? yaml::MachineStackObject::VariableSized
386 : yaml::MachineStackObject::DefaultType;
387 YamlObject.Offset = MFI.getObjectOffset(I);
388 YamlObject.Size = MFI.getObjectSize(I);
389 YamlObject.Alignment = MFI.getObjectAlignment(I);
391 YMF.StackObjects.push_back(YamlObject);
392 StackObjectOperandMapping.insert(std::make_pair(
393 I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
396 for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
397 yaml::StringValue Reg;
398 printReg(CSInfo.getReg(), Reg, TRI);
399 auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
400 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
401 "Invalid stack object index");
402 const FrameIndexOperand &StackObject = StackObjectInfo->second;
403 if (StackObject.IsFixed)
404 YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
406 YMF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
408 for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
409 auto LocalObject = MFI.getLocalFrameObjectMap(I);
410 auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
411 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
412 "Invalid stack object index");
413 const FrameIndexOperand &StackObject = StackObjectInfo->second;
414 assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
415 YMF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
418 // Print the stack object references in the frame information class after
419 // converting the stack objects.
420 if (MFI.hasStackProtectorIndex()) {
421 raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
422 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
423 .printStackObjectReference(MFI.getStackProtectorIndex());
426 // Print the debug variable information.
427 for (const MachineFunction::VariableDbgInfo &DebugVar :
428 MF.getVariableDbgInfo()) {
429 auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
430 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
431 "Invalid stack object index");
432 const FrameIndexOperand &StackObject = StackObjectInfo->second;
433 assert(!StackObject.IsFixed && "Expected a non-fixed stack object");
434 auto &Object = YMF.StackObjects[StackObject.ID];
436 raw_string_ostream StrOS(Object.DebugVar.Value);
437 DebugVar.Var->printAsOperand(StrOS, MST);
440 raw_string_ostream StrOS(Object.DebugExpr.Value);
441 DebugVar.Expr->printAsOperand(StrOS, MST);
444 raw_string_ostream StrOS(Object.DebugLoc.Value);
445 DebugVar.Loc->printAsOperand(StrOS, MST);
450 void MIRPrinter::convert(yaml::MachineFunction &MF,
451 const MachineConstantPool &ConstantPool) {
453 for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
454 // TODO: Serialize target specific constant pool entries.
455 if (Constant.isMachineConstantPoolEntry())
456 llvm_unreachable("Can't print target specific constant pool entries yet");
458 yaml::MachineConstantPoolValue YamlConstant;
460 raw_string_ostream StrOS(Str);
461 Constant.Val.ConstVal->printAsOperand(StrOS);
462 YamlConstant.ID = ID++;
463 YamlConstant.Value = StrOS.str();
464 YamlConstant.Alignment = Constant.getAlignment();
465 MF.Constants.push_back(YamlConstant);
469 void MIRPrinter::convert(ModuleSlotTracker &MST,
470 yaml::MachineJumpTable &YamlJTI,
471 const MachineJumpTableInfo &JTI) {
472 YamlJTI.Kind = JTI.getEntryKind();
474 for (const auto &Table : JTI.getJumpTables()) {
476 yaml::MachineJumpTable::Entry Entry;
478 for (const auto *MBB : Table.MBBs) {
479 raw_string_ostream StrOS(Str);
480 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
481 .printMBBReference(*MBB);
482 Entry.Blocks.push_back(StrOS.str());
485 YamlJTI.Entries.push_back(Entry);
489 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
490 const auto *TRI = MF.getSubtarget().getRegisterInfo();
492 for (const uint32_t *Mask : TRI->getRegMasks())
493 RegisterMaskIds.insert(std::make_pair(Mask, I++));
496 void llvm::guessSuccessors(const MachineBasicBlock &MBB,
497 SmallVectorImpl<MachineBasicBlock*> &Result,
498 bool &IsFallthrough) {
499 SmallPtrSet<MachineBasicBlock*,8> Seen;
501 for (const MachineInstr &MI : MBB) {
504 for (const MachineOperand &MO : MI.operands()) {
507 MachineBasicBlock *Succ = MO.getMBB();
508 auto RP = Seen.insert(Succ);
510 Result.push_back(Succ);
513 MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
514 IsFallthrough = I == MBB.end() || !I->isBarrier();
518 MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
519 if (MBB.succ_size() <= 1)
521 if (!MBB.hasSuccessorProbabilities())
524 SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(),
526 BranchProbability::normalizeProbabilities(Normalized.begin(),
528 SmallVector<BranchProbability,8> Equal(Normalized.size());
529 BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end());
531 return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
534 bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
535 SmallVector<MachineBasicBlock*,8> GuessedSuccs;
536 bool GuessedFallthrough;
537 guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
538 if (GuessedFallthrough) {
539 const MachineFunction &MF = *MBB.getParent();
540 MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
541 if (NextI != MF.end()) {
542 MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI);
543 if (!is_contained(GuessedSuccs, Next))
544 GuessedSuccs.push_back(Next);
547 if (GuessedSuccs.size() != MBB.succ_size())
549 return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
552 void MIPrinter::print(const MachineBasicBlock &MBB) {
553 assert(MBB.getNumber() >= 0 && "Invalid MBB number");
554 OS << "bb." << MBB.getNumber();
555 bool HasAttributes = false;
556 if (const auto *BB = MBB.getBasicBlock()) {
558 OS << "." << BB->getName();
560 HasAttributes = true;
562 int Slot = MST.getLocalSlot(BB);
564 OS << "<ir-block badref>";
566 OS << (Twine("%ir-block.") + Twine(Slot)).str();
569 if (MBB.hasAddressTaken()) {
570 OS << (HasAttributes ? ", " : " (");
571 OS << "address-taken";
572 HasAttributes = true;
575 OS << (HasAttributes ? ", " : " (");
577 HasAttributes = true;
579 if (MBB.getAlignment()) {
580 OS << (HasAttributes ? ", " : " (");
581 OS << "align " << MBB.getAlignment();
582 HasAttributes = true;
588 bool HasLineAttributes = false;
589 // Print the successors
590 bool canPredictProbs = canPredictBranchProbabilities(MBB);
591 if (!MBB.succ_empty() && (!SimplifyMIR || !canPredictProbs ||
592 !canPredictSuccessors(MBB))) {
593 OS.indent(2) << "successors: ";
594 for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
595 if (I != MBB.succ_begin())
597 printMBBReference(**I);
598 if (!SimplifyMIR || !canPredictProbs)
600 << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
604 HasLineAttributes = true;
607 // Print the live in registers.
608 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
609 if (MRI.tracksLiveness() && !MBB.livein_empty()) {
610 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
611 OS.indent(2) << "liveins: ";
613 for (const auto &LI : MBB.liveins()) {
617 printReg(LI.PhysReg, OS, &TRI);
618 if (!LI.LaneMask.all())
619 OS << ":0x" << PrintLaneMask(LI.LaneMask);
622 HasLineAttributes = true;
625 if (HasLineAttributes)
627 bool IsInBundle = false;
628 for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
629 const MachineInstr &MI = *I;
630 if (IsInBundle && !MI.isInsideBundle()) {
631 OS.indent(2) << "}\n";
634 OS.indent(IsInBundle ? 4 : 2);
636 if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
643 OS.indent(2) << "}\n";
646 /// Return true when an instruction has tied register that can't be determined
647 /// by the instruction's descriptor.
648 static bool hasComplexRegisterTies(const MachineInstr &MI) {
649 const MCInstrDesc &MCID = MI.getDesc();
650 for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I) {
651 const auto &Operand = MI.getOperand(I);
652 if (!Operand.isReg() || Operand.isDef())
653 // Ignore the defined registers as MCID marks only the uses as tied.
655 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
656 int TiedIdx = Operand.isTied() ? int(MI.findTiedOperandIdx(I)) : -1;
657 if (ExpectedTiedIdx != TiedIdx)
663 static LLT getTypeToPrint(const MachineInstr &MI, unsigned OpIdx,
664 SmallBitVector &PrintedTypes,
665 const MachineRegisterInfo &MRI) {
666 const MachineOperand &Op = MI.getOperand(OpIdx);
670 if (MI.isVariadic() || OpIdx >= MI.getNumExplicitOperands())
671 return MRI.getType(Op.getReg());
673 auto &OpInfo = MI.getDesc().OpInfo[OpIdx];
674 if (!OpInfo.isGenericType())
675 return MRI.getType(Op.getReg());
677 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
680 PrintedTypes.set(OpInfo.getGenericTypeIndex());
681 return MRI.getType(Op.getReg());
684 void MIPrinter::print(const MachineInstr &MI) {
685 const auto *MF = MI.getParent()->getParent();
686 const auto &MRI = MF->getRegInfo();
687 const auto &SubTarget = MF->getSubtarget();
688 const auto *TRI = SubTarget.getRegisterInfo();
689 assert(TRI && "Expected target register info");
690 const auto *TII = SubTarget.getInstrInfo();
691 assert(TII && "Expected target instruction info");
692 if (MI.isCFIInstruction())
693 assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
695 SmallBitVector PrintedTypes(8);
696 bool ShouldPrintRegisterTies = hasComplexRegisterTies(MI);
697 unsigned I = 0, E = MI.getNumOperands();
698 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
699 !MI.getOperand(I).isImplicit();
703 print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies,
704 getTypeToPrint(MI, I, PrintedTypes, MRI),
710 if (MI.getFlag(MachineInstr::FrameSetup))
711 OS << "frame-setup ";
712 OS << TII->getName(MI.getOpcode());
716 bool NeedComma = false;
720 print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies,
721 getTypeToPrint(MI, I, PrintedTypes, MRI));
725 if (MI.getDebugLoc()) {
728 OS << " debug-location ";
729 MI.getDebugLoc()->printAsOperand(OS, MST);
732 if (!MI.memoperands_empty()) {
734 bool NeedComma = false;
735 for (const auto *Op : MI.memoperands()) {
744 void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
745 OS << "%bb." << MBB.getNumber();
746 if (const auto *BB = MBB.getBasicBlock()) {
748 OS << '.' << BB->getName();
752 static void printIRSlotNumber(raw_ostream &OS, int Slot) {
759 void MIPrinter::printIRBlockReference(const BasicBlock &BB) {
762 printLLVMNameWithoutPrefix(OS, BB.getName());
765 const Function *F = BB.getParent();
767 if (F == MST.getCurrentFunction()) {
768 Slot = MST.getLocalSlot(&BB);
770 ModuleSlotTracker CustomMST(F->getParent(),
771 /*ShouldInitializeAllMetadata=*/false);
772 CustomMST.incorporateFunction(*F);
773 Slot = CustomMST.getLocalSlot(&BB);
775 printIRSlotNumber(OS, Slot);
778 void MIPrinter::printIRValueReference(const Value &V) {
779 if (isa<GlobalValue>(V)) {
780 V.printAsOperand(OS, /*PrintType=*/false, MST);
783 if (isa<Constant>(V)) {
784 // Machine memory operands can load/store to/from constant value pointers.
786 V.printAsOperand(OS, /*PrintType=*/true, MST);
792 printLLVMNameWithoutPrefix(OS, V.getName());
795 printIRSlotNumber(OS, MST.getLocalSlot(&V));
798 void MIPrinter::printStackObjectReference(int FrameIndex) {
799 auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
800 assert(ObjectInfo != StackObjectOperandMapping.end() &&
801 "Invalid frame index");
802 const FrameIndexOperand &Operand = ObjectInfo->second;
803 if (Operand.IsFixed) {
804 OS << "%fixed-stack." << Operand.ID;
807 OS << "%stack." << Operand.ID;
808 if (!Operand.Name.empty())
809 OS << '.' << Operand.Name;
812 void MIPrinter::printOffset(int64_t Offset) {
816 OS << " - " << -Offset;
819 OS << " + " << Offset;
822 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
823 auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
824 for (const auto &I : Flags) {
832 void MIPrinter::printTargetFlags(const MachineOperand &Op) {
833 if (!Op.getTargetFlags())
836 Op.getParent()->getParent()->getParent()->getSubtarget().getInstrInfo();
837 assert(TII && "expected instruction info");
838 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
839 OS << "target-flags(";
840 const bool HasDirectFlags = Flags.first;
841 const bool HasBitmaskFlags = Flags.second;
842 if (!HasDirectFlags && !HasBitmaskFlags) {
846 if (HasDirectFlags) {
847 if (const auto *Name = getTargetFlagName(TII, Flags.first))
850 OS << "<unknown target flag>";
852 if (!HasBitmaskFlags) {
856 bool IsCommaNeeded = HasDirectFlags;
857 unsigned BitMask = Flags.second;
858 auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
859 for (const auto &Mask : BitMasks) {
860 // Check if the flag's bitmask has the bits of the current mask set.
861 if ((BitMask & Mask.first) == Mask.first) {
864 IsCommaNeeded = true;
866 // Clear the bits which were serialized from the flag's bitmask.
867 BitMask &= ~(Mask.first);
871 // When the resulting flag's bitmask isn't zero, we know that we didn't
872 // serialize all of the bit flags.
875 OS << "<unknown bitmask target flag>";
880 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
881 const auto *TII = MF.getSubtarget().getInstrInfo();
882 assert(TII && "expected instruction info");
883 auto Indices = TII->getSerializableTargetIndices();
884 for (const auto &I : Indices) {
885 if (I.first == Index) {
892 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
893 unsigned I, bool ShouldPrintRegisterTies, LLT TypeToPrint,
895 printTargetFlags(Op);
896 switch (Op.getType()) {
897 case MachineOperand::MO_Register:
899 OS << (Op.isDef() ? "implicit-def " : "implicit ");
900 else if (!IsDef && Op.isDef())
901 // Print the 'def' flag only when the operand is defined after '='.
903 if (Op.isInternalRead())
911 if (Op.isEarlyClobber())
912 OS << "early-clobber ";
915 printReg(Op.getReg(), OS, TRI);
916 // Print the sub register.
917 if (Op.getSubReg() != 0)
918 OS << '.' << TRI->getSubRegIndexName(Op.getSubReg());
919 if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef())
920 OS << "(tied-def " << Op.getParent()->findTiedOperandIdx(I) << ")";
921 if (TypeToPrint.isValid())
922 OS << '(' << TypeToPrint << ')';
924 case MachineOperand::MO_Immediate:
927 case MachineOperand::MO_CImmediate:
928 Op.getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
930 case MachineOperand::MO_FPImmediate:
931 Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
933 case MachineOperand::MO_MachineBasicBlock:
934 printMBBReference(*Op.getMBB());
936 case MachineOperand::MO_FrameIndex:
937 printStackObjectReference(Op.getIndex());
939 case MachineOperand::MO_ConstantPoolIndex:
940 OS << "%const." << Op.getIndex();
941 printOffset(Op.getOffset());
943 case MachineOperand::MO_TargetIndex:
944 OS << "target-index(";
945 if (const auto *Name = getTargetIndexName(
946 *Op.getParent()->getParent()->getParent(), Op.getIndex()))
951 printOffset(Op.getOffset());
953 case MachineOperand::MO_JumpTableIndex:
954 OS << "%jump-table." << Op.getIndex();
956 case MachineOperand::MO_ExternalSymbol: {
957 StringRef Name = Op.getSymbolName();
962 printLLVMNameWithoutPrefix(OS, Name);
964 printOffset(Op.getOffset());
967 case MachineOperand::MO_GlobalAddress:
968 Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
969 printOffset(Op.getOffset());
971 case MachineOperand::MO_BlockAddress:
972 OS << "blockaddress(";
973 Op.getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
976 printIRBlockReference(*Op.getBlockAddress()->getBasicBlock());
978 printOffset(Op.getOffset());
980 case MachineOperand::MO_RegisterMask: {
981 auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
982 if (RegMaskInfo != RegisterMaskIds.end())
983 OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
985 printCustomRegMask(Op.getRegMask(), OS, TRI);
988 case MachineOperand::MO_RegisterLiveOut: {
989 const uint32_t *RegMask = Op.getRegLiveOut();
991 bool IsCommaNeeded = false;
992 for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
993 if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
996 printReg(Reg, OS, TRI);
997 IsCommaNeeded = true;
1003 case MachineOperand::MO_Metadata:
1004 Op.getMetadata()->printAsOperand(OS, MST);
1006 case MachineOperand::MO_MCSymbol:
1007 OS << "<mcsymbol " << *Op.getMCSymbol() << ">";
1009 case MachineOperand::MO_CFIIndex: {
1010 const MachineFunction &MF = *Op.getParent()->getParent()->getParent();
1011 print(MF.getFrameInstructions()[Op.getCFIIndex()], TRI);
1014 case MachineOperand::MO_IntrinsicID: {
1015 Intrinsic::ID ID = Op.getIntrinsicID();
1016 if (ID < Intrinsic::num_intrinsics)
1017 OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
1019 const MachineFunction &MF = *Op.getParent()->getParent()->getParent();
1020 const TargetIntrinsicInfo *TII = MF.getTarget().getIntrinsicInfo();
1021 OS << "intrinsic(@" << TII->getName(ID) << ')';
1025 case MachineOperand::MO_Predicate: {
1026 auto Pred = static_cast<CmpInst::Predicate>(Op.getPredicate());
1027 OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
1028 << CmpInst::getPredicateName(Pred) << ')';
1034 void MIPrinter::print(const MachineMemOperand &Op) {
1036 // TODO: Print operand's target specific flags.
1037 if (Op.isVolatile())
1039 if (Op.isNonTemporal())
1040 OS << "non-temporal ";
1041 if (Op.isDereferenceable())
1042 OS << "dereferenceable ";
1043 if (Op.isInvariant())
1048 assert(Op.isStore() && "Non load machine operand must be a store");
1052 if (Op.getSynchScope() == SynchronizationScope::SingleThread)
1053 OS << "singlethread ";
1055 if (Op.getOrdering() != AtomicOrdering::NotAtomic)
1056 OS << toIRString(Op.getOrdering()) << ' ';
1057 if (Op.getFailureOrdering() != AtomicOrdering::NotAtomic)
1058 OS << toIRString(Op.getFailureOrdering()) << ' ';
1061 if (const Value *Val = Op.getValue()) {
1062 OS << (Op.isLoad() ? " from " : " into ");
1063 printIRValueReference(*Val);
1064 } else if (const PseudoSourceValue *PVal = Op.getPseudoValue()) {
1065 OS << (Op.isLoad() ? " from " : " into ");
1066 assert(PVal && "Expected a pseudo source value");
1067 switch (PVal->kind()) {
1068 case PseudoSourceValue::Stack:
1071 case PseudoSourceValue::GOT:
1074 case PseudoSourceValue::JumpTable:
1077 case PseudoSourceValue::ConstantPool:
1078 OS << "constant-pool";
1080 case PseudoSourceValue::FixedStack:
1081 printStackObjectReference(
1082 cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex());
1084 case PseudoSourceValue::GlobalValueCallEntry:
1085 OS << "call-entry ";
1086 cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1087 OS, /*PrintType=*/false, MST);
1089 case PseudoSourceValue::ExternalSymbolCallEntry:
1090 OS << "call-entry $";
1091 printLLVMNameWithoutPrefix(
1092 OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1094 case PseudoSourceValue::TargetCustom:
1095 llvm_unreachable("TargetCustom pseudo source values are not supported");
1099 printOffset(Op.getOffset());
1100 if (Op.getBaseAlignment() != Op.getSize())
1101 OS << ", align " << Op.getBaseAlignment();
1102 auto AAInfo = Op.getAAInfo();
1105 AAInfo.TBAA->printAsOperand(OS, MST);
1108 OS << ", !alias.scope ";
1109 AAInfo.Scope->printAsOperand(OS, MST);
1111 if (AAInfo.NoAlias) {
1112 OS << ", !noalias ";
1113 AAInfo.NoAlias->printAsOperand(OS, MST);
1115 if (Op.getRanges()) {
1117 Op.getRanges()->printAsOperand(OS, MST);
1122 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
1123 const TargetRegisterInfo *TRI) {
1124 int Reg = TRI->getLLVMRegNum(DwarfReg, true);
1129 printReg(Reg, OS, TRI);
1132 void MIPrinter::print(const MCCFIInstruction &CFI,
1133 const TargetRegisterInfo *TRI) {
1134 switch (CFI.getOperation()) {
1135 case MCCFIInstruction::OpSameValue:
1136 OS << "same_value ";
1138 OS << "<mcsymbol> ";
1139 printCFIRegister(CFI.getRegister(), OS, TRI);
1141 case MCCFIInstruction::OpOffset:
1144 OS << "<mcsymbol> ";
1145 printCFIRegister(CFI.getRegister(), OS, TRI);
1146 OS << ", " << CFI.getOffset();
1148 case MCCFIInstruction::OpDefCfaRegister:
1149 OS << "def_cfa_register ";
1151 OS << "<mcsymbol> ";
1152 printCFIRegister(CFI.getRegister(), OS, TRI);
1154 case MCCFIInstruction::OpDefCfaOffset:
1155 OS << "def_cfa_offset ";
1157 OS << "<mcsymbol> ";
1158 OS << CFI.getOffset();
1160 case MCCFIInstruction::OpDefCfa:
1163 OS << "<mcsymbol> ";
1164 printCFIRegister(CFI.getRegister(), OS, TRI);
1165 OS << ", " << CFI.getOffset();
1168 // TODO: Print the other CFI Operations.
1169 OS << "<unserializable cfi operation>";
1174 void llvm::printMIR(raw_ostream &OS, const Module &M) {
1175 yaml::Output Out(OS);
1176 Out << const_cast<Module &>(M);
1179 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
1180 MIRPrinter Printer(OS);