1 //===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/ADT/APFloat.h"
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/FoldingSet.h"
18 #include "llvm/ADT/Hashing.h"
19 #include "llvm/ADT/None.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/SmallBitVector.h"
22 #include "llvm/ADT/SmallString.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/Analysis/AliasAnalysis.h"
25 #include "llvm/Analysis/Loads.h"
26 #include "llvm/Analysis/MemoryLocation.h"
27 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
28 #include "llvm/CodeGen/MachineBasicBlock.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineInstrBundle.h"
32 #include "llvm/CodeGen/MachineMemOperand.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineOperand.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/CodeGen/TargetInstrInfo.h"
38 #include "llvm/CodeGen/TargetRegisterInfo.h"
39 #include "llvm/CodeGen/TargetSubtargetInfo.h"
40 #include "llvm/Config/llvm-config.h"
41 #include "llvm/IR/Constants.h"
42 #include "llvm/IR/DebugInfoMetadata.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/DerivedTypes.h"
45 #include "llvm/IR/Function.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/InstrTypes.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/LLVMContext.h"
50 #include "llvm/IR/Metadata.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/ModuleSlotTracker.h"
53 #include "llvm/IR/Type.h"
54 #include "llvm/IR/Value.h"
55 #include "llvm/IR/Operator.h"
56 #include "llvm/MC/MCInstrDesc.h"
57 #include "llvm/MC/MCRegisterInfo.h"
58 #include "llvm/MC/MCSymbol.h"
59 #include "llvm/Support/Casting.h"
60 #include "llvm/Support/CommandLine.h"
61 #include "llvm/Support/Compiler.h"
62 #include "llvm/Support/Debug.h"
63 #include "llvm/Support/ErrorHandling.h"
64 #include "llvm/Support/LowLevelTypeImpl.h"
65 #include "llvm/Support/MathExtras.h"
66 #include "llvm/Support/raw_ostream.h"
67 #include "llvm/Target/TargetIntrinsicInfo.h"
68 #include "llvm/Target/TargetMachine.h"
79 static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) {
80 if (const MachineBasicBlock *MBB = MI.getParent())
81 if (const MachineFunction *MF = MBB->getParent())
86 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
88 static void tryToGetTargetInfo(const MachineInstr &MI,
89 const TargetRegisterInfo *&TRI,
90 const MachineRegisterInfo *&MRI,
91 const TargetIntrinsicInfo *&IntrinsicInfo,
92 const TargetInstrInfo *&TII) {
94 if (const MachineFunction *MF = getMFIfAvailable(MI)) {
95 TRI = MF->getSubtarget().getRegisterInfo();
96 MRI = &MF->getRegInfo();
97 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
98 TII = MF->getSubtarget().getInstrInfo();
102 void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
103 if (MCID->ImplicitDefs)
104 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
106 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
107 if (MCID->ImplicitUses)
108 for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
110 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
113 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
114 /// implicit operands. It reserves space for the number of operands specified by
116 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
117 DebugLoc dl, bool NoImp)
118 : MCID(&tid), debugLoc(std::move(dl)) {
119 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
121 // Reserve space for the expected number of operands.
122 if (unsigned NumOps = MCID->getNumOperands() +
123 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
124 CapOperands = OperandCapacity::get(NumOps);
125 Operands = MF.allocateOperandArray(CapOperands);
129 addImplicitDefUseOperands(MF);
132 /// MachineInstr ctor - Copies MachineInstr arg exactly
134 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
135 : MCID(&MI.getDesc()), Info(MI.Info), debugLoc(MI.getDebugLoc()) {
136 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
138 CapOperands = OperandCapacity::get(MI.getNumOperands());
139 Operands = MF.allocateOperandArray(CapOperands);
142 for (const MachineOperand &MO : MI.operands())
145 // Copy all the sensible flags.
149 /// getRegInfo - If this instruction is embedded into a MachineFunction,
150 /// return the MachineRegisterInfo object for the current function, otherwise
152 MachineRegisterInfo *MachineInstr::getRegInfo() {
153 if (MachineBasicBlock *MBB = getParent())
154 return &MBB->getParent()->getRegInfo();
158 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
159 /// this instruction from their respective use lists. This requires that the
160 /// operands already be on their use lists.
161 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
162 for (MachineOperand &MO : operands())
164 MRI.removeRegOperandFromUseList(&MO);
167 /// AddRegOperandsToUseLists - Add all of the register operands in
168 /// this instruction from their respective use lists. This requires that the
169 /// operands not be on their use lists yet.
170 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
171 for (MachineOperand &MO : operands())
173 MRI.addRegOperandToUseList(&MO);
176 void MachineInstr::addOperand(const MachineOperand &Op) {
177 MachineBasicBlock *MBB = getParent();
178 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
179 MachineFunction *MF = MBB->getParent();
180 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
184 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
185 /// ranges. If MRI is non-null also update use-def chains.
186 static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
187 unsigned NumOps, MachineRegisterInfo *MRI) {
189 return MRI->moveOperands(Dst, Src, NumOps);
191 // MachineOperand is a trivially copyable type so we can just use memmove.
192 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
195 /// addOperand - Add the specified operand to the instruction. If it is an
196 /// implicit operand, it is added to the end of the operand list. If it is
197 /// an explicit operand it is added at the end of the explicit operand list
198 /// (before the first implicit operand).
199 void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
200 assert(MCID && "Cannot add operands before providing an instr descriptor");
202 // Check if we're adding one of our existing operands.
203 if (&Op >= Operands && &Op < Operands + NumOperands) {
204 // This is unusual: MI->addOperand(MI->getOperand(i)).
205 // If adding Op requires reallocating or moving existing operands around,
206 // the Op reference could go stale. Support it by copying Op.
207 MachineOperand CopyOp(Op);
208 return addOperand(MF, CopyOp);
211 // Find the insert location for the new operand. Implicit registers go at
212 // the end, everything else goes before the implicit regs.
214 // FIXME: Allow mixed explicit and implicit operands on inline asm.
215 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
216 // implicit-defs, but they must not be moved around. See the FIXME in
218 unsigned OpNo = getNumOperands();
219 bool isImpReg = Op.isReg() && Op.isImplicit();
220 if (!isImpReg && !isInlineAsm()) {
221 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
223 assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
228 bool isDebugOp = Op.getType() == MachineOperand::MO_Metadata ||
229 Op.getType() == MachineOperand::MO_MCSymbol;
230 // OpNo now points as the desired insertion point. Unless this is a variadic
231 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
232 // RegMask operands go between the explicit and implicit operands.
233 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
234 OpNo < MCID->getNumOperands() || isDebugOp) &&
235 "Trying to add an operand to a machine instr that is already done!");
238 MachineRegisterInfo *MRI = getRegInfo();
240 // Determine if the Operands array needs to be reallocated.
241 // Save the old capacity and operand array.
242 OperandCapacity OldCap = CapOperands;
243 MachineOperand *OldOperands = Operands;
244 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
245 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
246 Operands = MF.allocateOperandArray(CapOperands);
247 // Move the operands before the insertion point.
249 moveOperands(Operands, OldOperands, OpNo, MRI);
252 // Move the operands following the insertion point.
253 if (OpNo != NumOperands)
254 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
258 // Deallocate the old operand array.
259 if (OldOperands != Operands && OldOperands)
260 MF.deallocateOperandArray(OldCap, OldOperands);
262 // Copy Op into place. It still needs to be inserted into the MRI use lists.
263 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
264 NewMO->ParentMI = this;
266 // When adding a register operand, tell MRI about it.
267 if (NewMO->isReg()) {
268 // Ensure isOnRegUseList() returns false, regardless of Op's status.
269 NewMO->Contents.Reg.Prev = nullptr;
270 // Ignore existing ties. This is not a property that can be copied.
272 // Add the new operand to MRI, but only for instructions in an MBB.
274 MRI->addRegOperandToUseList(NewMO);
275 // The MCID operand information isn't accurate until we start adding
276 // explicit operands. The implicit operands are added first, then the
277 // explicits are inserted before them.
279 // Tie uses to defs as indicated in MCInstrDesc.
280 if (NewMO->isUse()) {
281 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
283 tieOperands(DefIdx, OpNo);
285 // If the register operand is flagged as early, mark the operand as such.
286 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
287 NewMO->setIsEarlyClobber(true);
292 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
293 /// fewer operand than it started with.
295 void MachineInstr::RemoveOperand(unsigned OpNo) {
296 assert(OpNo < getNumOperands() && "Invalid operand number");
297 untieRegOperand(OpNo);
300 // Moving tied operands would break the ties.
301 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
302 if (Operands[i].isReg())
303 assert(!Operands[i].isTied() && "Cannot move tied operands");
306 MachineRegisterInfo *MRI = getRegInfo();
307 if (MRI && Operands[OpNo].isReg())
308 MRI->removeRegOperandFromUseList(Operands + OpNo);
310 // Don't call the MachineOperand destructor. A lot of this code depends on
311 // MachineOperand having a trivial destructor anyway, and adding a call here
312 // wouldn't make it 'destructor-correct'.
314 if (unsigned N = NumOperands - 1 - OpNo)
315 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
319 void MachineInstr::dropMemRefs(MachineFunction &MF) {
320 if (memoperands_empty())
323 // See if we can just drop all of our extra info.
324 if (!getPreInstrSymbol() && !getPostInstrSymbol()) {
328 if (!getPostInstrSymbol()) {
329 Info.set<EIIK_PreInstrSymbol>(getPreInstrSymbol());
332 if (!getPreInstrSymbol()) {
333 Info.set<EIIK_PostInstrSymbol>(getPostInstrSymbol());
337 // Otherwise allocate a fresh extra info with just these symbols.
338 Info.set<EIIK_OutOfLine>(
339 MF.createMIExtraInfo({}, getPreInstrSymbol(), getPostInstrSymbol()));
342 void MachineInstr::setMemRefs(MachineFunction &MF,
343 ArrayRef<MachineMemOperand *> MMOs) {
349 // Try to store a single MMO inline.
350 if (MMOs.size() == 1 && !getPreInstrSymbol() && !getPostInstrSymbol()) {
351 Info.set<EIIK_MMO>(MMOs[0]);
355 // Otherwise create an extra info struct with all of our info.
356 Info.set<EIIK_OutOfLine>(
357 MF.createMIExtraInfo(MMOs, getPreInstrSymbol(), getPostInstrSymbol()));
360 void MachineInstr::addMemOperand(MachineFunction &MF,
361 MachineMemOperand *MO) {
362 SmallVector<MachineMemOperand *, 2> MMOs;
363 MMOs.append(memoperands_begin(), memoperands_end());
365 setMemRefs(MF, MMOs);
368 void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) {
370 // Nothing to do for a self-clone!
373 assert(&MF == MI.getMF() &&
374 "Invalid machine functions when cloning memory refrences!");
375 // See if we can just steal the extra info already allocated for the
376 // instruction. We can do this whenever the pre- and post-instruction symbols
377 // are the same (including null).
378 if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
379 getPostInstrSymbol() == MI.getPostInstrSymbol()) {
384 // Otherwise, fall back on a copy-based clone.
385 setMemRefs(MF, MI.memoperands());
388 /// Check to see if the MMOs pointed to by the two MemRefs arrays are
390 static bool hasIdenticalMMOs(ArrayRef<MachineMemOperand *> LHS,
391 ArrayRef<MachineMemOperand *> RHS) {
392 if (LHS.size() != RHS.size())
395 auto LHSPointees = make_pointee_range(LHS);
396 auto RHSPointees = make_pointee_range(RHS);
397 return std::equal(LHSPointees.begin(), LHSPointees.end(),
398 RHSPointees.begin());
401 void MachineInstr::cloneMergedMemRefs(MachineFunction &MF,
402 ArrayRef<const MachineInstr *> MIs) {
403 // Try handling easy numbers of MIs with simpler mechanisms.
408 if (MIs.size() == 1) {
409 cloneMemRefs(MF, *MIs[0]);
412 // Because an empty memoperands list provides *no* information and must be
413 // handled conservatively (assuming the instruction can do anything), the only
414 // way to merge with it is to drop all other memoperands.
415 if (MIs[0]->memoperands_empty()) {
420 // Handle the general case.
421 SmallVector<MachineMemOperand *, 2> MergedMMOs;
422 // Start with the first instruction.
423 assert(&MF == MIs[0]->getMF() &&
424 "Invalid machine functions when cloning memory references!");
425 MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
426 // Now walk all the other instructions and accumulate any different MMOs.
427 for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
428 assert(&MF == MI.getMF() &&
429 "Invalid machine functions when cloning memory references!");
431 // Skip MIs with identical operands to the first. This is a somewhat
432 // arbitrary hack but will catch common cases without being quadratic.
433 // TODO: We could fully implement merge semantics here if needed.
434 if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
437 // Because an empty memoperands list provides *no* information and must be
438 // handled conservatively (assuming the instruction can do anything), the
439 // only way to merge with it is to drop all other memoperands.
440 if (MI.memoperands_empty()) {
445 // Otherwise accumulate these into our temporary buffer of the merged state.
446 MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
449 setMemRefs(MF, MergedMMOs);
452 void MachineInstr::setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
453 MCSymbol *OldSymbol = getPreInstrSymbol();
454 if (OldSymbol == Symbol)
456 if (OldSymbol && !Symbol) {
457 // We're removing a symbol rather than adding one. Try to clean up any
458 // extra info carried around.
459 if (Info.is<EIIK_PreInstrSymbol>()) {
464 if (memoperands_empty()) {
465 assert(getPostInstrSymbol() &&
466 "Should never have only a single symbol allocated out-of-line!");
467 Info.set<EIIK_PostInstrSymbol>(getPostInstrSymbol());
471 // Otherwise fallback on the generic update.
472 } else if (!Info || Info.is<EIIK_PreInstrSymbol>()) {
473 // If we don't have any other extra info, we can store this inline.
474 Info.set<EIIK_PreInstrSymbol>(Symbol);
478 // Otherwise, allocate a full new set of extra info.
479 // FIXME: Maybe we should make the symbols in the extra info mutable?
480 Info.set<EIIK_OutOfLine>(
481 MF.createMIExtraInfo(memoperands(), Symbol, getPostInstrSymbol()));
484 void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
485 MCSymbol *OldSymbol = getPostInstrSymbol();
486 if (OldSymbol == Symbol)
488 if (OldSymbol && !Symbol) {
489 // We're removing a symbol rather than adding one. Try to clean up any
490 // extra info carried around.
491 if (Info.is<EIIK_PostInstrSymbol>()) {
496 if (memoperands_empty()) {
497 assert(getPreInstrSymbol() &&
498 "Should never have only a single symbol allocated out-of-line!");
499 Info.set<EIIK_PreInstrSymbol>(getPreInstrSymbol());
503 // Otherwise fallback on the generic update.
504 } else if (!Info || Info.is<EIIK_PostInstrSymbol>()) {
505 // If we don't have any other extra info, we can store this inline.
506 Info.set<EIIK_PostInstrSymbol>(Symbol);
510 // Otherwise, allocate a full new set of extra info.
511 // FIXME: Maybe we should make the symbols in the extra info mutable?
512 Info.set<EIIK_OutOfLine>(
513 MF.createMIExtraInfo(memoperands(), getPreInstrSymbol(), Symbol));
516 uint16_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
517 // For now, the just return the union of the flags. If the flags get more
518 // complicated over time, we might need more logic here.
519 return getFlags() | Other.getFlags();
522 void MachineInstr::copyIRFlags(const Instruction &I) {
523 // Copy the wrapping flags.
524 if (const OverflowingBinaryOperator *OB =
525 dyn_cast<OverflowingBinaryOperator>(&I)) {
526 if (OB->hasNoSignedWrap())
527 setFlag(MachineInstr::MIFlag::NoSWrap);
528 if (OB->hasNoUnsignedWrap())
529 setFlag(MachineInstr::MIFlag::NoUWrap);
532 // Copy the exact flag.
533 if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
535 setFlag(MachineInstr::MIFlag::IsExact);
537 // Copy the fast-math flags.
538 if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
539 const FastMathFlags Flags = FP->getFastMathFlags();
541 setFlag(MachineInstr::MIFlag::FmNoNans);
543 setFlag(MachineInstr::MIFlag::FmNoInfs);
544 if (Flags.noSignedZeros())
545 setFlag(MachineInstr::MIFlag::FmNsz);
546 if (Flags.allowReciprocal())
547 setFlag(MachineInstr::MIFlag::FmArcp);
548 if (Flags.allowContract())
549 setFlag(MachineInstr::MIFlag::FmContract);
550 if (Flags.approxFunc())
551 setFlag(MachineInstr::MIFlag::FmAfn);
552 if (Flags.allowReassoc())
553 setFlag(MachineInstr::MIFlag::FmReassoc);
557 bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
558 assert(!isBundledWithPred() && "Must be called on bundle header");
559 for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
560 if (MII->getDesc().getFlags() & Mask) {
561 if (Type == AnyInBundle)
564 if (Type == AllInBundle && !MII->isBundle())
567 // This was the last instruction in the bundle.
568 if (!MII->isBundledWithSucc())
569 return Type == AllInBundle;
573 bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
574 MICheckType Check) const {
575 // If opcodes or number of operands are not the same then the two
576 // instructions are obviously not identical.
577 if (Other.getOpcode() != getOpcode() ||
578 Other.getNumOperands() != getNumOperands())
582 // We have passed the test above that both instructions have the same
583 // opcode, so we know that both instructions are bundles here. Let's compare
584 // MIs inside the bundle.
585 assert(Other.isBundle() && "Expected that both instructions are bundles.");
586 MachineBasicBlock::const_instr_iterator I1 = getIterator();
587 MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
588 // Loop until we analysed the last intruction inside at least one of the
590 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
593 if (!I1->isIdenticalTo(*I2, Check))
596 // If we've reached the end of just one of the two bundles, but not both,
597 // the instructions are not identical.
598 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
602 // Check operands to make sure they match.
603 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
604 const MachineOperand &MO = getOperand(i);
605 const MachineOperand &OMO = Other.getOperand(i);
607 if (!MO.isIdenticalTo(OMO))
612 // Clients may or may not want to ignore defs when testing for equality.
613 // For example, machine CSE pass only cares about finding common
614 // subexpressions, so it's safe to ignore virtual register defs.
616 if (Check == IgnoreDefs)
618 else if (Check == IgnoreVRegDefs) {
619 if (!TargetRegisterInfo::isVirtualRegister(MO.getReg()) ||
620 !TargetRegisterInfo::isVirtualRegister(OMO.getReg()))
621 if (!MO.isIdenticalTo(OMO))
624 if (!MO.isIdenticalTo(OMO))
626 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
630 if (!MO.isIdenticalTo(OMO))
632 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
636 // If DebugLoc does not match then two debug instructions are not identical.
638 if (getDebugLoc() && Other.getDebugLoc() &&
639 getDebugLoc() != Other.getDebugLoc())
644 const MachineFunction *MachineInstr::getMF() const {
645 return getParent()->getParent();
648 MachineInstr *MachineInstr::removeFromParent() {
649 assert(getParent() && "Not embedded in a basic block!");
650 return getParent()->remove(this);
653 MachineInstr *MachineInstr::removeFromBundle() {
654 assert(getParent() && "Not embedded in a basic block!");
655 return getParent()->remove_instr(this);
658 void MachineInstr::eraseFromParent() {
659 assert(getParent() && "Not embedded in a basic block!");
660 getParent()->erase(this);
663 void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
664 assert(getParent() && "Not embedded in a basic block!");
665 MachineBasicBlock *MBB = getParent();
666 MachineFunction *MF = MBB->getParent();
667 assert(MF && "Not embedded in a function!");
669 MachineInstr *MI = (MachineInstr *)this;
670 MachineRegisterInfo &MRI = MF->getRegInfo();
672 for (const MachineOperand &MO : MI->operands()) {
673 if (!MO.isReg() || !MO.isDef())
675 unsigned Reg = MO.getReg();
676 if (!TargetRegisterInfo::isVirtualRegister(Reg))
678 MRI.markUsesInDebugValueAsUndef(Reg);
680 MI->eraseFromParent();
683 void MachineInstr::eraseFromBundle() {
684 assert(getParent() && "Not embedded in a basic block!");
685 getParent()->erase_instr(this);
688 unsigned MachineInstr::getNumExplicitOperands() const {
689 unsigned NumOperands = MCID->getNumOperands();
690 if (!MCID->isVariadic())
693 for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
694 const MachineOperand &MO = getOperand(I);
695 // The operands must always be in the following order:
696 // - explicit reg defs,
697 // - other explicit operands (reg uses, immediates, etc.),
698 // - implicit reg defs
699 // - implicit reg uses
700 if (MO.isReg() && MO.isImplicit())
707 unsigned MachineInstr::getNumExplicitDefs() const {
708 unsigned NumDefs = MCID->getNumDefs();
709 if (!MCID->isVariadic())
712 for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
713 const MachineOperand &MO = getOperand(I);
714 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
721 void MachineInstr::bundleWithPred() {
722 assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
723 setFlag(BundledPred);
724 MachineBasicBlock::instr_iterator Pred = getIterator();
726 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
727 Pred->setFlag(BundledSucc);
730 void MachineInstr::bundleWithSucc() {
731 assert(!isBundledWithSucc() && "MI is already bundled with its successor");
732 setFlag(BundledSucc);
733 MachineBasicBlock::instr_iterator Succ = getIterator();
735 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
736 Succ->setFlag(BundledPred);
739 void MachineInstr::unbundleFromPred() {
740 assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
741 clearFlag(BundledPred);
742 MachineBasicBlock::instr_iterator Pred = getIterator();
744 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
745 Pred->clearFlag(BundledSucc);
748 void MachineInstr::unbundleFromSucc() {
749 assert(isBundledWithSucc() && "MI isn't bundled with its successor");
750 clearFlag(BundledSucc);
751 MachineBasicBlock::instr_iterator Succ = getIterator();
753 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
754 Succ->clearFlag(BundledPred);
757 bool MachineInstr::isStackAligningInlineAsm() const {
759 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
760 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
766 InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
767 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
768 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
769 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
772 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
773 unsigned *GroupNo) const {
774 assert(isInlineAsm() && "Expected an inline asm instruction");
775 assert(OpIdx < getNumOperands() && "OpIdx out of range");
777 // Ignore queries about the initial operands.
778 if (OpIdx < InlineAsm::MIOp_FirstOperand)
783 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
785 const MachineOperand &FlagMO = getOperand(i);
786 // If we reach the implicit register operands, stop looking.
789 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
790 if (i + NumOps > OpIdx) {
800 const DILabel *MachineInstr::getDebugLabel() const {
801 assert(isDebugLabel() && "not a DBG_LABEL");
802 return cast<DILabel>(getOperand(0).getMetadata());
805 const DILocalVariable *MachineInstr::getDebugVariable() const {
806 assert(isDebugValue() && "not a DBG_VALUE");
807 return cast<DILocalVariable>(getOperand(2).getMetadata());
810 const DIExpression *MachineInstr::getDebugExpression() const {
811 assert(isDebugValue() && "not a DBG_VALUE");
812 return cast<DIExpression>(getOperand(3).getMetadata());
815 const TargetRegisterClass*
816 MachineInstr::getRegClassConstraint(unsigned OpIdx,
817 const TargetInstrInfo *TII,
818 const TargetRegisterInfo *TRI) const {
819 assert(getParent() && "Can't have an MBB reference here!");
820 assert(getMF() && "Can't have an MF reference here!");
821 const MachineFunction &MF = *getMF();
823 // Most opcodes have fixed constraints in their MCInstrDesc.
825 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
827 if (!getOperand(OpIdx).isReg())
830 // For tied uses on inline asm, get the constraint from the def.
832 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
835 // Inline asm stores register class constraints in the flag word.
836 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
840 unsigned Flag = getOperand(FlagIdx).getImm();
842 if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
843 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
844 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
845 InlineAsm::hasRegClassConstraint(Flag, RCID))
846 return TRI->getRegClass(RCID);
848 // Assume that all registers in a memory operand are pointers.
849 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
850 return TRI->getPointerRegClass(MF);
855 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
856 unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
857 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
858 // Check every operands inside the bundle if we have
861 for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
863 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
864 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
866 // Otherwise, just check the current operands.
867 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
868 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
872 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
873 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
874 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
875 assert(CurRC && "Invalid initial register class");
876 // Check if Reg is constrained by some of its use/def from MI.
877 const MachineOperand &MO = getOperand(OpIdx);
878 if (!MO.isReg() || MO.getReg() != Reg)
880 // If yes, accumulate the constraints through the operand.
881 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
884 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
885 unsigned OpIdx, const TargetRegisterClass *CurRC,
886 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
887 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
888 const MachineOperand &MO = getOperand(OpIdx);
890 "Cannot get register constraints for non-register operand");
891 assert(CurRC && "Invalid initial register class");
892 if (unsigned SubIdx = MO.getSubReg()) {
894 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
896 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
898 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
902 /// Return the number of instructions inside the MI bundle, not counting the
903 /// header instruction.
904 unsigned MachineInstr::getBundleSize() const {
905 MachineBasicBlock::const_instr_iterator I = getIterator();
907 while (I->isBundledWithSucc()) {
914 /// Returns true if the MachineInstr has an implicit-use operand of exactly
915 /// the given register (not considering sub/super-registers).
916 bool MachineInstr::hasRegisterImplicitUseOperand(unsigned Reg) const {
917 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
918 const MachineOperand &MO = getOperand(i);
919 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
925 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
926 /// the specific register or -1 if it is not found. It further tightens
927 /// the search criteria to a use that kills the register if isKill is true.
928 int MachineInstr::findRegisterUseOperandIdx(
929 unsigned Reg, bool isKill, const TargetRegisterInfo *TRI) const {
930 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
931 const MachineOperand &MO = getOperand(i);
932 if (!MO.isReg() || !MO.isUse())
934 unsigned MOReg = MO.getReg();
937 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
938 if (!isKill || MO.isKill())
944 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
945 /// indicating if this instruction reads or writes Reg. This also considers
948 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
949 SmallVectorImpl<unsigned> *Ops) const {
950 bool PartDef = false; // Partial redefine.
951 bool FullDef = false; // Full define.
954 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
955 const MachineOperand &MO = getOperand(i);
956 if (!MO.isReg() || MO.getReg() != Reg)
961 Use |= !MO.isUndef();
962 else if (MO.getSubReg() && !MO.isUndef())
963 // A partial def undef doesn't count as reading the register.
968 // A partial redefine uses Reg unless there is also a full define.
969 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
972 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
973 /// the specified register or -1 if it is not found. If isDead is true, defs
974 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
975 /// also checks if there is a def of a super-register.
977 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
978 const TargetRegisterInfo *TRI) const {
979 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
980 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
981 const MachineOperand &MO = getOperand(i);
982 // Accept regmask operands when Overlap is set.
983 // Ignore them when looking for a specific def operand (Overlap == false).
984 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
986 if (!MO.isReg() || !MO.isDef())
988 unsigned MOReg = MO.getReg();
989 bool Found = (MOReg == Reg);
990 if (!Found && TRI && isPhys &&
991 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
993 Found = TRI->regsOverlap(MOReg, Reg);
995 Found = TRI->isSubRegister(MOReg, Reg);
997 if (Found && (!isDead || MO.isDead()))
1003 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1004 /// operand list that is used to represent the predicate. It returns -1 if
1006 int MachineInstr::findFirstPredOperandIdx() const {
1007 // Don't call MCID.findFirstPredOperandIdx() because this variant
1008 // is sometimes called on an instruction that's not yet complete, and
1009 // so the number of operands is less than the MCID indicates. In
1010 // particular, the PTX target does this.
1011 const MCInstrDesc &MCID = getDesc();
1012 if (MCID.isPredicable()) {
1013 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1014 if (MCID.OpInfo[i].isPredicate())
1021 // MachineOperand::TiedTo is 4 bits wide.
1022 const unsigned TiedMax = 15;
1024 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1026 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1027 /// field. TiedTo can have these values:
1029 /// 0: Operand is not tied to anything.
1030 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1031 /// TiedMax: Tied to an operand >= TiedMax-1.
1033 /// The tied def must be one of the first TiedMax operands on a normal
1034 /// instruction. INLINEASM instructions allow more tied defs.
1036 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1037 MachineOperand &DefMO = getOperand(DefIdx);
1038 MachineOperand &UseMO = getOperand(UseIdx);
1039 assert(DefMO.isDef() && "DefIdx must be a def operand");
1040 assert(UseMO.isUse() && "UseIdx must be a use operand");
1041 assert(!DefMO.isTied() && "Def is already tied to another use");
1042 assert(!UseMO.isTied() && "Use is already tied to another def");
1044 if (DefIdx < TiedMax)
1045 UseMO.TiedTo = DefIdx + 1;
1047 // Inline asm can use the group descriptors to find tied operands, but on
1048 // normal instruction, the tied def must be within the first TiedMax
1050 assert(isInlineAsm() && "DefIdx out of range");
1051 UseMO.TiedTo = TiedMax;
1054 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1055 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1058 /// Given the index of a tied register operand, find the operand it is tied to.
1059 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1060 /// which must exist.
1061 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1062 const MachineOperand &MO = getOperand(OpIdx);
1063 assert(MO.isTied() && "Operand isn't tied");
1065 // Normally TiedTo is in range.
1066 if (MO.TiedTo < TiedMax)
1067 return MO.TiedTo - 1;
1069 // Uses on normal instructions can be out of range.
1070 if (!isInlineAsm()) {
1071 // Normal tied defs must be in the 0..TiedMax-1 range.
1074 // MO is a def. Search for the tied use.
1075 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1076 const MachineOperand &UseMO = getOperand(i);
1077 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1080 llvm_unreachable("Can't find tied use");
1083 // Now deal with inline asm by parsing the operand group descriptor flags.
1084 // Find the beginning of each operand group.
1085 SmallVector<unsigned, 8> GroupIdx;
1086 unsigned OpIdxGroup = ~0u;
1088 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1090 const MachineOperand &FlagMO = getOperand(i);
1091 assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1092 unsigned CurGroup = GroupIdx.size();
1093 GroupIdx.push_back(i);
1094 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1095 // OpIdx belongs to this operand group.
1096 if (OpIdx > i && OpIdx < i + NumOps)
1097 OpIdxGroup = CurGroup;
1099 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1101 // Operands in this group are tied to operands in TiedGroup which must be
1102 // earlier. Find the number of operands between the two groups.
1103 unsigned Delta = i - GroupIdx[TiedGroup];
1105 // OpIdx is a use tied to TiedGroup.
1106 if (OpIdxGroup == CurGroup)
1107 return OpIdx - Delta;
1109 // OpIdx is a def tied to this use group.
1110 if (OpIdxGroup == TiedGroup)
1111 return OpIdx + Delta;
1113 llvm_unreachable("Invalid tied operand on inline asm");
1116 /// clearKillInfo - Clears kill flags on all operands.
1118 void MachineInstr::clearKillInfo() {
1119 for (MachineOperand &MO : operands()) {
1120 if (MO.isReg() && MO.isUse())
1121 MO.setIsKill(false);
1125 void MachineInstr::substituteRegister(unsigned FromReg, unsigned ToReg,
1127 const TargetRegisterInfo &RegInfo) {
1128 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1130 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1131 for (MachineOperand &MO : operands()) {
1132 if (!MO.isReg() || MO.getReg() != FromReg)
1134 MO.substPhysReg(ToReg, RegInfo);
1137 for (MachineOperand &MO : operands()) {
1138 if (!MO.isReg() || MO.getReg() != FromReg)
1140 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1145 /// isSafeToMove - Return true if it is safe to move this instruction. If
1146 /// SawStore is set to true, it means that there is a store (or call) between
1147 /// the instruction's location and its intended destination.
1148 bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
1149 // Ignore stuff that we obviously can't move.
1151 // Treat volatile loads as stores. This is not strictly necessary for
1152 // volatiles, but it is required for atomic loads. It is not allowed to move
1153 // a load across an atomic load with Ordering > Monotonic.
1154 if (mayStore() || isCall() || isPHI() ||
1155 (mayLoad() && hasOrderedMemoryRef())) {
1160 if (isPosition() || isDebugInstr() || isTerminator() ||
1161 hasUnmodeledSideEffects())
1164 // See if this instruction does a load. If so, we have to guarantee that the
1165 // loaded value doesn't change between the load and the its intended
1166 // destination. The check for isInvariantLoad gives the targe the chance to
1167 // classify the load as always returning a constant, e.g. a constant pool
1169 if (mayLoad() && !isDereferenceableInvariantLoad(AA))
1170 // Otherwise, this is a real load. If there is a store between the load and
1171 // end of block, we can't move it.
1177 bool MachineInstr::mayAlias(AliasAnalysis *AA, MachineInstr &Other,
1179 const MachineFunction *MF = getMF();
1180 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1181 const MachineFrameInfo &MFI = MF->getFrameInfo();
1183 // If neither instruction stores to memory, they can't alias in any
1184 // meaningful way, even if they read from the same address.
1185 if (!mayStore() && !Other.mayStore())
1188 // Let the target decide if memory accesses cannot possibly overlap.
1189 if (TII->areMemAccessesTriviallyDisjoint(*this, Other, AA))
1192 // FIXME: Need to handle multiple memory operands to support all targets.
1193 if (!hasOneMemOperand() || !Other.hasOneMemOperand())
1196 MachineMemOperand *MMOa = *memoperands_begin();
1197 MachineMemOperand *MMOb = *Other.memoperands_begin();
1199 // The following interface to AA is fashioned after DAGCombiner::isAlias
1200 // and operates with MachineMemOperand offset with some important
1202 // - LLVM fundamentally assumes flat address spaces.
1203 // - MachineOperand offset can *only* result from legalization and
1204 // cannot affect queries other than the trivial case of overlap
1206 // - These offsets never wrap and never step outside
1207 // of allocated objects.
1208 // - There should never be any negative offsets here.
1210 // FIXME: Modify API to hide this math from "user"
1211 // Even before we go to AA we can reason locally about some
1212 // memory objects. It can save compile time, and possibly catch some
1213 // corner cases not currently covered.
1215 int64_t OffsetA = MMOa->getOffset();
1216 int64_t OffsetB = MMOb->getOffset();
1217 int64_t MinOffset = std::min(OffsetA, OffsetB);
1219 uint64_t WidthA = MMOa->getSize();
1220 uint64_t WidthB = MMOb->getSize();
1221 bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
1222 bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
1224 const Value *ValA = MMOa->getValue();
1225 const Value *ValB = MMOb->getValue();
1226 bool SameVal = (ValA && ValB && (ValA == ValB));
1228 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1229 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1230 if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1232 if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1234 if (PSVa && PSVb && (PSVa == PSVb))
1239 if (!KnownWidthA || !KnownWidthB)
1241 int64_t MaxOffset = std::max(OffsetA, OffsetB);
1242 int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1243 return (MinOffset + LowWidth > MaxOffset);
1252 assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
1253 assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
1255 int64_t OverlapA = KnownWidthA ? WidthA + OffsetA - MinOffset
1256 : MemoryLocation::UnknownSize;
1257 int64_t OverlapB = KnownWidthB ? WidthB + OffsetB - MinOffset
1258 : MemoryLocation::UnknownSize;
1260 AliasResult AAResult = AA->alias(
1261 MemoryLocation(ValA, OverlapA,
1262 UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1263 MemoryLocation(ValB, OverlapB,
1264 UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1266 return (AAResult != NoAlias);
1269 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1270 /// or volatile memory reference, or if the information describing the memory
1271 /// reference is not available. Return false if it is known to have no ordered
1272 /// memory references.
1273 bool MachineInstr::hasOrderedMemoryRef() const {
1274 // An instruction known never to access memory won't have a volatile access.
1278 !hasUnmodeledSideEffects())
1281 // Otherwise, if the instruction has no memory reference information,
1282 // conservatively assume it wasn't preserved.
1283 if (memoperands_empty())
1286 // Check if any of our memory operands are ordered.
1287 return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1288 return !MMO->isUnordered();
1292 /// isDereferenceableInvariantLoad - Return true if this instruction will never
1293 /// trap and is loading from a location whose value is invariant across a run of
1295 bool MachineInstr::isDereferenceableInvariantLoad(AliasAnalysis *AA) const {
1296 // If the instruction doesn't load at all, it isn't an invariant load.
1300 // If the instruction has lost its memoperands, conservatively assume that
1301 // it may not be an invariant load.
1302 if (memoperands_empty())
1305 const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1307 for (MachineMemOperand *MMO : memoperands()) {
1308 if (MMO->isVolatile()) return false;
1309 if (MMO->isStore()) return false;
1310 if (MMO->isInvariant() && MMO->isDereferenceable())
1313 // A load from a constant PseudoSourceValue is invariant.
1314 if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1315 if (PSV->isConstant(&MFI))
1318 if (const Value *V = MMO->getValue()) {
1319 // If we have an AliasAnalysis, ask it whether the memory is constant.
1321 AA->pointsToConstantMemory(
1322 MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1326 // Otherwise assume conservatively.
1330 // Everything checks out.
1334 /// isConstantValuePHI - If the specified instruction is a PHI that always
1335 /// merges together the same virtual register, return the register, otherwise
1337 unsigned MachineInstr::isConstantValuePHI() const {
1340 assert(getNumOperands() >= 3 &&
1341 "It's illegal to have a PHI without source operands");
1343 unsigned Reg = getOperand(1).getReg();
1344 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1345 if (getOperand(i).getReg() != Reg)
1350 bool MachineInstr::hasUnmodeledSideEffects() const {
1351 if (hasProperty(MCID::UnmodeledSideEffects))
1353 if (isInlineAsm()) {
1354 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1355 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1362 bool MachineInstr::isLoadFoldBarrier() const {
1363 return mayStore() || isCall() || hasUnmodeledSideEffects();
1366 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1368 bool MachineInstr::allDefsAreDead() const {
1369 for (const MachineOperand &MO : operands()) {
1370 if (!MO.isReg() || MO.isUse())
1378 /// copyImplicitOps - Copy implicit register operands from specified
1379 /// instruction to this instruction.
1380 void MachineInstr::copyImplicitOps(MachineFunction &MF,
1381 const MachineInstr &MI) {
1382 for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
1384 const MachineOperand &MO = MI.getOperand(i);
1385 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1390 bool MachineInstr::hasComplexRegisterTies() const {
1391 const MCInstrDesc &MCID = getDesc();
1392 for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1393 const auto &Operand = getOperand(I);
1394 if (!Operand.isReg() || Operand.isDef())
1395 // Ignore the defined registers as MCID marks only the uses as tied.
1397 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1398 int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1399 if (ExpectedTiedIdx != TiedIdx)
1405 LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1406 const MachineRegisterInfo &MRI) const {
1407 const MachineOperand &Op = getOperand(OpIdx);
1411 if (isVariadic() || OpIdx >= getNumExplicitOperands())
1412 return MRI.getType(Op.getReg());
1414 auto &OpInfo = getDesc().OpInfo[OpIdx];
1415 if (!OpInfo.isGenericType())
1416 return MRI.getType(Op.getReg());
1418 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1421 LLT TypeToPrint = MRI.getType(Op.getReg());
1422 // Don't mark the type index printed if it wasn't actually printed: maybe
1423 // another operand with the same type index has an actual type attached:
1424 if (TypeToPrint.isValid())
1425 PrintedTypes.set(OpInfo.getGenericTypeIndex());
1429 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1430 LLVM_DUMP_METHOD void MachineInstr::dump() const {
1436 void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1437 bool SkipDebugLoc, bool AddNewLine,
1438 const TargetInstrInfo *TII) const {
1439 const Module *M = nullptr;
1440 const Function *F = nullptr;
1441 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1442 F = &MF->getFunction();
1445 TII = MF->getSubtarget().getInstrInfo();
1448 ModuleSlotTracker MST(M);
1450 MST.incorporateFunction(*F);
1451 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, TII);
1454 void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
1455 bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1456 bool AddNewLine, const TargetInstrInfo *TII) const {
1457 // We can be a bit tidier if we know the MachineFunction.
1458 const MachineFunction *MF = nullptr;
1459 const TargetRegisterInfo *TRI = nullptr;
1460 const MachineRegisterInfo *MRI = nullptr;
1461 const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1462 tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1464 if (isCFIInstruction())
1465 assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
1467 SmallBitVector PrintedTypes(8);
1468 bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1469 auto getTiedOperandIdx = [&](unsigned OpIdx) {
1470 if (!ShouldPrintRegisterTies)
1472 const MachineOperand &MO = getOperand(OpIdx);
1473 if (MO.isReg() && MO.isTied() && !MO.isDef())
1474 return findTiedOperandIdx(OpIdx);
1477 unsigned StartOp = 0;
1478 unsigned e = getNumOperands();
1480 // Print explicitly defined operands on the left of an assignment syntax.
1481 while (StartOp < e) {
1482 const MachineOperand &MO = getOperand(StartOp);
1483 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1489 LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1490 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1491 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/false, IsStandalone,
1492 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1499 if (getFlag(MachineInstr::FrameSetup))
1500 OS << "frame-setup ";
1501 if (getFlag(MachineInstr::FrameDestroy))
1502 OS << "frame-destroy ";
1503 if (getFlag(MachineInstr::FmNoNans))
1505 if (getFlag(MachineInstr::FmNoInfs))
1507 if (getFlag(MachineInstr::FmNsz))
1509 if (getFlag(MachineInstr::FmArcp))
1511 if (getFlag(MachineInstr::FmContract))
1513 if (getFlag(MachineInstr::FmAfn))
1515 if (getFlag(MachineInstr::FmReassoc))
1517 if (getFlag(MachineInstr::NoUWrap))
1519 if (getFlag(MachineInstr::NoSWrap))
1521 if (getFlag(MachineInstr::IsExact))
1524 // Print the opcode name.
1526 OS << TII->getName(getOpcode());
1533 // Print the rest of the operands.
1534 bool FirstOp = true;
1535 unsigned AsmDescOp = ~0u;
1536 unsigned AsmOpCount = 0;
1538 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1539 // Print asm string.
1541 const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1542 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1543 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1544 getOperand(OpIdx).print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1545 ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1548 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1549 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1550 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1551 OS << " [sideeffect]";
1552 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1554 if (ExtraInfo & InlineAsm::Extra_MayStore)
1555 OS << " [maystore]";
1556 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1557 OS << " [isconvergent]";
1558 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1559 OS << " [alignstack]";
1560 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1561 OS << " [attdialect]";
1562 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1563 OS << " [inteldialect]";
1565 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1569 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1570 const MachineOperand &MO = getOperand(i);
1572 if (FirstOp) FirstOp = false; else OS << ",";
1575 if (isDebugValue() && MO.isMetadata()) {
1576 // Pretty print DBG_VALUE instructions.
1577 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1578 if (DIV && !DIV->getName().empty())
1579 OS << "!\"" << DIV->getName() << '\"';
1581 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1582 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1583 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1584 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1586 } else if (isDebugLabel() && MO.isMetadata()) {
1587 // Pretty print DBG_LABEL instructions.
1588 auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1589 if (DIL && !DIL->getName().empty())
1590 OS << "\"" << DIL->getName() << '\"';
1592 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1593 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1594 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1595 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1597 } else if (i == AsmDescOp && MO.isImm()) {
1598 // Pretty print the inline asm operand descriptor.
1599 OS << '$' << AsmOpCount++;
1600 unsigned Flag = MO.getImm();
1601 switch (InlineAsm::getKind(Flag)) {
1602 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1603 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1604 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1605 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1606 case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1607 case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1608 default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1612 if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1613 InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1615 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1617 OS << ":RC" << RCID;
1620 if (InlineAsm::isMemKind(Flag)) {
1621 unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1623 case InlineAsm::Constraint_es: OS << ":es"; break;
1624 case InlineAsm::Constraint_i: OS << ":i"; break;
1625 case InlineAsm::Constraint_m: OS << ":m"; break;
1626 case InlineAsm::Constraint_o: OS << ":o"; break;
1627 case InlineAsm::Constraint_v: OS << ":v"; break;
1628 case InlineAsm::Constraint_Q: OS << ":Q"; break;
1629 case InlineAsm::Constraint_R: OS << ":R"; break;
1630 case InlineAsm::Constraint_S: OS << ":S"; break;
1631 case InlineAsm::Constraint_T: OS << ":T"; break;
1632 case InlineAsm::Constraint_Um: OS << ":Um"; break;
1633 case InlineAsm::Constraint_Un: OS << ":Un"; break;
1634 case InlineAsm::Constraint_Uq: OS << ":Uq"; break;
1635 case InlineAsm::Constraint_Us: OS << ":Us"; break;
1636 case InlineAsm::Constraint_Ut: OS << ":Ut"; break;
1637 case InlineAsm::Constraint_Uv: OS << ":Uv"; break;
1638 case InlineAsm::Constraint_Uy: OS << ":Uy"; break;
1639 case InlineAsm::Constraint_X: OS << ":X"; break;
1640 case InlineAsm::Constraint_Z: OS << ":Z"; break;
1641 case InlineAsm::Constraint_ZC: OS << ":ZC"; break;
1642 case InlineAsm::Constraint_Zy: OS << ":Zy"; break;
1643 default: OS << ":?"; break;
1647 unsigned TiedTo = 0;
1648 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1649 OS << " tiedto:$" << TiedTo;
1653 // Compute the index of the next operand descriptor.
1654 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1656 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1657 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1658 if (MO.isImm() && isOperandSubregIdx(i))
1659 MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI);
1661 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1662 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1666 // Print any optional symbols attached to this instruction as-if they were
1668 if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1673 OS << " pre-instr-symbol ";
1674 MachineOperand::printSymbol(OS, *PreInstrSymbol);
1676 if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1681 OS << " post-instr-symbol ";
1682 MachineOperand::printSymbol(OS, *PostInstrSymbol);
1685 if (!SkipDebugLoc) {
1686 if (const DebugLoc &DL = getDebugLoc()) {
1689 OS << " debug-location ";
1690 DL->printAsOperand(OS, MST);
1694 if (!memoperands_empty()) {
1695 SmallVector<StringRef, 0> SSNs;
1696 const LLVMContext *Context = nullptr;
1697 std::unique_ptr<LLVMContext> CtxPtr;
1698 const MachineFrameInfo *MFI = nullptr;
1699 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1700 MFI = &MF->getFrameInfo();
1701 Context = &MF->getFunction().getContext();
1703 CtxPtr = llvm::make_unique<LLVMContext>();
1704 Context = CtxPtr.get();
1708 bool NeedComma = false;
1709 for (const MachineMemOperand *Op : memoperands()) {
1712 Op->print(OS, MST, SSNs, *Context, MFI, TII);
1720 bool HaveSemi = false;
1722 // Print debug location information.
1723 if (const DebugLoc &DL = getDebugLoc()) {
1732 // Print extra comments for DEBUG_VALUE.
1733 if (isDebugValue() && getOperand(e - 2).isMetadata()) {
1738 auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
1739 OS << " line no:" << DV->getLine();
1740 if (auto *InlinedAt = debugLoc->getInlinedAt()) {
1741 DebugLoc InlinedAtDL(InlinedAt);
1742 if (InlinedAtDL && MF) {
1743 OS << " inlined @[ ";
1744 InlinedAtDL.print(OS);
1748 if (isIndirectDebugValue())
1757 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1758 const TargetRegisterInfo *RegInfo,
1759 bool AddIfNotFound) {
1760 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1761 bool hasAliases = isPhysReg &&
1762 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1764 SmallVector<unsigned,4> DeadOps;
1765 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1766 MachineOperand &MO = getOperand(i);
1767 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1770 // DEBUG_VALUE nodes do not contribute to code generation and should
1771 // always be ignored. Failure to do so may result in trying to modify
1772 // KILL flags on DEBUG_VALUE nodes.
1776 unsigned Reg = MO.getReg();
1780 if (Reg == IncomingReg) {
1783 // The register is already marked kill.
1785 if (isPhysReg && isRegTiedToDefOperand(i))
1786 // Two-address uses of physregs must not be marked kill.
1791 } else if (hasAliases && MO.isKill() &&
1792 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1793 // A super-register kill already exists.
1794 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1796 if (RegInfo->isSubRegister(IncomingReg, Reg))
1797 DeadOps.push_back(i);
1801 // Trim unneeded kill operands.
1802 while (!DeadOps.empty()) {
1803 unsigned OpIdx = DeadOps.back();
1804 if (getOperand(OpIdx).isImplicit() &&
1805 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1806 RemoveOperand(OpIdx);
1808 getOperand(OpIdx).setIsKill(false);
1812 // If not found, this means an alias of one of the operands is killed. Add a
1813 // new implicit operand if required.
1814 if (!Found && AddIfNotFound) {
1815 addOperand(MachineOperand::CreateReg(IncomingReg,
1824 void MachineInstr::clearRegisterKills(unsigned Reg,
1825 const TargetRegisterInfo *RegInfo) {
1826 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1828 for (MachineOperand &MO : operands()) {
1829 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1831 unsigned OpReg = MO.getReg();
1832 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1833 MO.setIsKill(false);
1837 bool MachineInstr::addRegisterDead(unsigned Reg,
1838 const TargetRegisterInfo *RegInfo,
1839 bool AddIfNotFound) {
1840 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
1841 bool hasAliases = isPhysReg &&
1842 MCRegAliasIterator(Reg, RegInfo, false).isValid();
1844 SmallVector<unsigned,4> DeadOps;
1845 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1846 MachineOperand &MO = getOperand(i);
1847 if (!MO.isReg() || !MO.isDef())
1849 unsigned MOReg = MO.getReg();
1856 } else if (hasAliases && MO.isDead() &&
1857 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1858 // There exists a super-register that's marked dead.
1859 if (RegInfo->isSuperRegister(Reg, MOReg))
1861 if (RegInfo->isSubRegister(Reg, MOReg))
1862 DeadOps.push_back(i);
1866 // Trim unneeded dead operands.
1867 while (!DeadOps.empty()) {
1868 unsigned OpIdx = DeadOps.back();
1869 if (getOperand(OpIdx).isImplicit() &&
1870 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1871 RemoveOperand(OpIdx);
1873 getOperand(OpIdx).setIsDead(false);
1877 // If not found, this means an alias of one of the operands is dead. Add a
1878 // new implicit operand if required.
1879 if (Found || !AddIfNotFound)
1882 addOperand(MachineOperand::CreateReg(Reg,
1890 void MachineInstr::clearRegisterDeads(unsigned Reg) {
1891 for (MachineOperand &MO : operands()) {
1892 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1894 MO.setIsDead(false);
1898 void MachineInstr::setRegisterDefReadUndef(unsigned Reg, bool IsUndef) {
1899 for (MachineOperand &MO : operands()) {
1900 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
1902 MO.setIsUndef(IsUndef);
1906 void MachineInstr::addRegisterDefined(unsigned Reg,
1907 const TargetRegisterInfo *RegInfo) {
1908 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1909 MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo);
1913 for (const MachineOperand &MO : operands()) {
1914 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1915 MO.getSubReg() == 0)
1919 addOperand(MachineOperand::CreateReg(Reg,
1924 void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1925 const TargetRegisterInfo &TRI) {
1926 bool HasRegMask = false;
1927 for (MachineOperand &MO : operands()) {
1928 if (MO.isRegMask()) {
1932 if (!MO.isReg() || !MO.isDef()) continue;
1933 unsigned Reg = MO.getReg();
1934 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1935 // If there are no uses, including partial uses, the def is dead.
1936 if (llvm::none_of(UsedRegs,
1937 [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); }))
1941 // This is a call with a register mask operand.
1942 // Mask clobbers are always dead, so add defs for the non-dead defines.
1944 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1946 addRegisterDefined(*I, &TRI);
1950 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1951 // Build up a buffer of hash code components.
1952 SmallVector<size_t, 8> HashComponents;
1953 HashComponents.reserve(MI->getNumOperands() + 1);
1954 HashComponents.push_back(MI->getOpcode());
1955 for (const MachineOperand &MO : MI->operands()) {
1956 if (MO.isReg() && MO.isDef() &&
1957 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1958 continue; // Skip virtual register defs.
1960 HashComponents.push_back(hash_value(MO));
1962 return hash_combine_range(HashComponents.begin(), HashComponents.end());
1965 void MachineInstr::emitError(StringRef Msg) const {
1966 // Find the source location cookie.
1967 unsigned LocCookie = 0;
1968 const MDNode *LocMD = nullptr;
1969 for (unsigned i = getNumOperands(); i != 0; --i) {
1970 if (getOperand(i-1).isMetadata() &&
1971 (LocMD = getOperand(i-1).getMetadata()) &&
1972 LocMD->getNumOperands() != 0) {
1973 if (const ConstantInt *CI =
1974 mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
1975 LocCookie = CI->getZExtValue();
1981 if (const MachineBasicBlock *MBB = getParent())
1982 if (const MachineFunction *MF = MBB->getParent())
1983 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1984 report_fatal_error(Msg);
1987 MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
1988 const MCInstrDesc &MCID, bool IsIndirect,
1989 unsigned Reg, const MDNode *Variable,
1990 const MDNode *Expr) {
1991 assert(isa<DILocalVariable>(Variable) && "not a variable");
1992 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
1993 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
1994 "Expected inlined-at fields to agree");
1995 auto MIB = BuildMI(MF, DL, MCID).addReg(Reg, RegState::Debug);
1999 MIB.addReg(0U, RegState::Debug);
2000 return MIB.addMetadata(Variable).addMetadata(Expr);
2003 MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2004 const MCInstrDesc &MCID, bool IsIndirect,
2005 MachineOperand &MO, const MDNode *Variable,
2006 const MDNode *Expr) {
2007 assert(isa<DILocalVariable>(Variable) && "not a variable");
2008 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2009 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2010 "Expected inlined-at fields to agree");
2012 return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
2014 auto MIB = BuildMI(MF, DL, MCID).add(MO);
2018 MIB.addReg(0U, RegState::Debug);
2019 return MIB.addMetadata(Variable).addMetadata(Expr);
2022 MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2023 MachineBasicBlock::iterator I,
2024 const DebugLoc &DL, const MCInstrDesc &MCID,
2025 bool IsIndirect, unsigned Reg,
2026 const MDNode *Variable, const MDNode *Expr) {
2027 MachineFunction &MF = *BB.getParent();
2028 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2030 return MachineInstrBuilder(MF, MI);
2033 MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2034 MachineBasicBlock::iterator I,
2035 const DebugLoc &DL, const MCInstrDesc &MCID,
2036 bool IsIndirect, MachineOperand &MO,
2037 const MDNode *Variable, const MDNode *Expr) {
2038 MachineFunction &MF = *BB.getParent();
2039 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
2041 return MachineInstrBuilder(MF, *MI);
2044 /// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2045 /// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2046 static const DIExpression *computeExprForSpill(const MachineInstr &MI) {
2047 assert(MI.getOperand(0).isReg() && "can't spill non-register");
2048 assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
2049 "Expected inlined-at fields to agree");
2051 const DIExpression *Expr = MI.getDebugExpression();
2052 if (MI.isIndirectDebugValue()) {
2053 assert(MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset");
2054 Expr = DIExpression::prepend(Expr, DIExpression::WithDeref);
2059 MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
2060 MachineBasicBlock::iterator I,
2061 const MachineInstr &Orig,
2063 const DIExpression *Expr = computeExprForSpill(Orig);
2064 return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc())
2065 .addFrameIndex(FrameIndex)
2067 .addMetadata(Orig.getDebugVariable())
2071 void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex) {
2072 const DIExpression *Expr = computeExprForSpill(Orig);
2073 Orig.getOperand(0).ChangeToFrameIndex(FrameIndex);
2074 Orig.getOperand(1).ChangeToImmediate(0U);
2075 Orig.getOperand(3).setMetadata(Expr);
2078 void MachineInstr::collectDebugValues(
2079 SmallVectorImpl<MachineInstr *> &DbgValues) {
2080 MachineInstr &MI = *this;
2081 if (!MI.getOperand(0).isReg())
2084 MachineBasicBlock::iterator DI = MI; ++DI;
2085 for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2087 if (!DI->isDebugValue())
2089 if (DI->getOperand(0).isReg() &&
2090 DI->getOperand(0).getReg() == MI.getOperand(0).getReg())
2091 DbgValues.push_back(&*DI);
2095 void MachineInstr::changeDebugValuesDefReg(unsigned Reg) {
2096 // Collect matching debug values.
2097 SmallVector<MachineInstr *, 2> DbgValues;
2098 collectDebugValues(DbgValues);
2100 // Propagate Reg to debug value instructions.
2101 for (auto *DBI : DbgValues)
2102 DBI->getOperand(0).setReg(Reg);