1 //===-- lib/CodeGen/MachineInstrBundle.cpp --------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/CodeGen/MachineInstrBundle.h"
11 #include "llvm/ADT/SmallSet.h"
12 #include "llvm/ADT/SmallVector.h"
13 #include "llvm/CodeGen/MachineFunctionPass.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/CodeGen/TargetInstrInfo.h"
17 #include "llvm/CodeGen/TargetRegisterInfo.h"
18 #include "llvm/CodeGen/TargetSubtargetInfo.h"
19 #include "llvm/Target/TargetMachine.h"
24 class UnpackMachineBundles : public MachineFunctionPass {
26 static char ID; // Pass identification
28 std::function<bool(const MachineFunction &)> Ftor = nullptr)
29 : MachineFunctionPass(ID), PredicateFtor(std::move(Ftor)) {
30 initializeUnpackMachineBundlesPass(*PassRegistry::getPassRegistry());
33 bool runOnMachineFunction(MachineFunction &MF) override;
36 std::function<bool(const MachineFunction &)> PredicateFtor;
38 } // end anonymous namespace
40 char UnpackMachineBundles::ID = 0;
41 char &llvm::UnpackMachineBundlesID = UnpackMachineBundles::ID;
42 INITIALIZE_PASS(UnpackMachineBundles, "unpack-mi-bundles",
43 "Unpack machine instruction bundles", false, false)
45 bool UnpackMachineBundles::runOnMachineFunction(MachineFunction &MF) {
46 if (PredicateFtor && !PredicateFtor(MF))
50 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
51 MachineBasicBlock *MBB = &*I;
53 for (MachineBasicBlock::instr_iterator MII = MBB->instr_begin(),
54 MIE = MBB->instr_end(); MII != MIE; ) {
55 MachineInstr *MI = &*MII;
57 // Remove BUNDLE instruction and the InsideBundle flags from bundled
60 while (++MII != MIE && MII->isBundledWithPred()) {
61 MII->unbundleFromPred();
62 for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
63 MachineOperand &MO = MII->getOperand(i);
64 if (MO.isReg() && MO.isInternalRead())
65 MO.setIsInternalRead(false);
68 MI->eraseFromParent();
82 llvm::createUnpackMachineBundles(
83 std::function<bool(const MachineFunction &)> Ftor) {
84 return new UnpackMachineBundles(std::move(Ftor));
88 class FinalizeMachineBundles : public MachineFunctionPass {
90 static char ID; // Pass identification
91 FinalizeMachineBundles() : MachineFunctionPass(ID) {
92 initializeFinalizeMachineBundlesPass(*PassRegistry::getPassRegistry());
95 bool runOnMachineFunction(MachineFunction &MF) override;
97 } // end anonymous namespace
99 char FinalizeMachineBundles::ID = 0;
100 char &llvm::FinalizeMachineBundlesID = FinalizeMachineBundles::ID;
101 INITIALIZE_PASS(FinalizeMachineBundles, "finalize-mi-bundles",
102 "Finalize machine instruction bundles", false, false)
104 bool FinalizeMachineBundles::runOnMachineFunction(MachineFunction &MF) {
105 return llvm::finalizeBundles(MF);
109 /// finalizeBundle - Finalize a machine instruction bundle which includes
110 /// a sequence of instructions starting from FirstMI to LastMI (exclusive).
111 /// This routine adds a BUNDLE instruction to represent the bundle, it adds
112 /// IsInternalRead markers to MachineOperands which are defined inside the
113 /// bundle, and it copies externally visible defs and uses to the BUNDLE
115 void llvm::finalizeBundle(MachineBasicBlock &MBB,
116 MachineBasicBlock::instr_iterator FirstMI,
117 MachineBasicBlock::instr_iterator LastMI) {
118 assert(FirstMI != LastMI && "Empty bundle?");
119 MIBundleBuilder Bundle(MBB, FirstMI, LastMI);
121 MachineFunction &MF = *MBB.getParent();
122 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
123 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
125 MachineInstrBuilder MIB =
126 BuildMI(MF, FirstMI->getDebugLoc(), TII->get(TargetOpcode::BUNDLE));
129 SmallVector<unsigned, 32> LocalDefs;
130 SmallSet<unsigned, 32> LocalDefSet;
131 SmallSet<unsigned, 8> DeadDefSet;
132 SmallSet<unsigned, 16> KilledDefSet;
133 SmallVector<unsigned, 8> ExternUses;
134 SmallSet<unsigned, 8> ExternUseSet;
135 SmallSet<unsigned, 8> KilledUseSet;
136 SmallSet<unsigned, 8> UndefUseSet;
137 SmallVector<MachineOperand*, 4> Defs;
138 for (; FirstMI != LastMI; ++FirstMI) {
139 for (unsigned i = 0, e = FirstMI->getNumOperands(); i != e; ++i) {
140 MachineOperand &MO = FirstMI->getOperand(i);
148 unsigned Reg = MO.getReg();
151 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
152 if (LocalDefSet.count(Reg)) {
153 MO.setIsInternalRead();
155 // Internal def is now killed.
156 KilledDefSet.insert(Reg);
158 if (ExternUseSet.insert(Reg).second) {
159 ExternUses.push_back(Reg);
161 UndefUseSet.insert(Reg);
164 // External def is now killed.
165 KilledUseSet.insert(Reg);
169 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
170 MachineOperand &MO = *Defs[i];
171 unsigned Reg = MO.getReg();
175 if (LocalDefSet.insert(Reg).second) {
176 LocalDefs.push_back(Reg);
178 DeadDefSet.insert(Reg);
181 // Re-defined inside the bundle, it's no longer killed.
182 KilledDefSet.erase(Reg);
184 // Previously defined but dead.
185 DeadDefSet.erase(Reg);
189 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
190 unsigned SubReg = *SubRegs;
191 if (LocalDefSet.insert(SubReg).second)
192 LocalDefs.push_back(SubReg);
200 SmallSet<unsigned, 32> Added;
201 for (unsigned i = 0, e = LocalDefs.size(); i != e; ++i) {
202 unsigned Reg = LocalDefs[i];
203 if (Added.insert(Reg).second) {
204 // If it's not live beyond end of the bundle, mark it dead.
205 bool isDead = DeadDefSet.count(Reg) || KilledDefSet.count(Reg);
206 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
207 getImplRegState(true));
211 for (unsigned i = 0, e = ExternUses.size(); i != e; ++i) {
212 unsigned Reg = ExternUses[i];
213 bool isKill = KilledUseSet.count(Reg);
214 bool isUndef = UndefUseSet.count(Reg);
215 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
216 getImplRegState(true));
220 /// finalizeBundle - Same functionality as the previous finalizeBundle except
221 /// the last instruction in the bundle is not provided as an input. This is
222 /// used in cases where bundles are pre-determined by marking instructions
223 /// with 'InsideBundle' marker. It returns the MBB instruction iterator that
224 /// points to the end of the bundle.
225 MachineBasicBlock::instr_iterator
226 llvm::finalizeBundle(MachineBasicBlock &MBB,
227 MachineBasicBlock::instr_iterator FirstMI) {
228 MachineBasicBlock::instr_iterator E = MBB.instr_end();
229 MachineBasicBlock::instr_iterator LastMI = std::next(FirstMI);
230 while (LastMI != E && LastMI->isInsideBundle())
232 finalizeBundle(MBB, FirstMI, LastMI);
236 /// finalizeBundles - Finalize instruction bundles in the specified
237 /// MachineFunction. Return true if any bundles are finalized.
238 bool llvm::finalizeBundles(MachineFunction &MF) {
239 bool Changed = false;
240 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
241 MachineBasicBlock &MBB = *I;
242 MachineBasicBlock::instr_iterator MII = MBB.instr_begin();
243 MachineBasicBlock::instr_iterator MIE = MBB.instr_end();
246 assert(!MII->isInsideBundle() &&
247 "First instr cannot be inside bundle before finalization!");
249 for (++MII; MII != MIE; ) {
250 if (!MII->isInsideBundle())
253 MII = finalizeBundle(MBB, std::prev(MII));
262 //===----------------------------------------------------------------------===//
263 // MachineOperand iterator
264 //===----------------------------------------------------------------------===//
266 MachineOperandIteratorBase::VirtRegInfo
267 MachineOperandIteratorBase::analyzeVirtReg(unsigned Reg,
268 SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops) {
269 VirtRegInfo RI = { false, false, false };
270 for(; isValid(); ++*this) {
271 MachineOperand &MO = deref();
272 if (!MO.isReg() || MO.getReg() != Reg)
275 // Remember each (MI, OpNo) that refers to Reg.
277 Ops->push_back(std::make_pair(MO.getParent(), getOperandNo()));
279 // Both defs and uses can read virtual registers.
286 // Only defs can write.
289 else if (!RI.Tied && MO.getParent()->isRegTiedToDefOperand(getOperandNo()))
295 MachineOperandIteratorBase::PhysRegInfo
296 MachineOperandIteratorBase::analyzePhysReg(unsigned Reg,
297 const TargetRegisterInfo *TRI) {
298 bool AllDefsDead = true;
299 PhysRegInfo PRI = {false, false, false, false, false, false, false, false};
301 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
302 "analyzePhysReg not given a physical register!");
303 for (; isValid(); ++*this) {
304 MachineOperand &MO = deref();
306 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) {
307 PRI.Clobbered = true;
314 unsigned MOReg = MO.getReg();
315 if (!MOReg || !TargetRegisterInfo::isPhysicalRegister(MOReg))
318 if (!TRI->regsOverlap(MOReg, Reg))
321 bool Covered = TRI->isSuperRegisterEq(Reg, MOReg);
325 PRI.FullyRead = true;
329 } else if (MO.isDef()) {
332 PRI.FullyDefined = true;
339 if (PRI.FullyDefined || PRI.Clobbered)
341 else if (PRI.Defined)
342 PRI.PartialDeadDef = true;