1 //===-- lib/CodeGen/MachineInstrBundle.cpp --------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/CodeGen/MachineInstrBundle.h"
11 #include "llvm/ADT/SmallSet.h"
12 #include "llvm/ADT/SmallVector.h"
13 #include "llvm/CodeGen/MachineFunctionPass.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/TargetRegisterInfo.h"
19 #include "llvm/Target/TargetSubtargetInfo.h"
24 class UnpackMachineBundles : public MachineFunctionPass {
26 static char ID; // Pass identification
27 UnpackMachineBundles(std::function<bool(const Function &)> Ftor = nullptr)
28 : MachineFunctionPass(ID), PredicateFtor(std::move(Ftor)) {
29 initializeUnpackMachineBundlesPass(*PassRegistry::getPassRegistry());
32 bool runOnMachineFunction(MachineFunction &MF) override;
35 std::function<bool(const Function &)> PredicateFtor;
37 } // end anonymous namespace
39 char UnpackMachineBundles::ID = 0;
40 char &llvm::UnpackMachineBundlesID = UnpackMachineBundles::ID;
41 INITIALIZE_PASS(UnpackMachineBundles, "unpack-mi-bundles",
42 "Unpack machine instruction bundles", false, false)
44 bool UnpackMachineBundles::runOnMachineFunction(MachineFunction &MF) {
45 if (PredicateFtor && !PredicateFtor(*MF.getFunction()))
49 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
50 MachineBasicBlock *MBB = &*I;
52 for (MachineBasicBlock::instr_iterator MII = MBB->instr_begin(),
53 MIE = MBB->instr_end(); MII != MIE; ) {
54 MachineInstr *MI = &*MII;
56 // Remove BUNDLE instruction and the InsideBundle flags from bundled
59 while (++MII != MIE && MII->isBundledWithPred()) {
60 MII->unbundleFromPred();
61 for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
62 MachineOperand &MO = MII->getOperand(i);
63 if (MO.isReg() && MO.isInternalRead())
64 MO.setIsInternalRead(false);
67 MI->eraseFromParent();
81 llvm::createUnpackMachineBundles(std::function<bool(const Function &)> Ftor) {
82 return new UnpackMachineBundles(std::move(Ftor));
86 class FinalizeMachineBundles : public MachineFunctionPass {
88 static char ID; // Pass identification
89 FinalizeMachineBundles() : MachineFunctionPass(ID) {
90 initializeFinalizeMachineBundlesPass(*PassRegistry::getPassRegistry());
93 bool runOnMachineFunction(MachineFunction &MF) override;
95 } // end anonymous namespace
97 char FinalizeMachineBundles::ID = 0;
98 char &llvm::FinalizeMachineBundlesID = FinalizeMachineBundles::ID;
99 INITIALIZE_PASS(FinalizeMachineBundles, "finalize-mi-bundles",
100 "Finalize machine instruction bundles", false, false)
102 bool FinalizeMachineBundles::runOnMachineFunction(MachineFunction &MF) {
103 return llvm::finalizeBundles(MF);
107 /// finalizeBundle - Finalize a machine instruction bundle which includes
108 /// a sequence of instructions starting from FirstMI to LastMI (exclusive).
109 /// This routine adds a BUNDLE instruction to represent the bundle, it adds
110 /// IsInternalRead markers to MachineOperands which are defined inside the
111 /// bundle, and it copies externally visible defs and uses to the BUNDLE
113 void llvm::finalizeBundle(MachineBasicBlock &MBB,
114 MachineBasicBlock::instr_iterator FirstMI,
115 MachineBasicBlock::instr_iterator LastMI) {
116 assert(FirstMI != LastMI && "Empty bundle?");
117 MIBundleBuilder Bundle(MBB, FirstMI, LastMI);
119 MachineFunction &MF = *MBB.getParent();
120 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
121 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
123 MachineInstrBuilder MIB =
124 BuildMI(MF, FirstMI->getDebugLoc(), TII->get(TargetOpcode::BUNDLE));
127 SmallVector<unsigned, 32> LocalDefs;
128 SmallSet<unsigned, 32> LocalDefSet;
129 SmallSet<unsigned, 8> DeadDefSet;
130 SmallSet<unsigned, 16> KilledDefSet;
131 SmallVector<unsigned, 8> ExternUses;
132 SmallSet<unsigned, 8> ExternUseSet;
133 SmallSet<unsigned, 8> KilledUseSet;
134 SmallSet<unsigned, 8> UndefUseSet;
135 SmallVector<MachineOperand*, 4> Defs;
136 for (; FirstMI != LastMI; ++FirstMI) {
137 for (unsigned i = 0, e = FirstMI->getNumOperands(); i != e; ++i) {
138 MachineOperand &MO = FirstMI->getOperand(i);
146 unsigned Reg = MO.getReg();
149 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
150 if (LocalDefSet.count(Reg)) {
151 MO.setIsInternalRead();
153 // Internal def is now killed.
154 KilledDefSet.insert(Reg);
156 if (ExternUseSet.insert(Reg).second) {
157 ExternUses.push_back(Reg);
159 UndefUseSet.insert(Reg);
162 // External def is now killed.
163 KilledUseSet.insert(Reg);
167 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
168 MachineOperand &MO = *Defs[i];
169 unsigned Reg = MO.getReg();
173 if (LocalDefSet.insert(Reg).second) {
174 LocalDefs.push_back(Reg);
176 DeadDefSet.insert(Reg);
179 // Re-defined inside the bundle, it's no longer killed.
180 KilledDefSet.erase(Reg);
182 // Previously defined but dead.
183 DeadDefSet.erase(Reg);
187 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
188 unsigned SubReg = *SubRegs;
189 if (LocalDefSet.insert(SubReg).second)
190 LocalDefs.push_back(SubReg);
198 SmallSet<unsigned, 32> Added;
199 for (unsigned i = 0, e = LocalDefs.size(); i != e; ++i) {
200 unsigned Reg = LocalDefs[i];
201 if (Added.insert(Reg).second) {
202 // If it's not live beyond end of the bundle, mark it dead.
203 bool isDead = DeadDefSet.count(Reg) || KilledDefSet.count(Reg);
204 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
205 getImplRegState(true));
209 for (unsigned i = 0, e = ExternUses.size(); i != e; ++i) {
210 unsigned Reg = ExternUses[i];
211 bool isKill = KilledUseSet.count(Reg);
212 bool isUndef = UndefUseSet.count(Reg);
213 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
214 getImplRegState(true));
218 /// finalizeBundle - Same functionality as the previous finalizeBundle except
219 /// the last instruction in the bundle is not provided as an input. This is
220 /// used in cases where bundles are pre-determined by marking instructions
221 /// with 'InsideBundle' marker. It returns the MBB instruction iterator that
222 /// points to the end of the bundle.
223 MachineBasicBlock::instr_iterator
224 llvm::finalizeBundle(MachineBasicBlock &MBB,
225 MachineBasicBlock::instr_iterator FirstMI) {
226 MachineBasicBlock::instr_iterator E = MBB.instr_end();
227 MachineBasicBlock::instr_iterator LastMI = std::next(FirstMI);
228 while (LastMI != E && LastMI->isInsideBundle())
230 finalizeBundle(MBB, FirstMI, LastMI);
234 /// finalizeBundles - Finalize instruction bundles in the specified
235 /// MachineFunction. Return true if any bundles are finalized.
236 bool llvm::finalizeBundles(MachineFunction &MF) {
237 bool Changed = false;
238 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
239 MachineBasicBlock &MBB = *I;
240 MachineBasicBlock::instr_iterator MII = MBB.instr_begin();
241 MachineBasicBlock::instr_iterator MIE = MBB.instr_end();
244 assert(!MII->isInsideBundle() &&
245 "First instr cannot be inside bundle before finalization!");
247 for (++MII; MII != MIE; ) {
248 if (!MII->isInsideBundle())
251 MII = finalizeBundle(MBB, std::prev(MII));
260 //===----------------------------------------------------------------------===//
261 // MachineOperand iterator
262 //===----------------------------------------------------------------------===//
264 MachineOperandIteratorBase::VirtRegInfo
265 MachineOperandIteratorBase::analyzeVirtReg(unsigned Reg,
266 SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops) {
267 VirtRegInfo RI = { false, false, false };
268 for(; isValid(); ++*this) {
269 MachineOperand &MO = deref();
270 if (!MO.isReg() || MO.getReg() != Reg)
273 // Remember each (MI, OpNo) that refers to Reg.
275 Ops->push_back(std::make_pair(MO.getParent(), getOperandNo()));
277 // Both defs and uses can read virtual registers.
284 // Only defs can write.
287 else if (!RI.Tied && MO.getParent()->isRegTiedToDefOperand(getOperandNo()))
293 MachineOperandIteratorBase::PhysRegInfo
294 MachineOperandIteratorBase::analyzePhysReg(unsigned Reg,
295 const TargetRegisterInfo *TRI) {
296 bool AllDefsDead = true;
297 PhysRegInfo PRI = {false, false, false, false, false, false, false, false};
299 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
300 "analyzePhysReg not given a physical register!");
301 for (; isValid(); ++*this) {
302 MachineOperand &MO = deref();
304 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) {
305 PRI.Clobbered = true;
312 unsigned MOReg = MO.getReg();
313 if (!MOReg || !TargetRegisterInfo::isPhysicalRegister(MOReg))
316 if (!TRI->regsOverlap(MOReg, Reg))
319 bool Covered = TRI->isSuperRegisterEq(Reg, MOReg);
323 PRI.FullyRead = true;
327 } else if (MO.isDef()) {
330 PRI.FullyDefined = true;
337 if (PRI.FullyDefined || PRI.Clobbered)
339 else if (PRI.Defined)
340 PRI.PartialDeadDef = true;