1 //===- MachineLICM.cpp - Machine Loop Invariant Code Motion Pass ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs loop invariant code motion on machine instructions. We
11 // attempt to remove as much code from the body of a loop as possible.
13 // This pass is not intended to be a replacement or a complete alternative
14 // for the LLVM-IR-level LICM pass. It is only designed to hoist simple
15 // constructs that are not exposed before lowering and instruction selection.
17 //===----------------------------------------------------------------------===//
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineDominators.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineInstr.h"
32 #include "llvm/CodeGen/MachineLoopInfo.h"
33 #include "llvm/CodeGen/MachineMemOperand.h"
34 #include "llvm/CodeGen/MachineOperand.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/CodeGen/TargetInstrInfo.h"
38 #include "llvm/CodeGen/TargetLowering.h"
39 #include "llvm/CodeGen/TargetRegisterInfo.h"
40 #include "llvm/CodeGen/TargetSchedule.h"
41 #include "llvm/CodeGen/TargetSubtargetInfo.h"
42 #include "llvm/IR/DebugLoc.h"
43 #include "llvm/MC/MCInstrDesc.h"
44 #include "llvm/MC/MCRegisterInfo.h"
45 #include "llvm/Pass.h"
46 #include "llvm/Support/Casting.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/raw_ostream.h"
57 #define DEBUG_TYPE "machinelicm"
60 AvoidSpeculation("avoid-speculation",
61 cl::desc("MachineLICM should avoid speculation"),
62 cl::init(true), cl::Hidden);
65 HoistCheapInsts("hoist-cheap-insts",
66 cl::desc("MachineLICM should hoist even cheap instructions"),
67 cl::init(false), cl::Hidden);
70 SinkInstsToAvoidSpills("sink-insts-to-avoid-spills",
71 cl::desc("MachineLICM should sink instructions into "
72 "loops to avoid register spills"),
73 cl::init(false), cl::Hidden);
75 HoistConstStores("hoist-const-stores",
76 cl::desc("Hoist invariant stores"),
77 cl::init(true), cl::Hidden);
80 "Number of machine instructions hoisted out of loops");
82 "Number of instructions hoisted in low reg pressure situation");
83 STATISTIC(NumHighLatency,
84 "Number of high latency instructions hoisted");
86 "Number of hoisted machine instructions CSEed");
87 STATISTIC(NumPostRAHoisted,
88 "Number of machine instructions hoisted out of loops post regalloc");
89 STATISTIC(NumStoreConst,
90 "Number of stores of const phys reg hoisted out of loops");
94 class MachineLICMBase : public MachineFunctionPass {
95 const TargetInstrInfo *TII;
96 const TargetLoweringBase *TLI;
97 const TargetRegisterInfo *TRI;
98 const MachineFrameInfo *MFI;
99 MachineRegisterInfo *MRI;
100 TargetSchedModel SchedModel;
103 // Various analyses that we use...
104 AliasAnalysis *AA; // Alias analysis info.
105 MachineLoopInfo *MLI; // Current MachineLoopInfo
106 MachineDominatorTree *DT; // Machine dominator tree for the cur loop
108 // State that is updated as we process loops
109 bool Changed; // True if a loop is changed.
110 bool FirstInLoop; // True if it's the first LICM in the loop.
111 MachineLoop *CurLoop; // The current loop we are working on.
112 MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
114 // Exit blocks for CurLoop.
115 SmallVector<MachineBasicBlock *, 8> ExitBlocks;
117 bool isExitBlock(const MachineBasicBlock *MBB) const {
118 return is_contained(ExitBlocks, MBB);
121 // Track 'estimated' register pressure.
122 SmallSet<unsigned, 32> RegSeen;
123 SmallVector<unsigned, 8> RegPressure;
125 // Register pressure "limit" per register pressure set. If the pressure
126 // is higher than the limit, then it's considered high.
127 SmallVector<unsigned, 8> RegLimit;
129 // Register pressure on path leading from loop preheader to current BB.
130 SmallVector<SmallVector<unsigned, 8>, 16> BackTrace;
132 // For each opcode, keep a list of potential CSE instructions.
133 DenseMap<unsigned, std::vector<const MachineInstr *>> CSEMap;
141 // If a MBB does not dominate loop exiting blocks then it may not safe
142 // to hoist loads from this block.
143 // Tri-state: 0 - false, 1 - true, 2 - unknown
144 unsigned SpeculationState;
147 MachineLICMBase(char &PassID, bool PreRegAlloc)
148 : MachineFunctionPass(PassID), PreRegAlloc(PreRegAlloc) {}
150 bool runOnMachineFunction(MachineFunction &MF) override;
152 void getAnalysisUsage(AnalysisUsage &AU) const override {
153 AU.addRequired<MachineLoopInfo>();
154 AU.addRequired<MachineDominatorTree>();
155 AU.addRequired<AAResultsWrapperPass>();
156 AU.addPreserved<MachineLoopInfo>();
157 AU.addPreserved<MachineDominatorTree>();
158 MachineFunctionPass::getAnalysisUsage(AU);
161 void releaseMemory() override {
170 /// Keep track of information about hoisting candidates.
171 struct CandidateInfo {
176 CandidateInfo(MachineInstr *mi, unsigned def, int fi)
177 : MI(mi), Def(def), FI(fi) {}
180 void HoistRegionPostRA();
182 void HoistPostRA(MachineInstr *MI, unsigned Def);
184 void ProcessMI(MachineInstr *MI, BitVector &PhysRegDefs,
185 BitVector &PhysRegClobbers, SmallSet<int, 32> &StoredFIs,
186 SmallVectorImpl<CandidateInfo> &Candidates);
188 void AddToLiveIns(unsigned Reg);
190 bool IsLICMCandidate(MachineInstr &I);
192 bool IsLoopInvariantInst(MachineInstr &I);
194 bool HasLoopPHIUse(const MachineInstr *MI) const;
196 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
199 bool IsCheapInstruction(MachineInstr &MI) const;
201 bool CanCauseHighRegPressure(const DenseMap<unsigned, int> &Cost,
204 void UpdateBackTraceRegPressure(const MachineInstr *MI);
206 bool IsProfitableToHoist(MachineInstr &MI);
208 bool IsGuaranteedToExecute(MachineBasicBlock *BB);
210 void EnterScope(MachineBasicBlock *MBB);
212 void ExitScope(MachineBasicBlock *MBB);
214 void ExitScopeIfDone(
215 MachineDomTreeNode *Node,
216 DenseMap<MachineDomTreeNode *, unsigned> &OpenChildren,
217 DenseMap<MachineDomTreeNode *, MachineDomTreeNode *> &ParentMap);
219 void HoistOutOfLoop(MachineDomTreeNode *HeaderN);
221 void HoistRegion(MachineDomTreeNode *N, bool IsHeader);
225 void InitRegPressure(MachineBasicBlock *BB);
227 DenseMap<unsigned, int> calcRegisterCost(const MachineInstr *MI,
229 bool ConsiderUnseenAsDef);
231 void UpdateRegPressure(const MachineInstr *MI,
232 bool ConsiderUnseenAsDef = false);
234 MachineInstr *ExtractHoistableLoad(MachineInstr *MI);
237 LookForDuplicate(const MachineInstr *MI,
238 std::vector<const MachineInstr *> &PrevMIs);
242 DenseMap<unsigned, std::vector<const MachineInstr *>>::iterator &CI);
244 bool MayCSE(MachineInstr *MI);
246 bool Hoist(MachineInstr *MI, MachineBasicBlock *Preheader);
248 void InitCSEMap(MachineBasicBlock *BB);
250 MachineBasicBlock *getCurPreheader();
253 class MachineLICM : public MachineLICMBase {
256 MachineLICM() : MachineLICMBase(ID, false) {
257 initializeMachineLICMPass(*PassRegistry::getPassRegistry());
261 class EarlyMachineLICM : public MachineLICMBase {
264 EarlyMachineLICM() : MachineLICMBase(ID, true) {
265 initializeEarlyMachineLICMPass(*PassRegistry::getPassRegistry());
269 } // end anonymous namespace
271 char MachineLICM::ID;
272 char EarlyMachineLICM::ID;
274 char &llvm::MachineLICMID = MachineLICM::ID;
275 char &llvm::EarlyMachineLICMID = EarlyMachineLICM::ID;
277 INITIALIZE_PASS_BEGIN(MachineLICM, DEBUG_TYPE,
278 "Machine Loop Invariant Code Motion", false, false)
279 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
280 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
281 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
282 INITIALIZE_PASS_END(MachineLICM, DEBUG_TYPE,
283 "Machine Loop Invariant Code Motion", false, false)
285 INITIALIZE_PASS_BEGIN(EarlyMachineLICM, "early-machinelicm",
286 "Early Machine Loop Invariant Code Motion", false, false)
287 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
288 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
289 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
290 INITIALIZE_PASS_END(EarlyMachineLICM, "early-machinelicm",
291 "Early Machine Loop Invariant Code Motion", false, false)
293 /// Test if the given loop is the outer-most loop that has a unique predecessor.
294 static bool LoopIsOuterMostWithPredecessor(MachineLoop *CurLoop) {
295 // Check whether this loop even has a unique predecessor.
296 if (!CurLoop->getLoopPredecessor())
298 // Ok, now check to see if any of its outer loops do.
299 for (MachineLoop *L = CurLoop->getParentLoop(); L; L = L->getParentLoop())
300 if (L->getLoopPredecessor())
302 // None of them did, so this is the outermost with a unique predecessor.
306 bool MachineLICMBase::runOnMachineFunction(MachineFunction &MF) {
307 if (skipFunction(MF.getFunction()))
310 Changed = FirstInLoop = false;
311 const TargetSubtargetInfo &ST = MF.getSubtarget();
312 TII = ST.getInstrInfo();
313 TLI = ST.getTargetLowering();
314 TRI = ST.getRegisterInfo();
315 MFI = &MF.getFrameInfo();
316 MRI = &MF.getRegInfo();
317 SchedModel.init(&ST);
319 PreRegAlloc = MRI->isSSA();
322 LLVM_DEBUG(dbgs() << "******** Pre-regalloc Machine LICM: ");
324 LLVM_DEBUG(dbgs() << "******** Post-regalloc Machine LICM: ");
325 LLVM_DEBUG(dbgs() << MF.getName() << " ********\n");
328 // Estimate register pressure during pre-regalloc pass.
329 unsigned NumRPS = TRI->getNumRegPressureSets();
330 RegPressure.resize(NumRPS);
331 std::fill(RegPressure.begin(), RegPressure.end(), 0);
332 RegLimit.resize(NumRPS);
333 for (unsigned i = 0, e = NumRPS; i != e; ++i)
334 RegLimit[i] = TRI->getRegPressureSetLimit(MF, i);
337 // Get our Loop information...
338 MLI = &getAnalysis<MachineLoopInfo>();
339 DT = &getAnalysis<MachineDominatorTree>();
340 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
342 SmallVector<MachineLoop *, 8> Worklist(MLI->begin(), MLI->end());
343 while (!Worklist.empty()) {
344 CurLoop = Worklist.pop_back_val();
345 CurPreheader = nullptr;
348 // If this is done before regalloc, only visit outer-most preheader-sporting
350 if (PreRegAlloc && !LoopIsOuterMostWithPredecessor(CurLoop)) {
351 Worklist.append(CurLoop->begin(), CurLoop->end());
355 CurLoop->getExitBlocks(ExitBlocks);
360 // CSEMap is initialized for loop header when the first instruction is
362 MachineDomTreeNode *N = DT->getNode(CurLoop->getHeader());
367 if (SinkInstsToAvoidSpills)
375 /// Return true if instruction stores to the specified frame.
376 static bool InstructionStoresToFI(const MachineInstr *MI, int FI) {
377 // Check mayStore before memory operands so that e.g. DBG_VALUEs will return
378 // true since they have no memory operands.
381 // If we lost memory operands, conservatively assume that the instruction
382 // writes to all slots.
383 if (MI->memoperands_empty())
385 for (const MachineMemOperand *MemOp : MI->memoperands()) {
386 if (!MemOp->isStore() || !MemOp->getPseudoValue())
388 if (const FixedStackPseudoSourceValue *Value =
389 dyn_cast<FixedStackPseudoSourceValue>(MemOp->getPseudoValue())) {
390 if (Value->getFrameIndex() == FI)
397 /// Examine the instruction for potentai LICM candidate. Also
398 /// gather register def and frame object update information.
399 void MachineLICMBase::ProcessMI(MachineInstr *MI,
400 BitVector &PhysRegDefs,
401 BitVector &PhysRegClobbers,
402 SmallSet<int, 32> &StoredFIs,
403 SmallVectorImpl<CandidateInfo> &Candidates) {
404 bool RuledOut = false;
405 bool HasNonInvariantUse = false;
407 for (const MachineOperand &MO : MI->operands()) {
409 // Remember if the instruction stores to the frame index.
410 int FI = MO.getIndex();
411 if (!StoredFIs.count(FI) &&
412 MFI->isSpillSlotObjectIndex(FI) &&
413 InstructionStoresToFI(MI, FI))
414 StoredFIs.insert(FI);
415 HasNonInvariantUse = true;
419 // We can't hoist an instruction defining a physreg that is clobbered in
421 if (MO.isRegMask()) {
422 PhysRegClobbers.setBitsNotInMask(MO.getRegMask());
428 unsigned Reg = MO.getReg();
431 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
432 "Not expecting virtual register!");
435 if (Reg && (PhysRegDefs.test(Reg) || PhysRegClobbers.test(Reg)))
436 // If it's using a non-loop-invariant register, then it's obviously not
438 HasNonInvariantUse = true;
442 if (MO.isImplicit()) {
443 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
444 PhysRegClobbers.set(*AI);
446 // Non-dead implicit def? This cannot be hoisted.
448 // No need to check if a dead implicit def is also defined by
449 // another instruction.
453 // FIXME: For now, avoid instructions with multiple defs, unless
454 // it's a dead implicit def.
460 // If we have already seen another instruction that defines the same
461 // register, then this is not safe. Two defs is indicated by setting a
462 // PhysRegClobbers bit.
463 for (MCRegAliasIterator AS(Reg, TRI, true); AS.isValid(); ++AS) {
464 if (PhysRegDefs.test(*AS))
465 PhysRegClobbers.set(*AS);
466 PhysRegDefs.set(*AS);
468 if (PhysRegClobbers.test(Reg))
469 // MI defined register is seen defined by another instruction in
470 // the loop, it cannot be a LICM candidate.
474 // Only consider reloads for now and remats which do not have register
475 // operands. FIXME: Consider unfold load folding instructions.
476 if (Def && !RuledOut) {
477 int FI = std::numeric_limits<int>::min();
478 if ((!HasNonInvariantUse && IsLICMCandidate(*MI)) ||
479 (TII->isLoadFromStackSlot(*MI, FI) && MFI->isSpillSlotObjectIndex(FI)))
480 Candidates.push_back(CandidateInfo(MI, Def, FI));
484 /// Walk the specified region of the CFG and hoist loop invariants out to the
486 void MachineLICMBase::HoistRegionPostRA() {
487 MachineBasicBlock *Preheader = getCurPreheader();
491 unsigned NumRegs = TRI->getNumRegs();
492 BitVector PhysRegDefs(NumRegs); // Regs defined once in the loop.
493 BitVector PhysRegClobbers(NumRegs); // Regs defined more than once.
495 SmallVector<CandidateInfo, 32> Candidates;
496 SmallSet<int, 32> StoredFIs;
498 // Walk the entire region, count number of defs for each register, and
499 // collect potential LICM candidates.
500 const std::vector<MachineBasicBlock *> &Blocks = CurLoop->getBlocks();
501 for (MachineBasicBlock *BB : Blocks) {
502 // If the header of the loop containing this basic block is a landing pad,
503 // then don't try to hoist instructions out of this loop.
504 const MachineLoop *ML = MLI->getLoopFor(BB);
505 if (ML && ML->getHeader()->isEHPad()) continue;
507 // Conservatively treat live-in's as an external def.
508 // FIXME: That means a reload that're reused in successor block(s) will not
510 for (const auto &LI : BB->liveins()) {
511 for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI)
512 PhysRegDefs.set(*AI);
515 SpeculationState = SpeculateUnknown;
516 for (MachineInstr &MI : *BB)
517 ProcessMI(&MI, PhysRegDefs, PhysRegClobbers, StoredFIs, Candidates);
520 // Gather the registers read / clobbered by the terminator.
521 BitVector TermRegs(NumRegs);
522 MachineBasicBlock::iterator TI = Preheader->getFirstTerminator();
523 if (TI != Preheader->end()) {
524 for (const MachineOperand &MO : TI->operands()) {
527 unsigned Reg = MO.getReg();
530 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
535 // Now evaluate whether the potential candidates qualify.
536 // 1. Check if the candidate defined register is defined by another
537 // instruction in the loop.
538 // 2. If the candidate is a load from stack slot (always true for now),
539 // check if the slot is stored anywhere in the loop.
540 // 3. Make sure candidate def should not clobber
541 // registers read by the terminator. Similarly its def should not be
542 // clobbered by the terminator.
543 for (CandidateInfo &Candidate : Candidates) {
544 if (Candidate.FI != std::numeric_limits<int>::min() &&
545 StoredFIs.count(Candidate.FI))
548 unsigned Def = Candidate.Def;
549 if (!PhysRegClobbers.test(Def) && !TermRegs.test(Def)) {
551 MachineInstr *MI = Candidate.MI;
552 for (const MachineOperand &MO : MI->operands()) {
553 if (!MO.isReg() || MO.isDef() || !MO.getReg())
555 unsigned Reg = MO.getReg();
556 if (PhysRegDefs.test(Reg) ||
557 PhysRegClobbers.test(Reg)) {
558 // If it's using a non-loop-invariant register, then it's obviously
559 // not safe to hoist.
565 HoistPostRA(MI, Candidate.Def);
570 /// Add register 'Reg' to the livein sets of BBs in the current loop, and make
571 /// sure it is not killed by any instructions in the loop.
572 void MachineLICMBase::AddToLiveIns(unsigned Reg) {
573 const std::vector<MachineBasicBlock *> &Blocks = CurLoop->getBlocks();
574 for (MachineBasicBlock *BB : Blocks) {
575 if (!BB->isLiveIn(Reg))
577 for (MachineInstr &MI : *BB) {
578 for (MachineOperand &MO : MI.operands()) {
579 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue;
580 if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg()))
587 /// When an instruction is found to only use loop invariant operands that is
588 /// safe to hoist, this instruction is called to do the dirty work.
589 void MachineLICMBase::HoistPostRA(MachineInstr *MI, unsigned Def) {
590 MachineBasicBlock *Preheader = getCurPreheader();
592 // Now move the instructions to the predecessor, inserting it before any
593 // terminator instructions.
594 LLVM_DEBUG(dbgs() << "Hoisting to " << printMBBReference(*Preheader)
595 << " from " << printMBBReference(*MI->getParent()) << ": "
598 // Splice the instruction to the preheader.
599 MachineBasicBlock *MBB = MI->getParent();
600 Preheader->splice(Preheader->getFirstTerminator(), MBB, MI);
602 // Add register to livein list to all the BBs in the current loop since a
603 // loop invariant must be kept live throughout the whole loop. This is
604 // important to ensure later passes do not scavenge the def register.
611 /// Check if this mbb is guaranteed to execute. If not then a load from this mbb
612 /// may not be safe to hoist.
613 bool MachineLICMBase::IsGuaranteedToExecute(MachineBasicBlock *BB) {
614 if (SpeculationState != SpeculateUnknown)
615 return SpeculationState == SpeculateFalse;
617 if (BB != CurLoop->getHeader()) {
618 // Check loop exiting blocks.
619 SmallVector<MachineBasicBlock*, 8> CurrentLoopExitingBlocks;
620 CurLoop->getExitingBlocks(CurrentLoopExitingBlocks);
621 for (MachineBasicBlock *CurrentLoopExitingBlock : CurrentLoopExitingBlocks)
622 if (!DT->dominates(BB, CurrentLoopExitingBlock)) {
623 SpeculationState = SpeculateTrue;
628 SpeculationState = SpeculateFalse;
632 void MachineLICMBase::EnterScope(MachineBasicBlock *MBB) {
633 LLVM_DEBUG(dbgs() << "Entering " << printMBBReference(*MBB) << '\n');
635 // Remember livein register pressure.
636 BackTrace.push_back(RegPressure);
639 void MachineLICMBase::ExitScope(MachineBasicBlock *MBB) {
640 LLVM_DEBUG(dbgs() << "Exiting " << printMBBReference(*MBB) << '\n');
641 BackTrace.pop_back();
644 /// Destroy scope for the MBB that corresponds to the given dominator tree node
645 /// if its a leaf or all of its children are done. Walk up the dominator tree to
646 /// destroy ancestors which are now done.
647 void MachineLICMBase::ExitScopeIfDone(MachineDomTreeNode *Node,
648 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren,
649 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> &ParentMap) {
650 if (OpenChildren[Node])
654 ExitScope(Node->getBlock());
656 // Now traverse upwards to pop ancestors whose offsprings are all done.
657 while (MachineDomTreeNode *Parent = ParentMap[Node]) {
658 unsigned Left = --OpenChildren[Parent];
661 ExitScope(Parent->getBlock());
666 /// Walk the specified loop in the CFG (defined by all blocks dominated by the
667 /// specified header block, and that are in the current loop) in depth first
668 /// order w.r.t the DominatorTree. This allows us to visit definitions before
669 /// uses, allowing us to hoist a loop body in one pass without iteration.
670 void MachineLICMBase::HoistOutOfLoop(MachineDomTreeNode *HeaderN) {
671 MachineBasicBlock *Preheader = getCurPreheader();
675 SmallVector<MachineDomTreeNode*, 32> Scopes;
676 SmallVector<MachineDomTreeNode*, 8> WorkList;
677 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> ParentMap;
678 DenseMap<MachineDomTreeNode*, unsigned> OpenChildren;
680 // Perform a DFS walk to determine the order of visit.
681 WorkList.push_back(HeaderN);
682 while (!WorkList.empty()) {
683 MachineDomTreeNode *Node = WorkList.pop_back_val();
684 assert(Node && "Null dominator tree node?");
685 MachineBasicBlock *BB = Node->getBlock();
687 // If the header of the loop containing this basic block is a landing pad,
688 // then don't try to hoist instructions out of this loop.
689 const MachineLoop *ML = MLI->getLoopFor(BB);
690 if (ML && ML->getHeader()->isEHPad())
693 // If this subregion is not in the top level loop at all, exit.
694 if (!CurLoop->contains(BB))
697 Scopes.push_back(Node);
698 const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
699 unsigned NumChildren = Children.size();
701 // Don't hoist things out of a large switch statement. This often causes
702 // code to be hoisted that wasn't going to be executed, and increases
703 // register pressure in a situation where it's likely to matter.
704 if (BB->succ_size() >= 25)
707 OpenChildren[Node] = NumChildren;
708 // Add children in reverse order as then the next popped worklist node is
709 // the first child of this node. This means we ultimately traverse the
710 // DOM tree in exactly the same order as if we'd recursed.
711 for (int i = (int)NumChildren-1; i >= 0; --i) {
712 MachineDomTreeNode *Child = Children[i];
713 ParentMap[Child] = Node;
714 WorkList.push_back(Child);
718 if (Scopes.size() == 0)
721 // Compute registers which are livein into the loop headers.
724 InitRegPressure(Preheader);
727 for (MachineDomTreeNode *Node : Scopes) {
728 MachineBasicBlock *MBB = Node->getBlock();
733 SpeculationState = SpeculateUnknown;
734 for (MachineBasicBlock::iterator
735 MII = MBB->begin(), E = MBB->end(); MII != E; ) {
736 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
737 MachineInstr *MI = &*MII;
738 if (!Hoist(MI, Preheader))
739 UpdateRegPressure(MI);
740 // If we have hoisted an instruction that may store, it can only be a
745 // If it's a leaf node, it's done. Traverse upwards to pop ancestors.
746 ExitScopeIfDone(Node, OpenChildren, ParentMap);
750 /// Sink instructions into loops if profitable. This especially tries to prevent
751 /// register spills caused by register pressure if there is little to no
752 /// overhead moving instructions into loops.
753 void MachineLICMBase::SinkIntoLoop() {
754 MachineBasicBlock *Preheader = getCurPreheader();
758 SmallVector<MachineInstr *, 8> Candidates;
759 for (MachineBasicBlock::instr_iterator I = Preheader->instr_begin();
760 I != Preheader->instr_end(); ++I) {
761 // We need to ensure that we can safely move this instruction into the loop.
762 // As such, it must not have side-effects, e.g. such as a call has.
763 if (IsLoopInvariantInst(*I) && !HasLoopPHIUse(&*I))
764 Candidates.push_back(&*I);
767 for (MachineInstr *I : Candidates) {
768 const MachineOperand &MO = I->getOperand(0);
769 if (!MO.isDef() || !MO.isReg() || !MO.getReg())
771 if (!MRI->hasOneDef(MO.getReg()))
774 MachineBasicBlock *B = nullptr;
775 for (MachineInstr &MI : MRI->use_instructions(MO.getReg())) {
776 // FIXME: Come up with a proper cost model that estimates whether sinking
777 // the instruction (and thus possibly executing it on every loop
778 // iteration) is more expensive than a register.
779 // For now assumes that copies are cheap and thus almost always worth it.
788 B = DT->findNearestCommonDominator(B, MI.getParent());
794 if (!CanSink || !B || B == Preheader)
796 B->splice(B->getFirstNonPHI(), Preheader, I);
800 static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI) {
801 return MO.isKill() || MRI->hasOneNonDBGUse(MO.getReg());
804 /// Find all virtual register references that are liveout of the preheader to
805 /// initialize the starting "register pressure". Note this does not count live
806 /// through (livein but not used) registers.
807 void MachineLICMBase::InitRegPressure(MachineBasicBlock *BB) {
808 std::fill(RegPressure.begin(), RegPressure.end(), 0);
810 // If the preheader has only a single predecessor and it ends with a
811 // fallthrough or an unconditional branch, then scan its predecessor for live
812 // defs as well. This happens whenever the preheader is created by splitting
813 // the critical edge from the loop predecessor to the loop header.
814 if (BB->pred_size() == 1) {
815 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
816 SmallVector<MachineOperand, 4> Cond;
817 if (!TII->analyzeBranch(*BB, TBB, FBB, Cond, false) && Cond.empty())
818 InitRegPressure(*BB->pred_begin());
821 for (const MachineInstr &MI : *BB)
822 UpdateRegPressure(&MI, /*ConsiderUnseenAsDef=*/true);
825 /// Update estimate of register pressure after the specified instruction.
826 void MachineLICMBase::UpdateRegPressure(const MachineInstr *MI,
827 bool ConsiderUnseenAsDef) {
828 auto Cost = calcRegisterCost(MI, /*ConsiderSeen=*/true, ConsiderUnseenAsDef);
829 for (const auto &RPIdAndCost : Cost) {
830 unsigned Class = RPIdAndCost.first;
831 if (static_cast<int>(RegPressure[Class]) < -RPIdAndCost.second)
832 RegPressure[Class] = 0;
834 RegPressure[Class] += RPIdAndCost.second;
838 /// Calculate the additional register pressure that the registers used in MI
841 /// If 'ConsiderSeen' is true, updates 'RegSeen' and uses the information to
842 /// figure out which usages are live-ins.
843 /// FIXME: Figure out a way to consider 'RegSeen' from all code paths.
844 DenseMap<unsigned, int>
845 MachineLICMBase::calcRegisterCost(const MachineInstr *MI, bool ConsiderSeen,
846 bool ConsiderUnseenAsDef) {
847 DenseMap<unsigned, int> Cost;
848 if (MI->isImplicitDef())
850 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
851 const MachineOperand &MO = MI->getOperand(i);
852 if (!MO.isReg() || MO.isImplicit())
854 unsigned Reg = MO.getReg();
855 if (!TargetRegisterInfo::isVirtualRegister(Reg))
858 // FIXME: It seems bad to use RegSeen only for some of these calculations.
859 bool isNew = ConsiderSeen ? RegSeen.insert(Reg).second : false;
860 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
862 RegClassWeight W = TRI->getRegClassWeight(RC);
865 RCCost = W.RegWeight;
867 bool isKill = isOperandKill(MO, MRI);
868 if (isNew && !isKill && ConsiderUnseenAsDef)
869 // Haven't seen this, it must be a livein.
870 RCCost = W.RegWeight;
871 else if (!isNew && isKill)
872 RCCost = -W.RegWeight;
876 const int *PS = TRI->getRegClassPressureSets(RC);
877 for (; *PS != -1; ++PS) {
878 if (Cost.find(*PS) == Cost.end())
887 /// Return true if this machine instruction loads from global offset table or
889 static bool mayLoadFromGOTOrConstantPool(MachineInstr &MI) {
890 assert(MI.mayLoad() && "Expected MI that loads!");
892 // If we lost memory operands, conservatively assume that the instruction
893 // reads from everything..
894 if (MI.memoperands_empty())
897 for (MachineMemOperand *MemOp : MI.memoperands())
898 if (const PseudoSourceValue *PSV = MemOp->getPseudoValue())
899 if (PSV->isGOT() || PSV->isConstantPool())
905 // This function iterates through all the operands of the input store MI and
906 // checks that each register operand statisfies isCallerPreservedPhysReg.
907 // This means, the value being stored and the address where it is being stored
908 // is constant throughout the body of the function (not including prologue and
909 // epilogue). When called with an MI that isn't a store, it returns false.
910 // A future improvement can be to check if the store registers are constant
911 // throughout the loop rather than throughout the funtion.
912 static bool isInvariantStore(const MachineInstr &MI,
913 const TargetRegisterInfo *TRI,
914 const MachineRegisterInfo *MRI) {
916 bool FoundCallerPresReg = false;
917 if (!MI.mayStore() || MI.hasUnmodeledSideEffects() ||
918 (MI.getNumOperands() == 0))
921 // Check that all register operands are caller-preserved physical registers.
922 for (const MachineOperand &MO : MI.operands()) {
924 unsigned Reg = MO.getReg();
925 // If operand is a virtual register, check if it comes from a copy of a
926 // physical register.
927 if (TargetRegisterInfo::isVirtualRegister(Reg))
928 Reg = TRI->lookThruCopyLike(MO.getReg(), MRI);
929 if (TargetRegisterInfo::isVirtualRegister(Reg))
931 if (!TRI->isCallerPreservedPhysReg(Reg, *MI.getMF()))
934 FoundCallerPresReg = true;
935 } else if (!MO.isImm()) {
939 return FoundCallerPresReg;
942 // Return true if the input MI is a copy instruction that feeds an invariant
943 // store instruction. This means that the src of the copy has to satisfy
944 // isCallerPreservedPhysReg and atleast one of it's users should satisfy
946 static bool isCopyFeedingInvariantStore(const MachineInstr &MI,
947 const MachineRegisterInfo *MRI,
948 const TargetRegisterInfo *TRI) {
950 // FIXME: If targets would like to look through instructions that aren't
951 // pure copies, this can be updated to a query.
955 const MachineFunction *MF = MI.getMF();
956 // Check that we are copying a constant physical register.
957 unsigned CopySrcReg = MI.getOperand(1).getReg();
958 if (TargetRegisterInfo::isVirtualRegister(CopySrcReg))
961 if (!TRI->isCallerPreservedPhysReg(CopySrcReg, *MF))
964 unsigned CopyDstReg = MI.getOperand(0).getReg();
965 // Check if any of the uses of the copy are invariant stores.
966 assert (TargetRegisterInfo::isVirtualRegister(CopyDstReg) &&
967 "copy dst is not a virtual reg");
969 for (MachineInstr &UseMI : MRI->use_instructions(CopyDstReg)) {
970 if (UseMI.mayStore() && isInvariantStore(UseMI, TRI, MRI))
976 /// Returns true if the instruction may be a suitable candidate for LICM.
977 /// e.g. If the instruction is a call, then it's obviously not safe to hoist it.
978 bool MachineLICMBase::IsLICMCandidate(MachineInstr &I) {
979 // Check if it's safe to move the instruction.
980 bool DontMoveAcrossStore = true;
981 if ((!I.isSafeToMove(AA, DontMoveAcrossStore)) &&
982 !(HoistConstStores && isInvariantStore(I, TRI, MRI))) {
986 // If it is load then check if it is guaranteed to execute by making sure that
987 // it dominates all exiting blocks. If it doesn't, then there is a path out of
988 // the loop which does not execute this load, so we can't hoist it. Loads
989 // from constant memory are not safe to speculate all the time, for example
990 // indexed load from a jump table.
991 // Stores and side effects are already checked by isSafeToMove.
992 if (I.mayLoad() && !mayLoadFromGOTOrConstantPool(I) &&
993 !IsGuaranteedToExecute(I.getParent()))
999 /// Returns true if the instruction is loop invariant.
1000 /// I.e., all virtual register operands are defined outside of the loop,
1001 /// physical registers aren't accessed explicitly, and there are no side
1002 /// effects that aren't captured by the operands or other flags.
1003 bool MachineLICMBase::IsLoopInvariantInst(MachineInstr &I) {
1004 if (!IsLICMCandidate(I))
1007 // The instruction is loop invariant if all of its operands are.
1008 for (const MachineOperand &MO : I.operands()) {
1012 unsigned Reg = MO.getReg();
1013 if (Reg == 0) continue;
1015 // Don't hoist an instruction that uses or defines a physical register.
1016 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1018 // If the physreg has no defs anywhere, it's just an ambient register
1019 // and we can freely move its uses. Alternatively, if it's allocatable,
1020 // it could get allocated to something with a def during allocation.
1021 // However, if the physreg is known to always be caller saved/restored
1022 // then this use is safe to hoist.
1023 if (!MRI->isConstantPhysReg(Reg) &&
1024 !(TRI->isCallerPreservedPhysReg(Reg, *I.getMF())))
1026 // Otherwise it's safe to move.
1028 } else if (!MO.isDead()) {
1029 // A def that isn't dead. We can't move it.
1031 } else if (CurLoop->getHeader()->isLiveIn(Reg)) {
1032 // If the reg is live into the loop, we can't hoist an instruction
1033 // which would clobber it.
1041 assert(MRI->getVRegDef(Reg) &&
1042 "Machine instr not mapped for this vreg?!");
1044 // If the loop contains the definition of an operand, then the instruction
1045 // isn't loop invariant.
1046 if (CurLoop->contains(MRI->getVRegDef(Reg)))
1050 // If we got this far, the instruction is loop invariant!
1054 /// Return true if the specified instruction is used by a phi node and hoisting
1055 /// it could cause a copy to be inserted.
1056 bool MachineLICMBase::HasLoopPHIUse(const MachineInstr *MI) const {
1057 SmallVector<const MachineInstr*, 8> Work(1, MI);
1059 MI = Work.pop_back_val();
1060 for (const MachineOperand &MO : MI->operands()) {
1061 if (!MO.isReg() || !MO.isDef())
1063 unsigned Reg = MO.getReg();
1064 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1066 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
1067 // A PHI may cause a copy to be inserted.
1068 if (UseMI.isPHI()) {
1069 // A PHI inside the loop causes a copy because the live range of Reg is
1070 // extended across the PHI.
1071 if (CurLoop->contains(&UseMI))
1073 // A PHI in an exit block can cause a copy to be inserted if the PHI
1074 // has multiple predecessors in the loop with different values.
1075 // For now, approximate by rejecting all exit blocks.
1076 if (isExitBlock(UseMI.getParent()))
1080 // Look past copies as well.
1081 if (UseMI.isCopy() && CurLoop->contains(&UseMI))
1082 Work.push_back(&UseMI);
1085 } while (!Work.empty());
1089 /// Compute operand latency between a def of 'Reg' and an use in the current
1090 /// loop, return true if the target considered it high.
1091 bool MachineLICMBase::HasHighOperandLatency(MachineInstr &MI,
1093 unsigned Reg) const {
1094 if (MRI->use_nodbg_empty(Reg))
1097 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) {
1098 if (UseMI.isCopyLike())
1100 if (!CurLoop->contains(UseMI.getParent()))
1102 for (unsigned i = 0, e = UseMI.getNumOperands(); i != e; ++i) {
1103 const MachineOperand &MO = UseMI.getOperand(i);
1104 if (!MO.isReg() || !MO.isUse())
1106 unsigned MOReg = MO.getReg();
1110 if (TII->hasHighOperandLatency(SchedModel, MRI, MI, DefIdx, UseMI, i))
1114 // Only look at the first in loop use.
1121 /// Return true if the instruction is marked "cheap" or the operand latency
1122 /// between its def and a use is one or less.
1123 bool MachineLICMBase::IsCheapInstruction(MachineInstr &MI) const {
1124 if (TII->isAsCheapAsAMove(MI) || MI.isCopyLike())
1127 bool isCheap = false;
1128 unsigned NumDefs = MI.getDesc().getNumDefs();
1129 for (unsigned i = 0, e = MI.getNumOperands(); NumDefs && i != e; ++i) {
1130 MachineOperand &DefMO = MI.getOperand(i);
1131 if (!DefMO.isReg() || !DefMO.isDef())
1134 unsigned Reg = DefMO.getReg();
1135 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1138 if (!TII->hasLowDefLatency(SchedModel, MI, i))
1146 /// Visit BBs from header to current BB, check if hoisting an instruction of the
1147 /// given cost matrix can cause high register pressure.
1149 MachineLICMBase::CanCauseHighRegPressure(const DenseMap<unsigned, int>& Cost,
1151 for (const auto &RPIdAndCost : Cost) {
1152 if (RPIdAndCost.second <= 0)
1155 unsigned Class = RPIdAndCost.first;
1156 int Limit = RegLimit[Class];
1158 // Don't hoist cheap instructions if they would increase register pressure,
1159 // even if we're under the limit.
1160 if (CheapInstr && !HoistCheapInsts)
1163 for (const auto &RP : BackTrace)
1164 if (static_cast<int>(RP[Class]) + RPIdAndCost.second >= Limit)
1171 /// Traverse the back trace from header to the current block and update their
1172 /// register pressures to reflect the effect of hoisting MI from the current
1173 /// block to the preheader.
1174 void MachineLICMBase::UpdateBackTraceRegPressure(const MachineInstr *MI) {
1175 // First compute the 'cost' of the instruction, i.e. its contribution
1176 // to register pressure.
1177 auto Cost = calcRegisterCost(MI, /*ConsiderSeen=*/false,
1178 /*ConsiderUnseenAsDef=*/false);
1180 // Update register pressure of blocks from loop header to current block.
1181 for (auto &RP : BackTrace)
1182 for (const auto &RPIdAndCost : Cost)
1183 RP[RPIdAndCost.first] += RPIdAndCost.second;
1186 /// Return true if it is potentially profitable to hoist the given loop
1188 bool MachineLICMBase::IsProfitableToHoist(MachineInstr &MI) {
1189 if (MI.isImplicitDef())
1192 // Besides removing computation from the loop, hoisting an instruction has
1195 // - The value defined by the instruction becomes live across the entire
1196 // loop. This increases register pressure in the loop.
1198 // - If the value is used by a PHI in the loop, a copy will be required for
1199 // lowering the PHI after extending the live range.
1201 // - When hoisting the last use of a value in the loop, that value no longer
1202 // needs to be live in the loop. This lowers register pressure in the loop.
1204 if (HoistConstStores && isCopyFeedingInvariantStore(MI, MRI, TRI))
1207 bool CheapInstr = IsCheapInstruction(MI);
1208 bool CreatesCopy = HasLoopPHIUse(&MI);
1210 // Don't hoist a cheap instruction if it would create a copy in the loop.
1211 if (CheapInstr && CreatesCopy) {
1212 LLVM_DEBUG(dbgs() << "Won't hoist cheap instr with loop PHI use: " << MI);
1216 // Rematerializable instructions should always be hoisted since the register
1217 // allocator can just pull them down again when needed.
1218 if (TII->isTriviallyReMaterializable(MI, AA))
1221 // FIXME: If there are long latency loop-invariant instructions inside the
1222 // loop at this point, why didn't the optimizer's LICM hoist them?
1223 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
1224 const MachineOperand &MO = MI.getOperand(i);
1225 if (!MO.isReg() || MO.isImplicit())
1227 unsigned Reg = MO.getReg();
1228 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1230 if (MO.isDef() && HasHighOperandLatency(MI, i, Reg)) {
1231 LLVM_DEBUG(dbgs() << "Hoist High Latency: " << MI);
1237 // Estimate register pressure to determine whether to LICM the instruction.
1238 // In low register pressure situation, we can be more aggressive about
1239 // hoisting. Also, favors hoisting long latency instructions even in
1240 // moderately high pressure situation.
1241 // Cheap instructions will only be hoisted if they don't increase register
1243 auto Cost = calcRegisterCost(&MI, /*ConsiderSeen=*/false,
1244 /*ConsiderUnseenAsDef=*/false);
1246 // Visit BBs from header to current BB, if hoisting this doesn't cause
1247 // high register pressure, then it's safe to proceed.
1248 if (!CanCauseHighRegPressure(Cost, CheapInstr)) {
1249 LLVM_DEBUG(dbgs() << "Hoist non-reg-pressure: " << MI);
1254 // Don't risk increasing register pressure if it would create copies.
1256 LLVM_DEBUG(dbgs() << "Won't hoist instr with loop PHI use: " << MI);
1260 // Do not "speculate" in high register pressure situation. If an
1261 // instruction is not guaranteed to be executed in the loop, it's best to be
1263 if (AvoidSpeculation &&
1264 (!IsGuaranteedToExecute(MI.getParent()) && !MayCSE(&MI))) {
1265 LLVM_DEBUG(dbgs() << "Won't speculate: " << MI);
1269 // High register pressure situation, only hoist if the instruction is going
1271 if (!TII->isTriviallyReMaterializable(MI, AA) &&
1272 !MI.isDereferenceableInvariantLoad(AA)) {
1273 LLVM_DEBUG(dbgs() << "Can't remat / high reg-pressure: " << MI);
1280 /// Unfold a load from the given machineinstr if the load itself could be
1281 /// hoisted. Return the unfolded and hoistable load, or null if the load
1282 /// couldn't be unfolded or if it wouldn't be hoistable.
1283 MachineInstr *MachineLICMBase::ExtractHoistableLoad(MachineInstr *MI) {
1284 // Don't unfold simple loads.
1285 if (MI->canFoldAsLoad())
1288 // If not, we may be able to unfold a load and hoist that.
1289 // First test whether the instruction is loading from an amenable
1291 if (!MI->isDereferenceableInvariantLoad(AA))
1294 // Next determine the register class for a temporary register.
1295 unsigned LoadRegIndex;
1297 TII->getOpcodeAfterMemoryUnfold(MI->getOpcode(),
1298 /*UnfoldLoad=*/true,
1299 /*UnfoldStore=*/false,
1301 if (NewOpc == 0) return nullptr;
1302 const MCInstrDesc &MID = TII->get(NewOpc);
1303 MachineFunction &MF = *MI->getMF();
1304 const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI, MF);
1305 // Ok, we're unfolding. Create a temporary register and do the unfold.
1306 unsigned Reg = MRI->createVirtualRegister(RC);
1308 SmallVector<MachineInstr *, 2> NewMIs;
1309 bool Success = TII->unfoldMemoryOperand(MF, *MI, Reg,
1310 /*UnfoldLoad=*/true,
1311 /*UnfoldStore=*/false, NewMIs);
1314 "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
1316 assert(NewMIs.size() == 2 &&
1317 "Unfolded a load into multiple instructions!");
1318 MachineBasicBlock *MBB = MI->getParent();
1319 MachineBasicBlock::iterator Pos = MI;
1320 MBB->insert(Pos, NewMIs[0]);
1321 MBB->insert(Pos, NewMIs[1]);
1322 // If unfolding produced a load that wasn't loop-invariant or profitable to
1323 // hoist, discard the new instructions and bail.
1324 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) {
1325 NewMIs[0]->eraseFromParent();
1326 NewMIs[1]->eraseFromParent();
1330 // Update register pressure for the unfolded instruction.
1331 UpdateRegPressure(NewMIs[1]);
1333 // Otherwise we successfully unfolded a load that we can hoist.
1334 MI->eraseFromParent();
1338 /// Initialize the CSE map with instructions that are in the current loop
1339 /// preheader that may become duplicates of instructions that are hoisted
1340 /// out of the loop.
1341 void MachineLICMBase::InitCSEMap(MachineBasicBlock *BB) {
1342 for (MachineInstr &MI : *BB)
1343 CSEMap[MI.getOpcode()].push_back(&MI);
1346 /// Find an instruction amount PrevMIs that is a duplicate of MI.
1347 /// Return this instruction if it's found.
1349 MachineLICMBase::LookForDuplicate(const MachineInstr *MI,
1350 std::vector<const MachineInstr*> &PrevMIs) {
1351 for (const MachineInstr *PrevMI : PrevMIs)
1352 if (TII->produceSameValue(*MI, *PrevMI, (PreRegAlloc ? MRI : nullptr)))
1358 /// Given a LICM'ed instruction, look for an instruction on the preheader that
1359 /// computes the same value. If it's found, do a RAU on with the definition of
1360 /// the existing instruction rather than hoisting the instruction to the
1362 bool MachineLICMBase::EliminateCSE(MachineInstr *MI,
1363 DenseMap<unsigned, std::vector<const MachineInstr *>>::iterator &CI) {
1364 // Do not CSE implicit_def so ProcessImplicitDefs can properly propagate
1365 // the undef property onto uses.
1366 if (CI == CSEMap.end() || MI->isImplicitDef())
1369 if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
1370 LLVM_DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup);
1372 // Replace virtual registers defined by MI by their counterparts defined
1374 SmallVector<unsigned, 2> Defs;
1375 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1376 const MachineOperand &MO = MI->getOperand(i);
1378 // Physical registers may not differ here.
1379 assert((!MO.isReg() || MO.getReg() == 0 ||
1380 !TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
1381 MO.getReg() == Dup->getOperand(i).getReg()) &&
1382 "Instructions with different phys regs are not identical!");
1384 if (MO.isReg() && MO.isDef() &&
1385 !TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1389 SmallVector<const TargetRegisterClass*, 2> OrigRCs;
1390 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
1391 unsigned Idx = Defs[i];
1392 unsigned Reg = MI->getOperand(Idx).getReg();
1393 unsigned DupReg = Dup->getOperand(Idx).getReg();
1394 OrigRCs.push_back(MRI->getRegClass(DupReg));
1396 if (!MRI->constrainRegClass(DupReg, MRI->getRegClass(Reg))) {
1397 // Restore old RCs if more than one defs.
1398 for (unsigned j = 0; j != i; ++j)
1399 MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]);
1404 for (unsigned Idx : Defs) {
1405 unsigned Reg = MI->getOperand(Idx).getReg();
1406 unsigned DupReg = Dup->getOperand(Idx).getReg();
1407 MRI->replaceRegWith(Reg, DupReg);
1408 MRI->clearKillFlags(DupReg);
1411 MI->eraseFromParent();
1418 /// Return true if the given instruction will be CSE'd if it's hoisted out of
1420 bool MachineLICMBase::MayCSE(MachineInstr *MI) {
1421 unsigned Opcode = MI->getOpcode();
1422 DenseMap<unsigned, std::vector<const MachineInstr *>>::iterator
1423 CI = CSEMap.find(Opcode);
1424 // Do not CSE implicit_def so ProcessImplicitDefs can properly propagate
1425 // the undef property onto uses.
1426 if (CI == CSEMap.end() || MI->isImplicitDef())
1429 return LookForDuplicate(MI, CI->second) != nullptr;
1432 /// When an instruction is found to use only loop invariant operands
1433 /// that are safe to hoist, this instruction is called to do the dirty work.
1434 /// It returns true if the instruction is hoisted.
1435 bool MachineLICMBase::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) {
1436 // First check whether we should hoist this instruction.
1437 if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) {
1438 // If not, try unfolding a hoistable load.
1439 MI = ExtractHoistableLoad(MI);
1440 if (!MI) return false;
1443 // If we have hoisted an instruction that may store, it can only be a constant
1448 // Now move the instructions to the predecessor, inserting it before any
1449 // terminator instructions.
1451 dbgs() << "Hoisting " << *MI;
1452 if (MI->getParent()->getBasicBlock())
1453 dbgs() << " from " << printMBBReference(*MI->getParent());
1454 if (Preheader->getBasicBlock())
1455 dbgs() << " to " << printMBBReference(*Preheader);
1459 // If this is the first instruction being hoisted to the preheader,
1460 // initialize the CSE map with potential common expressions.
1462 InitCSEMap(Preheader);
1463 FirstInLoop = false;
1466 // Look for opportunity to CSE the hoisted instruction.
1467 unsigned Opcode = MI->getOpcode();
1468 DenseMap<unsigned, std::vector<const MachineInstr *>>::iterator
1469 CI = CSEMap.find(Opcode);
1470 if (!EliminateCSE(MI, CI)) {
1471 // Otherwise, splice the instruction to the preheader.
1472 Preheader->splice(Preheader->getFirstTerminator(),MI->getParent(),MI);
1474 // Since we are moving the instruction out of its basic block, we do not
1475 // retain its debug location. Doing so would degrade the debugging
1476 // experience and adversely affect the accuracy of profiling information.
1477 MI->setDebugLoc(DebugLoc());
1479 // Update register pressure for BBs from header to this block.
1480 UpdateBackTraceRegPressure(MI);
1482 // Clear the kill flags of any register this instruction defines,
1483 // since they may need to be live throughout the entire loop
1484 // rather than just live for part of it.
1485 for (MachineOperand &MO : MI->operands())
1486 if (MO.isReg() && MO.isDef() && !MO.isDead())
1487 MRI->clearKillFlags(MO.getReg());
1489 // Add to the CSE map.
1490 if (CI != CSEMap.end())
1491 CI->second.push_back(MI);
1493 CSEMap[Opcode].push_back(MI);
1502 /// Get the preheader for the current loop, splitting a critical edge if needed.
1503 MachineBasicBlock *MachineLICMBase::getCurPreheader() {
1504 // Determine the block to which to hoist instructions. If we can't find a
1505 // suitable loop predecessor, we can't do any hoisting.
1507 // If we've tried to get a preheader and failed, don't try again.
1508 if (CurPreheader == reinterpret_cast<MachineBasicBlock *>(-1))
1511 if (!CurPreheader) {
1512 CurPreheader = CurLoop->getLoopPreheader();
1513 if (!CurPreheader) {
1514 MachineBasicBlock *Pred = CurLoop->getLoopPredecessor();
1516 CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);
1520 CurPreheader = Pred->SplitCriticalEdge(CurLoop->getHeader(), *this);
1521 if (!CurPreheader) {
1522 CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);
1527 return CurPreheader;