1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// \file Methods common to all machine operands.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineOperand.h"
15 #include "llvm/ADT/StringExtras.h"
16 #include "llvm/Analysis/Loads.h"
17 #include "llvm/CodeGen/MIRPrinter.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineJumpTableInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
22 #include "llvm/CodeGen/TargetRegisterInfo.h"
23 #include "llvm/Config/llvm-config.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/IRPrintingPasses.h"
26 #include "llvm/IR/ModuleSlotTracker.h"
27 #include "llvm/Target/TargetIntrinsicInfo.h"
28 #include "llvm/Target/TargetMachine.h"
33 PrintRegMaskNumRegs("print-regmask-num-regs",
34 cl::desc("Number of registers to limit to when "
35 "printing regmask operands in IR dumps. "
37 cl::init(32), cl::Hidden);
39 static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
40 if (const MachineInstr *MI = MO.getParent())
41 if (const MachineBasicBlock *MBB = MI->getParent())
42 if (const MachineFunction *MF = MBB->getParent())
46 static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
47 return const_cast<MachineFunction *>(
48 getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
51 void MachineOperand::setReg(unsigned Reg) {
55 // Clear the IsRenamable bit to keep it conservatively correct.
58 // Otherwise, we have to change the register. If this operand is embedded
59 // into a machine function, we need to update the old and new register's
61 if (MachineFunction *MF = getMFIfAvailable(*this)) {
62 MachineRegisterInfo &MRI = MF->getRegInfo();
63 MRI.removeRegOperandFromUseList(this);
64 SmallContents.RegNo = Reg;
65 MRI.addRegOperandToUseList(this);
69 // Otherwise, just change the register, no problem. :)
70 SmallContents.RegNo = Reg;
73 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
74 const TargetRegisterInfo &TRI) {
75 assert(TargetRegisterInfo::isVirtualRegister(Reg));
76 if (SubIdx && getSubReg())
77 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
83 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
84 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
86 Reg = TRI.getSubReg(Reg, getSubReg());
87 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
88 // That won't happen in legal code.
96 /// Change a def to a use, or a use to a def.
97 void MachineOperand::setIsDef(bool Val) {
98 assert(isReg() && "Wrong MachineOperand accessor");
99 assert((!Val || !isDebug()) && "Marking a debug operation as def");
102 assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
103 // MRI may keep uses and defs in different list positions.
104 if (MachineFunction *MF = getMFIfAvailable(*this)) {
105 MachineRegisterInfo &MRI = MF->getRegInfo();
106 MRI.removeRegOperandFromUseList(this);
108 MRI.addRegOperandToUseList(this);
114 bool MachineOperand::isRenamable() const {
115 assert(isReg() && "Wrong MachineOperand accessor");
116 assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&
117 "isRenamable should only be checked on physical registers");
121 const MachineInstr *MI = getParent();
126 return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
128 assert(isUse() && "Reg is not def or use");
129 return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
132 void MachineOperand::setIsRenamable(bool Val) {
133 assert(isReg() && "Wrong MachineOperand accessor");
134 assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&
135 "setIsRenamable should only be called on physical registers");
139 // If this operand is currently a register operand, and if this is in a
140 // function, deregister the operand from the register's use/def list.
141 void MachineOperand::removeRegFromUses() {
142 if (!isReg() || !isOnRegUseList())
145 if (MachineFunction *MF = getMFIfAvailable(*this))
146 MF->getRegInfo().removeRegOperandFromUseList(this);
149 /// ChangeToImmediate - Replace this operand with a new immediate operand of
150 /// the specified value. If an operand is known to be an immediate already,
151 /// the setImm method should be used.
152 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
153 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
157 OpKind = MO_Immediate;
158 Contents.ImmVal = ImmVal;
161 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
162 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
166 OpKind = MO_FPImmediate;
167 Contents.CFP = FPImm;
170 void MachineOperand::ChangeToES(const char *SymName,
171 unsigned char TargetFlags) {
172 assert((!isReg() || !isTied()) &&
173 "Cannot change a tied operand into an external symbol");
177 OpKind = MO_ExternalSymbol;
178 Contents.OffsetedInfo.Val.SymbolName = SymName;
179 setOffset(0); // Offset is always 0.
180 setTargetFlags(TargetFlags);
183 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
184 assert((!isReg() || !isTied()) &&
185 "Cannot change a tied operand into an MCSymbol");
189 OpKind = MO_MCSymbol;
193 void MachineOperand::ChangeToFrameIndex(int Idx) {
194 assert((!isReg() || !isTied()) &&
195 "Cannot change a tied operand into a FrameIndex");
199 OpKind = MO_FrameIndex;
203 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
204 unsigned char TargetFlags) {
205 assert((!isReg() || !isTied()) &&
206 "Cannot change a tied operand into a FrameIndex");
210 OpKind = MO_TargetIndex;
213 setTargetFlags(TargetFlags);
216 /// ChangeToRegister - Replace this operand with a new register operand of
217 /// the specified value. If an operand is known to be an register already,
218 /// the setReg method should be used.
219 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
220 bool isKill, bool isDead, bool isUndef,
222 MachineRegisterInfo *RegInfo = nullptr;
223 if (MachineFunction *MF = getMFIfAvailable(*this))
224 RegInfo = &MF->getRegInfo();
225 // If this operand is already a register operand, remove it from the
226 // register's use/def lists.
227 bool WasReg = isReg();
228 if (RegInfo && WasReg)
229 RegInfo->removeRegOperandFromUseList(this);
231 // Change this to a register and set the reg#.
232 assert(!(isDead && !isDef) && "Dead flag on non-def");
233 assert(!(isKill && isDef) && "Kill flag on def");
234 OpKind = MO_Register;
235 SmallContents.RegNo = Reg;
236 SubReg_TargetFlags = 0;
239 IsDeadOrKill = isKill | isDead;
242 IsInternalRead = false;
243 IsEarlyClobber = false;
245 // Ensure isOnRegUseList() returns false.
246 Contents.Reg.Prev = nullptr;
247 // Preserve the tie when the operand was already a register.
251 // If this operand is embedded in a function, add the operand to the
252 // register's use/def list.
254 RegInfo->addRegOperandToUseList(this);
257 /// isIdenticalTo - Return true if this operand is identical to the specified
258 /// operand. Note that this should stay in sync with the hash_value overload
260 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
261 if (getType() != Other.getType() ||
262 getTargetFlags() != Other.getTargetFlags())
266 case MachineOperand::MO_Register:
267 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
268 getSubReg() == Other.getSubReg();
269 case MachineOperand::MO_Immediate:
270 return getImm() == Other.getImm();
271 case MachineOperand::MO_CImmediate:
272 return getCImm() == Other.getCImm();
273 case MachineOperand::MO_FPImmediate:
274 return getFPImm() == Other.getFPImm();
275 case MachineOperand::MO_MachineBasicBlock:
276 return getMBB() == Other.getMBB();
277 case MachineOperand::MO_FrameIndex:
278 return getIndex() == Other.getIndex();
279 case MachineOperand::MO_ConstantPoolIndex:
280 case MachineOperand::MO_TargetIndex:
281 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
282 case MachineOperand::MO_JumpTableIndex:
283 return getIndex() == Other.getIndex();
284 case MachineOperand::MO_GlobalAddress:
285 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
286 case MachineOperand::MO_ExternalSymbol:
287 return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
288 getOffset() == Other.getOffset();
289 case MachineOperand::MO_BlockAddress:
290 return getBlockAddress() == Other.getBlockAddress() &&
291 getOffset() == Other.getOffset();
292 case MachineOperand::MO_RegisterMask:
293 case MachineOperand::MO_RegisterLiveOut: {
294 // Shallow compare of the two RegMasks
295 const uint32_t *RegMask = getRegMask();
296 const uint32_t *OtherRegMask = Other.getRegMask();
297 if (RegMask == OtherRegMask)
300 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
301 // Calculate the size of the RegMask
302 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
303 unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
305 // Deep compare of the two RegMasks
306 return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
308 // We don't know the size of the RegMask, so we can't deep compare the two
312 case MachineOperand::MO_MCSymbol:
313 return getMCSymbol() == Other.getMCSymbol();
314 case MachineOperand::MO_CFIIndex:
315 return getCFIIndex() == Other.getCFIIndex();
316 case MachineOperand::MO_Metadata:
317 return getMetadata() == Other.getMetadata();
318 case MachineOperand::MO_IntrinsicID:
319 return getIntrinsicID() == Other.getIntrinsicID();
320 case MachineOperand::MO_Predicate:
321 return getPredicate() == Other.getPredicate();
323 llvm_unreachable("Invalid machine operand type");
326 // Note: this must stay exactly in sync with isIdenticalTo above.
327 hash_code llvm::hash_value(const MachineOperand &MO) {
328 switch (MO.getType()) {
329 case MachineOperand::MO_Register:
330 // Register operands don't have target flags.
331 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
332 case MachineOperand::MO_Immediate:
333 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
334 case MachineOperand::MO_CImmediate:
335 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
336 case MachineOperand::MO_FPImmediate:
337 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
338 case MachineOperand::MO_MachineBasicBlock:
339 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
340 case MachineOperand::MO_FrameIndex:
341 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
342 case MachineOperand::MO_ConstantPoolIndex:
343 case MachineOperand::MO_TargetIndex:
344 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
346 case MachineOperand::MO_JumpTableIndex:
347 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
348 case MachineOperand::MO_ExternalSymbol:
349 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
351 case MachineOperand::MO_GlobalAddress:
352 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
354 case MachineOperand::MO_BlockAddress:
355 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
357 case MachineOperand::MO_RegisterMask:
358 case MachineOperand::MO_RegisterLiveOut:
359 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
360 case MachineOperand::MO_Metadata:
361 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
362 case MachineOperand::MO_MCSymbol:
363 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
364 case MachineOperand::MO_CFIIndex:
365 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
366 case MachineOperand::MO_IntrinsicID:
367 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
368 case MachineOperand::MO_Predicate:
369 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
371 llvm_unreachable("Invalid machine operand type");
374 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
376 static void tryToGetTargetInfo(const MachineOperand &MO,
377 const TargetRegisterInfo *&TRI,
378 const TargetIntrinsicInfo *&IntrinsicInfo) {
379 if (const MachineFunction *MF = getMFIfAvailable(MO)) {
380 TRI = MF->getSubtarget().getRegisterInfo();
381 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
385 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
386 const auto *TII = MF.getSubtarget().getInstrInfo();
387 assert(TII && "expected instruction info");
388 auto Indices = TII->getSerializableTargetIndices();
389 auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
390 return I.first == Index;
392 if (Found != Indices.end())
393 return Found->second;
397 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
398 auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
399 for (const auto &I : Flags) {
407 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
408 const TargetRegisterInfo *TRI) {
410 OS << "%dwarfreg." << DwarfReg;
414 int Reg = TRI->getLLVMRegNum(DwarfReg, true);
419 OS << printReg(Reg, TRI);
422 static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
423 ModuleSlotTracker &MST) {
426 printLLVMNameWithoutPrefix(OS, BB.getName());
430 if (const Function *F = BB.getParent()) {
431 if (F == MST.getCurrentFunction()) {
432 Slot = MST.getLocalSlot(&BB);
433 } else if (const Module *M = F->getParent()) {
434 ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
435 CustomMST.incorporateFunction(*F);
436 Slot = CustomMST.getLocalSlot(&BB);
440 MachineOperand::printIRSlotNumber(OS, *Slot);
445 static void printIRValueReference(raw_ostream &OS, const Value &V,
446 ModuleSlotTracker &MST) {
447 if (isa<GlobalValue>(V)) {
448 V.printAsOperand(OS, /*PrintType=*/false, MST);
451 if (isa<Constant>(V)) {
452 // Machine memory operands can load/store to/from constant value pointers.
454 V.printAsOperand(OS, /*PrintType=*/true, MST);
460 printLLVMNameWithoutPrefix(OS, V.getName());
463 MachineOperand::printIRSlotNumber(OS, MST.getLocalSlot(&V));
466 static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
468 SmallVectorImpl<StringRef> &SSNs) {
470 case SyncScope::System:
474 Context.getSyncScopeNames(SSNs);
476 OS << "syncscope(\"";
477 printEscapedString(SSNs[SSID], OS);
483 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
485 auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
486 for (const auto &I : Flags) {
487 if (I.first == TMMOFlag) {
494 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
495 const MachineFrameInfo *MFI) {
498 IsFixed = MFI->isFixedObjectIndex(FrameIndex);
499 if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
500 if (Alloca->hasName())
501 Name = Alloca->getName();
503 FrameIndex -= MFI->getObjectIndexBegin();
505 MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
508 void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,
509 const TargetRegisterInfo *TRI) {
512 OS << TRI->getSubRegIndexName(Index);
517 void MachineOperand::printTargetFlags(raw_ostream &OS,
518 const MachineOperand &Op) {
519 if (!Op.getTargetFlags())
521 const MachineFunction *MF = getMFIfAvailable(Op);
525 const auto *TII = MF->getSubtarget().getInstrInfo();
526 assert(TII && "expected instruction info");
527 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
528 OS << "target-flags(";
529 const bool HasDirectFlags = Flags.first;
530 const bool HasBitmaskFlags = Flags.second;
531 if (!HasDirectFlags && !HasBitmaskFlags) {
535 if (HasDirectFlags) {
536 if (const auto *Name = getTargetFlagName(TII, Flags.first))
539 OS << "<unknown target flag>";
541 if (!HasBitmaskFlags) {
545 bool IsCommaNeeded = HasDirectFlags;
546 unsigned BitMask = Flags.second;
547 auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
548 for (const auto &Mask : BitMasks) {
549 // Check if the flag's bitmask has the bits of the current mask set.
550 if ((BitMask & Mask.first) == Mask.first) {
553 IsCommaNeeded = true;
555 // Clear the bits which were serialized from the flag's bitmask.
556 BitMask &= ~(Mask.first);
560 // When the resulting flag's bitmask isn't zero, we know that we didn't
561 // serialize all of the bit flags.
564 OS << "<unknown bitmask target flag>";
569 void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) {
570 OS << "<mcsymbol " << Sym << ">";
573 void MachineOperand::printStackObjectReference(raw_ostream &OS,
575 bool IsFixed, StringRef Name) {
577 OS << "%fixed-stack." << FrameIndex;
581 OS << "%stack." << FrameIndex;
586 void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) {
590 OS << " - " << -Offset;
593 OS << " + " << Offset;
596 void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) {
603 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
604 const TargetRegisterInfo *TRI) {
605 switch (CFI.getOperation()) {
606 case MCCFIInstruction::OpSameValue:
608 if (MCSymbol *Label = CFI.getLabel())
609 MachineOperand::printSymbol(OS, *Label);
610 printCFIRegister(CFI.getRegister(), OS, TRI);
612 case MCCFIInstruction::OpRememberState:
613 OS << "remember_state ";
614 if (MCSymbol *Label = CFI.getLabel())
615 MachineOperand::printSymbol(OS, *Label);
617 case MCCFIInstruction::OpRestoreState:
618 OS << "restore_state ";
619 if (MCSymbol *Label = CFI.getLabel())
620 MachineOperand::printSymbol(OS, *Label);
622 case MCCFIInstruction::OpOffset:
624 if (MCSymbol *Label = CFI.getLabel())
625 MachineOperand::printSymbol(OS, *Label);
626 printCFIRegister(CFI.getRegister(), OS, TRI);
627 OS << ", " << CFI.getOffset();
629 case MCCFIInstruction::OpDefCfaRegister:
630 OS << "def_cfa_register ";
631 if (MCSymbol *Label = CFI.getLabel())
632 MachineOperand::printSymbol(OS, *Label);
633 printCFIRegister(CFI.getRegister(), OS, TRI);
635 case MCCFIInstruction::OpDefCfaOffset:
636 OS << "def_cfa_offset ";
637 if (MCSymbol *Label = CFI.getLabel())
638 MachineOperand::printSymbol(OS, *Label);
639 OS << CFI.getOffset();
641 case MCCFIInstruction::OpDefCfa:
643 if (MCSymbol *Label = CFI.getLabel())
644 MachineOperand::printSymbol(OS, *Label);
645 printCFIRegister(CFI.getRegister(), OS, TRI);
646 OS << ", " << CFI.getOffset();
648 case MCCFIInstruction::OpRelOffset:
650 if (MCSymbol *Label = CFI.getLabel())
651 MachineOperand::printSymbol(OS, *Label);
652 printCFIRegister(CFI.getRegister(), OS, TRI);
653 OS << ", " << CFI.getOffset();
655 case MCCFIInstruction::OpAdjustCfaOffset:
656 OS << "adjust_cfa_offset ";
657 if (MCSymbol *Label = CFI.getLabel())
658 MachineOperand::printSymbol(OS, *Label);
659 OS << CFI.getOffset();
661 case MCCFIInstruction::OpRestore:
663 if (MCSymbol *Label = CFI.getLabel())
664 MachineOperand::printSymbol(OS, *Label);
665 printCFIRegister(CFI.getRegister(), OS, TRI);
667 case MCCFIInstruction::OpEscape: {
669 if (MCSymbol *Label = CFI.getLabel())
670 MachineOperand::printSymbol(OS, *Label);
671 if (!CFI.getValues().empty()) {
672 size_t e = CFI.getValues().size() - 1;
673 for (size_t i = 0; i < e; ++i)
674 OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
675 OS << format("0x%02x", uint8_t(CFI.getValues()[e])) << ", ";
679 case MCCFIInstruction::OpUndefined:
681 if (MCSymbol *Label = CFI.getLabel())
682 MachineOperand::printSymbol(OS, *Label);
683 printCFIRegister(CFI.getRegister(), OS, TRI);
685 case MCCFIInstruction::OpRegister:
687 if (MCSymbol *Label = CFI.getLabel())
688 MachineOperand::printSymbol(OS, *Label);
689 printCFIRegister(CFI.getRegister(), OS, TRI);
691 printCFIRegister(CFI.getRegister2(), OS, TRI);
693 case MCCFIInstruction::OpWindowSave:
694 OS << "window_save ";
695 if (MCSymbol *Label = CFI.getLabel())
696 MachineOperand::printSymbol(OS, *Label);
699 // TODO: Print the other CFI Operations.
700 OS << "<unserializable cfi directive>";
705 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
706 const TargetIntrinsicInfo *IntrinsicInfo) const {
707 print(OS, LLT{}, TRI, IntrinsicInfo);
710 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
711 const TargetRegisterInfo *TRI,
712 const TargetIntrinsicInfo *IntrinsicInfo) const {
713 tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
714 ModuleSlotTracker DummyMST(nullptr);
715 print(OS, DummyMST, TypeToPrint, /*PrintDef=*/false, /*IsStandalone=*/true,
716 /*ShouldPrintRegisterTies=*/true,
717 /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
720 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
721 LLT TypeToPrint, bool PrintDef, bool IsStandalone,
722 bool ShouldPrintRegisterTies,
723 unsigned TiedOperandIdx,
724 const TargetRegisterInfo *TRI,
725 const TargetIntrinsicInfo *IntrinsicInfo) const {
726 printTargetFlags(OS, *this);
728 case MachineOperand::MO_Register: {
729 unsigned Reg = getReg();
731 OS << (isDef() ? "implicit-def " : "implicit ");
732 else if (PrintDef && isDef())
733 // Print the 'def' flag only when the operand is defined after '='.
735 if (isInternalRead())
743 if (isEarlyClobber())
744 OS << "early-clobber ";
747 if (TargetRegisterInfo::isPhysicalRegister(getReg()) && isRenamable())
750 const MachineRegisterInfo *MRI = nullptr;
751 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
752 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
753 MRI = &MF->getRegInfo();
757 OS << printReg(Reg, TRI, 0, MRI);
758 // Print the sub register.
759 if (unsigned SubReg = getSubReg()) {
761 OS << '.' << TRI->getSubRegIndexName(SubReg);
763 OS << ".subreg" << SubReg;
765 // Print the register class / bank.
766 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
767 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
768 const MachineRegisterInfo &MRI = MF->getRegInfo();
769 if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
771 OS << printRegClassOrBank(Reg, MRI, TRI);
776 if (ShouldPrintRegisterTies && isTied() && !isDef())
777 OS << "(tied-def " << TiedOperandIdx << ")";
779 if (TypeToPrint.isValid())
780 OS << '(' << TypeToPrint << ')';
783 case MachineOperand::MO_Immediate:
786 case MachineOperand::MO_CImmediate:
787 getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
789 case MachineOperand::MO_FPImmediate:
790 getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
792 case MachineOperand::MO_MachineBasicBlock:
793 OS << printMBBReference(*getMBB());
795 case MachineOperand::MO_FrameIndex: {
796 int FrameIndex = getIndex();
797 bool IsFixed = false;
798 const MachineFrameInfo *MFI = nullptr;
799 if (const MachineFunction *MF = getMFIfAvailable(*this))
800 MFI = &MF->getFrameInfo();
801 printFrameIndex(OS, FrameIndex, IsFixed, MFI);
804 case MachineOperand::MO_ConstantPoolIndex:
805 OS << "%const." << getIndex();
806 printOperandOffset(OS, getOffset());
808 case MachineOperand::MO_TargetIndex: {
809 OS << "target-index(";
810 const char *Name = "<unknown>";
811 if (const MachineFunction *MF = getMFIfAvailable(*this))
812 if (const auto *TargetIndexName = getTargetIndexName(*MF, getIndex()))
813 Name = TargetIndexName;
815 printOperandOffset(OS, getOffset());
818 case MachineOperand::MO_JumpTableIndex:
819 OS << printJumpTableEntryReference(getIndex());
821 case MachineOperand::MO_GlobalAddress:
822 getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
823 printOperandOffset(OS, getOffset());
825 case MachineOperand::MO_ExternalSymbol: {
826 StringRef Name = getSymbolName();
831 printLLVMNameWithoutPrefix(OS, Name);
833 printOperandOffset(OS, getOffset());
836 case MachineOperand::MO_BlockAddress: {
837 OS << "blockaddress(";
838 getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
841 printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
843 MachineOperand::printOperandOffset(OS, getOffset());
846 case MachineOperand::MO_RegisterMask: {
849 unsigned NumRegsInMask = 0;
850 unsigned NumRegsEmitted = 0;
851 for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
852 unsigned MaskWord = i / 32;
853 unsigned MaskBit = i % 32;
854 if (getRegMask()[MaskWord] & (1 << MaskBit)) {
855 if (PrintRegMaskNumRegs < 0 ||
856 NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
857 OS << " " << printReg(i, TRI);
863 if (NumRegsEmitted != NumRegsInMask)
864 OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
871 case MachineOperand::MO_RegisterLiveOut: {
872 const uint32_t *RegMask = getRegLiveOut();
877 bool IsCommaNeeded = false;
878 for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
879 if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
882 OS << printReg(Reg, TRI);
883 IsCommaNeeded = true;
890 case MachineOperand::MO_Metadata:
891 getMetadata()->printAsOperand(OS, MST);
893 case MachineOperand::MO_MCSymbol:
894 printSymbol(OS, *getMCSymbol());
896 case MachineOperand::MO_CFIIndex: {
897 if (const MachineFunction *MF = getMFIfAvailable(*this))
898 printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
900 OS << "<cfi directive>";
903 case MachineOperand::MO_IntrinsicID: {
904 Intrinsic::ID ID = getIntrinsicID();
905 if (ID < Intrinsic::num_intrinsics)
906 OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
907 else if (IntrinsicInfo)
908 OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
910 OS << "intrinsic(" << ID << ')';
913 case MachineOperand::MO_Predicate: {
914 auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
915 OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
916 << CmpInst::getPredicateName(Pred) << ')';
922 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
923 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
926 //===----------------------------------------------------------------------===//
927 // MachineMemOperand Implementation
928 //===----------------------------------------------------------------------===//
930 /// getAddrSpace - Return the LLVM IR address space number that this pointer
932 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
934 /// isDereferenceable - Return true if V is always dereferenceable for
935 /// Offset + Size byte.
936 bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
937 const DataLayout &DL) const {
938 if (!V.is<const Value *>())
941 const Value *BasePtr = V.get<const Value *>();
942 if (BasePtr == nullptr)
945 return isDereferenceableAndAlignedPointer(
946 BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
949 /// getConstantPool - Return a MachinePointerInfo record that refers to the
951 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
952 return MachinePointerInfo(MF.getPSVManager().getConstantPool());
955 /// getFixedStack - Return a MachinePointerInfo record that refers to the
956 /// the specified FrameIndex.
957 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
958 int FI, int64_t Offset) {
959 return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
962 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
963 return MachinePointerInfo(MF.getPSVManager().getJumpTable());
966 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
967 return MachinePointerInfo(MF.getPSVManager().getGOT());
970 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
971 int64_t Offset, uint8_t ID) {
972 return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
975 MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
976 return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
979 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
980 uint64_t s, uint64_t a,
981 const AAMDNodes &AAInfo,
982 const MDNode *Ranges, SyncScope::ID SSID,
983 AtomicOrdering Ordering,
984 AtomicOrdering FailureOrdering)
985 : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
986 AAInfo(AAInfo), Ranges(Ranges) {
987 assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
988 isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
989 "invalid pointer value");
990 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
991 assert((isLoad() || isStore()) && "Not a load/store!");
993 AtomicInfo.SSID = static_cast<unsigned>(SSID);
994 assert(getSyncScopeID() == SSID && "Value truncated");
995 AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
996 assert(getOrdering() == Ordering && "Value truncated");
997 AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
998 assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1001 /// Profile - Gather unique data for the object.
1003 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
1004 ID.AddInteger(getOffset());
1005 ID.AddInteger(Size);
1006 ID.AddPointer(getOpaqueValue());
1007 ID.AddInteger(getFlags());
1008 ID.AddInteger(getBaseAlignment());
1011 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
1012 // The Value and Offset may differ due to CSE. But the flags and size
1013 // should be the same.
1014 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1015 assert(MMO->getSize() == getSize() && "Size mismatch!");
1017 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
1018 // Update the alignment value.
1019 BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
1020 // Also update the base and offset, because the new alignment may
1021 // not be applicable with the old ones.
1022 PtrInfo = MMO->PtrInfo;
1026 /// getAlignment - Return the minimum known alignment in bytes of the
1027 /// actual memory reference.
1028 uint64_t MachineMemOperand::getAlignment() const {
1029 return MinAlign(getBaseAlignment(), getOffset());
1032 void MachineMemOperand::print(raw_ostream &OS) const {
1033 ModuleSlotTracker DummyMST(nullptr);
1034 print(OS, DummyMST);
1037 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
1038 SmallVector<StringRef, 0> SSNs;
1040 print(OS, MST, SSNs, Ctx, nullptr, nullptr);
1043 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
1044 SmallVectorImpl<StringRef> &SSNs,
1045 const LLVMContext &Context,
1046 const MachineFrameInfo *MFI,
1047 const TargetInstrInfo *TII) const {
1051 if (isNonTemporal())
1052 OS << "non-temporal ";
1053 if (isDereferenceable())
1054 OS << "dereferenceable ";
1057 if (getFlags() & MachineMemOperand::MOTargetFlag1)
1058 OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag1)
1060 if (getFlags() & MachineMemOperand::MOTargetFlag2)
1061 OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag2)
1063 if (getFlags() & MachineMemOperand::MOTargetFlag3)
1064 OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag3)
1067 assert((isLoad() || isStore()) &&
1068 "machine memory operand must be a load or store (or both)");
1074 printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1076 if (getOrdering() != AtomicOrdering::NotAtomic)
1077 OS << toIRString(getOrdering()) << ' ';
1078 if (getFailureOrdering() != AtomicOrdering::NotAtomic)
1079 OS << toIRString(getFailureOrdering()) << ' ';
1082 if (const Value *Val = getValue()) {
1083 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1084 printIRValueReference(OS, *Val, MST);
1085 } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1086 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1087 assert(PVal && "Expected a pseudo source value");
1088 switch (PVal->kind()) {
1089 case PseudoSourceValue::Stack:
1092 case PseudoSourceValue::GOT:
1095 case PseudoSourceValue::JumpTable:
1098 case PseudoSourceValue::ConstantPool:
1099 OS << "constant-pool";
1101 case PseudoSourceValue::FixedStack: {
1102 int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1103 bool IsFixed = true;
1104 printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1107 case PseudoSourceValue::GlobalValueCallEntry:
1108 OS << "call-entry ";
1109 cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1110 OS, /*PrintType=*/false, MST);
1112 case PseudoSourceValue::ExternalSymbolCallEntry:
1113 OS << "call-entry &";
1114 printLLVMNameWithoutPrefix(
1115 OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1117 case PseudoSourceValue::TargetCustom:
1118 // FIXME: This is not necessarily the correct MIR serialization format for
1119 // a custom pseudo source value, but at least it allows
1120 // -print-machineinstrs to work on a target with custom pseudo source
1123 PVal->printCustom(OS);
1127 MachineOperand::printOperandOffset(OS, getOffset());
1128 if (getBaseAlignment() != getSize())
1129 OS << ", align " << getBaseAlignment();
1130 auto AAInfo = getAAInfo();
1133 AAInfo.TBAA->printAsOperand(OS, MST);
1136 OS << ", !alias.scope ";
1137 AAInfo.Scope->printAsOperand(OS, MST);
1139 if (AAInfo.NoAlias) {
1140 OS << ", !noalias ";
1141 AAInfo.NoAlias->printAsOperand(OS, MST);
1145 getRanges()->printAsOperand(OS, MST);
1147 // FIXME: Implement addrspace printing/parsing in MIR.
1148 // For now, print this even though parsing it is not available in MIR.
1149 if (unsigned AS = getAddrSpace())
1150 OS << ", addrspace " << AS;