1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// \file Methods common to all machine operands.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineOperand.h"
15 #include "llvm/ADT/StringExtras.h"
16 #include "llvm/Analysis/Loads.h"
17 #include "llvm/Analysis/MemoryLocation.h"
18 #include "llvm/CodeGen/MIRPrinter.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #include "llvm/CodeGen/TargetRegisterInfo.h"
24 #include "llvm/Config/llvm-config.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/IR/IRPrintingPasses.h"
27 #include "llvm/IR/ModuleSlotTracker.h"
28 #include "llvm/Target/TargetIntrinsicInfo.h"
29 #include "llvm/Target/TargetMachine.h"
34 PrintRegMaskNumRegs("print-regmask-num-regs",
35 cl::desc("Number of registers to limit to when "
36 "printing regmask operands in IR dumps. "
38 cl::init(32), cl::Hidden);
40 static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
41 if (const MachineInstr *MI = MO.getParent())
42 if (const MachineBasicBlock *MBB = MI->getParent())
43 if (const MachineFunction *MF = MBB->getParent())
47 static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
48 return const_cast<MachineFunction *>(
49 getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
52 void MachineOperand::setReg(unsigned Reg) {
56 // Clear the IsRenamable bit to keep it conservatively correct.
59 // Otherwise, we have to change the register. If this operand is embedded
60 // into a machine function, we need to update the old and new register's
62 if (MachineFunction *MF = getMFIfAvailable(*this)) {
63 MachineRegisterInfo &MRI = MF->getRegInfo();
64 MRI.removeRegOperandFromUseList(this);
65 SmallContents.RegNo = Reg;
66 MRI.addRegOperandToUseList(this);
70 // Otherwise, just change the register, no problem. :)
71 SmallContents.RegNo = Reg;
74 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
75 const TargetRegisterInfo &TRI) {
76 assert(TargetRegisterInfo::isVirtualRegister(Reg));
77 if (SubIdx && getSubReg())
78 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
84 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
85 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
87 Reg = TRI.getSubReg(Reg, getSubReg());
88 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
89 // That won't happen in legal code.
97 /// Change a def to a use, or a use to a def.
98 void MachineOperand::setIsDef(bool Val) {
99 assert(isReg() && "Wrong MachineOperand accessor");
100 assert((!Val || !isDebug()) && "Marking a debug operation as def");
103 assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
104 // MRI may keep uses and defs in different list positions.
105 if (MachineFunction *MF = getMFIfAvailable(*this)) {
106 MachineRegisterInfo &MRI = MF->getRegInfo();
107 MRI.removeRegOperandFromUseList(this);
109 MRI.addRegOperandToUseList(this);
115 bool MachineOperand::isRenamable() const {
116 assert(isReg() && "Wrong MachineOperand accessor");
117 assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&
118 "isRenamable should only be checked on physical registers");
122 const MachineInstr *MI = getParent();
127 return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
129 assert(isUse() && "Reg is not def or use");
130 return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
133 void MachineOperand::setIsRenamable(bool Val) {
134 assert(isReg() && "Wrong MachineOperand accessor");
135 assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&
136 "setIsRenamable should only be called on physical registers");
140 // If this operand is currently a register operand, and if this is in a
141 // function, deregister the operand from the register's use/def list.
142 void MachineOperand::removeRegFromUses() {
143 if (!isReg() || !isOnRegUseList())
146 if (MachineFunction *MF = getMFIfAvailable(*this))
147 MF->getRegInfo().removeRegOperandFromUseList(this);
150 /// ChangeToImmediate - Replace this operand with a new immediate operand of
151 /// the specified value. If an operand is known to be an immediate already,
152 /// the setImm method should be used.
153 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
154 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
158 OpKind = MO_Immediate;
159 Contents.ImmVal = ImmVal;
162 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
163 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
167 OpKind = MO_FPImmediate;
168 Contents.CFP = FPImm;
171 void MachineOperand::ChangeToES(const char *SymName,
172 unsigned char TargetFlags) {
173 assert((!isReg() || !isTied()) &&
174 "Cannot change a tied operand into an external symbol");
178 OpKind = MO_ExternalSymbol;
179 Contents.OffsetedInfo.Val.SymbolName = SymName;
180 setOffset(0); // Offset is always 0.
181 setTargetFlags(TargetFlags);
184 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
185 assert((!isReg() || !isTied()) &&
186 "Cannot change a tied operand into an MCSymbol");
190 OpKind = MO_MCSymbol;
194 void MachineOperand::ChangeToFrameIndex(int Idx) {
195 assert((!isReg() || !isTied()) &&
196 "Cannot change a tied operand into a FrameIndex");
200 OpKind = MO_FrameIndex;
204 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
205 unsigned char TargetFlags) {
206 assert((!isReg() || !isTied()) &&
207 "Cannot change a tied operand into a FrameIndex");
211 OpKind = MO_TargetIndex;
214 setTargetFlags(TargetFlags);
217 /// ChangeToRegister - Replace this operand with a new register operand of
218 /// the specified value. If an operand is known to be an register already,
219 /// the setReg method should be used.
220 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
221 bool isKill, bool isDead, bool isUndef,
223 MachineRegisterInfo *RegInfo = nullptr;
224 if (MachineFunction *MF = getMFIfAvailable(*this))
225 RegInfo = &MF->getRegInfo();
226 // If this operand is already a register operand, remove it from the
227 // register's use/def lists.
228 bool WasReg = isReg();
229 if (RegInfo && WasReg)
230 RegInfo->removeRegOperandFromUseList(this);
232 // Change this to a register and set the reg#.
233 assert(!(isDead && !isDef) && "Dead flag on non-def");
234 assert(!(isKill && isDef) && "Kill flag on def");
235 OpKind = MO_Register;
236 SmallContents.RegNo = Reg;
237 SubReg_TargetFlags = 0;
240 IsDeadOrKill = isKill | isDead;
243 IsInternalRead = false;
244 IsEarlyClobber = false;
246 // Ensure isOnRegUseList() returns false.
247 Contents.Reg.Prev = nullptr;
248 // Preserve the tie when the operand was already a register.
252 // If this operand is embedded in a function, add the operand to the
253 // register's use/def list.
255 RegInfo->addRegOperandToUseList(this);
258 /// isIdenticalTo - Return true if this operand is identical to the specified
259 /// operand. Note that this should stay in sync with the hash_value overload
261 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
262 if (getType() != Other.getType() ||
263 getTargetFlags() != Other.getTargetFlags())
267 case MachineOperand::MO_Register:
268 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
269 getSubReg() == Other.getSubReg();
270 case MachineOperand::MO_Immediate:
271 return getImm() == Other.getImm();
272 case MachineOperand::MO_CImmediate:
273 return getCImm() == Other.getCImm();
274 case MachineOperand::MO_FPImmediate:
275 return getFPImm() == Other.getFPImm();
276 case MachineOperand::MO_MachineBasicBlock:
277 return getMBB() == Other.getMBB();
278 case MachineOperand::MO_FrameIndex:
279 return getIndex() == Other.getIndex();
280 case MachineOperand::MO_ConstantPoolIndex:
281 case MachineOperand::MO_TargetIndex:
282 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
283 case MachineOperand::MO_JumpTableIndex:
284 return getIndex() == Other.getIndex();
285 case MachineOperand::MO_GlobalAddress:
286 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
287 case MachineOperand::MO_ExternalSymbol:
288 return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
289 getOffset() == Other.getOffset();
290 case MachineOperand::MO_BlockAddress:
291 return getBlockAddress() == Other.getBlockAddress() &&
292 getOffset() == Other.getOffset();
293 case MachineOperand::MO_RegisterMask:
294 case MachineOperand::MO_RegisterLiveOut: {
295 // Shallow compare of the two RegMasks
296 const uint32_t *RegMask = getRegMask();
297 const uint32_t *OtherRegMask = Other.getRegMask();
298 if (RegMask == OtherRegMask)
301 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
302 // Calculate the size of the RegMask
303 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
304 unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
306 // Deep compare of the two RegMasks
307 return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
309 // We don't know the size of the RegMask, so we can't deep compare the two
313 case MachineOperand::MO_MCSymbol:
314 return getMCSymbol() == Other.getMCSymbol();
315 case MachineOperand::MO_CFIIndex:
316 return getCFIIndex() == Other.getCFIIndex();
317 case MachineOperand::MO_Metadata:
318 return getMetadata() == Other.getMetadata();
319 case MachineOperand::MO_IntrinsicID:
320 return getIntrinsicID() == Other.getIntrinsicID();
321 case MachineOperand::MO_Predicate:
322 return getPredicate() == Other.getPredicate();
324 llvm_unreachable("Invalid machine operand type");
327 // Note: this must stay exactly in sync with isIdenticalTo above.
328 hash_code llvm::hash_value(const MachineOperand &MO) {
329 switch (MO.getType()) {
330 case MachineOperand::MO_Register:
331 // Register operands don't have target flags.
332 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
333 case MachineOperand::MO_Immediate:
334 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
335 case MachineOperand::MO_CImmediate:
336 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
337 case MachineOperand::MO_FPImmediate:
338 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
339 case MachineOperand::MO_MachineBasicBlock:
340 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
341 case MachineOperand::MO_FrameIndex:
342 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
343 case MachineOperand::MO_ConstantPoolIndex:
344 case MachineOperand::MO_TargetIndex:
345 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
347 case MachineOperand::MO_JumpTableIndex:
348 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
349 case MachineOperand::MO_ExternalSymbol:
350 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
352 case MachineOperand::MO_GlobalAddress:
353 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
355 case MachineOperand::MO_BlockAddress:
356 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
358 case MachineOperand::MO_RegisterMask:
359 case MachineOperand::MO_RegisterLiveOut:
360 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
361 case MachineOperand::MO_Metadata:
362 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
363 case MachineOperand::MO_MCSymbol:
364 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
365 case MachineOperand::MO_CFIIndex:
366 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
367 case MachineOperand::MO_IntrinsicID:
368 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
369 case MachineOperand::MO_Predicate:
370 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
372 llvm_unreachable("Invalid machine operand type");
375 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
377 static void tryToGetTargetInfo(const MachineOperand &MO,
378 const TargetRegisterInfo *&TRI,
379 const TargetIntrinsicInfo *&IntrinsicInfo) {
380 if (const MachineFunction *MF = getMFIfAvailable(MO)) {
381 TRI = MF->getSubtarget().getRegisterInfo();
382 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
386 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
387 const auto *TII = MF.getSubtarget().getInstrInfo();
388 assert(TII && "expected instruction info");
389 auto Indices = TII->getSerializableTargetIndices();
390 auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
391 return I.first == Index;
393 if (Found != Indices.end())
394 return Found->second;
398 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
399 auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
400 for (const auto &I : Flags) {
408 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
409 const TargetRegisterInfo *TRI) {
411 OS << "%dwarfreg." << DwarfReg;
415 int Reg = TRI->getLLVMRegNum(DwarfReg, true);
420 OS << printReg(Reg, TRI);
423 static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
424 ModuleSlotTracker &MST) {
427 printLLVMNameWithoutPrefix(OS, BB.getName());
431 if (const Function *F = BB.getParent()) {
432 if (F == MST.getCurrentFunction()) {
433 Slot = MST.getLocalSlot(&BB);
434 } else if (const Module *M = F->getParent()) {
435 ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
436 CustomMST.incorporateFunction(*F);
437 Slot = CustomMST.getLocalSlot(&BB);
441 MachineOperand::printIRSlotNumber(OS, *Slot);
446 static void printIRValueReference(raw_ostream &OS, const Value &V,
447 ModuleSlotTracker &MST) {
448 if (isa<GlobalValue>(V)) {
449 V.printAsOperand(OS, /*PrintType=*/false, MST);
452 if (isa<Constant>(V)) {
453 // Machine memory operands can load/store to/from constant value pointers.
455 V.printAsOperand(OS, /*PrintType=*/true, MST);
461 printLLVMNameWithoutPrefix(OS, V.getName());
464 int Slot = MST.getCurrentFunction() ? MST.getLocalSlot(&V) : -1;
465 MachineOperand::printIRSlotNumber(OS, Slot);
468 static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
470 SmallVectorImpl<StringRef> &SSNs) {
472 case SyncScope::System:
476 Context.getSyncScopeNames(SSNs);
478 OS << "syncscope(\"";
479 printEscapedString(SSNs[SSID], OS);
485 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
487 auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
488 for (const auto &I : Flags) {
489 if (I.first == TMMOFlag) {
496 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
497 const MachineFrameInfo *MFI) {
500 IsFixed = MFI->isFixedObjectIndex(FrameIndex);
501 if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
502 if (Alloca->hasName())
503 Name = Alloca->getName();
505 FrameIndex -= MFI->getObjectIndexBegin();
507 MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
510 void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,
511 const TargetRegisterInfo *TRI) {
514 OS << TRI->getSubRegIndexName(Index);
519 void MachineOperand::printTargetFlags(raw_ostream &OS,
520 const MachineOperand &Op) {
521 if (!Op.getTargetFlags())
523 const MachineFunction *MF = getMFIfAvailable(Op);
527 const auto *TII = MF->getSubtarget().getInstrInfo();
528 assert(TII && "expected instruction info");
529 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
530 OS << "target-flags(";
531 const bool HasDirectFlags = Flags.first;
532 const bool HasBitmaskFlags = Flags.second;
533 if (!HasDirectFlags && !HasBitmaskFlags) {
537 if (HasDirectFlags) {
538 if (const auto *Name = getTargetFlagName(TII, Flags.first))
541 OS << "<unknown target flag>";
543 if (!HasBitmaskFlags) {
547 bool IsCommaNeeded = HasDirectFlags;
548 unsigned BitMask = Flags.second;
549 auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
550 for (const auto &Mask : BitMasks) {
551 // Check if the flag's bitmask has the bits of the current mask set.
552 if ((BitMask & Mask.first) == Mask.first) {
555 IsCommaNeeded = true;
557 // Clear the bits which were serialized from the flag's bitmask.
558 BitMask &= ~(Mask.first);
562 // When the resulting flag's bitmask isn't zero, we know that we didn't
563 // serialize all of the bit flags.
566 OS << "<unknown bitmask target flag>";
571 void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) {
572 OS << "<mcsymbol " << Sym << ">";
575 void MachineOperand::printStackObjectReference(raw_ostream &OS,
577 bool IsFixed, StringRef Name) {
579 OS << "%fixed-stack." << FrameIndex;
583 OS << "%stack." << FrameIndex;
588 void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) {
592 OS << " - " << -Offset;
595 OS << " + " << Offset;
598 void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) {
605 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
606 const TargetRegisterInfo *TRI) {
607 switch (CFI.getOperation()) {
608 case MCCFIInstruction::OpSameValue:
610 if (MCSymbol *Label = CFI.getLabel())
611 MachineOperand::printSymbol(OS, *Label);
612 printCFIRegister(CFI.getRegister(), OS, TRI);
614 case MCCFIInstruction::OpRememberState:
615 OS << "remember_state ";
616 if (MCSymbol *Label = CFI.getLabel())
617 MachineOperand::printSymbol(OS, *Label);
619 case MCCFIInstruction::OpRestoreState:
620 OS << "restore_state ";
621 if (MCSymbol *Label = CFI.getLabel())
622 MachineOperand::printSymbol(OS, *Label);
624 case MCCFIInstruction::OpOffset:
626 if (MCSymbol *Label = CFI.getLabel())
627 MachineOperand::printSymbol(OS, *Label);
628 printCFIRegister(CFI.getRegister(), OS, TRI);
629 OS << ", " << CFI.getOffset();
631 case MCCFIInstruction::OpDefCfaRegister:
632 OS << "def_cfa_register ";
633 if (MCSymbol *Label = CFI.getLabel())
634 MachineOperand::printSymbol(OS, *Label);
635 printCFIRegister(CFI.getRegister(), OS, TRI);
637 case MCCFIInstruction::OpDefCfaOffset:
638 OS << "def_cfa_offset ";
639 if (MCSymbol *Label = CFI.getLabel())
640 MachineOperand::printSymbol(OS, *Label);
641 OS << CFI.getOffset();
643 case MCCFIInstruction::OpDefCfa:
645 if (MCSymbol *Label = CFI.getLabel())
646 MachineOperand::printSymbol(OS, *Label);
647 printCFIRegister(CFI.getRegister(), OS, TRI);
648 OS << ", " << CFI.getOffset();
650 case MCCFIInstruction::OpRelOffset:
652 if (MCSymbol *Label = CFI.getLabel())
653 MachineOperand::printSymbol(OS, *Label);
654 printCFIRegister(CFI.getRegister(), OS, TRI);
655 OS << ", " << CFI.getOffset();
657 case MCCFIInstruction::OpAdjustCfaOffset:
658 OS << "adjust_cfa_offset ";
659 if (MCSymbol *Label = CFI.getLabel())
660 MachineOperand::printSymbol(OS, *Label);
661 OS << CFI.getOffset();
663 case MCCFIInstruction::OpRestore:
665 if (MCSymbol *Label = CFI.getLabel())
666 MachineOperand::printSymbol(OS, *Label);
667 printCFIRegister(CFI.getRegister(), OS, TRI);
669 case MCCFIInstruction::OpEscape: {
671 if (MCSymbol *Label = CFI.getLabel())
672 MachineOperand::printSymbol(OS, *Label);
673 if (!CFI.getValues().empty()) {
674 size_t e = CFI.getValues().size() - 1;
675 for (size_t i = 0; i < e; ++i)
676 OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
677 OS << format("0x%02x", uint8_t(CFI.getValues()[e])) << ", ";
681 case MCCFIInstruction::OpUndefined:
683 if (MCSymbol *Label = CFI.getLabel())
684 MachineOperand::printSymbol(OS, *Label);
685 printCFIRegister(CFI.getRegister(), OS, TRI);
687 case MCCFIInstruction::OpRegister:
689 if (MCSymbol *Label = CFI.getLabel())
690 MachineOperand::printSymbol(OS, *Label);
691 printCFIRegister(CFI.getRegister(), OS, TRI);
693 printCFIRegister(CFI.getRegister2(), OS, TRI);
695 case MCCFIInstruction::OpWindowSave:
696 OS << "window_save ";
697 if (MCSymbol *Label = CFI.getLabel())
698 MachineOperand::printSymbol(OS, *Label);
700 case MCCFIInstruction::OpNegateRAState:
701 OS << "negate_ra_sign_state ";
702 if (MCSymbol *Label = CFI.getLabel())
703 MachineOperand::printSymbol(OS, *Label);
706 // TODO: Print the other CFI Operations.
707 OS << "<unserializable cfi directive>";
712 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
713 const TargetIntrinsicInfo *IntrinsicInfo) const {
714 print(OS, LLT{}, TRI, IntrinsicInfo);
717 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
718 const TargetRegisterInfo *TRI,
719 const TargetIntrinsicInfo *IntrinsicInfo) const {
720 tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
721 ModuleSlotTracker DummyMST(nullptr);
722 print(OS, DummyMST, TypeToPrint, /*PrintDef=*/false, /*IsStandalone=*/true,
723 /*ShouldPrintRegisterTies=*/true,
724 /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
727 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
728 LLT TypeToPrint, bool PrintDef, bool IsStandalone,
729 bool ShouldPrintRegisterTies,
730 unsigned TiedOperandIdx,
731 const TargetRegisterInfo *TRI,
732 const TargetIntrinsicInfo *IntrinsicInfo) const {
733 printTargetFlags(OS, *this);
735 case MachineOperand::MO_Register: {
736 unsigned Reg = getReg();
738 OS << (isDef() ? "implicit-def " : "implicit ");
739 else if (PrintDef && isDef())
740 // Print the 'def' flag only when the operand is defined after '='.
742 if (isInternalRead())
750 if (isEarlyClobber())
751 OS << "early-clobber ";
752 if (TargetRegisterInfo::isPhysicalRegister(getReg()) && isRenamable())
754 // isDebug() is exactly true for register operands of a DBG_VALUE. So we
755 // simply infer it when parsing and do not need to print it.
757 const MachineRegisterInfo *MRI = nullptr;
758 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
759 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
760 MRI = &MF->getRegInfo();
764 OS << printReg(Reg, TRI, 0, MRI);
765 // Print the sub register.
766 if (unsigned SubReg = getSubReg()) {
768 OS << '.' << TRI->getSubRegIndexName(SubReg);
770 OS << ".subreg" << SubReg;
772 // Print the register class / bank.
773 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
774 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
775 const MachineRegisterInfo &MRI = MF->getRegInfo();
776 if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
778 OS << printRegClassOrBank(Reg, MRI, TRI);
783 if (ShouldPrintRegisterTies && isTied() && !isDef())
784 OS << "(tied-def " << TiedOperandIdx << ")";
786 if (TypeToPrint.isValid())
787 OS << '(' << TypeToPrint << ')';
790 case MachineOperand::MO_Immediate:
793 case MachineOperand::MO_CImmediate:
794 getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
796 case MachineOperand::MO_FPImmediate:
797 getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
799 case MachineOperand::MO_MachineBasicBlock:
800 OS << printMBBReference(*getMBB());
802 case MachineOperand::MO_FrameIndex: {
803 int FrameIndex = getIndex();
804 bool IsFixed = false;
805 const MachineFrameInfo *MFI = nullptr;
806 if (const MachineFunction *MF = getMFIfAvailable(*this))
807 MFI = &MF->getFrameInfo();
808 printFrameIndex(OS, FrameIndex, IsFixed, MFI);
811 case MachineOperand::MO_ConstantPoolIndex:
812 OS << "%const." << getIndex();
813 printOperandOffset(OS, getOffset());
815 case MachineOperand::MO_TargetIndex: {
816 OS << "target-index(";
817 const char *Name = "<unknown>";
818 if (const MachineFunction *MF = getMFIfAvailable(*this))
819 if (const auto *TargetIndexName = getTargetIndexName(*MF, getIndex()))
820 Name = TargetIndexName;
822 printOperandOffset(OS, getOffset());
825 case MachineOperand::MO_JumpTableIndex:
826 OS << printJumpTableEntryReference(getIndex());
828 case MachineOperand::MO_GlobalAddress:
829 getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
830 printOperandOffset(OS, getOffset());
832 case MachineOperand::MO_ExternalSymbol: {
833 StringRef Name = getSymbolName();
838 printLLVMNameWithoutPrefix(OS, Name);
840 printOperandOffset(OS, getOffset());
843 case MachineOperand::MO_BlockAddress: {
844 OS << "blockaddress(";
845 getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
848 printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
850 MachineOperand::printOperandOffset(OS, getOffset());
853 case MachineOperand::MO_RegisterMask: {
856 unsigned NumRegsInMask = 0;
857 unsigned NumRegsEmitted = 0;
858 for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
859 unsigned MaskWord = i / 32;
860 unsigned MaskBit = i % 32;
861 if (getRegMask()[MaskWord] & (1 << MaskBit)) {
862 if (PrintRegMaskNumRegs < 0 ||
863 NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
864 OS << " " << printReg(i, TRI);
870 if (NumRegsEmitted != NumRegsInMask)
871 OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
878 case MachineOperand::MO_RegisterLiveOut: {
879 const uint32_t *RegMask = getRegLiveOut();
884 bool IsCommaNeeded = false;
885 for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
886 if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
889 OS << printReg(Reg, TRI);
890 IsCommaNeeded = true;
897 case MachineOperand::MO_Metadata:
898 getMetadata()->printAsOperand(OS, MST);
900 case MachineOperand::MO_MCSymbol:
901 printSymbol(OS, *getMCSymbol());
903 case MachineOperand::MO_CFIIndex: {
904 if (const MachineFunction *MF = getMFIfAvailable(*this))
905 printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
907 OS << "<cfi directive>";
910 case MachineOperand::MO_IntrinsicID: {
911 Intrinsic::ID ID = getIntrinsicID();
912 if (ID < Intrinsic::num_intrinsics)
913 OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
914 else if (IntrinsicInfo)
915 OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
917 OS << "intrinsic(" << ID << ')';
920 case MachineOperand::MO_Predicate: {
921 auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
922 OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
923 << CmpInst::getPredicateName(Pred) << ')';
929 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
930 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
933 //===----------------------------------------------------------------------===//
934 // MachineMemOperand Implementation
935 //===----------------------------------------------------------------------===//
937 /// getAddrSpace - Return the LLVM IR address space number that this pointer
939 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
941 /// isDereferenceable - Return true if V is always dereferenceable for
942 /// Offset + Size byte.
943 bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
944 const DataLayout &DL) const {
945 if (!V.is<const Value *>())
948 const Value *BasePtr = V.get<const Value *>();
949 if (BasePtr == nullptr)
952 return isDereferenceableAndAlignedPointer(
953 BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
956 /// getConstantPool - Return a MachinePointerInfo record that refers to the
958 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
959 return MachinePointerInfo(MF.getPSVManager().getConstantPool());
962 /// getFixedStack - Return a MachinePointerInfo record that refers to the
963 /// the specified FrameIndex.
964 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
965 int FI, int64_t Offset) {
966 return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
969 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
970 return MachinePointerInfo(MF.getPSVManager().getJumpTable());
973 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
974 return MachinePointerInfo(MF.getPSVManager().getGOT());
977 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
978 int64_t Offset, uint8_t ID) {
979 return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
982 MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
983 return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
986 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
987 uint64_t s, uint64_t a,
988 const AAMDNodes &AAInfo,
989 const MDNode *Ranges, SyncScope::ID SSID,
990 AtomicOrdering Ordering,
991 AtomicOrdering FailureOrdering)
992 : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
993 AAInfo(AAInfo), Ranges(Ranges) {
994 assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
995 isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
996 "invalid pointer value");
997 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
998 assert((isLoad() || isStore()) && "Not a load/store!");
1000 AtomicInfo.SSID = static_cast<unsigned>(SSID);
1001 assert(getSyncScopeID() == SSID && "Value truncated");
1002 AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1003 assert(getOrdering() == Ordering && "Value truncated");
1004 AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1005 assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1008 /// Profile - Gather unique data for the object.
1010 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
1011 ID.AddInteger(getOffset());
1012 ID.AddInteger(Size);
1013 ID.AddPointer(getOpaqueValue());
1014 ID.AddInteger(getFlags());
1015 ID.AddInteger(getBaseAlignment());
1018 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
1019 // The Value and Offset may differ due to CSE. But the flags and size
1020 // should be the same.
1021 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1022 assert(MMO->getSize() == getSize() && "Size mismatch!");
1024 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
1025 // Update the alignment value.
1026 BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
1027 // Also update the base and offset, because the new alignment may
1028 // not be applicable with the old ones.
1029 PtrInfo = MMO->PtrInfo;
1033 /// getAlignment - Return the minimum known alignment in bytes of the
1034 /// actual memory reference.
1035 uint64_t MachineMemOperand::getAlignment() const {
1036 return MinAlign(getBaseAlignment(), getOffset());
1039 void MachineMemOperand::print(raw_ostream &OS) const {
1040 ModuleSlotTracker DummyMST(nullptr);
1041 print(OS, DummyMST);
1044 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
1045 SmallVector<StringRef, 0> SSNs;
1047 print(OS, MST, SSNs, Ctx, nullptr, nullptr);
1050 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
1051 SmallVectorImpl<StringRef> &SSNs,
1052 const LLVMContext &Context,
1053 const MachineFrameInfo *MFI,
1054 const TargetInstrInfo *TII) const {
1058 if (isNonTemporal())
1059 OS << "non-temporal ";
1060 if (isDereferenceable())
1061 OS << "dereferenceable ";
1064 if (getFlags() & MachineMemOperand::MOTargetFlag1)
1065 OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag1)
1067 if (getFlags() & MachineMemOperand::MOTargetFlag2)
1068 OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag2)
1070 if (getFlags() & MachineMemOperand::MOTargetFlag3)
1071 OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag3)
1074 assert((isLoad() || isStore()) &&
1075 "machine memory operand must be a load or store (or both)");
1081 printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1083 if (getOrdering() != AtomicOrdering::NotAtomic)
1084 OS << toIRString(getOrdering()) << ' ';
1085 if (getFailureOrdering() != AtomicOrdering::NotAtomic)
1086 OS << toIRString(getFailureOrdering()) << ' ';
1088 if (getSize() == MemoryLocation::UnknownSize)
1089 OS << "unknown-size";
1093 if (const Value *Val = getValue()) {
1094 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1095 printIRValueReference(OS, *Val, MST);
1096 } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1097 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1098 assert(PVal && "Expected a pseudo source value");
1099 switch (PVal->kind()) {
1100 case PseudoSourceValue::Stack:
1103 case PseudoSourceValue::GOT:
1106 case PseudoSourceValue::JumpTable:
1109 case PseudoSourceValue::ConstantPool:
1110 OS << "constant-pool";
1112 case PseudoSourceValue::FixedStack: {
1113 int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1114 bool IsFixed = true;
1115 printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1118 case PseudoSourceValue::GlobalValueCallEntry:
1119 OS << "call-entry ";
1120 cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1121 OS, /*PrintType=*/false, MST);
1123 case PseudoSourceValue::ExternalSymbolCallEntry:
1124 OS << "call-entry &";
1125 printLLVMNameWithoutPrefix(
1126 OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1128 case PseudoSourceValue::TargetCustom:
1129 // FIXME: This is not necessarily the correct MIR serialization format for
1130 // a custom pseudo source value, but at least it allows
1131 // -print-machineinstrs to work on a target with custom pseudo source
1134 PVal->printCustom(OS);
1138 MachineOperand::printOperandOffset(OS, getOffset());
1139 if (getBaseAlignment() != getSize())
1140 OS << ", align " << getBaseAlignment();
1141 auto AAInfo = getAAInfo();
1144 AAInfo.TBAA->printAsOperand(OS, MST);
1147 OS << ", !alias.scope ";
1148 AAInfo.Scope->printAsOperand(OS, MST);
1150 if (AAInfo.NoAlias) {
1151 OS << ", !noalias ";
1152 AAInfo.NoAlias->printAsOperand(OS, MST);
1156 getRanges()->printAsOperand(OS, MST);
1158 // FIXME: Implement addrspace printing/parsing in MIR.
1159 // For now, print this even though parsing it is not available in MIR.
1160 if (unsigned AS = getAddrSpace())
1161 OS << ", addrspace " << AS;