1 //===- MachineSink.cpp - Sinking for machine instructions -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass moves instructions into successor blocks when possible, so that
11 // they aren't executed on paths where their results aren't needed.
13 // This pass is not intended to be a replacement or a complete alternative
14 // for an LLVM-IR-level sinking pass. It is only designed to sink simple
15 // constructs that are not exposed before lowering and instruction selection.
17 //===----------------------------------------------------------------------===//
19 #include "llvm/ADT/SetVector.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/SparseBitVector.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/Analysis/AliasAnalysis.h"
25 #include "llvm/CodeGen/MachineBasicBlock.h"
26 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
27 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
28 #include "llvm/CodeGen/MachineDominators.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineInstr.h"
32 #include "llvm/CodeGen/MachineLoopInfo.h"
33 #include "llvm/CodeGen/MachineOperand.h"
34 #include "llvm/CodeGen/MachinePostDominators.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/TargetInstrInfo.h"
37 #include "llvm/CodeGen/TargetRegisterInfo.h"
38 #include "llvm/CodeGen/TargetSubtargetInfo.h"
39 #include "llvm/IR/BasicBlock.h"
40 #include "llvm/IR/LLVMContext.h"
41 #include "llvm/IR/DebugInfoMetadata.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/BranchProbability.h"
44 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/raw_ostream.h"
56 #define DEBUG_TYPE "machine-sink"
59 SplitEdges("machine-sink-split",
60 cl::desc("Split critical edges during machine sinking"),
61 cl::init(true), cl::Hidden);
64 UseBlockFreqInfo("machine-sink-bfi",
65 cl::desc("Use block frequency info to find successors to sink"),
66 cl::init(true), cl::Hidden);
68 static cl::opt<unsigned> SplitEdgeProbabilityThreshold(
69 "machine-sink-split-probability-threshold",
71 "Percentage threshold for splitting single-instruction critical edge. "
72 "If the branch threshold is higher than this threshold, we allow "
73 "speculative execution of up to 1 instruction to avoid branching to "
74 "splitted critical edge"),
75 cl::init(40), cl::Hidden);
77 STATISTIC(NumSunk, "Number of machine instructions sunk");
78 STATISTIC(NumSplit, "Number of critical edges split");
79 STATISTIC(NumCoalesces, "Number of copies coalesced");
80 STATISTIC(NumPostRACopySink, "Number of copies sunk after RA");
84 class MachineSinking : public MachineFunctionPass {
85 const TargetInstrInfo *TII;
86 const TargetRegisterInfo *TRI;
87 MachineRegisterInfo *MRI; // Machine register information
88 MachineDominatorTree *DT; // Machine dominator tree
89 MachinePostDominatorTree *PDT; // Machine post dominator tree
91 const MachineBlockFrequencyInfo *MBFI;
92 const MachineBranchProbabilityInfo *MBPI;
95 // Remember which edges have been considered for breaking.
96 SmallSet<std::pair<MachineBasicBlock*, MachineBasicBlock*>, 8>
98 // Remember which edges we are about to split.
99 // This is different from CEBCandidates since those edges
101 SetVector<std::pair<MachineBasicBlock *, MachineBasicBlock *>> ToSplit;
103 SparseBitVector<> RegsToClearKillFlags;
105 using AllSuccsCache =
106 std::map<MachineBasicBlock *, SmallVector<MachineBasicBlock *, 4>>;
109 static char ID; // Pass identification
111 MachineSinking() : MachineFunctionPass(ID) {
112 initializeMachineSinkingPass(*PassRegistry::getPassRegistry());
115 bool runOnMachineFunction(MachineFunction &MF) override;
117 void getAnalysisUsage(AnalysisUsage &AU) const override {
118 AU.setPreservesCFG();
119 MachineFunctionPass::getAnalysisUsage(AU);
120 AU.addRequired<AAResultsWrapperPass>();
121 AU.addRequired<MachineDominatorTree>();
122 AU.addRequired<MachinePostDominatorTree>();
123 AU.addRequired<MachineLoopInfo>();
124 AU.addRequired<MachineBranchProbabilityInfo>();
125 AU.addPreserved<MachineDominatorTree>();
126 AU.addPreserved<MachinePostDominatorTree>();
127 AU.addPreserved<MachineLoopInfo>();
128 if (UseBlockFreqInfo)
129 AU.addRequired<MachineBlockFrequencyInfo>();
132 void releaseMemory() override {
133 CEBCandidates.clear();
137 bool ProcessBlock(MachineBasicBlock &MBB);
138 bool isWorthBreakingCriticalEdge(MachineInstr &MI,
139 MachineBasicBlock *From,
140 MachineBasicBlock *To);
142 /// Postpone the splitting of the given critical
143 /// edge (\p From, \p To).
145 /// We do not split the edges on the fly. Indeed, this invalidates
146 /// the dominance information and thus triggers a lot of updates
147 /// of that information underneath.
148 /// Instead, we postpone all the splits after each iteration of
149 /// the main loop. That way, the information is at least valid
150 /// for the lifetime of an iteration.
152 /// \return True if the edge is marked as toSplit, false otherwise.
153 /// False can be returned if, for instance, this is not profitable.
154 bool PostponeSplitCriticalEdge(MachineInstr &MI,
155 MachineBasicBlock *From,
156 MachineBasicBlock *To,
158 bool SinkInstruction(MachineInstr &MI, bool &SawStore,
160 AllSuccsCache &AllSuccessors);
161 bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB,
162 MachineBasicBlock *DefMBB,
163 bool &BreakPHIEdge, bool &LocalUse) const;
164 MachineBasicBlock *FindSuccToSinkTo(MachineInstr &MI, MachineBasicBlock *MBB,
165 bool &BreakPHIEdge, AllSuccsCache &AllSuccessors);
166 bool isProfitableToSinkTo(unsigned Reg, MachineInstr &MI,
167 MachineBasicBlock *MBB,
168 MachineBasicBlock *SuccToSinkTo,
169 AllSuccsCache &AllSuccessors);
171 bool PerformTrivialForwardCoalescing(MachineInstr &MI,
172 MachineBasicBlock *MBB);
174 SmallVector<MachineBasicBlock *, 4> &
175 GetAllSortedSuccessors(MachineInstr &MI, MachineBasicBlock *MBB,
176 AllSuccsCache &AllSuccessors) const;
179 } // end anonymous namespace
181 char MachineSinking::ID = 0;
183 char &llvm::MachineSinkingID = MachineSinking::ID;
185 INITIALIZE_PASS_BEGIN(MachineSinking, DEBUG_TYPE,
186 "Machine code sinking", false, false)
187 INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
188 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
189 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
190 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
191 INITIALIZE_PASS_END(MachineSinking, DEBUG_TYPE,
192 "Machine code sinking", false, false)
194 bool MachineSinking::PerformTrivialForwardCoalescing(MachineInstr &MI,
195 MachineBasicBlock *MBB) {
199 unsigned SrcReg = MI.getOperand(1).getReg();
200 unsigned DstReg = MI.getOperand(0).getReg();
201 if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
202 !TargetRegisterInfo::isVirtualRegister(DstReg) ||
203 !MRI->hasOneNonDBGUse(SrcReg))
206 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
207 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg);
211 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
212 if (DefMI->isCopyLike())
214 LLVM_DEBUG(dbgs() << "Coalescing: " << *DefMI);
215 LLVM_DEBUG(dbgs() << "*** to: " << MI);
216 MRI->replaceRegWith(DstReg, SrcReg);
217 MI.eraseFromParent();
219 // Conservatively, clear any kill flags, since it's possible that they are no
221 MRI->clearKillFlags(SrcReg);
227 /// AllUsesDominatedByBlock - Return true if all uses of the specified register
228 /// occur in blocks dominated by the specified block. If any use is in the
229 /// definition block, then return false since it is never legal to move def
232 MachineSinking::AllUsesDominatedByBlock(unsigned Reg,
233 MachineBasicBlock *MBB,
234 MachineBasicBlock *DefMBB,
236 bool &LocalUse) const {
237 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
238 "Only makes sense for vregs");
240 // Ignore debug uses because debug info doesn't affect the code.
241 if (MRI->use_nodbg_empty(Reg))
244 // BreakPHIEdge is true if all the uses are in the successor MBB being sunken
245 // into and they are all PHI nodes. In this case, machine-sink must break
246 // the critical edge first. e.g.
248 // %bb.1: derived from LLVM BB %bb4.preheader
249 // Predecessors according to CFG: %bb.0
251 // %reg16385 = DEC64_32r %reg16437, implicit-def dead %eflags
253 // JE_4 <%bb.37>, implicit %eflags
254 // Successors according to CFG: %bb.37 %bb.2
256 // %bb.2: derived from LLVM BB %bb.nph
257 // Predecessors according to CFG: %bb.0 %bb.1
258 // %reg16386 = PHI %reg16434, %bb.0, %reg16385, %bb.1
260 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
261 MachineInstr *UseInst = MO.getParent();
262 unsigned OpNo = &MO - &UseInst->getOperand(0);
263 MachineBasicBlock *UseBlock = UseInst->getParent();
264 if (!(UseBlock == MBB && UseInst->isPHI() &&
265 UseInst->getOperand(OpNo+1).getMBB() == DefMBB)) {
266 BreakPHIEdge = false;
273 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
274 // Determine the block of the use.
275 MachineInstr *UseInst = MO.getParent();
276 unsigned OpNo = &MO - &UseInst->getOperand(0);
277 MachineBasicBlock *UseBlock = UseInst->getParent();
278 if (UseInst->isPHI()) {
279 // PHI nodes use the operand in the predecessor block, not the block with
281 UseBlock = UseInst->getOperand(OpNo+1).getMBB();
282 } else if (UseBlock == DefMBB) {
287 // Check that it dominates.
288 if (!DT->dominates(MBB, UseBlock))
295 bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
296 if (skipFunction(MF.getFunction()))
299 LLVM_DEBUG(dbgs() << "******** Machine Sinking ********\n");
301 TII = MF.getSubtarget().getInstrInfo();
302 TRI = MF.getSubtarget().getRegisterInfo();
303 MRI = &MF.getRegInfo();
304 DT = &getAnalysis<MachineDominatorTree>();
305 PDT = &getAnalysis<MachinePostDominatorTree>();
306 LI = &getAnalysis<MachineLoopInfo>();
307 MBFI = UseBlockFreqInfo ? &getAnalysis<MachineBlockFrequencyInfo>() : nullptr;
308 MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
309 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
311 bool EverMadeChange = false;
314 bool MadeChange = false;
316 // Process all basic blocks.
317 CEBCandidates.clear();
320 MadeChange |= ProcessBlock(MBB);
322 // If we have anything we marked as toSplit, split it now.
323 for (auto &Pair : ToSplit) {
324 auto NewSucc = Pair.first->SplitCriticalEdge(Pair.second, *this);
325 if (NewSucc != nullptr) {
326 LLVM_DEBUG(dbgs() << " *** Splitting critical edge: "
327 << printMBBReference(*Pair.first) << " -- "
328 << printMBBReference(*NewSucc) << " -- "
329 << printMBBReference(*Pair.second) << '\n');
333 LLVM_DEBUG(dbgs() << " *** Not legal to break critical edge\n");
335 // If this iteration over the code changed anything, keep iterating.
336 if (!MadeChange) break;
337 EverMadeChange = true;
340 // Now clear any kill flags for recorded registers.
341 for (auto I : RegsToClearKillFlags)
342 MRI->clearKillFlags(I);
343 RegsToClearKillFlags.clear();
345 return EverMadeChange;
348 bool MachineSinking::ProcessBlock(MachineBasicBlock &MBB) {
349 // Can't sink anything out of a block that has less than two successors.
350 if (MBB.succ_size() <= 1 || MBB.empty()) return false;
352 // Don't bother sinking code out of unreachable blocks. In addition to being
353 // unprofitable, it can also lead to infinite looping, because in an
354 // unreachable loop there may be nowhere to stop.
355 if (!DT->isReachableFromEntry(&MBB)) return false;
357 bool MadeChange = false;
359 // Cache all successors, sorted by frequency info and loop depth.
360 AllSuccsCache AllSuccessors;
362 // Walk the basic block bottom-up. Remember if we saw a store.
363 MachineBasicBlock::iterator I = MBB.end();
365 bool ProcessedBegin, SawStore = false;
367 MachineInstr &MI = *I; // The instruction to sink.
369 // Predecrement I (if it's not begin) so that it isn't invalidated by
371 ProcessedBegin = I == MBB.begin();
375 if (MI.isDebugInstr())
378 bool Joined = PerformTrivialForwardCoalescing(MI, &MBB);
384 if (SinkInstruction(MI, SawStore, AllSuccessors)) {
389 // If we just processed the first instruction in the block, we're done.
390 } while (!ProcessedBegin);
395 bool MachineSinking::isWorthBreakingCriticalEdge(MachineInstr &MI,
396 MachineBasicBlock *From,
397 MachineBasicBlock *To) {
398 // FIXME: Need much better heuristics.
400 // If the pass has already considered breaking this edge (during this pass
401 // through the function), then let's go ahead and break it. This means
402 // sinking multiple "cheap" instructions into the same block.
403 if (!CEBCandidates.insert(std::make_pair(From, To)).second)
406 if (!MI.isCopy() && !TII->isAsCheapAsAMove(MI))
409 if (From->isSuccessor(To) && MBPI->getEdgeProbability(From, To) <=
410 BranchProbability(SplitEdgeProbabilityThreshold, 100))
413 // MI is cheap, we probably don't want to break the critical edge for it.
414 // However, if this would allow some definitions of its source operands
415 // to be sunk then it's probably worth it.
416 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
417 const MachineOperand &MO = MI.getOperand(i);
418 if (!MO.isReg() || !MO.isUse())
420 unsigned Reg = MO.getReg();
424 // We don't move live definitions of physical registers,
425 // so sinking their uses won't enable any opportunities.
426 if (TargetRegisterInfo::isPhysicalRegister(Reg))
429 // If this instruction is the only user of a virtual register,
430 // check if breaking the edge will enable sinking
431 // both this instruction and the defining instruction.
432 if (MRI->hasOneNonDBGUse(Reg)) {
433 // If the definition resides in same MBB,
434 // claim it's likely we can sink these together.
435 // If definition resides elsewhere, we aren't
436 // blocking it from being sunk so don't break the edge.
437 MachineInstr *DefMI = MRI->getVRegDef(Reg);
438 if (DefMI->getParent() == MI.getParent())
446 bool MachineSinking::PostponeSplitCriticalEdge(MachineInstr &MI,
447 MachineBasicBlock *FromBB,
448 MachineBasicBlock *ToBB,
450 if (!isWorthBreakingCriticalEdge(MI, FromBB, ToBB))
453 // Avoid breaking back edge. From == To means backedge for single BB loop.
454 if (!SplitEdges || FromBB == ToBB)
457 // Check for backedges of more "complex" loops.
458 if (LI->getLoopFor(FromBB) == LI->getLoopFor(ToBB) &&
459 LI->isLoopHeader(ToBB))
462 // It's not always legal to break critical edges and sink the computation
470 // ... no uses of v1024
476 // If %bb.1 -> %bb.3 edge is broken and computation of v1024 is inserted:
485 // ... no uses of v1024
491 // This is incorrect since v1024 is not computed along the %bb.1->%bb.2->%bb.3
492 // flow. We need to ensure the new basic block where the computation is
493 // sunk to dominates all the uses.
494 // It's only legal to break critical edge and sink the computation to the
495 // new block if all the predecessors of "To", except for "From", are
496 // not dominated by "From". Given SSA property, this means these
497 // predecessors are dominated by "To".
499 // There is no need to do this check if all the uses are PHI nodes. PHI
500 // sources are only defined on the specific predecessor edges.
502 for (MachineBasicBlock::pred_iterator PI = ToBB->pred_begin(),
503 E = ToBB->pred_end(); PI != E; ++PI) {
506 if (!DT->dominates(ToBB, *PI))
511 ToSplit.insert(std::make_pair(FromBB, ToBB));
516 /// isProfitableToSinkTo - Return true if it is profitable to sink MI.
517 bool MachineSinking::isProfitableToSinkTo(unsigned Reg, MachineInstr &MI,
518 MachineBasicBlock *MBB,
519 MachineBasicBlock *SuccToSinkTo,
520 AllSuccsCache &AllSuccessors) {
521 assert (SuccToSinkTo && "Invalid SinkTo Candidate BB");
523 if (MBB == SuccToSinkTo)
526 // It is profitable if SuccToSinkTo does not post dominate current block.
527 if (!PDT->dominates(SuccToSinkTo, MBB))
530 // It is profitable to sink an instruction from a deeper loop to a shallower
531 // loop, even if the latter post-dominates the former (PR21115).
532 if (LI->getLoopDepth(MBB) > LI->getLoopDepth(SuccToSinkTo))
535 // Check if only use in post dominated block is PHI instruction.
536 bool NonPHIUse = false;
537 for (MachineInstr &UseInst : MRI->use_nodbg_instructions(Reg)) {
538 MachineBasicBlock *UseBlock = UseInst.getParent();
539 if (UseBlock == SuccToSinkTo && !UseInst.isPHI())
545 // If SuccToSinkTo post dominates then also it may be profitable if MI
546 // can further profitably sinked into another block in next round.
547 bool BreakPHIEdge = false;
548 // FIXME - If finding successor is compile time expensive then cache results.
549 if (MachineBasicBlock *MBB2 =
550 FindSuccToSinkTo(MI, SuccToSinkTo, BreakPHIEdge, AllSuccessors))
551 return isProfitableToSinkTo(Reg, MI, SuccToSinkTo, MBB2, AllSuccessors);
553 // If SuccToSinkTo is final destination and it is a post dominator of current
554 // block then it is not profitable to sink MI into SuccToSinkTo block.
558 /// Get the sorted sequence of successors for this MachineBasicBlock, possibly
559 /// computing it if it was not already cached.
560 SmallVector<MachineBasicBlock *, 4> &
561 MachineSinking::GetAllSortedSuccessors(MachineInstr &MI, MachineBasicBlock *MBB,
562 AllSuccsCache &AllSuccessors) const {
563 // Do we have the sorted successors in cache ?
564 auto Succs = AllSuccessors.find(MBB);
565 if (Succs != AllSuccessors.end())
566 return Succs->second;
568 SmallVector<MachineBasicBlock *, 4> AllSuccs(MBB->succ_begin(),
571 // Handle cases where sinking can happen but where the sink point isn't a
572 // successor. For example:
578 const std::vector<MachineDomTreeNode *> &Children =
579 DT->getNode(MBB)->getChildren();
580 for (const auto &DTChild : Children)
581 // DomTree children of MBB that have MBB as immediate dominator are added.
582 if (DTChild->getIDom()->getBlock() == MI.getParent() &&
583 // Skip MBBs already added to the AllSuccs vector above.
584 !MBB->isSuccessor(DTChild->getBlock()))
585 AllSuccs.push_back(DTChild->getBlock());
587 // Sort Successors according to their loop depth or block frequency info.
589 AllSuccs.begin(), AllSuccs.end(),
590 [this](const MachineBasicBlock *L, const MachineBasicBlock *R) {
591 uint64_t LHSFreq = MBFI ? MBFI->getBlockFreq(L).getFrequency() : 0;
592 uint64_t RHSFreq = MBFI ? MBFI->getBlockFreq(R).getFrequency() : 0;
593 bool HasBlockFreq = LHSFreq != 0 && RHSFreq != 0;
594 return HasBlockFreq ? LHSFreq < RHSFreq
595 : LI->getLoopDepth(L) < LI->getLoopDepth(R);
598 auto it = AllSuccessors.insert(std::make_pair(MBB, AllSuccs));
600 return it.first->second;
603 /// FindSuccToSinkTo - Find a successor to sink this instruction to.
605 MachineSinking::FindSuccToSinkTo(MachineInstr &MI, MachineBasicBlock *MBB,
607 AllSuccsCache &AllSuccessors) {
608 assert (MBB && "Invalid MachineBasicBlock!");
610 // Loop over all the operands of the specified instruction. If there is
611 // anything we can't handle, bail out.
613 // SuccToSinkTo - This is the successor to sink this instruction to, once we
615 MachineBasicBlock *SuccToSinkTo = nullptr;
616 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
617 const MachineOperand &MO = MI.getOperand(i);
618 if (!MO.isReg()) continue; // Ignore non-register operands.
620 unsigned Reg = MO.getReg();
621 if (Reg == 0) continue;
623 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
625 // If the physreg has no defs anywhere, it's just an ambient register
626 // and we can freely move its uses. Alternatively, if it's allocatable,
627 // it could get allocated to something with a def during allocation.
628 if (!MRI->isConstantPhysReg(Reg))
630 } else if (!MO.isDead()) {
631 // A def that isn't dead. We can't move it.
635 // Virtual register uses are always safe to sink.
636 if (MO.isUse()) continue;
638 // If it's not safe to move defs of the register class, then abort.
639 if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg)))
642 // Virtual register defs can only be sunk if all their uses are in blocks
643 // dominated by one of the successors.
645 // If a previous operand picked a block to sink to, then this operand
646 // must be sinkable to the same block.
647 bool LocalUse = false;
648 if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo, MBB,
649 BreakPHIEdge, LocalUse))
655 // Otherwise, we should look at all the successors and decide which one
656 // we should sink to. If we have reliable block frequency information
657 // (frequency != 0) available, give successors with smaller frequencies
658 // higher priority, otherwise prioritize smaller loop depths.
659 for (MachineBasicBlock *SuccBlock :
660 GetAllSortedSuccessors(MI, MBB, AllSuccessors)) {
661 bool LocalUse = false;
662 if (AllUsesDominatedByBlock(Reg, SuccBlock, MBB,
663 BreakPHIEdge, LocalUse)) {
664 SuccToSinkTo = SuccBlock;
668 // Def is used locally, it's never safe to move this def.
672 // If we couldn't find a block to sink to, ignore this instruction.
675 if (!isProfitableToSinkTo(Reg, MI, MBB, SuccToSinkTo, AllSuccessors))
680 // It is not possible to sink an instruction into its own block. This can
681 // happen with loops.
682 if (MBB == SuccToSinkTo)
685 // It's not safe to sink instructions to EH landing pad. Control flow into
686 // landing pad is implicitly defined.
687 if (SuccToSinkTo && SuccToSinkTo->isEHPad())
693 /// Return true if MI is likely to be usable as a memory operation by the
694 /// implicit null check optimization.
696 /// This is a "best effort" heuristic, and should not be relied upon for
697 /// correctness. This returning true does not guarantee that the implicit null
698 /// check optimization is legal over MI, and this returning false does not
699 /// guarantee MI cannot possibly be used to do a null check.
700 static bool SinkingPreventsImplicitNullCheck(MachineInstr &MI,
701 const TargetInstrInfo *TII,
702 const TargetRegisterInfo *TRI) {
703 using MachineBranchPredicate = TargetInstrInfo::MachineBranchPredicate;
705 auto *MBB = MI.getParent();
706 if (MBB->pred_size() != 1)
709 auto *PredMBB = *MBB->pred_begin();
710 auto *PredBB = PredMBB->getBasicBlock();
712 // Frontends that don't use implicit null checks have no reason to emit
713 // branches with make.implicit metadata, and this function should always
714 // return false for them.
716 !PredBB->getTerminator()->getMetadata(LLVMContext::MD_make_implicit))
719 MachineOperand *BaseOp;
721 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, TRI))
724 if (!BaseOp->isReg())
727 if (!(MI.mayLoad() && !MI.isPredicable()))
730 MachineBranchPredicate MBP;
731 if (TII->analyzeBranchPredicate(*PredMBB, MBP, false))
734 return MBP.LHS.isReg() && MBP.RHS.isImm() && MBP.RHS.getImm() == 0 &&
735 (MBP.Predicate == MachineBranchPredicate::PRED_NE ||
736 MBP.Predicate == MachineBranchPredicate::PRED_EQ) &&
737 MBP.LHS.getReg() == BaseOp->getReg();
740 /// Sink an instruction and its associated debug instructions. If the debug
741 /// instructions to be sunk are already known, they can be provided in DbgVals.
742 static void performSink(MachineInstr &MI, MachineBasicBlock &SuccToSinkTo,
743 MachineBasicBlock::iterator InsertPos,
744 SmallVectorImpl<MachineInstr *> *DbgVals = nullptr) {
745 // If debug values are provided use those, otherwise call collectDebugValues.
746 SmallVector<MachineInstr *, 2> DbgValuesToSink;
748 DbgValuesToSink.insert(DbgValuesToSink.begin(),
749 DbgVals->begin(), DbgVals->end());
751 MI.collectDebugValues(DbgValuesToSink);
753 // If we cannot find a location to use (merge with), then we erase the debug
754 // location to prevent debug-info driven tools from potentially reporting
755 // wrong location information.
756 if (!SuccToSinkTo.empty() && InsertPos != SuccToSinkTo.end())
757 MI.setDebugLoc(DILocation::getMergedLocation(MI.getDebugLoc(),
758 InsertPos->getDebugLoc()));
760 MI.setDebugLoc(DebugLoc());
762 // Move the instruction.
763 MachineBasicBlock *ParentBlock = MI.getParent();
764 SuccToSinkTo.splice(InsertPos, ParentBlock, MI,
765 ++MachineBasicBlock::iterator(MI));
767 // Move previously adjacent debug value instructions to the insert position.
768 for (SmallVectorImpl<MachineInstr *>::iterator DBI = DbgValuesToSink.begin(),
769 DBE = DbgValuesToSink.end();
771 MachineInstr *DbgMI = *DBI;
772 SuccToSinkTo.splice(InsertPos, ParentBlock, DbgMI,
773 ++MachineBasicBlock::iterator(DbgMI));
777 /// SinkInstruction - Determine whether it is safe to sink the specified machine
778 /// instruction out of its current block into a successor.
779 bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore,
780 AllSuccsCache &AllSuccessors) {
781 // Don't sink instructions that the target prefers not to sink.
782 if (!TII->shouldSink(MI))
785 // Check if it's safe to move the instruction.
786 if (!MI.isSafeToMove(AA, SawStore))
789 // Convergent operations may not be made control-dependent on additional
791 if (MI.isConvergent())
794 // Don't break implicit null checks. This is a performance heuristic, and not
795 // required for correctness.
796 if (SinkingPreventsImplicitNullCheck(MI, TII, TRI))
799 // FIXME: This should include support for sinking instructions within the
800 // block they are currently in to shorten the live ranges. We often get
801 // instructions sunk into the top of a large block, but it would be better to
802 // also sink them down before their first use in the block. This xform has to
803 // be careful not to *increase* register pressure though, e.g. sinking
804 // "x = y + z" down if it kills y and z would increase the live ranges of y
805 // and z and only shrink the live range of x.
807 bool BreakPHIEdge = false;
808 MachineBasicBlock *ParentBlock = MI.getParent();
809 MachineBasicBlock *SuccToSinkTo =
810 FindSuccToSinkTo(MI, ParentBlock, BreakPHIEdge, AllSuccessors);
812 // If there are no outputs, it must have side-effects.
816 // If the instruction to move defines a dead physical register which is live
817 // when leaving the basic block, don't move it because it could turn into a
818 // "zombie" define of that preg. E.g., EFLAGS. (<rdar://problem/8030636>)
819 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
820 const MachineOperand &MO = MI.getOperand(I);
821 if (!MO.isReg()) continue;
822 unsigned Reg = MO.getReg();
823 if (Reg == 0 || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
824 if (SuccToSinkTo->isLiveIn(Reg))
828 LLVM_DEBUG(dbgs() << "Sink instr " << MI << "\tinto block " << *SuccToSinkTo);
830 // If the block has multiple predecessors, this is a critical edge.
831 // Decide if we can sink along it or need to break the edge.
832 if (SuccToSinkTo->pred_size() > 1) {
833 // We cannot sink a load across a critical edge - there may be stores in
835 bool TryBreak = false;
837 if (!MI.isSafeToMove(AA, store)) {
838 LLVM_DEBUG(dbgs() << " *** NOTE: Won't sink load along critical edge.\n");
842 // We don't want to sink across a critical edge if we don't dominate the
843 // successor. We could be introducing calculations to new code paths.
844 if (!TryBreak && !DT->dominates(ParentBlock, SuccToSinkTo)) {
845 LLVM_DEBUG(dbgs() << " *** NOTE: Critical edge found\n");
849 // Don't sink instructions into a loop.
850 if (!TryBreak && LI->isLoopHeader(SuccToSinkTo)) {
851 LLVM_DEBUG(dbgs() << " *** NOTE: Loop header found\n");
855 // Otherwise we are OK with sinking along a critical edge.
857 LLVM_DEBUG(dbgs() << "Sinking along critical edge.\n");
859 // Mark this edge as to be split.
860 // If the edge can actually be split, the next iteration of the main loop
861 // will sink MI in the newly created block.
863 PostponeSplitCriticalEdge(MI, ParentBlock, SuccToSinkTo, BreakPHIEdge);
865 LLVM_DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to "
866 "break critical edge\n");
867 // The instruction will not be sunk this time.
873 // BreakPHIEdge is true if all the uses are in the successor MBB being
874 // sunken into and they are all PHI nodes. In this case, machine-sink must
875 // break the critical edge first.
876 bool Status = PostponeSplitCriticalEdge(MI, ParentBlock,
877 SuccToSinkTo, BreakPHIEdge);
879 LLVM_DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to "
880 "break critical edge\n");
881 // The instruction will not be sunk this time.
885 // Determine where to insert into. Skip phi nodes.
886 MachineBasicBlock::iterator InsertPos = SuccToSinkTo->begin();
887 while (InsertPos != SuccToSinkTo->end() && InsertPos->isPHI())
890 performSink(MI, *SuccToSinkTo, InsertPos);
892 // Conservatively, clear any kill flags, since it's possible that they are no
894 // Note that we have to clear the kill flags for any register this instruction
895 // uses as we may sink over another instruction which currently kills the
897 for (MachineOperand &MO : MI.operands()) {
898 if (MO.isReg() && MO.isUse())
899 RegsToClearKillFlags.set(MO.getReg()); // Remember to clear kill flags.
905 //===----------------------------------------------------------------------===//
906 // This pass is not intended to be a replacement or a complete alternative
907 // for the pre-ra machine sink pass. It is only designed to sink COPY
908 // instructions which should be handled after RA.
910 // This pass sinks COPY instructions into a successor block, if the COPY is not
911 // used in the current block and the COPY is live-in to a single successor
912 // (i.e., doesn't require the COPY to be duplicated). This avoids executing the
913 // copy on paths where their results aren't needed. This also exposes
914 // additional opportunites for dead copy elimination and shrink wrapping.
916 // These copies were either not handled by or are inserted after the MachineSink
917 // pass. As an example of the former case, the MachineSink pass cannot sink
918 // COPY instructions with allocatable source registers; for AArch64 these type
919 // of copy instructions are frequently used to move function parameters (PhyReg)
920 // into virtual registers in the entry block.
922 // For the machine IR below, this pass will sink %w19 in the entry into its
923 // successor (%bb.1) because %w19 is only live-in in %bb.1.
925 // %wzr = SUBSWri %w1, 1
931 // %w0 = ADDWrr %w0, %w19
936 // As we sink %w19 (CSR in AArch64) into %bb.1, the shrink-wrapping pass will be
937 // able to see %bb.0 as a candidate.
938 //===----------------------------------------------------------------------===//
941 class PostRAMachineSinking : public MachineFunctionPass {
943 bool runOnMachineFunction(MachineFunction &MF) override;
946 PostRAMachineSinking() : MachineFunctionPass(ID) {}
947 StringRef getPassName() const override { return "PostRA Machine Sink"; }
949 void getAnalysisUsage(AnalysisUsage &AU) const override {
950 AU.setPreservesCFG();
951 MachineFunctionPass::getAnalysisUsage(AU);
954 MachineFunctionProperties getRequiredProperties() const override {
955 return MachineFunctionProperties().set(
956 MachineFunctionProperties::Property::NoVRegs);
960 /// Track which register units have been modified and used.
961 LiveRegUnits ModifiedRegUnits, UsedRegUnits;
963 /// Track DBG_VALUEs of (unmodified) register units.
964 DenseMap<unsigned, TinyPtrVector<MachineInstr*>> SeenDbgInstrs;
966 /// Sink Copy instructions unused in the same block close to their uses in
968 bool tryToSinkCopy(MachineBasicBlock &BB, MachineFunction &MF,
969 const TargetRegisterInfo *TRI, const TargetInstrInfo *TII);
973 char PostRAMachineSinking::ID = 0;
974 char &llvm::PostRAMachineSinkingID = PostRAMachineSinking::ID;
976 INITIALIZE_PASS(PostRAMachineSinking, "postra-machine-sink",
977 "PostRA Machine Sink", false, false)
979 static bool aliasWithRegsInLiveIn(MachineBasicBlock &MBB, unsigned Reg,
980 const TargetRegisterInfo *TRI) {
981 LiveRegUnits LiveInRegUnits(*TRI);
982 LiveInRegUnits.addLiveIns(MBB);
983 return !LiveInRegUnits.available(Reg);
986 static MachineBasicBlock *
987 getSingleLiveInSuccBB(MachineBasicBlock &CurBB,
988 const SmallPtrSetImpl<MachineBasicBlock *> &SinkableBBs,
989 unsigned Reg, const TargetRegisterInfo *TRI) {
990 // Try to find a single sinkable successor in which Reg is live-in.
991 MachineBasicBlock *BB = nullptr;
992 for (auto *SI : SinkableBBs) {
993 if (aliasWithRegsInLiveIn(*SI, Reg, TRI)) {
994 // If BB is set here, Reg is live-in to at least two sinkable successors,
1001 // Reg is not live-in to any sinkable successors.
1005 // Check if any register aliased with Reg is live-in in other successors.
1006 for (auto *SI : CurBB.successors()) {
1007 if (!SinkableBBs.count(SI) && aliasWithRegsInLiveIn(*SI, Reg, TRI))
1013 static MachineBasicBlock *
1014 getSingleLiveInSuccBB(MachineBasicBlock &CurBB,
1015 const SmallPtrSetImpl<MachineBasicBlock *> &SinkableBBs,
1016 ArrayRef<unsigned> DefedRegsInCopy,
1017 const TargetRegisterInfo *TRI) {
1018 MachineBasicBlock *SingleBB = nullptr;
1019 for (auto DefReg : DefedRegsInCopy) {
1020 MachineBasicBlock *BB =
1021 getSingleLiveInSuccBB(CurBB, SinkableBBs, DefReg, TRI);
1022 if (!BB || (SingleBB && SingleBB != BB))
1029 static void clearKillFlags(MachineInstr *MI, MachineBasicBlock &CurBB,
1030 SmallVectorImpl<unsigned> &UsedOpsInCopy,
1031 LiveRegUnits &UsedRegUnits,
1032 const TargetRegisterInfo *TRI) {
1033 for (auto U : UsedOpsInCopy) {
1034 MachineOperand &MO = MI->getOperand(U);
1035 unsigned SrcReg = MO.getReg();
1036 if (!UsedRegUnits.available(SrcReg)) {
1037 MachineBasicBlock::iterator NI = std::next(MI->getIterator());
1038 for (MachineInstr &UI : make_range(NI, CurBB.end())) {
1039 if (UI.killsRegister(SrcReg, TRI)) {
1040 UI.clearRegisterKills(SrcReg, TRI);
1049 static void updateLiveIn(MachineInstr *MI, MachineBasicBlock *SuccBB,
1050 SmallVectorImpl<unsigned> &UsedOpsInCopy,
1051 SmallVectorImpl<unsigned> &DefedRegsInCopy) {
1052 MachineFunction &MF = *SuccBB->getParent();
1053 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1054 for (unsigned DefReg : DefedRegsInCopy)
1055 for (MCSubRegIterator S(DefReg, TRI, true); S.isValid(); ++S)
1056 SuccBB->removeLiveIn(*S);
1057 for (auto U : UsedOpsInCopy) {
1058 unsigned Reg = MI->getOperand(U).getReg();
1059 if (!SuccBB->isLiveIn(Reg))
1060 SuccBB->addLiveIn(Reg);
1064 static bool hasRegisterDependency(MachineInstr *MI,
1065 SmallVectorImpl<unsigned> &UsedOpsInCopy,
1066 SmallVectorImpl<unsigned> &DefedRegsInCopy,
1067 LiveRegUnits &ModifiedRegUnits,
1068 LiveRegUnits &UsedRegUnits) {
1069 bool HasRegDependency = false;
1070 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1071 MachineOperand &MO = MI->getOperand(i);
1074 unsigned Reg = MO.getReg();
1078 if (!ModifiedRegUnits.available(Reg) || !UsedRegUnits.available(Reg)) {
1079 HasRegDependency = true;
1082 DefedRegsInCopy.push_back(Reg);
1084 // FIXME: instead of isUse(), readsReg() would be a better fix here,
1085 // For example, we can ignore modifications in reg with undef. However,
1086 // it's not perfectly clear if skipping the internal read is safe in all
1088 } else if (MO.isUse()) {
1089 if (!ModifiedRegUnits.available(Reg)) {
1090 HasRegDependency = true;
1093 UsedOpsInCopy.push_back(i);
1096 return HasRegDependency;
1099 bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB,
1100 MachineFunction &MF,
1101 const TargetRegisterInfo *TRI,
1102 const TargetInstrInfo *TII) {
1103 SmallPtrSet<MachineBasicBlock *, 2> SinkableBBs;
1104 // FIXME: For now, we sink only to a successor which has a single predecessor
1105 // so that we can directly sink COPY instructions to the successor without
1106 // adding any new block or branch instruction.
1107 for (MachineBasicBlock *SI : CurBB.successors())
1108 if (!SI->livein_empty() && SI->pred_size() == 1)
1109 SinkableBBs.insert(SI);
1111 if (SinkableBBs.empty())
1114 bool Changed = false;
1116 // Track which registers have been modified and used between the end of the
1117 // block and the current instruction.
1118 ModifiedRegUnits.clear();
1119 UsedRegUnits.clear();
1120 SeenDbgInstrs.clear();
1122 for (auto I = CurBB.rbegin(), E = CurBB.rend(); I != E;) {
1123 MachineInstr *MI = &*I;
1126 // Track the operand index for use in Copy.
1127 SmallVector<unsigned, 2> UsedOpsInCopy;
1128 // Track the register number defed in Copy.
1129 SmallVector<unsigned, 2> DefedRegsInCopy;
1131 // We must sink this DBG_VALUE if its operand is sunk. To avoid searching
1132 // for DBG_VALUEs later, record them when they're encountered.
1133 if (MI->isDebugValue()) {
1134 auto &MO = MI->getOperand(0);
1135 if (MO.isReg() && TRI->isPhysicalRegister(MO.getReg())) {
1136 // Bail if we can already tell the sink would be rejected, rather
1137 // than needlessly accumulating lots of DBG_VALUEs.
1138 if (hasRegisterDependency(MI, UsedOpsInCopy, DefedRegsInCopy,
1139 ModifiedRegUnits, UsedRegUnits))
1142 // Record debug use of this register.
1143 SeenDbgInstrs[MO.getReg()].push_back(MI);
1148 if (MI->isDebugInstr())
1151 // Do not move any instruction across function call.
1155 if (!MI->isCopy() || !MI->getOperand(0).isRenamable()) {
1156 LiveRegUnits::accumulateUsedDefed(*MI, ModifiedRegUnits, UsedRegUnits,
1161 // Don't sink the COPY if it would violate a register dependency.
1162 if (hasRegisterDependency(MI, UsedOpsInCopy, DefedRegsInCopy,
1163 ModifiedRegUnits, UsedRegUnits)) {
1164 LiveRegUnits::accumulateUsedDefed(*MI, ModifiedRegUnits, UsedRegUnits,
1168 assert((!UsedOpsInCopy.empty() && !DefedRegsInCopy.empty()) &&
1169 "Unexpect SrcReg or DefReg");
1170 MachineBasicBlock *SuccBB =
1171 getSingleLiveInSuccBB(CurBB, SinkableBBs, DefedRegsInCopy, TRI);
1172 // Don't sink if we cannot find a single sinkable successor in which Reg
1175 LiveRegUnits::accumulateUsedDefed(*MI, ModifiedRegUnits, UsedRegUnits,
1179 assert((SuccBB->pred_size() == 1 && *SuccBB->pred_begin() == &CurBB) &&
1180 "Unexpected predecessor");
1182 // Collect DBG_VALUEs that must sink with this copy.
1183 SmallVector<MachineInstr *, 4> DbgValsToSink;
1184 for (auto &MO : MI->operands()) {
1185 if (!MO.isReg() || !MO.isDef())
1187 unsigned reg = MO.getReg();
1188 for (auto *MI : SeenDbgInstrs.lookup(reg))
1189 DbgValsToSink.push_back(MI);
1192 // Clear the kill flag if SrcReg is killed between MI and the end of the
1194 clearKillFlags(MI, CurBB, UsedOpsInCopy, UsedRegUnits, TRI);
1195 MachineBasicBlock::iterator InsertPos = SuccBB->getFirstNonPHI();
1196 performSink(*MI, *SuccBB, InsertPos, &DbgValsToSink);
1197 updateLiveIn(MI, SuccBB, UsedOpsInCopy, DefedRegsInCopy);
1200 ++NumPostRACopySink;
1205 bool PostRAMachineSinking::runOnMachineFunction(MachineFunction &MF) {
1206 bool Changed = false;
1207 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1208 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
1210 ModifiedRegUnits.init(*TRI);
1211 UsedRegUnits.init(*TRI);
1213 Changed |= tryToSinkCopy(BB, MF, TRI, TII);