1 //===- PhiElimination.cpp - Eliminate PHI nodes by inserting copies -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass eliminates machine instruction PHI nodes by inserting copy
11 // instructions. This destroys SSA information, but is the desired input for
12 // some register allocators.
14 //===----------------------------------------------------------------------===//
16 #include "PHIEliminationUtils.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallPtrSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/LoopInfo.h"
21 #include "llvm/CodeGen/LiveInterval.h"
22 #include "llvm/CodeGen/LiveIntervals.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineBasicBlock.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/MachineInstr.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineLoopInfo.h"
31 #include "llvm/CodeGen/MachineOperand.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/SlotIndexes.h"
34 #include "llvm/CodeGen/TargetInstrInfo.h"
35 #include "llvm/CodeGen/TargetOpcodes.h"
36 #include "llvm/CodeGen/TargetRegisterInfo.h"
37 #include "llvm/CodeGen/TargetSubtargetInfo.h"
38 #include "llvm/Pass.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/raw_ostream.h"
48 #define DEBUG_TYPE "phi-node-elimination"
51 DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false),
52 cl::Hidden, cl::desc("Disable critical edge splitting "
53 "during PHI elimination"));
56 SplitAllCriticalEdges("phi-elim-split-all-critical-edges", cl::init(false),
57 cl::Hidden, cl::desc("Split all critical edges during "
60 static cl::opt<bool> NoPhiElimLiveOutEarlyExit(
61 "no-phi-elim-live-out-early-exit", cl::init(false), cl::Hidden,
62 cl::desc("Do not use an early exit if isLiveOutPastPHIs returns true."));
66 class PHIElimination : public MachineFunctionPass {
67 MachineRegisterInfo *MRI; // Machine register information
72 static char ID; // Pass identification, replacement for typeid
74 PHIElimination() : MachineFunctionPass(ID) {
75 initializePHIEliminationPass(*PassRegistry::getPassRegistry());
78 bool runOnMachineFunction(MachineFunction &Fn) override;
79 void getAnalysisUsage(AnalysisUsage &AU) const override;
82 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
83 /// in predecessor basic blocks.
84 bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
86 void LowerPHINode(MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator LastPHIIt);
89 /// analyzePHINodes - Gather information about the PHI nodes in
90 /// here. In particular, we want to map the number of uses of a virtual
91 /// register which is used in a PHI node. We map that to the BB the
92 /// vreg is coming from. This is used later to determine when the vreg
93 /// is killed in the BB.
94 void analyzePHINodes(const MachineFunction& Fn);
96 /// Split critical edges where necessary for good coalescer performance.
97 bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
98 MachineLoopInfo *MLI);
100 // These functions are temporary abstractions around LiveVariables and
101 // LiveIntervals, so they can go away when LiveVariables does.
102 bool isLiveIn(unsigned Reg, const MachineBasicBlock *MBB);
103 bool isLiveOutPastPHIs(unsigned Reg, const MachineBasicBlock *MBB);
105 using BBVRegPair = std::pair<unsigned, unsigned>;
106 using VRegPHIUse = DenseMap<BBVRegPair, unsigned>;
108 VRegPHIUse VRegPHIUseCount;
110 // Defs of PHI sources which are implicit_def.
111 SmallPtrSet<MachineInstr*, 4> ImpDefs;
113 // Map reusable lowered PHI node -> incoming join register.
114 using LoweredPHIMap =
115 DenseMap<MachineInstr*, unsigned, MachineInstrExpressionTrait>;
116 LoweredPHIMap LoweredPHIs;
119 } // end anonymous namespace
121 STATISTIC(NumLowered, "Number of phis lowered");
122 STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split");
123 STATISTIC(NumReused, "Number of reused lowered phis");
125 char PHIElimination::ID = 0;
127 char& llvm::PHIEliminationID = PHIElimination::ID;
129 INITIALIZE_PASS_BEGIN(PHIElimination, DEBUG_TYPE,
130 "Eliminate PHI nodes for register allocation",
132 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
133 INITIALIZE_PASS_END(PHIElimination, DEBUG_TYPE,
134 "Eliminate PHI nodes for register allocation", false, false)
136 void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
137 AU.addUsedIfAvailable<LiveVariables>();
138 AU.addPreserved<LiveVariables>();
139 AU.addPreserved<SlotIndexes>();
140 AU.addPreserved<LiveIntervals>();
141 AU.addPreserved<MachineDominatorTree>();
142 AU.addPreserved<MachineLoopInfo>();
143 MachineFunctionPass::getAnalysisUsage(AU);
146 bool PHIElimination::runOnMachineFunction(MachineFunction &MF) {
147 MRI = &MF.getRegInfo();
148 LV = getAnalysisIfAvailable<LiveVariables>();
149 LIS = getAnalysisIfAvailable<LiveIntervals>();
151 bool Changed = false;
153 // This pass takes the function out of SSA form.
156 // Split critical edges to help the coalescer. This does not yet support
157 // updating LiveIntervals, so we disable it.
158 if (!DisableEdgeSplitting && (LV || LIS)) {
159 MachineLoopInfo *MLI = getAnalysisIfAvailable<MachineLoopInfo>();
161 Changed |= SplitPHIEdges(MF, MBB, MLI);
164 // Populate VRegPHIUseCount
167 // Eliminate PHI instructions by inserting copies into predecessor blocks.
169 Changed |= EliminatePHINodes(MF, MBB);
171 // Remove dead IMPLICIT_DEF instructions.
172 for (MachineInstr *DefMI : ImpDefs) {
173 unsigned DefReg = DefMI->getOperand(0).getReg();
174 if (MRI->use_nodbg_empty(DefReg)) {
176 LIS->RemoveMachineInstrFromMaps(*DefMI);
177 DefMI->eraseFromParent();
181 // Clean up the lowered PHI instructions.
182 for (auto &I : LoweredPHIs) {
184 LIS->RemoveMachineInstrFromMaps(*I.first);
185 MF.DeleteMachineInstr(I.first);
190 VRegPHIUseCount.clear();
192 MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
197 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
198 /// predecessor basic blocks.
199 bool PHIElimination::EliminatePHINodes(MachineFunction &MF,
200 MachineBasicBlock &MBB) {
201 if (MBB.empty() || !MBB.front().isPHI())
202 return false; // Quick exit for basic blocks without PHIs.
204 // Get an iterator to the first instruction after the last PHI node (this may
205 // also be the end of the basic block).
206 MachineBasicBlock::iterator LastPHIIt =
207 std::prev(MBB.SkipPHIsAndLabels(MBB.begin()));
209 while (MBB.front().isPHI())
210 LowerPHINode(MBB, LastPHIIt);
215 /// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
216 /// This includes registers with no defs.
217 static bool isImplicitlyDefined(unsigned VirtReg,
218 const MachineRegisterInfo *MRI) {
219 for (MachineInstr &DI : MRI->def_instructions(VirtReg))
220 if (!DI.isImplicitDef())
225 /// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
226 /// are implicit_def's.
227 static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
228 const MachineRegisterInfo *MRI) {
229 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
230 if (!isImplicitlyDefined(MPhi->getOperand(i).getReg(), MRI))
235 /// LowerPHINode - Lower the PHI node at the top of the specified block.
236 void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
237 MachineBasicBlock::iterator LastPHIIt) {
240 MachineBasicBlock::iterator AfterPHIsIt = std::next(LastPHIIt);
242 // Unlink the PHI node from the basic block, but don't delete the PHI yet.
243 MachineInstr *MPhi = MBB.remove(&*MBB.begin());
245 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
246 unsigned DestReg = MPhi->getOperand(0).getReg();
247 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
248 bool isDead = MPhi->getOperand(0).isDead();
250 // Create a new register for the incoming PHI arguments.
251 MachineFunction &MF = *MBB.getParent();
252 unsigned IncomingReg = 0;
253 bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI?
255 // Insert a register to register copy at the top of the current block (but
256 // after any remaining phi nodes) which copies the new incoming register
257 // into the phi node destination.
258 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
259 if (isSourceDefinedByImplicitDef(MPhi, MRI))
260 // If all sources of a PHI node are implicit_def, just emit an
261 // implicit_def instead of a copy.
262 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
263 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
265 // Can we reuse an earlier PHI node? This only happens for critical edges,
266 // typically those created by tail duplication.
267 unsigned &entry = LoweredPHIs[MPhi];
269 // An identical PHI node was already lowered. Reuse the incoming register.
271 reusedIncoming = true;
273 DEBUG(dbgs() << "Reusing " << printReg(IncomingReg) << " for " << *MPhi);
275 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
276 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
278 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
279 TII->get(TargetOpcode::COPY), DestReg)
280 .addReg(IncomingReg);
283 // Update live variable information if there is any.
285 MachineInstr &PHICopy = *std::prev(AfterPHIsIt);
288 LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
290 // Increment use count of the newly created virtual register.
291 LV->setPHIJoin(IncomingReg);
293 // When we are reusing the incoming register, it may already have been
294 // killed in this block. The old kill will also have been inserted at
295 // AfterPHIsIt, so it appears before the current PHICopy.
297 if (MachineInstr *OldKill = VI.findKill(&MBB)) {
298 DEBUG(dbgs() << "Remove old kill from " << *OldKill);
299 LV->removeVirtualRegisterKilled(IncomingReg, *OldKill);
303 // Add information to LiveVariables to know that the incoming value is
304 // killed. Note that because the value is defined in several places (once
305 // each for each incoming block), the "def" block and instruction fields
306 // for the VarInfo is not filled in.
307 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
310 // Since we are going to be deleting the PHI node, if it is the last use of
311 // any registers, or if the value itself is dead, we need to move this
312 // information over to the new copy we just inserted.
313 LV->removeVirtualRegistersKilled(*MPhi);
315 // If the result is dead, update LV.
317 LV->addVirtualRegisterDead(DestReg, PHICopy);
318 LV->removeVirtualRegisterDead(DestReg, *MPhi);
322 // Update LiveIntervals for the new copy or implicit def.
324 SlotIndex DestCopyIndex =
325 LIS->InsertMachineInstrInMaps(*std::prev(AfterPHIsIt));
327 SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
329 // Add the region from the beginning of MBB to the copy instruction to
330 // IncomingReg's live interval.
331 LiveInterval &IncomingLI = LIS->createEmptyInterval(IncomingReg);
332 VNInfo *IncomingVNI = IncomingLI.getVNInfoAt(MBBStartIndex);
334 IncomingVNI = IncomingLI.getNextValue(MBBStartIndex,
335 LIS->getVNInfoAllocator());
336 IncomingLI.addSegment(LiveInterval::Segment(MBBStartIndex,
337 DestCopyIndex.getRegSlot(),
341 LiveInterval &DestLI = LIS->getInterval(DestReg);
342 assert(DestLI.begin() != DestLI.end() &&
343 "PHIs should have nonempty LiveIntervals.");
344 if (DestLI.endIndex().isDead()) {
345 // A dead PHI's live range begins and ends at the start of the MBB, but
346 // the lowered copy, which will still be dead, needs to begin and end at
347 // the copy instruction.
348 VNInfo *OrigDestVNI = DestLI.getVNInfoAt(MBBStartIndex);
349 assert(OrigDestVNI && "PHI destination should be live at block entry.");
350 DestLI.removeSegment(MBBStartIndex, MBBStartIndex.getDeadSlot());
351 DestLI.createDeadDef(DestCopyIndex.getRegSlot(),
352 LIS->getVNInfoAllocator());
353 DestLI.removeValNo(OrigDestVNI);
355 // Otherwise, remove the region from the beginning of MBB to the copy
356 // instruction from DestReg's live interval.
357 DestLI.removeSegment(MBBStartIndex, DestCopyIndex.getRegSlot());
358 VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getRegSlot());
359 assert(DestVNI && "PHI destination should be live at its definition.");
360 DestVNI->def = DestCopyIndex.getRegSlot();
364 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
365 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
366 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(),
367 MPhi->getOperand(i).getReg())];
369 // Now loop over all of the incoming arguments, changing them to copy into the
370 // IncomingReg register in the corresponding predecessor basic block.
371 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
372 for (int i = NumSrcs - 1; i >= 0; --i) {
373 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
374 unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
375 bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() ||
376 isImplicitlyDefined(SrcReg, MRI);
377 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
378 "Machine PHI Operands must all be virtual registers!");
380 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
382 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
384 // Check to make sure we haven't already emitted the copy for this block.
385 // This can happen because PHI nodes may have multiple entries for the same
387 if (!MBBsInsertedInto.insert(&opBlock).second)
388 continue; // If the copy has already been emitted, we're done.
390 // Find a safe location to insert the copy, this may be the first terminator
391 // in the block (or end()).
392 MachineBasicBlock::iterator InsertPos =
393 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
396 MachineInstr *NewSrcInstr = nullptr;
397 if (!reusedIncoming && IncomingReg) {
399 // The source register is undefined, so there is no need for a real
400 // COPY, but we still need to ensure joint dominance by defs.
401 // Insert an IMPLICIT_DEF instruction.
402 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
403 TII->get(TargetOpcode::IMPLICIT_DEF),
406 // Clean up the old implicit-def, if there even was one.
407 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
408 if (DefMI->isImplicitDef())
409 ImpDefs.insert(DefMI);
411 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
412 TII->get(TargetOpcode::COPY), IncomingReg)
413 .addReg(SrcReg, 0, SrcSubReg);
417 // We only need to update the LiveVariables kill of SrcReg if this was the
418 // last PHI use of SrcReg to be lowered on this CFG edge and it is not live
419 // out of the predecessor. We can also ignore undef sources.
420 if (LV && !SrcUndef &&
421 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
422 !LV->isLiveOut(SrcReg, opBlock)) {
423 // We want to be able to insert a kill of the register if this PHI (aka,
424 // the copy we just inserted) is the last use of the source value. Live
425 // variable analysis conservatively handles this by saying that the value
426 // is live until the end of the block the PHI entry lives in. If the value
427 // really is dead at the PHI copy, there will be no successor blocks which
428 // have the value live-in.
430 // Okay, if we now know that the value is not live out of the block, we
431 // can add a kill marker in this block saying that it kills the incoming
434 // In our final twist, we have to decide which instruction kills the
435 // register. In most cases this is the copy, however, terminator
436 // instructions at the end of the block may also use the value. In this
437 // case, we should mark the last such terminator as being the killing
438 // block, not the copy.
439 MachineBasicBlock::iterator KillInst = opBlock.end();
440 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
441 for (MachineBasicBlock::iterator Term = FirstTerm;
442 Term != opBlock.end(); ++Term) {
443 if (Term->readsRegister(SrcReg))
447 if (KillInst == opBlock.end()) {
448 // No terminator uses the register.
450 if (reusedIncoming || !IncomingReg) {
451 // We may have to rewind a bit if we didn't insert a copy this time.
452 KillInst = FirstTerm;
453 while (KillInst != opBlock.begin()) {
455 if (KillInst->isDebugValue())
457 if (KillInst->readsRegister(SrcReg))
461 // We just inserted this copy.
462 KillInst = std::prev(InsertPos);
465 assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
467 // Finally, mark it killed.
468 LV->addVirtualRegisterKilled(SrcReg, *KillInst);
470 // This vreg no longer lives all of the way through opBlock.
471 unsigned opBlockNum = opBlock.getNumber();
472 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
477 LIS->InsertMachineInstrInMaps(*NewSrcInstr);
478 LIS->addSegmentToEndOfBlock(IncomingReg, *NewSrcInstr);
482 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]) {
483 LiveInterval &SrcLI = LIS->getInterval(SrcReg);
485 bool isLiveOut = false;
486 for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(),
487 SE = opBlock.succ_end(); SI != SE; ++SI) {
488 SlotIndex startIdx = LIS->getMBBStartIdx(*SI);
489 VNInfo *VNI = SrcLI.getVNInfoAt(startIdx);
491 // Definitions by other PHIs are not truly live-in for our purposes.
492 if (VNI && VNI->def != startIdx) {
499 MachineBasicBlock::iterator KillInst = opBlock.end();
500 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
501 for (MachineBasicBlock::iterator Term = FirstTerm;
502 Term != opBlock.end(); ++Term) {
503 if (Term->readsRegister(SrcReg))
507 if (KillInst == opBlock.end()) {
508 // No terminator uses the register.
510 if (reusedIncoming || !IncomingReg) {
511 // We may have to rewind a bit if we didn't just insert a copy.
512 KillInst = FirstTerm;
513 while (KillInst != opBlock.begin()) {
515 if (KillInst->isDebugValue())
517 if (KillInst->readsRegister(SrcReg))
521 // We just inserted this copy.
522 KillInst = std::prev(InsertPos);
525 assert(KillInst->readsRegister(SrcReg) &&
526 "Cannot find kill instruction");
528 SlotIndex LastUseIndex = LIS->getInstructionIndex(*KillInst);
529 SrcLI.removeSegment(LastUseIndex.getRegSlot(),
530 LIS->getMBBEndIdx(&opBlock));
536 // Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
537 if (reusedIncoming || !IncomingReg) {
539 LIS->RemoveMachineInstrFromMaps(*MPhi);
540 MF.DeleteMachineInstr(MPhi);
544 /// analyzePHINodes - Gather information about the PHI nodes in here. In
545 /// particular, we want to map the number of uses of a virtual register which is
546 /// used in a PHI node. We map that to the BB the vreg is coming from. This is
547 /// used later to determine when the vreg is killed in the BB.
548 void PHIElimination::analyzePHINodes(const MachineFunction& MF) {
549 for (const auto &MBB : MF)
550 for (const auto &BBI : MBB) {
553 for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2)
554 ++VRegPHIUseCount[BBVRegPair(BBI.getOperand(i+1).getMBB()->getNumber(),
555 BBI.getOperand(i).getReg())];
559 bool PHIElimination::SplitPHIEdges(MachineFunction &MF,
560 MachineBasicBlock &MBB,
561 MachineLoopInfo *MLI) {
562 if (MBB.empty() || !MBB.front().isPHI() || MBB.isEHPad())
563 return false; // Quick exit for basic blocks without PHIs.
565 const MachineLoop *CurLoop = MLI ? MLI->getLoopFor(&MBB) : nullptr;
566 bool IsLoopHeader = CurLoop && &MBB == CurLoop->getHeader();
568 bool Changed = false;
569 for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end();
570 BBI != BBE && BBI->isPHI(); ++BBI) {
571 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
572 unsigned Reg = BBI->getOperand(i).getReg();
573 MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
574 // Is there a critical edge from PreMBB to MBB?
575 if (PreMBB->succ_size() == 1)
578 // Avoid splitting backedges of loops. It would introduce small
579 // out-of-line blocks into the loop which is very bad for code placement.
580 if (PreMBB == &MBB && !SplitAllCriticalEdges)
582 const MachineLoop *PreLoop = MLI ? MLI->getLoopFor(PreMBB) : nullptr;
583 if (IsLoopHeader && PreLoop == CurLoop && !SplitAllCriticalEdges)
586 // LV doesn't consider a phi use live-out, so isLiveOut only returns true
587 // when the source register is live-out for some other reason than a phi
588 // use. That means the copy we will insert in PreMBB won't be a kill, and
589 // there is a risk it may not be coalesced away.
591 // If the copy would be a kill, there is no need to split the edge.
592 bool ShouldSplit = isLiveOutPastPHIs(Reg, PreMBB);
593 if (!ShouldSplit && !NoPhiElimLiveOutEarlyExit)
596 DEBUG(dbgs() << printReg(Reg) << " live-out before critical edge "
597 << printMBBReference(*PreMBB) << " -> "
598 << printMBBReference(MBB) << ": " << *BBI);
601 // If Reg is not live-in to MBB, it means it must be live-in to some
602 // other PreMBB successor, and we can avoid the interference by splitting
605 // If Reg *is* live-in to MBB, the interference is inevitable and a copy
606 // is likely to be left after coalescing. If we are looking at a loop
607 // exiting edge, split it so we won't insert code in the loop, otherwise
609 ShouldSplit = ShouldSplit && !isLiveIn(Reg, &MBB);
611 // Check for a loop exiting edge.
612 if (!ShouldSplit && CurLoop != PreLoop) {
614 dbgs() << "Split wouldn't help, maybe avoid loop copies?\n";
615 if (PreLoop) dbgs() << "PreLoop: " << *PreLoop;
616 if (CurLoop) dbgs() << "CurLoop: " << *CurLoop;
618 // This edge could be entering a loop, exiting a loop, or it could be
619 // both: Jumping directly form one loop to the header of a sibling
621 // Split unless this edge is entering CurLoop from an outer loop.
622 ShouldSplit = PreLoop && !PreLoop->contains(CurLoop);
624 if (!ShouldSplit && !SplitAllCriticalEdges)
626 if (!PreMBB->SplitCriticalEdge(&MBB, *this)) {
627 DEBUG(dbgs() << "Failed to split critical edge.\n");
631 ++NumCriticalEdgesSplit;
637 bool PHIElimination::isLiveIn(unsigned Reg, const MachineBasicBlock *MBB) {
638 assert((LV || LIS) &&
639 "isLiveIn() requires either LiveVariables or LiveIntervals");
641 return LIS->isLiveInToMBB(LIS->getInterval(Reg), MBB);
643 return LV->isLiveIn(Reg, *MBB);
646 bool PHIElimination::isLiveOutPastPHIs(unsigned Reg,
647 const MachineBasicBlock *MBB) {
648 assert((LV || LIS) &&
649 "isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals");
650 // LiveVariables considers uses in PHIs to be in the predecessor basic block,
651 // so that a register used only in a PHI is not live out of the block. In
652 // contrast, LiveIntervals considers uses in PHIs to be on the edge rather than
653 // in the predecessor basic block, so that a register used only in a PHI is live
656 const LiveInterval &LI = LIS->getInterval(Reg);
657 for (const MachineBasicBlock *SI : MBB->successors())
658 if (LI.liveAt(LIS->getMBBStartIdx(SI)))
662 return LV->isLiveOut(Reg, *MBB);