1 //===- PhiElimination.cpp - Eliminate PHI nodes by inserting copies -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass eliminates machine instruction PHI nodes by inserting copy
11 // instructions. This destroys SSA information, but is the desired input for
12 // some register allocators.
14 //===----------------------------------------------------------------------===//
16 #include "PHIEliminationUtils.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallPtrSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/LoopInfo.h"
21 #include "llvm/CodeGen/LiveInterval.h"
22 #include "llvm/CodeGen/LiveIntervals.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineBasicBlock.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/MachineInstr.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineLoopInfo.h"
31 #include "llvm/CodeGen/MachineOperand.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/SlotIndexes.h"
34 #include "llvm/CodeGen/TargetInstrInfo.h"
35 #include "llvm/CodeGen/TargetOpcodes.h"
36 #include "llvm/CodeGen/TargetRegisterInfo.h"
37 #include "llvm/CodeGen/TargetSubtargetInfo.h"
38 #include "llvm/Pass.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/raw_ostream.h"
48 #define DEBUG_TYPE "phi-node-elimination"
51 DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false),
52 cl::Hidden, cl::desc("Disable critical edge splitting "
53 "during PHI elimination"));
56 SplitAllCriticalEdges("phi-elim-split-all-critical-edges", cl::init(false),
57 cl::Hidden, cl::desc("Split all critical edges during "
60 static cl::opt<bool> NoPhiElimLiveOutEarlyExit(
61 "no-phi-elim-live-out-early-exit", cl::init(false), cl::Hidden,
62 cl::desc("Do not use an early exit if isLiveOutPastPHIs returns true."));
66 class PHIElimination : public MachineFunctionPass {
67 MachineRegisterInfo *MRI; // Machine register information
72 static char ID; // Pass identification, replacement for typeid
74 PHIElimination() : MachineFunctionPass(ID) {
75 initializePHIEliminationPass(*PassRegistry::getPassRegistry());
78 bool runOnMachineFunction(MachineFunction &MF) override;
79 void getAnalysisUsage(AnalysisUsage &AU) const override;
82 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
83 /// in predecessor basic blocks.
84 bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
86 void LowerPHINode(MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator LastPHIIt);
89 /// analyzePHINodes - Gather information about the PHI nodes in
90 /// here. In particular, we want to map the number of uses of a virtual
91 /// register which is used in a PHI node. We map that to the BB the
92 /// vreg is coming from. This is used later to determine when the vreg
93 /// is killed in the BB.
94 void analyzePHINodes(const MachineFunction& MF);
96 /// Split critical edges where necessary for good coalescer performance.
97 bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
98 MachineLoopInfo *MLI);
100 // These functions are temporary abstractions around LiveVariables and
101 // LiveIntervals, so they can go away when LiveVariables does.
102 bool isLiveIn(unsigned Reg, const MachineBasicBlock *MBB);
103 bool isLiveOutPastPHIs(unsigned Reg, const MachineBasicBlock *MBB);
105 using BBVRegPair = std::pair<unsigned, unsigned>;
106 using VRegPHIUse = DenseMap<BBVRegPair, unsigned>;
108 VRegPHIUse VRegPHIUseCount;
110 // Defs of PHI sources which are implicit_def.
111 SmallPtrSet<MachineInstr*, 4> ImpDefs;
113 // Map reusable lowered PHI node -> incoming join register.
114 using LoweredPHIMap =
115 DenseMap<MachineInstr*, unsigned, MachineInstrExpressionTrait>;
116 LoweredPHIMap LoweredPHIs;
119 } // end anonymous namespace
121 STATISTIC(NumLowered, "Number of phis lowered");
122 STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split");
123 STATISTIC(NumReused, "Number of reused lowered phis");
125 char PHIElimination::ID = 0;
127 char& llvm::PHIEliminationID = PHIElimination::ID;
129 INITIALIZE_PASS_BEGIN(PHIElimination, DEBUG_TYPE,
130 "Eliminate PHI nodes for register allocation",
132 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
133 INITIALIZE_PASS_END(PHIElimination, DEBUG_TYPE,
134 "Eliminate PHI nodes for register allocation", false, false)
136 void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
137 AU.addUsedIfAvailable<LiveVariables>();
138 AU.addPreserved<LiveVariables>();
139 AU.addPreserved<SlotIndexes>();
140 AU.addPreserved<LiveIntervals>();
141 AU.addPreserved<MachineDominatorTree>();
142 AU.addPreserved<MachineLoopInfo>();
143 MachineFunctionPass::getAnalysisUsage(AU);
146 bool PHIElimination::runOnMachineFunction(MachineFunction &MF) {
147 MRI = &MF.getRegInfo();
148 LV = getAnalysisIfAvailable<LiveVariables>();
149 LIS = getAnalysisIfAvailable<LiveIntervals>();
151 bool Changed = false;
153 // This pass takes the function out of SSA form.
156 // Split critical edges to help the coalescer. This does not yet support
157 // updating LiveIntervals, so we disable it.
158 if (!DisableEdgeSplitting && (LV || LIS)) {
159 MachineLoopInfo *MLI = getAnalysisIfAvailable<MachineLoopInfo>();
161 Changed |= SplitPHIEdges(MF, MBB, MLI);
164 // Populate VRegPHIUseCount
167 // Eliminate PHI instructions by inserting copies into predecessor blocks.
169 Changed |= EliminatePHINodes(MF, MBB);
171 // Remove dead IMPLICIT_DEF instructions.
172 for (MachineInstr *DefMI : ImpDefs) {
173 unsigned DefReg = DefMI->getOperand(0).getReg();
174 if (MRI->use_nodbg_empty(DefReg)) {
176 LIS->RemoveMachineInstrFromMaps(*DefMI);
177 DefMI->eraseFromParent();
181 // Clean up the lowered PHI instructions.
182 for (auto &I : LoweredPHIs) {
184 LIS->RemoveMachineInstrFromMaps(*I.first);
185 MF.DeleteMachineInstr(I.first);
190 VRegPHIUseCount.clear();
192 MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
197 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
198 /// predecessor basic blocks.
199 bool PHIElimination::EliminatePHINodes(MachineFunction &MF,
200 MachineBasicBlock &MBB) {
201 if (MBB.empty() || !MBB.front().isPHI())
202 return false; // Quick exit for basic blocks without PHIs.
204 // Get an iterator to the first instruction after the last PHI node (this may
205 // also be the end of the basic block).
206 MachineBasicBlock::iterator LastPHIIt =
207 std::prev(MBB.SkipPHIsAndLabels(MBB.begin()));
209 while (MBB.front().isPHI())
210 LowerPHINode(MBB, LastPHIIt);
215 /// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
216 /// This includes registers with no defs.
217 static bool isImplicitlyDefined(unsigned VirtReg,
218 const MachineRegisterInfo *MRI) {
219 for (MachineInstr &DI : MRI->def_instructions(VirtReg))
220 if (!DI.isImplicitDef())
225 /// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
226 /// are implicit_def's.
227 static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
228 const MachineRegisterInfo *MRI) {
229 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
230 if (!isImplicitlyDefined(MPhi->getOperand(i).getReg(), MRI))
235 /// LowerPHINode - Lower the PHI node at the top of the specified block.
236 void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
237 MachineBasicBlock::iterator LastPHIIt) {
240 MachineBasicBlock::iterator AfterPHIsIt = std::next(LastPHIIt);
242 // Unlink the PHI node from the basic block, but don't delete the PHI yet.
243 MachineInstr *MPhi = MBB.remove(&*MBB.begin());
245 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
246 unsigned DestReg = MPhi->getOperand(0).getReg();
247 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
248 bool isDead = MPhi->getOperand(0).isDead();
250 // Create a new register for the incoming PHI arguments.
251 MachineFunction &MF = *MBB.getParent();
252 unsigned IncomingReg = 0;
253 bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI?
255 // Insert a register to register copy at the top of the current block (but
256 // after any remaining phi nodes) which copies the new incoming register
257 // into the phi node destination.
258 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
259 if (isSourceDefinedByImplicitDef(MPhi, MRI))
260 // If all sources of a PHI node are implicit_def, just emit an
261 // implicit_def instead of a copy.
262 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
263 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
265 // Can we reuse an earlier PHI node? This only happens for critical edges,
266 // typically those created by tail duplication.
267 unsigned &entry = LoweredPHIs[MPhi];
269 // An identical PHI node was already lowered. Reuse the incoming register.
271 reusedIncoming = true;
273 LLVM_DEBUG(dbgs() << "Reusing " << printReg(IncomingReg) << " for "
276 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
277 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
279 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
280 TII->get(TargetOpcode::COPY), DestReg)
281 .addReg(IncomingReg);
284 // Update live variable information if there is any.
286 MachineInstr &PHICopy = *std::prev(AfterPHIsIt);
289 LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
291 // Increment use count of the newly created virtual register.
292 LV->setPHIJoin(IncomingReg);
294 // When we are reusing the incoming register, it may already have been
295 // killed in this block. The old kill will also have been inserted at
296 // AfterPHIsIt, so it appears before the current PHICopy.
298 if (MachineInstr *OldKill = VI.findKill(&MBB)) {
299 LLVM_DEBUG(dbgs() << "Remove old kill from " << *OldKill);
300 LV->removeVirtualRegisterKilled(IncomingReg, *OldKill);
301 LLVM_DEBUG(MBB.dump());
304 // Add information to LiveVariables to know that the incoming value is
305 // killed. Note that because the value is defined in several places (once
306 // each for each incoming block), the "def" block and instruction fields
307 // for the VarInfo is not filled in.
308 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
311 // Since we are going to be deleting the PHI node, if it is the last use of
312 // any registers, or if the value itself is dead, we need to move this
313 // information over to the new copy we just inserted.
314 LV->removeVirtualRegistersKilled(*MPhi);
316 // If the result is dead, update LV.
318 LV->addVirtualRegisterDead(DestReg, PHICopy);
319 LV->removeVirtualRegisterDead(DestReg, *MPhi);
323 // Update LiveIntervals for the new copy or implicit def.
325 SlotIndex DestCopyIndex =
326 LIS->InsertMachineInstrInMaps(*std::prev(AfterPHIsIt));
328 SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
330 // Add the region from the beginning of MBB to the copy instruction to
331 // IncomingReg's live interval.
332 LiveInterval &IncomingLI = LIS->createEmptyInterval(IncomingReg);
333 VNInfo *IncomingVNI = IncomingLI.getVNInfoAt(MBBStartIndex);
335 IncomingVNI = IncomingLI.getNextValue(MBBStartIndex,
336 LIS->getVNInfoAllocator());
337 IncomingLI.addSegment(LiveInterval::Segment(MBBStartIndex,
338 DestCopyIndex.getRegSlot(),
342 LiveInterval &DestLI = LIS->getInterval(DestReg);
343 assert(DestLI.begin() != DestLI.end() &&
344 "PHIs should have nonempty LiveIntervals.");
345 if (DestLI.endIndex().isDead()) {
346 // A dead PHI's live range begins and ends at the start of the MBB, but
347 // the lowered copy, which will still be dead, needs to begin and end at
348 // the copy instruction.
349 VNInfo *OrigDestVNI = DestLI.getVNInfoAt(MBBStartIndex);
350 assert(OrigDestVNI && "PHI destination should be live at block entry.");
351 DestLI.removeSegment(MBBStartIndex, MBBStartIndex.getDeadSlot());
352 DestLI.createDeadDef(DestCopyIndex.getRegSlot(),
353 LIS->getVNInfoAllocator());
354 DestLI.removeValNo(OrigDestVNI);
356 // Otherwise, remove the region from the beginning of MBB to the copy
357 // instruction from DestReg's live interval.
358 DestLI.removeSegment(MBBStartIndex, DestCopyIndex.getRegSlot());
359 VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getRegSlot());
360 assert(DestVNI && "PHI destination should be live at its definition.");
361 DestVNI->def = DestCopyIndex.getRegSlot();
365 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
366 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
367 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(),
368 MPhi->getOperand(i).getReg())];
370 // Now loop over all of the incoming arguments, changing them to copy into the
371 // IncomingReg register in the corresponding predecessor basic block.
372 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
373 for (int i = NumSrcs - 1; i >= 0; --i) {
374 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
375 unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
376 bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() ||
377 isImplicitlyDefined(SrcReg, MRI);
378 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
379 "Machine PHI Operands must all be virtual registers!");
381 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
383 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
385 // Check to make sure we haven't already emitted the copy for this block.
386 // This can happen because PHI nodes may have multiple entries for the same
388 if (!MBBsInsertedInto.insert(&opBlock).second)
389 continue; // If the copy has already been emitted, we're done.
391 // Find a safe location to insert the copy, this may be the first terminator
392 // in the block (or end()).
393 MachineBasicBlock::iterator InsertPos =
394 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
397 MachineInstr *NewSrcInstr = nullptr;
398 if (!reusedIncoming && IncomingReg) {
400 // The source register is undefined, so there is no need for a real
401 // COPY, but we still need to ensure joint dominance by defs.
402 // Insert an IMPLICIT_DEF instruction.
403 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
404 TII->get(TargetOpcode::IMPLICIT_DEF),
407 // Clean up the old implicit-def, if there even was one.
408 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
409 if (DefMI->isImplicitDef())
410 ImpDefs.insert(DefMI);
412 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
413 TII->get(TargetOpcode::COPY), IncomingReg)
414 .addReg(SrcReg, 0, SrcSubReg);
418 // We only need to update the LiveVariables kill of SrcReg if this was the
419 // last PHI use of SrcReg to be lowered on this CFG edge and it is not live
420 // out of the predecessor. We can also ignore undef sources.
421 if (LV && !SrcUndef &&
422 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
423 !LV->isLiveOut(SrcReg, opBlock)) {
424 // We want to be able to insert a kill of the register if this PHI (aka,
425 // the copy we just inserted) is the last use of the source value. Live
426 // variable analysis conservatively handles this by saying that the value
427 // is live until the end of the block the PHI entry lives in. If the value
428 // really is dead at the PHI copy, there will be no successor blocks which
429 // have the value live-in.
431 // Okay, if we now know that the value is not live out of the block, we
432 // can add a kill marker in this block saying that it kills the incoming
435 // In our final twist, we have to decide which instruction kills the
436 // register. In most cases this is the copy, however, terminator
437 // instructions at the end of the block may also use the value. In this
438 // case, we should mark the last such terminator as being the killing
439 // block, not the copy.
440 MachineBasicBlock::iterator KillInst = opBlock.end();
441 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
442 for (MachineBasicBlock::iterator Term = FirstTerm;
443 Term != opBlock.end(); ++Term) {
444 if (Term->readsRegister(SrcReg))
448 if (KillInst == opBlock.end()) {
449 // No terminator uses the register.
451 if (reusedIncoming || !IncomingReg) {
452 // We may have to rewind a bit if we didn't insert a copy this time.
453 KillInst = FirstTerm;
454 while (KillInst != opBlock.begin()) {
456 if (KillInst->isDebugInstr())
458 if (KillInst->readsRegister(SrcReg))
462 // We just inserted this copy.
463 KillInst = std::prev(InsertPos);
466 assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
468 // Finally, mark it killed.
469 LV->addVirtualRegisterKilled(SrcReg, *KillInst);
471 // This vreg no longer lives all of the way through opBlock.
472 unsigned opBlockNum = opBlock.getNumber();
473 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
478 LIS->InsertMachineInstrInMaps(*NewSrcInstr);
479 LIS->addSegmentToEndOfBlock(IncomingReg, *NewSrcInstr);
483 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]) {
484 LiveInterval &SrcLI = LIS->getInterval(SrcReg);
486 bool isLiveOut = false;
487 for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(),
488 SE = opBlock.succ_end(); SI != SE; ++SI) {
489 SlotIndex startIdx = LIS->getMBBStartIdx(*SI);
490 VNInfo *VNI = SrcLI.getVNInfoAt(startIdx);
492 // Definitions by other PHIs are not truly live-in for our purposes.
493 if (VNI && VNI->def != startIdx) {
500 MachineBasicBlock::iterator KillInst = opBlock.end();
501 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
502 for (MachineBasicBlock::iterator Term = FirstTerm;
503 Term != opBlock.end(); ++Term) {
504 if (Term->readsRegister(SrcReg))
508 if (KillInst == opBlock.end()) {
509 // No terminator uses the register.
511 if (reusedIncoming || !IncomingReg) {
512 // We may have to rewind a bit if we didn't just insert a copy.
513 KillInst = FirstTerm;
514 while (KillInst != opBlock.begin()) {
516 if (KillInst->isDebugInstr())
518 if (KillInst->readsRegister(SrcReg))
522 // We just inserted this copy.
523 KillInst = std::prev(InsertPos);
526 assert(KillInst->readsRegister(SrcReg) &&
527 "Cannot find kill instruction");
529 SlotIndex LastUseIndex = LIS->getInstructionIndex(*KillInst);
530 SrcLI.removeSegment(LastUseIndex.getRegSlot(),
531 LIS->getMBBEndIdx(&opBlock));
537 // Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
538 if (reusedIncoming || !IncomingReg) {
540 LIS->RemoveMachineInstrFromMaps(*MPhi);
541 MF.DeleteMachineInstr(MPhi);
545 /// analyzePHINodes - Gather information about the PHI nodes in here. In
546 /// particular, we want to map the number of uses of a virtual register which is
547 /// used in a PHI node. We map that to the BB the vreg is coming from. This is
548 /// used later to determine when the vreg is killed in the BB.
549 void PHIElimination::analyzePHINodes(const MachineFunction& MF) {
550 for (const auto &MBB : MF)
551 for (const auto &BBI : MBB) {
554 for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2)
555 ++VRegPHIUseCount[BBVRegPair(BBI.getOperand(i+1).getMBB()->getNumber(),
556 BBI.getOperand(i).getReg())];
560 bool PHIElimination::SplitPHIEdges(MachineFunction &MF,
561 MachineBasicBlock &MBB,
562 MachineLoopInfo *MLI) {
563 if (MBB.empty() || !MBB.front().isPHI() || MBB.isEHPad())
564 return false; // Quick exit for basic blocks without PHIs.
566 const MachineLoop *CurLoop = MLI ? MLI->getLoopFor(&MBB) : nullptr;
567 bool IsLoopHeader = CurLoop && &MBB == CurLoop->getHeader();
569 bool Changed = false;
570 for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end();
571 BBI != BBE && BBI->isPHI(); ++BBI) {
572 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
573 unsigned Reg = BBI->getOperand(i).getReg();
574 MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
575 // Is there a critical edge from PreMBB to MBB?
576 if (PreMBB->succ_size() == 1)
579 // Avoid splitting backedges of loops. It would introduce small
580 // out-of-line blocks into the loop which is very bad for code placement.
581 if (PreMBB == &MBB && !SplitAllCriticalEdges)
583 const MachineLoop *PreLoop = MLI ? MLI->getLoopFor(PreMBB) : nullptr;
584 if (IsLoopHeader && PreLoop == CurLoop && !SplitAllCriticalEdges)
587 // LV doesn't consider a phi use live-out, so isLiveOut only returns true
588 // when the source register is live-out for some other reason than a phi
589 // use. That means the copy we will insert in PreMBB won't be a kill, and
590 // there is a risk it may not be coalesced away.
592 // If the copy would be a kill, there is no need to split the edge.
593 bool ShouldSplit = isLiveOutPastPHIs(Reg, PreMBB);
594 if (!ShouldSplit && !NoPhiElimLiveOutEarlyExit)
597 LLVM_DEBUG(dbgs() << printReg(Reg) << " live-out before critical edge "
598 << printMBBReference(*PreMBB) << " -> "
599 << printMBBReference(MBB) << ": " << *BBI);
602 // If Reg is not live-in to MBB, it means it must be live-in to some
603 // other PreMBB successor, and we can avoid the interference by splitting
606 // If Reg *is* live-in to MBB, the interference is inevitable and a copy
607 // is likely to be left after coalescing. If we are looking at a loop
608 // exiting edge, split it so we won't insert code in the loop, otherwise
610 ShouldSplit = ShouldSplit && !isLiveIn(Reg, &MBB);
612 // Check for a loop exiting edge.
613 if (!ShouldSplit && CurLoop != PreLoop) {
615 dbgs() << "Split wouldn't help, maybe avoid loop copies?\n";
617 dbgs() << "PreLoop: " << *PreLoop;
619 dbgs() << "CurLoop: " << *CurLoop;
621 // This edge could be entering a loop, exiting a loop, or it could be
622 // both: Jumping directly form one loop to the header of a sibling
624 // Split unless this edge is entering CurLoop from an outer loop.
625 ShouldSplit = PreLoop && !PreLoop->contains(CurLoop);
627 if (!ShouldSplit && !SplitAllCriticalEdges)
629 if (!PreMBB->SplitCriticalEdge(&MBB, *this)) {
630 LLVM_DEBUG(dbgs() << "Failed to split critical edge.\n");
634 ++NumCriticalEdgesSplit;
640 bool PHIElimination::isLiveIn(unsigned Reg, const MachineBasicBlock *MBB) {
641 assert((LV || LIS) &&
642 "isLiveIn() requires either LiveVariables or LiveIntervals");
644 return LIS->isLiveInToMBB(LIS->getInterval(Reg), MBB);
646 return LV->isLiveIn(Reg, *MBB);
649 bool PHIElimination::isLiveOutPastPHIs(unsigned Reg,
650 const MachineBasicBlock *MBB) {
651 assert((LV || LIS) &&
652 "isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals");
653 // LiveVariables considers uses in PHIs to be in the predecessor basic block,
654 // so that a register used only in a PHI is not live out of the block. In
655 // contrast, LiveIntervals considers uses in PHIs to be on the edge rather than
656 // in the predecessor basic block, so that a register used only in a PHI is live
659 const LiveInterval &LI = LIS->getInterval(Reg);
660 for (const MachineBasicBlock *SI : MBB->successors())
661 if (LI.liveAt(LIS->getMBBStartIdx(SI)))
665 return LV->isLiveOut(Reg, *MBB);