1 //===-- PeepholeOptimizer.cpp - Peephole Optimizations --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Perform peephole optimizations on the machine code:
12 // - Optimize Extensions
14 // Optimization of sign / zero extension instructions. It may be extended to
15 // handle other instructions with similar properties.
17 // On some targets, some instructions, e.g. X86 sign / zero extension, may
18 // leave the source value in the lower part of the result. This optimization
19 // will replace some uses of the pre-extension value with uses of the
20 // sub-register of the results.
22 // - Optimize Comparisons
24 // Optimization of comparison instructions. For instance, in this code:
30 // If the "sub" instruction all ready sets (or could be modified to set) the
31 // same flag that the "cmp" instruction sets and that "bz" uses, then we can
32 // eliminate the "cmp" instruction.
34 // Another instance, in this code:
36 // sub r1, r3 | sub r1, imm
37 // cmp r3, r1 or cmp r1, r3 | cmp r1, imm
40 // If the branch instruction can use flag from "sub", then we can replace
41 // "sub" with "subs" and eliminate the "cmp" instruction.
45 // Loads that can be folded into a later instruction. A load is foldable
46 // if it loads to virtual registers and the virtual register defined has
49 // - Optimize Copies and Bitcast (more generally, target specific copies):
51 // Rewrite copies and bitcasts to avoid cross register bank copies
53 // E.g., Consider the following example, where capital and lower
54 // letters denote different register file:
55 // b = copy A <-- cross-bank copy
56 // C = copy b <-- cross-bank copy
58 // b = copy A <-- cross-bank copy
59 // C = copy A <-- same-bank copy
62 // b = bitcast A <-- cross-bank copy
63 // C = bitcast b <-- cross-bank copy
65 // b = bitcast A <-- cross-bank copy
66 // C = copy A <-- same-bank copy
67 //===----------------------------------------------------------------------===//
69 #include "llvm/CodeGen/Passes.h"
70 #include "llvm/ADT/DenseMap.h"
71 #include "llvm/ADT/SmallPtrSet.h"
72 #include "llvm/ADT/SmallSet.h"
73 #include "llvm/ADT/SmallVector.h"
74 #include "llvm/ADT/Statistic.h"
75 #include "llvm/CodeGen/MachineBasicBlock.h"
76 #include "llvm/CodeGen/MachineDominators.h"
77 #include "llvm/CodeGen/MachineFunction.h"
78 #include "llvm/CodeGen/MachineInstr.h"
79 #include "llvm/CodeGen/MachineInstrBuilder.h"
80 #include "llvm/CodeGen/MachineOperand.h"
81 #include "llvm/CodeGen/MachineRegisterInfo.h"
82 #include "llvm/MC/MCInstrDesc.h"
83 #include "llvm/Support/CommandLine.h"
84 #include "llvm/Support/Debug.h"
85 #include "llvm/Support/ErrorHandling.h"
86 #include "llvm/Support/raw_ostream.h"
87 #include "llvm/Target/TargetInstrInfo.h"
88 #include "llvm/Target/TargetRegisterInfo.h"
89 #include "llvm/Target/TargetSubtargetInfo.h"
97 #define DEBUG_TYPE "peephole-opt"
99 // Optimize Extensions
101 Aggressive("aggressive-ext-opt", cl::Hidden,
102 cl::desc("Aggressive extension optimization"));
105 DisablePeephole("disable-peephole", cl::Hidden, cl::init(false),
106 cl::desc("Disable the peephole optimizer"));
109 DisableAdvCopyOpt("disable-adv-copy-opt", cl::Hidden, cl::init(false),
110 cl::desc("Disable advanced copy optimization"));
112 static cl::opt<bool> DisableNAPhysCopyOpt(
113 "disable-non-allocatable-phys-copy-opt", cl::Hidden, cl::init(false),
114 cl::desc("Disable non-allocatable physical register copy optimization"));
116 // Limit the number of PHI instructions to process
117 // in PeepholeOptimizer::getNextSource.
118 static cl::opt<unsigned> RewritePHILimit(
119 "rewrite-phi-limit", cl::Hidden, cl::init(10),
120 cl::desc("Limit the length of PHI chains to lookup"));
122 STATISTIC(NumReuse, "Number of extension results reused");
123 STATISTIC(NumCmps, "Number of compares eliminated");
124 STATISTIC(NumImmFold, "Number of move immediate folded");
125 STATISTIC(NumLoadFold, "Number of loads folded");
126 STATISTIC(NumSelects, "Number of selects optimized");
127 STATISTIC(NumUncoalescableCopies, "Number of uncoalescable copies optimized");
128 STATISTIC(NumRewrittenCopies, "Number of copies rewritten");
129 STATISTIC(NumNAPhysCopies, "Number of non-allocatable physical copies removed");
133 class ValueTrackerResult;
135 class PeepholeOptimizer : public MachineFunctionPass {
136 const TargetInstrInfo *TII;
137 const TargetRegisterInfo *TRI;
138 MachineRegisterInfo *MRI;
139 MachineDominatorTree *DT; // Machine dominator tree
142 static char ID; // Pass identification
144 PeepholeOptimizer() : MachineFunctionPass(ID) {
145 initializePeepholeOptimizerPass(*PassRegistry::getPassRegistry());
148 bool runOnMachineFunction(MachineFunction &MF) override;
150 void getAnalysisUsage(AnalysisUsage &AU) const override {
151 AU.setPreservesCFG();
152 MachineFunctionPass::getAnalysisUsage(AU);
154 AU.addRequired<MachineDominatorTree>();
155 AU.addPreserved<MachineDominatorTree>();
159 /// \brief Track Def -> Use info used for rewriting copies.
160 typedef SmallDenseMap<TargetInstrInfo::RegSubRegPair, ValueTrackerResult>
164 bool optimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB);
165 bool optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
166 SmallPtrSetImpl<MachineInstr*> &LocalMIs);
167 bool optimizeSelect(MachineInstr *MI,
168 SmallPtrSetImpl<MachineInstr *> &LocalMIs);
169 bool optimizeCondBranch(MachineInstr *MI);
170 bool optimizeCoalescableCopy(MachineInstr *MI);
171 bool optimizeUncoalescableCopy(MachineInstr *MI,
172 SmallPtrSetImpl<MachineInstr *> &LocalMIs);
173 bool findNextSource(unsigned Reg, unsigned SubReg,
174 RewriteMapTy &RewriteMap);
175 bool isMoveImmediate(MachineInstr *MI,
176 SmallSet<unsigned, 4> &ImmDefRegs,
177 DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
178 bool foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
179 SmallSet<unsigned, 4> &ImmDefRegs,
180 DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
182 /// \brief If copy instruction \p MI is a virtual register copy, track it in
183 /// the set \p CopySrcRegs and \p CopyMIs. If this virtual register was
184 /// previously seen as a copy, replace the uses of this copy with the
185 /// previously seen copy's destination register.
186 bool foldRedundantCopy(MachineInstr *MI,
187 SmallSet<unsigned, 4> &CopySrcRegs,
188 DenseMap<unsigned, MachineInstr *> &CopyMIs);
190 /// \brief Is the register \p Reg a non-allocatable physical register?
191 bool isNAPhysCopy(unsigned Reg);
193 /// \brief If copy instruction \p MI is a non-allocatable virtual<->physical
194 /// register copy, track it in the \p NAPhysToVirtMIs map. If this
195 /// non-allocatable physical register was previously copied to a virtual
196 /// registered and hasn't been clobbered, the virt->phys copy can be
198 bool foldRedundantNAPhysCopy(
200 DenseMap<unsigned, MachineInstr *> &NAPhysToVirtMIs);
202 bool isLoadFoldable(MachineInstr *MI,
203 SmallSet<unsigned, 16> &FoldAsLoadDefCandidates);
205 /// \brief Check whether \p MI is understood by the register coalescer
206 /// but may require some rewriting.
207 bool isCoalescableCopy(const MachineInstr &MI) {
208 // SubregToRegs are not interesting, because they are already register
209 // coalescer friendly.
210 return MI.isCopy() || (!DisableAdvCopyOpt &&
211 (MI.isRegSequence() || MI.isInsertSubreg() ||
212 MI.isExtractSubreg()));
215 /// \brief Check whether \p MI is a copy like instruction that is
216 /// not recognized by the register coalescer.
217 bool isUncoalescableCopy(const MachineInstr &MI) {
218 return MI.isBitcast() ||
219 (!DisableAdvCopyOpt &&
220 (MI.isRegSequenceLike() || MI.isInsertSubregLike() ||
221 MI.isExtractSubregLike()));
225 /// \brief Helper class to hold a reply for ValueTracker queries. Contains the
226 /// returned sources for a given search and the instructions where the sources
227 /// were tracked from.
228 class ValueTrackerResult {
230 /// Track all sources found by one ValueTracker query.
231 SmallVector<TargetInstrInfo::RegSubRegPair, 2> RegSrcs;
233 /// Instruction using the sources in 'RegSrcs'.
234 const MachineInstr *Inst;
237 ValueTrackerResult() : Inst(nullptr) {}
238 ValueTrackerResult(unsigned Reg, unsigned SubReg) : Inst(nullptr) {
239 addSource(Reg, SubReg);
242 bool isValid() const { return getNumSources() > 0; }
244 void setInst(const MachineInstr *I) { Inst = I; }
245 const MachineInstr *getInst() const { return Inst; }
252 void addSource(unsigned SrcReg, unsigned SrcSubReg) {
253 RegSrcs.push_back(TargetInstrInfo::RegSubRegPair(SrcReg, SrcSubReg));
256 void setSource(int Idx, unsigned SrcReg, unsigned SrcSubReg) {
257 assert(Idx < getNumSources() && "Reg pair source out of index");
258 RegSrcs[Idx] = TargetInstrInfo::RegSubRegPair(SrcReg, SrcSubReg);
261 int getNumSources() const { return RegSrcs.size(); }
263 unsigned getSrcReg(int Idx) const {
264 assert(Idx < getNumSources() && "Reg source out of index");
265 return RegSrcs[Idx].Reg;
268 unsigned getSrcSubReg(int Idx) const {
269 assert(Idx < getNumSources() && "SubReg source out of index");
270 return RegSrcs[Idx].SubReg;
273 bool operator==(const ValueTrackerResult &Other) {
274 if (Other.getInst() != getInst())
277 if (Other.getNumSources() != getNumSources())
280 for (int i = 0, e = Other.getNumSources(); i != e; ++i)
281 if (Other.getSrcReg(i) != getSrcReg(i) ||
282 Other.getSrcSubReg(i) != getSrcSubReg(i))
288 /// \brief Helper class to track the possible sources of a value defined by
289 /// a (chain of) copy related instructions.
290 /// Given a definition (instruction and definition index), this class
291 /// follows the use-def chain to find successive suitable sources.
292 /// The given source can be used to rewrite the definition into
295 /// For instance, let us consider the following snippet:
297 /// v2 = INSERT_SUBREG v1, v0, sub0
298 /// def = COPY v2.sub0
300 /// Using a ValueTracker for def = COPY v2.sub0 will give the following
301 /// suitable sources:
303 /// Then, def can be rewritten into def = COPY v0.
306 /// The current point into the use-def chain.
307 const MachineInstr *Def;
308 /// The index of the definition in Def.
310 /// The sub register index of the definition.
312 /// The register where the value can be found.
314 /// Specifiy whether or not the value tracking looks through
315 /// complex instructions. When this is false, the value tracker
316 /// bails on everything that is not a copy or a bitcast.
318 /// Note: This could have been implemented as a specialized version of
319 /// the ValueTracker class but that would have complicated the code of
320 /// the users of this class.
321 bool UseAdvancedTracking;
322 /// MachineRegisterInfo used to perform tracking.
323 const MachineRegisterInfo &MRI;
324 /// Optional TargetInstrInfo used to perform some complex
326 const TargetInstrInfo *TII;
328 /// \brief Dispatcher to the right underlying implementation of
330 ValueTrackerResult getNextSourceImpl();
331 /// \brief Specialized version of getNextSource for Copy instructions.
332 ValueTrackerResult getNextSourceFromCopy();
333 /// \brief Specialized version of getNextSource for Bitcast instructions.
334 ValueTrackerResult getNextSourceFromBitcast();
335 /// \brief Specialized version of getNextSource for RegSequence
337 ValueTrackerResult getNextSourceFromRegSequence();
338 /// \brief Specialized version of getNextSource for InsertSubreg
340 ValueTrackerResult getNextSourceFromInsertSubreg();
341 /// \brief Specialized version of getNextSource for ExtractSubreg
343 ValueTrackerResult getNextSourceFromExtractSubreg();
344 /// \brief Specialized version of getNextSource for SubregToReg
346 ValueTrackerResult getNextSourceFromSubregToReg();
347 /// \brief Specialized version of getNextSource for PHI instructions.
348 ValueTrackerResult getNextSourceFromPHI();
351 /// \brief Create a ValueTracker instance for the value defined by \p Reg.
352 /// \p DefSubReg represents the sub register index the value tracker will
353 /// track. It does not need to match the sub register index used in the
354 /// definition of \p Reg.
355 /// \p UseAdvancedTracking specifies whether or not the value tracker looks
356 /// through complex instructions. By default (false), it handles only copy
357 /// and bitcast instructions.
358 /// If \p Reg is a physical register, a value tracker constructed with
359 /// this constructor will not find any alternative source.
360 /// Indeed, when \p Reg is a physical register that constructor does not
361 /// know which definition of \p Reg it should track.
362 /// Use the next constructor to track a physical register.
363 ValueTracker(unsigned Reg, unsigned DefSubReg,
364 const MachineRegisterInfo &MRI,
365 bool UseAdvancedTracking = false,
366 const TargetInstrInfo *TII = nullptr)
367 : Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg),
368 UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) {
369 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) {
370 Def = MRI.getVRegDef(Reg);
371 DefIdx = MRI.def_begin(Reg).getOperandNo();
375 /// \brief Create a ValueTracker instance for the value defined by
376 /// the pair \p MI, \p DefIdx.
377 /// Unlike the other constructor, the value tracker produced by this one
378 /// may be able to find a new source when the definition is a physical
380 /// This could be useful to rewrite target specific instructions into
381 /// generic copy instructions.
382 ValueTracker(const MachineInstr &MI, unsigned DefIdx, unsigned DefSubReg,
383 const MachineRegisterInfo &MRI,
384 bool UseAdvancedTracking = false,
385 const TargetInstrInfo *TII = nullptr)
386 : Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg),
387 UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) {
388 assert(DefIdx < Def->getDesc().getNumDefs() &&
389 Def->getOperand(DefIdx).isReg() && "Invalid definition");
390 Reg = Def->getOperand(DefIdx).getReg();
393 /// \brief Following the use-def chain, get the next available source
394 /// for the tracked value.
395 /// \return A ValueTrackerResult containing a set of registers
396 /// and sub registers with tracked values. A ValueTrackerResult with
397 /// an empty set of registers means no source was found.
398 ValueTrackerResult getNextSource();
400 /// \brief Get the last register where the initial value can be found.
401 /// Initially this is the register of the definition.
402 /// Then, after each successful call to getNextSource, this is the
403 /// register of the last source.
404 unsigned getReg() const { return Reg; }
407 } // end anonymous namespace
409 char PeepholeOptimizer::ID = 0;
410 char &llvm::PeepholeOptimizerID = PeepholeOptimizer::ID;
412 INITIALIZE_PASS_BEGIN(PeepholeOptimizer, DEBUG_TYPE,
413 "Peephole Optimizations", false, false)
414 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
415 INITIALIZE_PASS_END(PeepholeOptimizer, DEBUG_TYPE,
416 "Peephole Optimizations", false, false)
418 /// If instruction is a copy-like instruction, i.e. it reads a single register
419 /// and writes a single register and it does not modify the source, and if the
420 /// source value is preserved as a sub-register of the result, then replace all
421 /// reachable uses of the source with the subreg of the result.
423 /// Do not generate an EXTRACT that is used only in a debug use, as this changes
424 /// the code. Since this code does not currently share EXTRACTs, just ignore all
426 bool PeepholeOptimizer::
427 optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
428 SmallPtrSetImpl<MachineInstr*> &LocalMIs) {
429 unsigned SrcReg, DstReg, SubIdx;
430 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
433 if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||
434 TargetRegisterInfo::isPhysicalRegister(SrcReg))
437 if (MRI->hasOneNonDBGUse(SrcReg))
441 // Ensure DstReg can get a register class that actually supports
442 // sub-registers. Don't change the class until we commit.
443 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
444 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx);
448 // The ext instr may be operating on a sub-register of SrcReg as well.
449 // PPC::EXTSW is a 32 -> 64-bit sign extension, but it reads a 64-bit
451 // If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only uses of
452 // SrcReg:SubIdx should be replaced.
454 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr;
456 // The source has other uses. See if we can replace the other uses with use of
457 // the result of the extension.
458 SmallPtrSet<MachineBasicBlock*, 4> ReachedBBs;
459 for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
460 ReachedBBs.insert(UI.getParent());
462 // Uses that are in the same BB of uses of the result of the instruction.
463 SmallVector<MachineOperand*, 8> Uses;
465 // Uses that the result of the instruction can reach.
466 SmallVector<MachineOperand*, 8> ExtendedUses;
468 bool ExtendLife = true;
469 for (MachineOperand &UseMO : MRI->use_nodbg_operands(SrcReg)) {
470 MachineInstr *UseMI = UseMO.getParent();
474 if (UseMI->isPHI()) {
479 // Only accept uses of SrcReg:SubIdx.
480 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
483 // It's an error to translate this:
485 // %reg1025 = <sext> %reg1024
487 // %reg1026 = SUBREG_TO_REG 0, %reg1024, 4
491 // %reg1025 = <sext> %reg1024
493 // %reg1027 = COPY %reg1025:4
494 // %reg1026 = SUBREG_TO_REG 0, %reg1027, 4
496 // The problem here is that SUBREG_TO_REG is there to assert that an
497 // implicit zext occurs. It doesn't insert a zext instruction. If we allow
498 // the COPY here, it will give us the value after the <sext>, not the
499 // original value of %reg1024 before <sext>.
500 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
503 MachineBasicBlock *UseMBB = UseMI->getParent();
505 // Local uses that come after the extension.
506 if (!LocalMIs.count(UseMI))
507 Uses.push_back(&UseMO);
508 } else if (ReachedBBs.count(UseMBB)) {
509 // Non-local uses where the result of the extension is used. Always
510 // replace these unless it's a PHI.
511 Uses.push_back(&UseMO);
512 } else if (Aggressive && DT->dominates(MBB, UseMBB)) {
513 // We may want to extend the live range of the extension result in order
514 // to replace these uses.
515 ExtendedUses.push_back(&UseMO);
517 // Both will be live out of the def MBB anyway. Don't extend live range of
518 // the extension result.
524 if (ExtendLife && !ExtendedUses.empty())
525 // Extend the liveness of the extension result.
526 Uses.append(ExtendedUses.begin(), ExtendedUses.end());
528 // Now replace all uses.
529 bool Changed = false;
531 SmallPtrSet<MachineBasicBlock*, 4> PHIBBs;
533 // Look for PHI uses of the extended result, we don't want to extend the
534 // liveness of a PHI input. It breaks all kinds of assumptions down
535 // stream. A PHI use is expected to be the kill of its source values.
536 for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
538 PHIBBs.insert(UI.getParent());
540 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
541 for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
542 MachineOperand *UseMO = Uses[i];
543 MachineInstr *UseMI = UseMO->getParent();
544 MachineBasicBlock *UseMBB = UseMI->getParent();
545 if (PHIBBs.count(UseMBB))
548 // About to add uses of DstReg, clear DstReg's kill flags.
550 MRI->clearKillFlags(DstReg);
551 MRI->constrainRegClass(DstReg, DstRC);
554 unsigned NewVR = MRI->createVirtualRegister(RC);
555 MachineInstr *Copy = BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
556 TII->get(TargetOpcode::COPY), NewVR)
557 .addReg(DstReg, 0, SubIdx);
558 // SubIdx applies to both SrcReg and DstReg when UseSrcSubIdx is set.
560 Copy->getOperand(0).setSubReg(SubIdx);
561 Copy->getOperand(0).setIsUndef();
563 UseMO->setReg(NewVR);
572 /// If the instruction is a compare and the previous instruction it's comparing
573 /// against already sets (or could be modified to set) the same flag as the
574 /// compare, then we can remove the comparison and use the flag from the
575 /// previous instruction.
576 bool PeepholeOptimizer::optimizeCmpInstr(MachineInstr *MI,
577 MachineBasicBlock *MBB) {
578 // If this instruction is a comparison against zero and isn't comparing a
579 // physical register, we can try to optimize it.
580 unsigned SrcReg, SrcReg2;
581 int CmpMask, CmpValue;
582 if (!TII->analyzeCompare(*MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
583 TargetRegisterInfo::isPhysicalRegister(SrcReg) ||
584 (SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2)))
587 // Attempt to optimize the comparison instruction.
588 if (TII->optimizeCompareInstr(*MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
596 /// Optimize a select instruction.
597 bool PeepholeOptimizer::optimizeSelect(MachineInstr *MI,
598 SmallPtrSetImpl<MachineInstr *> &LocalMIs) {
600 unsigned FalseOp = 0;
601 bool Optimizable = false;
602 SmallVector<MachineOperand, 4> Cond;
603 if (TII->analyzeSelect(*MI, Cond, TrueOp, FalseOp, Optimizable))
607 if (!TII->optimizeSelect(*MI, LocalMIs))
609 MI->eraseFromParent();
614 /// \brief Check if a simpler conditional branch can be
616 bool PeepholeOptimizer::optimizeCondBranch(MachineInstr *MI) {
617 return TII->optimizeCondBranch(*MI);
620 /// \brief Try to find the next source that share the same register file
621 /// for the value defined by \p Reg and \p SubReg.
622 /// When true is returned, the \p RewriteMap can be used by the client to
623 /// retrieve all Def -> Use along the way up to the next source. Any found
624 /// Use that is not itself a key for another entry, is the next source to
625 /// use. During the search for the next source, multiple sources can be found
626 /// given multiple incoming sources of a PHI instruction. In this case, we
627 /// look in each PHI source for the next source; all found next sources must
628 /// share the same register file as \p Reg and \p SubReg. The client should
629 /// then be capable to rewrite all intermediate PHIs to get the next source.
630 /// \return False if no alternative sources are available. True otherwise.
631 bool PeepholeOptimizer::findNextSource(unsigned Reg, unsigned SubReg,
632 RewriteMapTy &RewriteMap) {
633 // Do not try to find a new source for a physical register.
634 // So far we do not have any motivating example for doing that.
635 // Thus, instead of maintaining untested code, we will revisit that if
636 // that changes at some point.
637 if (TargetRegisterInfo::isPhysicalRegister(Reg))
639 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
641 SmallVector<TargetInstrInfo::RegSubRegPair, 4> SrcToLook;
642 TargetInstrInfo::RegSubRegPair CurSrcPair(Reg, SubReg);
643 SrcToLook.push_back(CurSrcPair);
645 unsigned PHICount = 0;
646 while (!SrcToLook.empty() && PHICount < RewritePHILimit) {
647 TargetInstrInfo::RegSubRegPair Pair = SrcToLook.pop_back_val();
648 // As explained above, do not handle physical registers
649 if (TargetRegisterInfo::isPhysicalRegister(Pair.Reg))
653 ValueTracker ValTracker(CurSrcPair.Reg, CurSrcPair.SubReg, *MRI,
654 !DisableAdvCopyOpt, TII);
655 ValueTrackerResult Res;
656 bool ShouldRewrite = false;
659 // Follow the chain of copies until we reach the top of the use-def chain
660 // or find a more suitable source.
661 Res = ValTracker.getNextSource();
665 // Insert the Def -> Use entry for the recently found source.
666 ValueTrackerResult CurSrcRes = RewriteMap.lookup(CurSrcPair);
667 if (CurSrcRes.isValid()) {
668 assert(CurSrcRes == Res && "ValueTrackerResult found must match");
669 // An existent entry with multiple sources is a PHI cycle we must avoid.
670 // Otherwise it's an entry with a valid next source we already found.
671 if (CurSrcRes.getNumSources() > 1) {
672 DEBUG(dbgs() << "findNextSource: found PHI cycle, aborting...\n");
677 RewriteMap.insert(std::make_pair(CurSrcPair, Res));
679 // ValueTrackerResult usually have one source unless it's the result from
680 // a PHI instruction. Add the found PHI edges to be looked up further.
681 unsigned NumSrcs = Res.getNumSources();
684 for (unsigned i = 0; i < NumSrcs; ++i)
685 SrcToLook.push_back(TargetInstrInfo::RegSubRegPair(
686 Res.getSrcReg(i), Res.getSrcSubReg(i)));
690 CurSrcPair.Reg = Res.getSrcReg(0);
691 CurSrcPair.SubReg = Res.getSrcSubReg(0);
692 // Do not extend the live-ranges of physical registers as they add
693 // constraints to the register allocator. Moreover, if we want to extend
694 // the live-range of a physical register, unlike SSA virtual register,
695 // we will have to check that they aren't redefine before the related use.
696 if (TargetRegisterInfo::isPhysicalRegister(CurSrcPair.Reg))
699 const TargetRegisterClass *SrcRC = MRI->getRegClass(CurSrcPair.Reg);
700 ShouldRewrite = TRI->shouldRewriteCopySrc(DefRC, SubReg, SrcRC,
702 } while (!ShouldRewrite);
704 // Continue looking for new sources...
708 // Do not continue searching for a new source if the there's at least
709 // one use-def which cannot be rewritten.
714 if (PHICount >= RewritePHILimit) {
715 DEBUG(dbgs() << "findNextSource: PHI limit reached\n");
719 // If we did not find a more suitable source, there is nothing to optimize.
720 return CurSrcPair.Reg != Reg;
723 /// \brief Insert a PHI instruction with incoming edges \p SrcRegs that are
724 /// guaranteed to have the same register class. This is necessary whenever we
725 /// successfully traverse a PHI instruction and find suitable sources coming
726 /// from its edges. By inserting a new PHI, we provide a rewritten PHI def
727 /// suitable to be used in a new COPY instruction.
728 static MachineInstr *
729 insertPHI(MachineRegisterInfo *MRI, const TargetInstrInfo *TII,
730 const SmallVectorImpl<TargetInstrInfo::RegSubRegPair> &SrcRegs,
731 MachineInstr *OrigPHI) {
732 assert(!SrcRegs.empty() && "No sources to create a PHI instruction?");
734 const TargetRegisterClass *NewRC = MRI->getRegClass(SrcRegs[0].Reg);
735 unsigned NewVR = MRI->createVirtualRegister(NewRC);
736 MachineBasicBlock *MBB = OrigPHI->getParent();
737 MachineInstrBuilder MIB = BuildMI(*MBB, OrigPHI, OrigPHI->getDebugLoc(),
738 TII->get(TargetOpcode::PHI), NewVR);
740 unsigned MBBOpIdx = 2;
741 for (auto RegPair : SrcRegs) {
742 MIB.addReg(RegPair.Reg, 0, RegPair.SubReg);
743 MIB.addMBB(OrigPHI->getOperand(MBBOpIdx).getMBB());
744 // Since we're extended the lifetime of RegPair.Reg, clear the
745 // kill flags to account for that and make RegPair.Reg reaches
747 MRI->clearKillFlags(RegPair.Reg);
756 /// \brief Helper class to rewrite the arguments of a copy-like instruction.
759 /// The copy-like instruction.
760 MachineInstr &CopyLike;
761 /// The index of the source being rewritten.
762 unsigned CurrentSrcIdx;
765 CopyRewriter(MachineInstr &MI) : CopyLike(MI), CurrentSrcIdx(0) {}
767 virtual ~CopyRewriter() {}
769 /// \brief Get the next rewritable source (SrcReg, SrcSubReg) and
770 /// the related value that it affects (TrackReg, TrackSubReg).
771 /// A source is considered rewritable if its register class and the
772 /// register class of the related TrackReg may not be register
773 /// coalescer friendly. In other words, given a copy-like instruction
774 /// not all the arguments may be returned at rewritable source, since
775 /// some arguments are none to be register coalescer friendly.
777 /// Each call of this method moves the current source to the next
778 /// rewritable source.
779 /// For instance, let CopyLike be the instruction to rewrite.
780 /// CopyLike has one definition and one source:
781 /// dst.dstSubIdx = CopyLike src.srcSubIdx.
783 /// The first call will give the first rewritable source, i.e.,
784 /// the only source this instruction has:
785 /// (SrcReg, SrcSubReg) = (src, srcSubIdx).
786 /// This source defines the whole definition, i.e.,
787 /// (TrackReg, TrackSubReg) = (dst, dstSubIdx).
789 /// The second and subsequent calls will return false, as there is only one
790 /// rewritable source.
792 /// \return True if a rewritable source has been found, false otherwise.
793 /// The output arguments are valid if and only if true is returned.
794 virtual bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
796 unsigned &TrackSubReg) {
797 // If CurrentSrcIdx == 1, this means this function has already been called
798 // once. CopyLike has one definition and one argument, thus, there is
799 // nothing else to rewrite.
800 if (!CopyLike.isCopy() || CurrentSrcIdx == 1)
802 // This is the first call to getNextRewritableSource.
803 // Move the CurrentSrcIdx to remember that we made that call.
805 // The rewritable source is the argument.
806 const MachineOperand &MOSrc = CopyLike.getOperand(1);
807 SrcReg = MOSrc.getReg();
808 SrcSubReg = MOSrc.getSubReg();
809 // What we track are the alternative sources of the definition.
810 const MachineOperand &MODef = CopyLike.getOperand(0);
811 TrackReg = MODef.getReg();
812 TrackSubReg = MODef.getSubReg();
816 /// \brief Rewrite the current source with \p NewReg and \p NewSubReg
818 /// \return True if the rewriting was possible, false otherwise.
819 virtual bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) {
820 if (!CopyLike.isCopy() || CurrentSrcIdx != 1)
822 MachineOperand &MOSrc = CopyLike.getOperand(CurrentSrcIdx);
823 MOSrc.setReg(NewReg);
824 MOSrc.setSubReg(NewSubReg);
828 /// \brief Given a \p Def.Reg and Def.SubReg pair, use \p RewriteMap to find
829 /// the new source to use for rewrite. If \p HandleMultipleSources is true and
830 /// multiple sources for a given \p Def are found along the way, we found a
831 /// PHI instructions that needs to be rewritten.
832 /// TODO: HandleMultipleSources should be removed once we test PHI handling
833 /// with coalescable copies.
834 TargetInstrInfo::RegSubRegPair
835 getNewSource(MachineRegisterInfo *MRI, const TargetInstrInfo *TII,
836 TargetInstrInfo::RegSubRegPair Def,
837 PeepholeOptimizer::RewriteMapTy &RewriteMap,
838 bool HandleMultipleSources = true) {
839 TargetInstrInfo::RegSubRegPair LookupSrc(Def.Reg, Def.SubReg);
841 ValueTrackerResult Res = RewriteMap.lookup(LookupSrc);
842 // If there are no entries on the map, LookupSrc is the new source.
846 // There's only one source for this definition, keep searching...
847 unsigned NumSrcs = Res.getNumSources();
849 LookupSrc.Reg = Res.getSrcReg(0);
850 LookupSrc.SubReg = Res.getSrcSubReg(0);
854 // TODO: Remove once multiple srcs w/ coalescable copies are supported.
855 if (!HandleMultipleSources)
858 // Multiple sources, recurse into each source to find a new source
859 // for it. Then, rewrite the PHI accordingly to its new edges.
860 SmallVector<TargetInstrInfo::RegSubRegPair, 4> NewPHISrcs;
861 for (unsigned i = 0; i < NumSrcs; ++i) {
862 TargetInstrInfo::RegSubRegPair PHISrc(Res.getSrcReg(i),
863 Res.getSrcSubReg(i));
864 NewPHISrcs.push_back(
865 getNewSource(MRI, TII, PHISrc, RewriteMap, HandleMultipleSources));
868 // Build the new PHI node and return its def register as the new source.
869 MachineInstr *OrigPHI = const_cast<MachineInstr *>(Res.getInst());
870 MachineInstr *NewPHI = insertPHI(MRI, TII, NewPHISrcs, OrigPHI);
871 DEBUG(dbgs() << "-- getNewSource\n");
872 DEBUG(dbgs() << " Replacing: " << *OrigPHI);
873 DEBUG(dbgs() << " With: " << *NewPHI);
874 const MachineOperand &MODef = NewPHI->getOperand(0);
875 return TargetInstrInfo::RegSubRegPair(MODef.getReg(), MODef.getSubReg());
879 return TargetInstrInfo::RegSubRegPair(0, 0);
882 /// \brief Rewrite the source found through \p Def, by using the \p RewriteMap
883 /// and create a new COPY instruction. More info about RewriteMap in
884 /// PeepholeOptimizer::findNextSource. Right now this is only used to handle
885 /// Uncoalescable copies, since they are copy like instructions that aren't
886 /// recognized by the register allocator.
887 virtual MachineInstr *
888 RewriteSource(TargetInstrInfo::RegSubRegPair Def,
889 PeepholeOptimizer::RewriteMapTy &RewriteMap) {
894 /// \brief Helper class to rewrite uncoalescable copy like instructions
895 /// into new COPY (coalescable friendly) instructions.
896 class UncoalescableRewriter : public CopyRewriter {
898 const TargetInstrInfo &TII;
899 MachineRegisterInfo &MRI;
900 /// The number of defs in the bitcast
904 UncoalescableRewriter(MachineInstr &MI, const TargetInstrInfo &TII,
905 MachineRegisterInfo &MRI)
906 : CopyRewriter(MI), TII(TII), MRI(MRI) {
907 NumDefs = MI.getDesc().getNumDefs();
910 /// \brief Get the next rewritable def source (TrackReg, TrackSubReg)
911 /// All such sources need to be considered rewritable in order to
912 /// rewrite a uncoalescable copy-like instruction. This method return
913 /// each definition that must be checked if rewritable.
915 bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
917 unsigned &TrackSubReg) override {
918 // Find the next non-dead definition and continue from there.
919 if (CurrentSrcIdx == NumDefs)
922 while (CopyLike.getOperand(CurrentSrcIdx).isDead()) {
924 if (CurrentSrcIdx == NumDefs)
928 // What we track are the alternative sources of the definition.
929 const MachineOperand &MODef = CopyLike.getOperand(CurrentSrcIdx);
930 TrackReg = MODef.getReg();
931 TrackSubReg = MODef.getSubReg();
937 /// \brief Rewrite the source found through \p Def, by using the \p RewriteMap
938 /// and create a new COPY instruction. More info about RewriteMap in
939 /// PeepholeOptimizer::findNextSource. Right now this is only used to handle
940 /// Uncoalescable copies, since they are copy like instructions that aren't
941 /// recognized by the register allocator.
943 RewriteSource(TargetInstrInfo::RegSubRegPair Def,
944 PeepholeOptimizer::RewriteMapTy &RewriteMap) override {
945 assert(!TargetRegisterInfo::isPhysicalRegister(Def.Reg) &&
946 "We do not rewrite physical registers");
948 // Find the new source to use in the COPY rewrite.
949 TargetInstrInfo::RegSubRegPair NewSrc =
950 getNewSource(&MRI, &TII, Def, RewriteMap);
953 const TargetRegisterClass *DefRC = MRI.getRegClass(Def.Reg);
954 unsigned NewVR = MRI.createVirtualRegister(DefRC);
956 MachineInstr *NewCopy =
957 BuildMI(*CopyLike.getParent(), &CopyLike, CopyLike.getDebugLoc(),
958 TII.get(TargetOpcode::COPY), NewVR)
959 .addReg(NewSrc.Reg, 0, NewSrc.SubReg);
961 NewCopy->getOperand(0).setSubReg(Def.SubReg);
963 NewCopy->getOperand(0).setIsUndef();
965 DEBUG(dbgs() << "-- RewriteSource\n");
966 DEBUG(dbgs() << " Replacing: " << CopyLike);
967 DEBUG(dbgs() << " With: " << *NewCopy);
968 MRI.replaceRegWith(Def.Reg, NewVR);
969 MRI.clearKillFlags(NewVR);
971 // We extended the lifetime of NewSrc.Reg, clear the kill flags to
973 MRI.clearKillFlags(NewSrc.Reg);
979 /// \brief Specialized rewriter for INSERT_SUBREG instruction.
980 class InsertSubregRewriter : public CopyRewriter {
982 InsertSubregRewriter(MachineInstr &MI) : CopyRewriter(MI) {
983 assert(MI.isInsertSubreg() && "Invalid instruction");
986 /// \brief See CopyRewriter::getNextRewritableSource.
987 /// Here CopyLike has the following form:
988 /// dst = INSERT_SUBREG Src1, Src2.src2SubIdx, subIdx.
989 /// Src1 has the same register class has dst, hence, there is
990 /// nothing to rewrite.
991 /// Src2.src2SubIdx, may not be register coalescer friendly.
992 /// Therefore, the first call to this method returns:
993 /// (SrcReg, SrcSubReg) = (Src2, src2SubIdx).
994 /// (TrackReg, TrackSubReg) = (dst, subIdx).
996 /// Subsequence calls will return false.
997 bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
999 unsigned &TrackSubReg) override {
1000 // If we already get the only source we can rewrite, return false.
1001 if (CurrentSrcIdx == 2)
1003 // We are looking at v2 = INSERT_SUBREG v0, v1, sub0.
1005 const MachineOperand &MOInsertedReg = CopyLike.getOperand(2);
1006 SrcReg = MOInsertedReg.getReg();
1007 SrcSubReg = MOInsertedReg.getSubReg();
1008 const MachineOperand &MODef = CopyLike.getOperand(0);
1010 // We want to track something that is compatible with the
1011 // partial definition.
1012 TrackReg = MODef.getReg();
1013 if (MODef.getSubReg())
1014 // Bail if we have to compose sub-register indices.
1016 TrackSubReg = (unsigned)CopyLike.getOperand(3).getImm();
1020 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
1021 if (CurrentSrcIdx != 2)
1023 // We are rewriting the inserted reg.
1024 MachineOperand &MO = CopyLike.getOperand(CurrentSrcIdx);
1026 MO.setSubReg(NewSubReg);
1031 /// \brief Specialized rewriter for EXTRACT_SUBREG instruction.
1032 class ExtractSubregRewriter : public CopyRewriter {
1033 const TargetInstrInfo &TII;
1036 ExtractSubregRewriter(MachineInstr &MI, const TargetInstrInfo &TII)
1037 : CopyRewriter(MI), TII(TII) {
1038 assert(MI.isExtractSubreg() && "Invalid instruction");
1041 /// \brief See CopyRewriter::getNextRewritableSource.
1042 /// Here CopyLike has the following form:
1043 /// dst.dstSubIdx = EXTRACT_SUBREG Src, subIdx.
1044 /// There is only one rewritable source: Src.subIdx,
1045 /// which defines dst.dstSubIdx.
1046 bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
1048 unsigned &TrackSubReg) override {
1049 // If we already get the only source we can rewrite, return false.
1050 if (CurrentSrcIdx == 1)
1052 // We are looking at v1 = EXTRACT_SUBREG v0, sub0.
1054 const MachineOperand &MOExtractedReg = CopyLike.getOperand(1);
1055 SrcReg = MOExtractedReg.getReg();
1056 // If we have to compose sub-register indices, bail out.
1057 if (MOExtractedReg.getSubReg())
1060 SrcSubReg = CopyLike.getOperand(2).getImm();
1062 // We want to track something that is compatible with the definition.
1063 const MachineOperand &MODef = CopyLike.getOperand(0);
1064 TrackReg = MODef.getReg();
1065 TrackSubReg = MODef.getSubReg();
1069 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
1070 // The only source we can rewrite is the input register.
1071 if (CurrentSrcIdx != 1)
1074 CopyLike.getOperand(CurrentSrcIdx).setReg(NewReg);
1076 // If we find a source that does not require to extract something,
1077 // rewrite the operation with a copy.
1079 // Move the current index to an invalid position.
1080 // We do not want another call to this method to be able
1081 // to do any change.
1083 // Rewrite the operation as a COPY.
1084 // Get rid of the sub-register index.
1085 CopyLike.RemoveOperand(2);
1086 // Morph the operation into a COPY.
1087 CopyLike.setDesc(TII.get(TargetOpcode::COPY));
1090 CopyLike.getOperand(CurrentSrcIdx + 1).setImm(NewSubReg);
1095 /// \brief Specialized rewriter for REG_SEQUENCE instruction.
1096 class RegSequenceRewriter : public CopyRewriter {
1098 RegSequenceRewriter(MachineInstr &MI) : CopyRewriter(MI) {
1099 assert(MI.isRegSequence() && "Invalid instruction");
1102 /// \brief See CopyRewriter::getNextRewritableSource.
1103 /// Here CopyLike has the following form:
1104 /// dst = REG_SEQUENCE Src1.src1SubIdx, subIdx1, Src2.src2SubIdx, subIdx2.
1105 /// Each call will return a different source, walking all the available
1108 /// The first call returns:
1109 /// (SrcReg, SrcSubReg) = (Src1, src1SubIdx).
1110 /// (TrackReg, TrackSubReg) = (dst, subIdx1).
1112 /// The second call returns:
1113 /// (SrcReg, SrcSubReg) = (Src2, src2SubIdx).
1114 /// (TrackReg, TrackSubReg) = (dst, subIdx2).
1116 /// And so on, until all the sources have been traversed, then
1117 /// it returns false.
1118 bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
1120 unsigned &TrackSubReg) override {
1121 // We are looking at v0 = REG_SEQUENCE v1, sub1, v2, sub2, etc.
1123 // If this is the first call, move to the first argument.
1124 if (CurrentSrcIdx == 0) {
1127 // Otherwise, move to the next argument and check that it is valid.
1129 if (CurrentSrcIdx >= CopyLike.getNumOperands())
1132 const MachineOperand &MOInsertedReg = CopyLike.getOperand(CurrentSrcIdx);
1133 SrcReg = MOInsertedReg.getReg();
1134 // If we have to compose sub-register indices, bail out.
1135 if ((SrcSubReg = MOInsertedReg.getSubReg()))
1138 // We want to track something that is compatible with the related
1139 // partial definition.
1140 TrackSubReg = CopyLike.getOperand(CurrentSrcIdx + 1).getImm();
1142 const MachineOperand &MODef = CopyLike.getOperand(0);
1143 TrackReg = MODef.getReg();
1144 // If we have to compose sub-registers, bail.
1145 return MODef.getSubReg() == 0;
1148 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
1149 // We cannot rewrite out of bound operands.
1150 // Moreover, rewritable sources are at odd positions.
1151 if ((CurrentSrcIdx & 1) != 1 || CurrentSrcIdx > CopyLike.getNumOperands())
1154 MachineOperand &MO = CopyLike.getOperand(CurrentSrcIdx);
1156 MO.setSubReg(NewSubReg);
1161 } // end anonymous namespace
1163 /// \brief Get the appropriated CopyRewriter for \p MI.
1164 /// \return A pointer to a dynamically allocated CopyRewriter or nullptr
1165 /// if no rewriter works for \p MI.
1166 static CopyRewriter *getCopyRewriter(MachineInstr &MI,
1167 const TargetInstrInfo &TII,
1168 MachineRegisterInfo &MRI) {
1169 // Handle uncoalescable copy-like instructions.
1170 if (MI.isBitcast() || (MI.isRegSequenceLike() || MI.isInsertSubregLike() ||
1171 MI.isExtractSubregLike()))
1172 return new UncoalescableRewriter(MI, TII, MRI);
1174 switch (MI.getOpcode()) {
1177 case TargetOpcode::COPY:
1178 return new CopyRewriter(MI);
1179 case TargetOpcode::INSERT_SUBREG:
1180 return new InsertSubregRewriter(MI);
1181 case TargetOpcode::EXTRACT_SUBREG:
1182 return new ExtractSubregRewriter(MI, TII);
1183 case TargetOpcode::REG_SEQUENCE:
1184 return new RegSequenceRewriter(MI);
1186 llvm_unreachable(nullptr);
1189 /// \brief Optimize generic copy instructions to avoid cross
1190 /// register bank copy. The optimization looks through a chain of
1191 /// copies and tries to find a source that has a compatible register
1193 /// Two register classes are considered to be compatible if they share
1194 /// the same register bank.
1195 /// New copies issued by this optimization are register allocator
1196 /// friendly. This optimization does not remove any copy as it may
1197 /// overconstrain the register allocator, but replaces some operands
1199 /// \pre isCoalescableCopy(*MI) is true.
1200 /// \return True, when \p MI has been rewritten. False otherwise.
1201 bool PeepholeOptimizer::optimizeCoalescableCopy(MachineInstr *MI) {
1202 assert(MI && isCoalescableCopy(*MI) && "Invalid argument");
1203 assert(MI->getDesc().getNumDefs() == 1 &&
1204 "Coalescer can understand multiple defs?!");
1205 const MachineOperand &MODef = MI->getOperand(0);
1206 // Do not rewrite physical definitions.
1207 if (TargetRegisterInfo::isPhysicalRegister(MODef.getReg()))
1210 bool Changed = false;
1211 // Get the right rewriter for the current copy.
1212 std::unique_ptr<CopyRewriter> CpyRewriter(getCopyRewriter(*MI, *TII, *MRI));
1213 // If none exists, bail out.
1216 // Rewrite each rewritable source.
1217 unsigned SrcReg, SrcSubReg, TrackReg, TrackSubReg;
1218 while (CpyRewriter->getNextRewritableSource(SrcReg, SrcSubReg, TrackReg,
1220 // Keep track of PHI nodes and its incoming edges when looking for sources.
1221 RewriteMapTy RewriteMap;
1222 // Try to find a more suitable source. If we failed to do so, or get the
1223 // actual source, move to the next source.
1224 if (!findNextSource(TrackReg, TrackSubReg, RewriteMap))
1227 // Get the new source to rewrite. TODO: Only enable handling of multiple
1228 // sources (PHIs) once we have a motivating example and testcases for it.
1229 TargetInstrInfo::RegSubRegPair TrackPair(TrackReg, TrackSubReg);
1230 TargetInstrInfo::RegSubRegPair NewSrc = CpyRewriter->getNewSource(
1231 MRI, TII, TrackPair, RewriteMap, false /* multiple sources */);
1232 if (SrcReg == NewSrc.Reg || NewSrc.Reg == 0)
1236 if (CpyRewriter->RewriteCurrentSource(NewSrc.Reg, NewSrc.SubReg)) {
1237 // We may have extended the live-range of NewSrc, account for that.
1238 MRI->clearKillFlags(NewSrc.Reg);
1242 // TODO: We could have a clean-up method to tidy the instruction.
1243 // E.g., v0 = INSERT_SUBREG v1, v1.sub0, sub0
1245 // Currently we haven't seen motivating example for that and we
1246 // want to avoid untested code.
1247 NumRewrittenCopies += Changed;
1251 /// \brief Optimize copy-like instructions to create
1252 /// register coalescer friendly instruction.
1253 /// The optimization tries to kill-off the \p MI by looking
1254 /// through a chain of copies to find a source that has a compatible
1256 /// If such a source is found, it replace \p MI by a generic COPY
1258 /// \pre isUncoalescableCopy(*MI) is true.
1259 /// \return True, when \p MI has been optimized. In that case, \p MI has
1260 /// been removed from its parent.
1261 /// All COPY instructions created, are inserted in \p LocalMIs.
1262 bool PeepholeOptimizer::optimizeUncoalescableCopy(
1263 MachineInstr *MI, SmallPtrSetImpl<MachineInstr *> &LocalMIs) {
1264 assert(MI && isUncoalescableCopy(*MI) && "Invalid argument");
1266 // Check if we can rewrite all the values defined by this instruction.
1267 SmallVector<TargetInstrInfo::RegSubRegPair, 4> RewritePairs;
1268 // Get the right rewriter for the current copy.
1269 std::unique_ptr<CopyRewriter> CpyRewriter(getCopyRewriter(*MI, *TII, *MRI));
1270 // If none exists, bail out.
1274 // Rewrite each rewritable source by generating new COPYs. This works
1275 // differently from optimizeCoalescableCopy since it first makes sure that all
1276 // definitions can be rewritten.
1277 RewriteMapTy RewriteMap;
1278 unsigned Reg, SubReg, CopyDefReg, CopyDefSubReg;
1279 while (CpyRewriter->getNextRewritableSource(Reg, SubReg, CopyDefReg,
1281 // If a physical register is here, this is probably for a good reason.
1282 // Do not rewrite that.
1283 if (TargetRegisterInfo::isPhysicalRegister(CopyDefReg))
1286 // If we do not know how to rewrite this definition, there is no point
1287 // in trying to kill this instruction.
1288 TargetInstrInfo::RegSubRegPair Def(CopyDefReg, CopyDefSubReg);
1289 if (!findNextSource(Def.Reg, Def.SubReg, RewriteMap))
1292 RewritePairs.push_back(Def);
1295 // The change is possible for all defs, do it.
1296 for (const auto &Def : RewritePairs) {
1297 // Rewrite the "copy" in a way the register coalescer understands.
1298 MachineInstr *NewCopy = CpyRewriter->RewriteSource(Def, RewriteMap);
1299 assert(NewCopy && "Should be able to always generate a new copy");
1300 LocalMIs.insert(NewCopy);
1304 MI->eraseFromParent();
1305 ++NumUncoalescableCopies;
1309 /// Check whether MI is a candidate for folding into a later instruction.
1310 /// We only fold loads to virtual registers and the virtual register defined
1311 /// has a single use.
1312 bool PeepholeOptimizer::isLoadFoldable(
1313 MachineInstr *MI, SmallSet<unsigned, 16> &FoldAsLoadDefCandidates) {
1314 if (!MI->canFoldAsLoad() || !MI->mayLoad())
1316 const MCInstrDesc &MCID = MI->getDesc();
1317 if (MCID.getNumDefs() != 1)
1320 unsigned Reg = MI->getOperand(0).getReg();
1321 // To reduce compilation time, we check MRI->hasOneNonDBGUse when inserting
1322 // loads. It should be checked when processing uses of the load, since
1323 // uses can be removed during peephole.
1324 if (!MI->getOperand(0).getSubReg() &&
1325 TargetRegisterInfo::isVirtualRegister(Reg) &&
1326 MRI->hasOneNonDBGUse(Reg)) {
1327 FoldAsLoadDefCandidates.insert(Reg);
1333 bool PeepholeOptimizer::isMoveImmediate(
1334 MachineInstr *MI, SmallSet<unsigned, 4> &ImmDefRegs,
1335 DenseMap<unsigned, MachineInstr *> &ImmDefMIs) {
1336 const MCInstrDesc &MCID = MI->getDesc();
1337 if (!MI->isMoveImmediate())
1339 if (MCID.getNumDefs() != 1)
1341 unsigned Reg = MI->getOperand(0).getReg();
1342 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1343 ImmDefMIs.insert(std::make_pair(Reg, MI));
1344 ImmDefRegs.insert(Reg);
1351 /// Try folding register operands that are defined by move immediate
1352 /// instructions, i.e. a trivial constant folding optimization, if
1353 /// and only if the def and use are in the same BB.
1354 bool PeepholeOptimizer::foldImmediate(
1355 MachineInstr *MI, MachineBasicBlock *MBB, SmallSet<unsigned, 4> &ImmDefRegs,
1356 DenseMap<unsigned, MachineInstr *> &ImmDefMIs) {
1357 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
1358 MachineOperand &MO = MI->getOperand(i);
1359 if (!MO.isReg() || MO.isDef())
1361 // Ignore dead implicit defs.
1362 if (MO.isImplicit() && MO.isDead())
1364 unsigned Reg = MO.getReg();
1365 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1367 if (ImmDefRegs.count(Reg) == 0)
1369 DenseMap<unsigned, MachineInstr*>::iterator II = ImmDefMIs.find(Reg);
1370 assert(II != ImmDefMIs.end() && "couldn't find immediate definition");
1371 if (TII->FoldImmediate(*MI, *II->second, Reg, MRI)) {
1379 // FIXME: This is very simple and misses some cases which should be handled when
1380 // motivating examples are found.
1382 // The copy rewriting logic should look at uses as well as defs and be able to
1383 // eliminate copies across blocks.
1385 // Later copies that are subregister extracts will also not be eliminated since
1386 // only the first copy is considered.
1389 // %vreg1 = COPY %vreg0
1390 // %vreg2 = COPY %vreg0:sub1
1392 // Should replace %vreg2 uses with %vreg1:sub1
1393 bool PeepholeOptimizer::foldRedundantCopy(
1394 MachineInstr *MI, SmallSet<unsigned, 4> &CopySrcRegs,
1395 DenseMap<unsigned, MachineInstr *> &CopyMIs) {
1396 assert(MI->isCopy() && "expected a COPY machine instruction");
1398 unsigned SrcReg = MI->getOperand(1).getReg();
1399 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
1402 unsigned DstReg = MI->getOperand(0).getReg();
1403 if (!TargetRegisterInfo::isVirtualRegister(DstReg))
1406 if (CopySrcRegs.insert(SrcReg).second) {
1407 // First copy of this reg seen.
1408 CopyMIs.insert(std::make_pair(SrcReg, MI));
1412 MachineInstr *PrevCopy = CopyMIs.find(SrcReg)->second;
1414 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1415 unsigned PrevSrcSubReg = PrevCopy->getOperand(1).getSubReg();
1417 // Can't replace different subregister extracts.
1418 if (SrcSubReg != PrevSrcSubReg)
1421 unsigned PrevDstReg = PrevCopy->getOperand(0).getReg();
1423 // Only replace if the copy register class is the same.
1425 // TODO: If we have multiple copies to different register classes, we may want
1426 // to track multiple copies of the same source register.
1427 if (MRI->getRegClass(DstReg) != MRI->getRegClass(PrevDstReg))
1430 MRI->replaceRegWith(DstReg, PrevDstReg);
1432 // Lifetime of the previous copy has been extended.
1433 MRI->clearKillFlags(PrevDstReg);
1437 bool PeepholeOptimizer::isNAPhysCopy(unsigned Reg) {
1438 return TargetRegisterInfo::isPhysicalRegister(Reg) &&
1439 !MRI->isAllocatable(Reg);
1442 bool PeepholeOptimizer::foldRedundantNAPhysCopy(
1443 MachineInstr *MI, DenseMap<unsigned, MachineInstr *> &NAPhysToVirtMIs) {
1444 assert(MI->isCopy() && "expected a COPY machine instruction");
1446 if (DisableNAPhysCopyOpt)
1449 unsigned DstReg = MI->getOperand(0).getReg();
1450 unsigned SrcReg = MI->getOperand(1).getReg();
1451 if (isNAPhysCopy(SrcReg) && TargetRegisterInfo::isVirtualRegister(DstReg)) {
1452 // %vreg = COPY %PHYSREG
1453 // Avoid using a datastructure which can track multiple live non-allocatable
1454 // phys->virt copies since LLVM doesn't seem to do this.
1455 NAPhysToVirtMIs.insert({SrcReg, MI});
1459 if (!(TargetRegisterInfo::isVirtualRegister(SrcReg) && isNAPhysCopy(DstReg)))
1462 // %PHYSREG = COPY %vreg
1463 auto PrevCopy = NAPhysToVirtMIs.find(DstReg);
1464 if (PrevCopy == NAPhysToVirtMIs.end()) {
1465 // We can't remove the copy: there was an intervening clobber of the
1466 // non-allocatable physical register after the copy to virtual.
1467 DEBUG(dbgs() << "NAPhysCopy: intervening clobber forbids erasing " << *MI
1472 unsigned PrevDstReg = PrevCopy->second->getOperand(0).getReg();
1473 if (PrevDstReg == SrcReg) {
1474 // Remove the virt->phys copy: we saw the virtual register definition, and
1475 // the non-allocatable physical register's state hasn't changed since then.
1476 DEBUG(dbgs() << "NAPhysCopy: erasing " << *MI << '\n');
1481 // Potential missed optimization opportunity: we saw a different virtual
1482 // register get a copy of the non-allocatable physical register, and we only
1483 // track one such copy. Avoid getting confused by this new non-allocatable
1484 // physical register definition, and remove it from the tracked copies.
1485 DEBUG(dbgs() << "NAPhysCopy: missed opportunity " << *MI << '\n');
1486 NAPhysToVirtMIs.erase(PrevCopy);
1490 bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
1491 if (skipFunction(*MF.getFunction()))
1494 DEBUG(dbgs() << "********** PEEPHOLE OPTIMIZER **********\n");
1495 DEBUG(dbgs() << "********** Function: " << MF.getName() << '\n');
1497 if (DisablePeephole)
1500 TII = MF.getSubtarget().getInstrInfo();
1501 TRI = MF.getSubtarget().getRegisterInfo();
1502 MRI = &MF.getRegInfo();
1503 DT = Aggressive ? &getAnalysis<MachineDominatorTree>() : nullptr;
1505 bool Changed = false;
1507 for (MachineBasicBlock &MBB : MF) {
1508 bool SeenMoveImm = false;
1510 // During this forward scan, at some point it needs to answer the question
1511 // "given a pointer to an MI in the current BB, is it located before or
1512 // after the current instruction".
1513 // To perform this, the following set keeps track of the MIs already seen
1514 // during the scan, if a MI is not in the set, it is assumed to be located
1515 // after. Newly created MIs have to be inserted in the set as well.
1516 SmallPtrSet<MachineInstr*, 16> LocalMIs;
1517 SmallSet<unsigned, 4> ImmDefRegs;
1518 DenseMap<unsigned, MachineInstr*> ImmDefMIs;
1519 SmallSet<unsigned, 16> FoldAsLoadDefCandidates;
1521 // Track when a non-allocatable physical register is copied to a virtual
1522 // register so that useless moves can be removed.
1524 // %PHYSREG is the map index; MI is the last valid `%vreg = COPY %PHYSREG`
1525 // without any intervening re-definition of %PHYSREG.
1526 DenseMap<unsigned, MachineInstr *> NAPhysToVirtMIs;
1528 // Set of virtual registers that are copied from.
1529 SmallSet<unsigned, 4> CopySrcRegs;
1530 DenseMap<unsigned, MachineInstr *> CopySrcMIs;
1532 for (MachineBasicBlock::iterator MII = MBB.begin(), MIE = MBB.end();
1534 MachineInstr *MI = &*MII;
1535 // We may be erasing MI below, increment MII now.
1537 LocalMIs.insert(MI);
1539 // Skip debug values. They should not affect this peephole optimization.
1540 if (MI->isDebugValue())
1543 if (MI->isPosition() || MI->isPHI())
1546 if (!MI->isCopy()) {
1547 for (const auto &Op : MI->operands()) {
1548 // Visit all operands: definitions can be implicit or explicit.
1550 unsigned Reg = Op.getReg();
1551 if (Op.isDef() && isNAPhysCopy(Reg)) {
1552 const auto &Def = NAPhysToVirtMIs.find(Reg);
1553 if (Def != NAPhysToVirtMIs.end()) {
1554 // A new definition of the non-allocatable physical register
1555 // invalidates previous copies.
1556 DEBUG(dbgs() << "NAPhysCopy: invalidating because of " << *MI
1558 NAPhysToVirtMIs.erase(Def);
1561 } else if (Op.isRegMask()) {
1562 const uint32_t *RegMask = Op.getRegMask();
1563 for (auto &RegMI : NAPhysToVirtMIs) {
1564 unsigned Def = RegMI.first;
1565 if (MachineOperand::clobbersPhysReg(RegMask, Def)) {
1566 DEBUG(dbgs() << "NAPhysCopy: invalidating because of " << *MI
1568 NAPhysToVirtMIs.erase(Def);
1575 if (MI->isImplicitDef() || MI->isKill())
1578 if (MI->isInlineAsm() || MI->hasUnmodeledSideEffects()) {
1579 // Blow away all non-allocatable physical registers knowledge since we
1580 // don't know what's correct anymore.
1582 // FIXME: handle explicit asm clobbers.
1583 DEBUG(dbgs() << "NAPhysCopy: blowing away all info due to " << *MI
1585 NAPhysToVirtMIs.clear();
1588 if ((isUncoalescableCopy(*MI) &&
1589 optimizeUncoalescableCopy(MI, LocalMIs)) ||
1590 (MI->isCompare() && optimizeCmpInstr(MI, &MBB)) ||
1591 (MI->isSelect() && optimizeSelect(MI, LocalMIs))) {
1598 if (MI->isConditionalBranch() && optimizeCondBranch(MI)) {
1603 if (isCoalescableCopy(*MI) && optimizeCoalescableCopy(MI)) {
1604 // MI is just rewritten.
1610 (foldRedundantCopy(MI, CopySrcRegs, CopySrcMIs) ||
1611 foldRedundantNAPhysCopy(MI, NAPhysToVirtMIs))) {
1613 MI->eraseFromParent();
1618 if (isMoveImmediate(MI, ImmDefRegs, ImmDefMIs)) {
1621 Changed |= optimizeExtInstr(MI, &MBB, LocalMIs);
1622 // optimizeExtInstr might have created new instructions after MI
1623 // and before the already incremented MII. Adjust MII so that the
1624 // next iteration sees the new instructions.
1628 Changed |= foldImmediate(MI, &MBB, ImmDefRegs, ImmDefMIs);
1631 // Check whether MI is a load candidate for folding into a later
1632 // instruction. If MI is not a candidate, check whether we can fold an
1633 // earlier load into MI.
1634 if (!isLoadFoldable(MI, FoldAsLoadDefCandidates) &&
1635 !FoldAsLoadDefCandidates.empty()) {
1637 // We visit each operand even after successfully folding a previous
1638 // one. This allows us to fold multiple loads into a single
1639 // instruction. We do assume that optimizeLoadInstr doesn't insert
1640 // foldable uses earlier in the argument list. Since we don't restart
1641 // iteration, we'd miss such cases.
1642 const MCInstrDesc &MIDesc = MI->getDesc();
1643 for (unsigned i = MIDesc.getNumDefs(); i != MI->getNumOperands();
1645 const MachineOperand &MOp = MI->getOperand(i);
1648 unsigned FoldAsLoadDefReg = MOp.getReg();
1649 if (FoldAsLoadDefCandidates.count(FoldAsLoadDefReg)) {
1650 // We need to fold load after optimizeCmpInstr, since
1651 // optimizeCmpInstr can enable folding by converting SUB to CMP.
1652 // Save FoldAsLoadDefReg because optimizeLoadInstr() resets it and
1653 // we need it for markUsesInDebugValueAsUndef().
1654 unsigned FoldedReg = FoldAsLoadDefReg;
1655 MachineInstr *DefMI = nullptr;
1656 if (MachineInstr *FoldMI =
1657 TII->optimizeLoadInstr(*MI, MRI, FoldAsLoadDefReg, DefMI)) {
1658 // Update LocalMIs since we replaced MI with FoldMI and deleted
1660 DEBUG(dbgs() << "Replacing: " << *MI);
1661 DEBUG(dbgs() << " With: " << *FoldMI);
1663 LocalMIs.erase(DefMI);
1664 LocalMIs.insert(FoldMI);
1665 MI->eraseFromParent();
1666 DefMI->eraseFromParent();
1667 MRI->markUsesInDebugValueAsUndef(FoldedReg);
1668 FoldAsLoadDefCandidates.erase(FoldedReg);
1671 // MI is replaced with FoldMI so we can continue trying to fold
1679 // If we run into an instruction we can't fold across, discard
1680 // the load candidates. Note: We might be able to fold *into* this
1681 // instruction, so this needs to be after the folding logic.
1682 if (MI->isLoadFoldBarrier()) {
1683 DEBUG(dbgs() << "Encountered load fold barrier on " << *MI << "\n");
1684 FoldAsLoadDefCandidates.clear();
1693 ValueTrackerResult ValueTracker::getNextSourceFromCopy() {
1694 assert(Def->isCopy() && "Invalid definition");
1695 // Copy instruction are supposed to be: Def = Src.
1696 // If someone breaks this assumption, bad things will happen everywhere.
1697 assert(Def->getNumOperands() == 2 && "Invalid number of operands");
1699 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
1700 // If we look for a different subreg, it means we want a subreg of src.
1701 // Bails as we do not support composing subregs yet.
1702 return ValueTrackerResult();
1703 // Otherwise, we want the whole source.
1704 const MachineOperand &Src = Def->getOperand(1);
1705 return ValueTrackerResult(Src.getReg(), Src.getSubReg());
1708 ValueTrackerResult ValueTracker::getNextSourceFromBitcast() {
1709 assert(Def->isBitcast() && "Invalid definition");
1711 // Bail if there are effects that a plain copy will not expose.
1712 if (Def->hasUnmodeledSideEffects())
1713 return ValueTrackerResult();
1715 // Bitcasts with more than one def are not supported.
1716 if (Def->getDesc().getNumDefs() != 1)
1717 return ValueTrackerResult();
1718 const MachineOperand DefOp = Def->getOperand(DefIdx);
1719 if (DefOp.getSubReg() != DefSubReg)
1720 // If we look for a different subreg, it means we want a subreg of the src.
1721 // Bails as we do not support composing subregs yet.
1722 return ValueTrackerResult();
1724 unsigned SrcIdx = Def->getNumOperands();
1725 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx;
1727 const MachineOperand &MO = Def->getOperand(OpIdx);
1728 if (!MO.isReg() || !MO.getReg())
1730 // Ignore dead implicit defs.
1731 if (MO.isImplicit() && MO.isDead())
1733 assert(!MO.isDef() && "We should have skipped all the definitions by now");
1734 if (SrcIdx != EndOpIdx)
1735 // Multiple sources?
1736 return ValueTrackerResult();
1740 // Stop when any user of the bitcast is a SUBREG_TO_REG, replacing with a COPY
1741 // will break the assumed guarantees for the upper bits.
1742 for (const MachineInstr &UseMI : MRI.use_nodbg_instructions(DefOp.getReg())) {
1743 if (UseMI.isSubregToReg())
1744 return ValueTrackerResult();
1747 const MachineOperand &Src = Def->getOperand(SrcIdx);
1748 return ValueTrackerResult(Src.getReg(), Src.getSubReg());
1751 ValueTrackerResult ValueTracker::getNextSourceFromRegSequence() {
1752 assert((Def->isRegSequence() || Def->isRegSequenceLike()) &&
1753 "Invalid definition");
1755 if (Def->getOperand(DefIdx).getSubReg())
1756 // If we are composing subregs, bail out.
1757 // The case we are checking is Def.<subreg> = REG_SEQUENCE.
1758 // This should almost never happen as the SSA property is tracked at
1759 // the register level (as opposed to the subreg level).
1763 // is a valid SSA representation for Def.sub0 and Def.sub1, but not for
1764 // Def. Thus, it must not be generated.
1765 // However, some code could theoretically generates a single
1766 // Def.sub0 (i.e, not defining the other subregs) and we would
1768 // If we can ascertain (or force) that this never happens, we could
1769 // turn that into an assertion.
1770 return ValueTrackerResult();
1773 // We could handle the REG_SEQUENCE here, but we do not want to
1774 // duplicate the code from the generic TII.
1775 return ValueTrackerResult();
1777 SmallVector<TargetInstrInfo::RegSubRegPairAndIdx, 8> RegSeqInputRegs;
1778 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs))
1779 return ValueTrackerResult();
1781 // We are looking at:
1782 // Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
1783 // Check if one of the operand defines the subreg we are interested in.
1784 for (auto &RegSeqInput : RegSeqInputRegs) {
1785 if (RegSeqInput.SubIdx == DefSubReg) {
1786 if (RegSeqInput.SubReg)
1787 // Bail if we have to compose sub registers.
1788 return ValueTrackerResult();
1790 return ValueTrackerResult(RegSeqInput.Reg, RegSeqInput.SubReg);
1794 // If the subreg we are tracking is super-defined by another subreg,
1795 // we could follow this value. However, this would require to compose
1796 // the subreg and we do not do that for now.
1797 return ValueTrackerResult();
1800 ValueTrackerResult ValueTracker::getNextSourceFromInsertSubreg() {
1801 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) &&
1802 "Invalid definition");
1804 if (Def->getOperand(DefIdx).getSubReg())
1805 // If we are composing subreg, bail out.
1806 // Same remark as getNextSourceFromRegSequence.
1807 // I.e., this may be turned into an assert.
1808 return ValueTrackerResult();
1811 // We could handle the REG_SEQUENCE here, but we do not want to
1812 // duplicate the code from the generic TII.
1813 return ValueTrackerResult();
1815 TargetInstrInfo::RegSubRegPair BaseReg;
1816 TargetInstrInfo::RegSubRegPairAndIdx InsertedReg;
1817 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg))
1818 return ValueTrackerResult();
1820 // We are looking at:
1821 // Def = INSERT_SUBREG v0, v1, sub1
1822 // There are two cases:
1823 // 1. DefSubReg == sub1, get v1.
1824 // 2. DefSubReg != sub1, the value may be available through v0.
1826 // #1 Check if the inserted register matches the required sub index.
1827 if (InsertedReg.SubIdx == DefSubReg) {
1828 return ValueTrackerResult(InsertedReg.Reg, InsertedReg.SubReg);
1830 // #2 Otherwise, if the sub register we are looking for is not partial
1831 // defined by the inserted element, we can look through the main
1833 const MachineOperand &MODef = Def->getOperand(DefIdx);
1834 // If the result register (Def) and the base register (v0) do not
1835 // have the same register class or if we have to compose
1836 // subregisters, bail out.
1837 if (MRI.getRegClass(MODef.getReg()) != MRI.getRegClass(BaseReg.Reg) ||
1839 return ValueTrackerResult();
1841 // Get the TRI and check if the inserted sub-register overlaps with the
1842 // sub-register we are tracking.
1843 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
1845 !(TRI->getSubRegIndexLaneMask(DefSubReg) &
1846 TRI->getSubRegIndexLaneMask(InsertedReg.SubIdx)).none())
1847 return ValueTrackerResult();
1848 // At this point, the value is available in v0 via the same subreg
1850 return ValueTrackerResult(BaseReg.Reg, DefSubReg);
1853 ValueTrackerResult ValueTracker::getNextSourceFromExtractSubreg() {
1854 assert((Def->isExtractSubreg() ||
1855 Def->isExtractSubregLike()) && "Invalid definition");
1856 // We are looking at:
1857 // Def = EXTRACT_SUBREG v0, sub0
1859 // Bail if we have to compose sub registers.
1860 // Indeed, if DefSubReg != 0, we would have to compose it with sub0.
1862 return ValueTrackerResult();
1865 // We could handle the EXTRACT_SUBREG here, but we do not want to
1866 // duplicate the code from the generic TII.
1867 return ValueTrackerResult();
1869 TargetInstrInfo::RegSubRegPairAndIdx ExtractSubregInputReg;
1870 if (!TII->getExtractSubregInputs(*Def, DefIdx, ExtractSubregInputReg))
1871 return ValueTrackerResult();
1873 // Bail if we have to compose sub registers.
1874 // Likewise, if v0.subreg != 0, we would have to compose v0.subreg with sub0.
1875 if (ExtractSubregInputReg.SubReg)
1876 return ValueTrackerResult();
1877 // Otherwise, the value is available in the v0.sub0.
1878 return ValueTrackerResult(ExtractSubregInputReg.Reg,
1879 ExtractSubregInputReg.SubIdx);
1882 ValueTrackerResult ValueTracker::getNextSourceFromSubregToReg() {
1883 assert(Def->isSubregToReg() && "Invalid definition");
1884 // We are looking at:
1885 // Def = SUBREG_TO_REG Imm, v0, sub0
1887 // Bail if we have to compose sub registers.
1888 // If DefSubReg != sub0, we would have to check that all the bits
1889 // we track are included in sub0 and if yes, we would have to
1890 // determine the right subreg in v0.
1891 if (DefSubReg != Def->getOperand(3).getImm())
1892 return ValueTrackerResult();
1893 // Bail if we have to compose sub registers.
1894 // Likewise, if v0.subreg != 0, we would have to compose it with sub0.
1895 if (Def->getOperand(2).getSubReg())
1896 return ValueTrackerResult();
1898 return ValueTrackerResult(Def->getOperand(2).getReg(),
1899 Def->getOperand(3).getImm());
1902 /// \brief Explore each PHI incoming operand and return its sources
1903 ValueTrackerResult ValueTracker::getNextSourceFromPHI() {
1904 assert(Def->isPHI() && "Invalid definition");
1905 ValueTrackerResult Res;
1907 // If we look for a different subreg, bail as we do not support composing
1909 if (Def->getOperand(0).getSubReg() != DefSubReg)
1910 return ValueTrackerResult();
1912 // Return all register sources for PHI instructions.
1913 for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2) {
1914 auto &MO = Def->getOperand(i);
1915 assert(MO.isReg() && "Invalid PHI instruction");
1916 Res.addSource(MO.getReg(), MO.getSubReg());
1922 ValueTrackerResult ValueTracker::getNextSourceImpl() {
1923 assert(Def && "This method needs a valid definition");
1925 assert(((Def->getOperand(DefIdx).isDef() &&
1926 (DefIdx < Def->getDesc().getNumDefs() ||
1927 Def->getDesc().isVariadic())) ||
1928 Def->getOperand(DefIdx).isImplicit()) &&
1931 return getNextSourceFromCopy();
1932 if (Def->isBitcast())
1933 return getNextSourceFromBitcast();
1934 // All the remaining cases involve "complex" instructions.
1935 // Bail if we did not ask for the advanced tracking.
1936 if (!UseAdvancedTracking)
1937 return ValueTrackerResult();
1938 if (Def->isRegSequence() || Def->isRegSequenceLike())
1939 return getNextSourceFromRegSequence();
1940 if (Def->isInsertSubreg() || Def->isInsertSubregLike())
1941 return getNextSourceFromInsertSubreg();
1942 if (Def->isExtractSubreg() || Def->isExtractSubregLike())
1943 return getNextSourceFromExtractSubreg();
1944 if (Def->isSubregToReg())
1945 return getNextSourceFromSubregToReg();
1947 return getNextSourceFromPHI();
1948 return ValueTrackerResult();
1951 ValueTrackerResult ValueTracker::getNextSource() {
1952 // If we reach a point where we cannot move up in the use-def chain,
1953 // there is nothing we can get.
1955 return ValueTrackerResult();
1957 ValueTrackerResult Res = getNextSourceImpl();
1958 if (Res.isValid()) {
1959 // Update definition, definition index, and subregister for the
1960 // next call of getNextSource.
1961 // Update the current register.
1962 bool OneRegSrc = Res.getNumSources() == 1;
1964 Reg = Res.getSrcReg(0);
1965 // Update the result before moving up in the use-def chain
1966 // with the instruction containing the last found sources.
1969 // If we can still move up in the use-def chain, move to the next
1971 if (!TargetRegisterInfo::isPhysicalRegister(Reg) && OneRegSrc) {
1972 Def = MRI.getVRegDef(Reg);
1973 DefIdx = MRI.def_begin(Reg).getOperandNo();
1974 DefSubReg = Res.getSrcSubReg(0);
1978 // If we end up here, this means we will not be able to find another source
1979 // for the next iteration. Make sure any new call to getNextSource bails out
1980 // early by cutting the use-def chain.