1 //===----- SchedulePostRAList.cpp - list scheduler ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a top-down list scheduler, using standard algorithms.
11 // The basic approach uses a priority queue of available nodes to schedule.
12 // One at a time, nodes are taken from the priority queue (thus in priority
13 // order), checked for legality to schedule, and emitted if legal.
15 // Nodes may not be legal to schedule either due to structural hazards (e.g.
16 // pipeline or resource constraints) or because an input to the instruction has
17 // not completed execution.
19 //===----------------------------------------------------------------------===//
21 #include "AggressiveAntiDepBreaker.h"
22 #include "AntiDepBreaker.h"
23 #include "CriticalAntiDepBreaker.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/CodeGen/LatencyPriorityQueue.h"
27 #include "llvm/CodeGen/MachineDominators.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineLoopInfo.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/CodeGen/RegisterClassInfo.h"
33 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
34 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
35 #include "llvm/CodeGen/SchedulerRegistry.h"
36 #include "llvm/CodeGen/TargetInstrInfo.h"
37 #include "llvm/CodeGen/TargetLowering.h"
38 #include "llvm/CodeGen/TargetPassConfig.h"
39 #include "llvm/CodeGen/TargetRegisterInfo.h"
40 #include "llvm/CodeGen/TargetSubtargetInfo.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/raw_ostream.h"
47 #define DEBUG_TYPE "post-RA-sched"
49 STATISTIC(NumNoops, "Number of noops inserted");
50 STATISTIC(NumStalls, "Number of pipeline stalls");
51 STATISTIC(NumFixedAnti, "Number of fixed anti-dependencies");
53 // Post-RA scheduling is enabled with
54 // TargetSubtargetInfo.enablePostRAScheduler(). This flag can be used to
55 // override the target.
57 EnablePostRAScheduler("post-RA-scheduler",
58 cl::desc("Enable scheduling after register allocation"),
59 cl::init(false), cl::Hidden);
60 static cl::opt<std::string>
61 EnableAntiDepBreaking("break-anti-dependencies",
62 cl::desc("Break post-RA scheduling anti-dependencies: "
63 "\"critical\", \"all\", or \"none\""),
64 cl::init("none"), cl::Hidden);
66 // If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
68 DebugDiv("postra-sched-debugdiv",
69 cl::desc("Debug control MBBs that are scheduled"),
70 cl::init(0), cl::Hidden);
72 DebugMod("postra-sched-debugmod",
73 cl::desc("Debug control MBBs that are scheduled"),
74 cl::init(0), cl::Hidden);
76 AntiDepBreaker::~AntiDepBreaker() { }
79 class PostRAScheduler : public MachineFunctionPass {
80 const TargetInstrInfo *TII;
81 RegisterClassInfo RegClassInfo;
85 PostRAScheduler() : MachineFunctionPass(ID) {}
87 void getAnalysisUsage(AnalysisUsage &AU) const override {
89 AU.addRequired<AAResultsWrapperPass>();
90 AU.addRequired<TargetPassConfig>();
91 AU.addRequired<MachineDominatorTree>();
92 AU.addPreserved<MachineDominatorTree>();
93 AU.addRequired<MachineLoopInfo>();
94 AU.addPreserved<MachineLoopInfo>();
95 MachineFunctionPass::getAnalysisUsage(AU);
98 MachineFunctionProperties getRequiredProperties() const override {
99 return MachineFunctionProperties().set(
100 MachineFunctionProperties::Property::NoVRegs);
103 bool runOnMachineFunction(MachineFunction &Fn) override;
106 bool enablePostRAScheduler(
107 const TargetSubtargetInfo &ST, CodeGenOpt::Level OptLevel,
108 TargetSubtargetInfo::AntiDepBreakMode &Mode,
109 TargetSubtargetInfo::RegClassVector &CriticalPathRCs) const;
111 char PostRAScheduler::ID = 0;
113 class SchedulePostRATDList : public ScheduleDAGInstrs {
114 /// AvailableQueue - The priority queue to use for the available SUnits.
116 LatencyPriorityQueue AvailableQueue;
118 /// PendingQueue - This contains all of the instructions whose operands have
119 /// been issued, but their results are not ready yet (due to the latency of
120 /// the operation). Once the operands becomes available, the instruction is
121 /// added to the AvailableQueue.
122 std::vector<SUnit*> PendingQueue;
124 /// HazardRec - The hazard recognizer to use.
125 ScheduleHazardRecognizer *HazardRec;
127 /// AntiDepBreak - Anti-dependence breaking object, or NULL if none
128 AntiDepBreaker *AntiDepBreak;
130 /// AA - AliasAnalysis for making memory reference queries.
133 /// The schedule. Null SUnit*'s represent noop instructions.
134 std::vector<SUnit*> Sequence;
136 /// Ordered list of DAG postprocessing steps.
137 std::vector<std::unique_ptr<ScheduleDAGMutation>> Mutations;
139 /// The index in BB of RegionEnd.
141 /// This is the instruction number from the top of the current block, not
142 /// the SlotIndex. It is only used by the AntiDepBreaker.
146 SchedulePostRATDList(
147 MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA,
148 const RegisterClassInfo &,
149 TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
150 SmallVectorImpl<const TargetRegisterClass *> &CriticalPathRCs);
152 ~SchedulePostRATDList() override;
154 /// startBlock - Initialize register live-range state for scheduling in
157 void startBlock(MachineBasicBlock *BB) override;
159 // Set the index of RegionEnd within the current BB.
160 void setEndIndex(unsigned EndIdx) { EndIndex = EndIdx; }
162 /// Initialize the scheduler state for the next scheduling region.
163 void enterRegion(MachineBasicBlock *bb,
164 MachineBasicBlock::iterator begin,
165 MachineBasicBlock::iterator end,
166 unsigned regioninstrs) override;
168 /// Notify that the scheduler has finished scheduling the current region.
169 void exitRegion() override;
171 /// Schedule - Schedule the instruction range using list scheduling.
173 void schedule() override;
177 /// Observe - Update liveness information to account for the current
178 /// instruction, which will not be scheduled.
180 void Observe(MachineInstr &MI, unsigned Count);
182 /// finishBlock - Clean up register live-range state.
184 void finishBlock() override;
187 /// Apply each ScheduleDAGMutation step in order.
188 void postprocessDAG();
190 void ReleaseSucc(SUnit *SU, SDep *SuccEdge);
191 void ReleaseSuccessors(SUnit *SU);
192 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
193 void ListScheduleTopDown();
195 void dumpSchedule() const;
196 void emitNoop(unsigned CurCycle);
200 char &llvm::PostRASchedulerID = PostRAScheduler::ID;
202 INITIALIZE_PASS(PostRAScheduler, DEBUG_TYPE,
203 "Post RA top-down list latency scheduler", false, false)
205 SchedulePostRATDList::SchedulePostRATDList(
206 MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA,
207 const RegisterClassInfo &RCI,
208 TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
209 SmallVectorImpl<const TargetRegisterClass *> &CriticalPathRCs)
210 : ScheduleDAGInstrs(MF, &MLI), AA(AA), EndIndex(0) {
212 const InstrItineraryData *InstrItins =
213 MF.getSubtarget().getInstrItineraryData();
215 MF.getSubtarget().getInstrInfo()->CreateTargetPostRAHazardRecognizer(
217 MF.getSubtarget().getPostRAMutations(Mutations);
219 assert((AntiDepMode == TargetSubtargetInfo::ANTIDEP_NONE ||
220 MRI.tracksLiveness()) &&
221 "Live-ins must be accurate for anti-dependency breaking");
223 ((AntiDepMode == TargetSubtargetInfo::ANTIDEP_ALL) ?
224 (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) :
225 ((AntiDepMode == TargetSubtargetInfo::ANTIDEP_CRITICAL) ?
226 (AntiDepBreaker *)new CriticalAntiDepBreaker(MF, RCI) : nullptr));
229 SchedulePostRATDList::~SchedulePostRATDList() {
234 /// Initialize state associated with the next scheduling region.
235 void SchedulePostRATDList::enterRegion(MachineBasicBlock *bb,
236 MachineBasicBlock::iterator begin,
237 MachineBasicBlock::iterator end,
238 unsigned regioninstrs) {
239 ScheduleDAGInstrs::enterRegion(bb, begin, end, regioninstrs);
243 /// Print the schedule before exiting the region.
244 void SchedulePostRATDList::exitRegion() {
246 dbgs() << "*** Final schedule ***\n";
250 ScheduleDAGInstrs::exitRegion();
253 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
254 /// dumpSchedule - dump the scheduled Sequence.
255 LLVM_DUMP_METHOD void SchedulePostRATDList::dumpSchedule() const {
256 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
257 if (SUnit *SU = Sequence[i])
260 dbgs() << "**** NOOP ****\n";
265 bool PostRAScheduler::enablePostRAScheduler(
266 const TargetSubtargetInfo &ST,
267 CodeGenOpt::Level OptLevel,
268 TargetSubtargetInfo::AntiDepBreakMode &Mode,
269 TargetSubtargetInfo::RegClassVector &CriticalPathRCs) const {
270 Mode = ST.getAntiDepBreakMode();
271 ST.getCriticalPathRCs(CriticalPathRCs);
273 // Check for explicit enable/disable of post-ra scheduling.
274 if (EnablePostRAScheduler.getPosition() > 0)
275 return EnablePostRAScheduler;
277 return ST.enablePostRAScheduler() &&
278 OptLevel >= ST.getOptLevelToEnablePostRAScheduler();
281 bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
282 if (skipFunction(Fn.getFunction()))
285 TII = Fn.getSubtarget().getInstrInfo();
286 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
287 AliasAnalysis *AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
288 TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
290 RegClassInfo.runOnMachineFunction(Fn);
292 TargetSubtargetInfo::AntiDepBreakMode AntiDepMode =
293 TargetSubtargetInfo::ANTIDEP_NONE;
294 SmallVector<const TargetRegisterClass*, 4> CriticalPathRCs;
296 // Check that post-RA scheduling is enabled for this target.
297 // This may upgrade the AntiDepMode.
298 if (!enablePostRAScheduler(Fn.getSubtarget(), PassConfig->getOptLevel(),
299 AntiDepMode, CriticalPathRCs))
302 // Check for antidep breaking override...
303 if (EnableAntiDepBreaking.getPosition() > 0) {
304 AntiDepMode = (EnableAntiDepBreaking == "all")
305 ? TargetSubtargetInfo::ANTIDEP_ALL
306 : ((EnableAntiDepBreaking == "critical")
307 ? TargetSubtargetInfo::ANTIDEP_CRITICAL
308 : TargetSubtargetInfo::ANTIDEP_NONE);
311 DEBUG(dbgs() << "PostRAScheduler\n");
313 SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode,
316 // Loop over all of the basic blocks
317 for (auto &MBB : Fn) {
319 // If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
321 static int bbcnt = 0;
322 if (bbcnt++ % DebugDiv != DebugMod)
324 dbgs() << "*** DEBUG scheduling " << Fn.getName() << ":"
325 << printMBBReference(MBB) << " ***\n";
329 // Initialize register live-range state for scheduling in this block.
330 Scheduler.startBlock(&MBB);
332 // Schedule each sequence of instructions not interrupted by a label
333 // or anything else that effectively needs to shut down scheduling.
334 MachineBasicBlock::iterator Current = MBB.end();
335 unsigned Count = MBB.size(), CurrentCount = Count;
336 for (MachineBasicBlock::iterator I = Current; I != MBB.begin();) {
337 MachineInstr &MI = *std::prev(I);
339 // Calls are not scheduling boundaries before register allocation, but
340 // post-ra we don't gain anything by scheduling across calls since we
341 // don't need to worry about register pressure.
342 if (MI.isCall() || TII->isSchedulingBoundary(MI, &MBB, Fn)) {
343 Scheduler.enterRegion(&MBB, I, Current, CurrentCount - Count);
344 Scheduler.setEndIndex(CurrentCount);
345 Scheduler.schedule();
346 Scheduler.exitRegion();
347 Scheduler.EmitSchedule();
349 CurrentCount = Count;
350 Scheduler.Observe(MI, CurrentCount);
354 Count -= MI.getBundleSize();
356 assert(Count == 0 && "Instruction count mismatch!");
357 assert((MBB.begin() == Current || CurrentCount != 0) &&
358 "Instruction count mismatch!");
359 Scheduler.enterRegion(&MBB, MBB.begin(), Current, CurrentCount);
360 Scheduler.setEndIndex(CurrentCount);
361 Scheduler.schedule();
362 Scheduler.exitRegion();
363 Scheduler.EmitSchedule();
365 // Clean up register live-range state.
366 Scheduler.finishBlock();
368 // Update register kills
369 Scheduler.fixupKills(MBB);
375 /// StartBlock - Initialize register live-range state for scheduling in
378 void SchedulePostRATDList::startBlock(MachineBasicBlock *BB) {
379 // Call the superclass.
380 ScheduleDAGInstrs::startBlock(BB);
382 // Reset the hazard recognizer and anti-dep breaker.
385 AntiDepBreak->StartBlock(BB);
388 /// Schedule - Schedule the instruction range using list scheduling.
390 void SchedulePostRATDList::schedule() {
391 // Build the scheduling graph.
396 AntiDepBreak->BreakAntiDependencies(SUnits, RegionBegin, RegionEnd,
397 EndIndex, DbgValues);
400 // We made changes. Update the dependency graph.
401 // Theoretically we could update the graph in place:
402 // When a live range is changed to use a different register, remove
403 // the def's anti-dependence *and* output-dependence edges due to
404 // that register, and add new anti-dependence and output-dependence
405 // edges based on the next live range of the register.
406 ScheduleDAG::clearDAG();
409 NumFixedAnti += Broken;
415 DEBUG(dbgs() << "********** List Scheduling **********\n");
417 for (const SUnit &SU : SUnits) {
423 AvailableQueue.initNodes(SUnits);
424 ListScheduleTopDown();
425 AvailableQueue.releaseState();
428 /// Observe - Update liveness information to account for the current
429 /// instruction, which will not be scheduled.
431 void SchedulePostRATDList::Observe(MachineInstr &MI, unsigned Count) {
433 AntiDepBreak->Observe(MI, Count, EndIndex);
436 /// FinishBlock - Clean up register live-range state.
438 void SchedulePostRATDList::finishBlock() {
440 AntiDepBreak->FinishBlock();
442 // Call the superclass.
443 ScheduleDAGInstrs::finishBlock();
446 /// Apply each ScheduleDAGMutation step in order.
447 void SchedulePostRATDList::postprocessDAG() {
448 for (auto &M : Mutations)
452 //===----------------------------------------------------------------------===//
453 // Top-Down Scheduling
454 //===----------------------------------------------------------------------===//
456 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
457 /// the PendingQueue if the count reaches zero.
458 void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
459 SUnit *SuccSU = SuccEdge->getSUnit();
461 if (SuccEdge->isWeak()) {
462 --SuccSU->WeakPredsLeft;
466 if (SuccSU->NumPredsLeft == 0) {
467 dbgs() << "*** Scheduling failed! ***\n";
469 dbgs() << " has been released too many times!\n";
470 llvm_unreachable(nullptr);
473 --SuccSU->NumPredsLeft;
475 // Standard scheduler algorithms will recompute the depth of the successor
477 // SuccSU->setDepthToAtLeast(SU->getDepth() + SuccEdge->getLatency());
479 // However, we lazily compute node depth instead. Note that
480 // ScheduleNodeTopDown has already updated the depth of this node which causes
481 // all descendents to be marked dirty. Setting the successor depth explicitly
482 // here would cause depth to be recomputed for all its ancestors. If the
483 // successor is not yet ready (because of a transitively redundant edge) then
484 // this causes depth computation to be quadratic in the size of the DAG.
486 // If all the node's predecessors are scheduled, this node is ready
487 // to be scheduled. Ignore the special ExitSU node.
488 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
489 PendingQueue.push_back(SuccSU);
492 /// ReleaseSuccessors - Call ReleaseSucc on each of SU's successors.
493 void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) {
494 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
496 ReleaseSucc(SU, &*I);
500 /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
501 /// count of its successors. If a successor pending count is zero, add it to
502 /// the Available queue.
503 void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
504 DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: ");
505 DEBUG(SU->dump(this));
507 Sequence.push_back(SU);
508 assert(CurCycle >= SU->getDepth() &&
509 "Node scheduled above its depth!");
510 SU->setDepthToAtLeast(CurCycle);
512 ReleaseSuccessors(SU);
513 SU->isScheduled = true;
514 AvailableQueue.scheduledNode(SU);
517 /// emitNoop - Add a noop to the current instruction sequence.
518 void SchedulePostRATDList::emitNoop(unsigned CurCycle) {
519 DEBUG(dbgs() << "*** Emitting noop in cycle " << CurCycle << '\n');
520 HazardRec->EmitNoop();
521 Sequence.push_back(nullptr); // NULL here means noop
525 /// ListScheduleTopDown - The main loop of list scheduling for top-down
527 void SchedulePostRATDList::ListScheduleTopDown() {
528 unsigned CurCycle = 0;
530 // We're scheduling top-down but we're visiting the regions in
531 // bottom-up order, so we don't know the hazards at the start of a
532 // region. So assume no hazards (this should usually be ok as most
533 // blocks are a single region).
536 // Release any successors of the special Entry node.
537 ReleaseSuccessors(&EntrySU);
539 // Add all leaves to Available queue.
540 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
541 // It is available if it has no predecessors.
542 if (!SUnits[i].NumPredsLeft && !SUnits[i].isAvailable) {
543 AvailableQueue.push(&SUnits[i]);
544 SUnits[i].isAvailable = true;
548 // In any cycle where we can't schedule any instructions, we must
549 // stall or emit a noop, depending on the target.
550 bool CycleHasInsts = false;
552 // While Available queue is not empty, grab the node with the highest
553 // priority. If it is not ready put it back. Schedule the node.
554 std::vector<SUnit*> NotReady;
555 Sequence.reserve(SUnits.size());
556 while (!AvailableQueue.empty() || !PendingQueue.empty()) {
557 // Check to see if any of the pending instructions are ready to issue. If
558 // so, add them to the available queue.
559 unsigned MinDepth = ~0u;
560 for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
561 if (PendingQueue[i]->getDepth() <= CurCycle) {
562 AvailableQueue.push(PendingQueue[i]);
563 PendingQueue[i]->isAvailable = true;
564 PendingQueue[i] = PendingQueue.back();
565 PendingQueue.pop_back();
567 } else if (PendingQueue[i]->getDepth() < MinDepth)
568 MinDepth = PendingQueue[i]->getDepth();
571 DEBUG(dbgs() << "\n*** Examining Available\n"; AvailableQueue.dump(this));
573 SUnit *FoundSUnit = nullptr, *NotPreferredSUnit = nullptr;
574 bool HasNoopHazards = false;
575 while (!AvailableQueue.empty()) {
576 SUnit *CurSUnit = AvailableQueue.pop();
578 ScheduleHazardRecognizer::HazardType HT =
579 HazardRec->getHazardType(CurSUnit, 0/*no stalls*/);
580 if (HT == ScheduleHazardRecognizer::NoHazard) {
581 if (HazardRec->ShouldPreferAnother(CurSUnit)) {
582 if (!NotPreferredSUnit) {
583 // If this is the first non-preferred node for this cycle, then
584 // record it and continue searching for a preferred node. If this
585 // is not the first non-preferred node, then treat it as though
586 // there had been a hazard.
587 NotPreferredSUnit = CurSUnit;
591 FoundSUnit = CurSUnit;
596 // Remember if this is a noop hazard.
597 HasNoopHazards |= HT == ScheduleHazardRecognizer::NoopHazard;
599 NotReady.push_back(CurSUnit);
602 // If we have a non-preferred node, push it back onto the available list.
603 // If we did not find a preferred node, then schedule this first
604 // non-preferred node.
605 if (NotPreferredSUnit) {
607 DEBUG(dbgs() << "*** Will schedule a non-preferred instruction...\n");
608 FoundSUnit = NotPreferredSUnit;
610 AvailableQueue.push(NotPreferredSUnit);
613 NotPreferredSUnit = nullptr;
616 // Add the nodes that aren't ready back onto the available list.
617 if (!NotReady.empty()) {
618 AvailableQueue.push_all(NotReady);
622 // If we found a node to schedule...
624 // If we need to emit noops prior to this instruction, then do so.
625 unsigned NumPreNoops = HazardRec->PreEmitNoops(FoundSUnit);
626 for (unsigned i = 0; i != NumPreNoops; ++i)
629 // ... schedule the node...
630 ScheduleNodeTopDown(FoundSUnit, CurCycle);
631 HazardRec->EmitInstruction(FoundSUnit);
632 CycleHasInsts = true;
633 if (HazardRec->atIssueLimit()) {
634 DEBUG(dbgs() << "*** Max instructions per cycle " << CurCycle << '\n');
635 HazardRec->AdvanceCycle();
637 CycleHasInsts = false;
641 DEBUG(dbgs() << "*** Finished cycle " << CurCycle << '\n');
642 HazardRec->AdvanceCycle();
643 } else if (!HasNoopHazards) {
644 // Otherwise, we have a pipeline stall, but no other problem,
645 // just advance the current cycle and try again.
646 DEBUG(dbgs() << "*** Stall in cycle " << CurCycle << '\n');
647 HazardRec->AdvanceCycle();
650 // Otherwise, we have no instructions to issue and we have instructions
651 // that will fault if we don't do this right. This is the case for
652 // processors without pipeline interlocks and other cases.
657 CycleHasInsts = false;
662 unsigned ScheduledNodes = VerifyScheduledDAG(/*isBottomUp=*/false);
664 for (unsigned i = 0, e = Sequence.size(); i != e; ++i)
667 assert(Sequence.size() - Noops == ScheduledNodes &&
668 "The number of nodes scheduled doesn't match the expected number!");
672 // EmitSchedule - Emit the machine code in scheduled order.
673 void SchedulePostRATDList::EmitSchedule() {
674 RegionBegin = RegionEnd;
676 // If first instruction was a DBG_VALUE then put it back.
678 BB->splice(RegionEnd, BB, FirstDbgValue);
680 // Then re-insert them according to the given schedule.
681 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
682 if (SUnit *SU = Sequence[i])
683 BB->splice(RegionEnd, BB, SU->getInstr());
685 // Null SUnit* is a noop.
686 TII->insertNoop(*BB, RegionEnd);
688 // Update the Begin iterator, as the first instruction in the block
689 // may have been scheduled later.
691 RegionBegin = std::prev(RegionEnd);
694 // Reinsert any remaining debug_values.
695 for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
696 DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
697 std::pair<MachineInstr *, MachineInstr *> P = *std::prev(DI);
698 MachineInstr *DbgValue = P.first;
699 MachineBasicBlock::iterator OrigPrivMI = P.second;
700 BB->splice(++OrigPrivMI, BB, DbgValue);
703 FirstDbgValue = nullptr;