1 //===-- RegAllocBasic.cpp - Basic Register Allocator ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RABasic function pass, which provides a minimal
11 // implementation of the basic register allocator.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/Passes.h"
16 #include "AllocationOrder.h"
17 #include "LiveDebugVariables.h"
18 #include "RegAllocBase.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/CodeGen/CalcSpillWeights.h"
22 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
23 #include "llvm/CodeGen/LiveRangeEdit.h"
24 #include "llvm/CodeGen/LiveRegMatrix.h"
25 #include "llvm/CodeGen/LiveStackAnalysis.h"
26 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/MachineInstr.h"
29 #include "llvm/CodeGen/MachineLoopInfo.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegAllocRegistry.h"
32 #include "llvm/CodeGen/VirtRegMap.h"
33 #include "llvm/PassAnalysisSupport.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetRegisterInfo.h"
42 #define DEBUG_TYPE "regalloc"
44 static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
45 createBasicRegisterAllocator);
48 struct CompSpillWeight {
49 bool operator()(LiveInterval *A, LiveInterval *B) const {
50 return A->weight < B->weight;
56 /// RABasic provides a minimal implementation of the basic register allocation
57 /// algorithm. It prioritizes live virtual registers by spill weight and spills
58 /// whenever a register is unavailable. This is not practical in production but
59 /// provides a useful baseline both for measuring other allocators and comparing
60 /// the speed of the basic algorithm against other styles of allocators.
61 class RABasic : public MachineFunctionPass, public RegAllocBase
67 std::unique_ptr<Spiller> SpillerInstance;
68 std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
69 CompSpillWeight> Queue;
71 // Scratch space. Allocated here to avoid repeated malloc calls in
78 /// Return the pass name.
79 StringRef getPassName() const override { return "Basic Register Allocator"; }
81 /// RABasic analysis usage.
82 void getAnalysisUsage(AnalysisUsage &AU) const override;
84 void releaseMemory() override;
86 Spiller &spiller() override { return *SpillerInstance; }
88 void enqueue(LiveInterval *LI) override {
92 LiveInterval *dequeue() override {
95 LiveInterval *LI = Queue.top();
100 unsigned selectOrSplit(LiveInterval &VirtReg,
101 SmallVectorImpl<unsigned> &SplitVRegs) override;
103 /// Perform register allocation.
104 bool runOnMachineFunction(MachineFunction &mf) override;
106 MachineFunctionProperties getRequiredProperties() const override {
107 return MachineFunctionProperties().set(
108 MachineFunctionProperties::Property::NoPHIs);
111 // Helper for spilling all live virtual registers currently unified under preg
112 // that interfere with the most recently queried lvr. Return true if spilling
113 // was successful, and append any new spilled/split intervals to splitLVRs.
114 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
115 SmallVectorImpl<unsigned> &SplitVRegs);
120 char RABasic::ID = 0;
122 } // end anonymous namespace
124 RABasic::RABasic(): MachineFunctionPass(ID) {
125 initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
126 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
127 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
128 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
129 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
130 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
131 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
132 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
133 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
134 initializeLiveRegMatrixPass(*PassRegistry::getPassRegistry());
137 void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
138 AU.setPreservesCFG();
139 AU.addRequired<AAResultsWrapperPass>();
140 AU.addPreserved<AAResultsWrapperPass>();
141 AU.addRequired<LiveIntervals>();
142 AU.addPreserved<LiveIntervals>();
143 AU.addPreserved<SlotIndexes>();
144 AU.addRequired<LiveDebugVariables>();
145 AU.addPreserved<LiveDebugVariables>();
146 AU.addRequired<LiveStacks>();
147 AU.addPreserved<LiveStacks>();
148 AU.addRequired<MachineBlockFrequencyInfo>();
149 AU.addPreserved<MachineBlockFrequencyInfo>();
150 AU.addRequiredID(MachineDominatorsID);
151 AU.addPreservedID(MachineDominatorsID);
152 AU.addRequired<MachineLoopInfo>();
153 AU.addPreserved<MachineLoopInfo>();
154 AU.addRequired<VirtRegMap>();
155 AU.addPreserved<VirtRegMap>();
156 AU.addRequired<LiveRegMatrix>();
157 AU.addPreserved<LiveRegMatrix>();
158 MachineFunctionPass::getAnalysisUsage(AU);
161 void RABasic::releaseMemory() {
162 SpillerInstance.reset();
166 // Spill or split all live virtual registers currently unified under PhysReg
167 // that interfere with VirtReg. The newly spilled or split live intervals are
168 // returned by appending them to SplitVRegs.
169 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
170 SmallVectorImpl<unsigned> &SplitVRegs) {
171 // Record each interference and determine if all are spillable before mutating
172 // either the union or live intervals.
173 SmallVector<LiveInterval*, 8> Intfs;
175 // Collect interferences assigned to any alias of the physical register.
176 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
177 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
178 Q.collectInterferingVRegs();
179 for (unsigned i = Q.interferingVRegs().size(); i; --i) {
180 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
181 if (!Intf->isSpillable() || Intf->weight > VirtReg.weight)
183 Intfs.push_back(Intf);
186 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
187 " interferences with " << VirtReg << "\n");
188 assert(!Intfs.empty() && "expected interference");
190 // Spill each interfering vreg allocated to PhysReg or an alias.
191 for (unsigned i = 0, e = Intfs.size(); i != e; ++i) {
192 LiveInterval &Spill = *Intfs[i];
195 if (!VRM->hasPhys(Spill.reg))
198 // Deallocate the interfering vreg by removing it from the union.
199 // A LiveInterval instance may not be in a union during modification!
200 Matrix->unassign(Spill);
202 // Spill the extracted interval.
203 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM, nullptr, &DeadRemats);
204 spiller().spill(LRE);
209 // Driver for the register assignment and splitting heuristics.
210 // Manages iteration over the LiveIntervalUnions.
212 // This is a minimal implementation of register assignment and splitting that
213 // spills whenever we run out of registers.
215 // selectOrSplit can only be called once per live virtual register. We then do a
216 // single interference test for each register the correct class until we find an
217 // available register. So, the number of interference tests in the worst case is
218 // |vregs| * |machineregs|. And since the number of interference tests is
219 // minimal, there is no value in caching them outside the scope of
221 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
222 SmallVectorImpl<unsigned> &SplitVRegs) {
223 // Populate a list of physical register spill candidates.
224 SmallVector<unsigned, 8> PhysRegSpillCands;
226 // Check for an available register in this class.
227 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
228 while (unsigned PhysReg = Order.next()) {
229 // Check for interference in PhysReg
230 switch (Matrix->checkInterference(VirtReg, PhysReg)) {
231 case LiveRegMatrix::IK_Free:
232 // PhysReg is available, allocate it.
235 case LiveRegMatrix::IK_VirtReg:
236 // Only virtual registers in the way, we may be able to spill them.
237 PhysRegSpillCands.push_back(PhysReg);
241 // RegMask or RegUnit interference.
246 // Try to spill another interfering reg with less spill weight.
247 for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
248 PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
249 if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs))
252 assert(!Matrix->checkInterference(VirtReg, *PhysRegI) &&
253 "Interference after spill.");
254 // Tell the caller to allocate to this newly freed physical register.
258 // No other spill candidates were found, so spill the current VirtReg.
259 DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
260 if (!VirtReg.isSpillable())
262 LiveRangeEdit LRE(&VirtReg, SplitVRegs, *MF, *LIS, VRM, nullptr, &DeadRemats);
263 spiller().spill(LRE);
265 // The live virtual register requesting allocation was spilled, so tell
266 // the caller not to allocate anything during this round.
270 bool RABasic::runOnMachineFunction(MachineFunction &mf) {
271 DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
272 << "********** Function: "
273 << mf.getName() << '\n');
276 RegAllocBase::init(getAnalysis<VirtRegMap>(),
277 getAnalysis<LiveIntervals>(),
278 getAnalysis<LiveRegMatrix>());
280 calculateSpillWeightsAndHints(*LIS, *MF, VRM,
281 getAnalysis<MachineLoopInfo>(),
282 getAnalysis<MachineBlockFrequencyInfo>());
284 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
289 // Diagnostic output before rewriting
290 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
296 FunctionPass* llvm::createBasicRegisterAllocator()
298 return new RABasic();