1 //===-- RegAllocBasic.cpp - Basic Register Allocator ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RABasic function pass, which provides a minimal
11 // implementation of the basic register allocator.
13 //===----------------------------------------------------------------------===//
15 #include "AllocationOrder.h"
16 #include "LiveDebugVariables.h"
17 #include "RegAllocBase.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/CodeGen/CalcSpillWeights.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/LiveRangeEdit.h"
23 #include "llvm/CodeGen/LiveRegMatrix.h"
24 #include "llvm/CodeGen/LiveStackAnalysis.h"
25 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstr.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/CodeGen/RegAllocRegistry.h"
32 #include "llvm/CodeGen/VirtRegMap.h"
33 #include "llvm/PassAnalysisSupport.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetRegisterInfo.h"
42 #define DEBUG_TYPE "regalloc"
44 static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
45 createBasicRegisterAllocator);
48 struct CompSpillWeight {
49 bool operator()(LiveInterval *A, LiveInterval *B) const {
50 return A->weight < B->weight;
56 /// RABasic provides a minimal implementation of the basic register allocation
57 /// algorithm. It prioritizes live virtual registers by spill weight and spills
58 /// whenever a register is unavailable. This is not practical in production but
59 /// provides a useful baseline both for measuring other allocators and comparing
60 /// the speed of the basic algorithm against other styles of allocators.
61 class RABasic : public MachineFunctionPass,
63 private LiveRangeEdit::Delegate {
68 std::unique_ptr<Spiller> SpillerInstance;
69 std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
70 CompSpillWeight> Queue;
72 // Scratch space. Allocated here to avoid repeated malloc calls in
76 bool LRE_CanEraseVirtReg(unsigned) override;
77 void LRE_WillShrinkVirtReg(unsigned) override;
82 /// Return the pass name.
83 StringRef getPassName() const override { return "Basic Register Allocator"; }
85 /// RABasic analysis usage.
86 void getAnalysisUsage(AnalysisUsage &AU) const override;
88 void releaseMemory() override;
90 Spiller &spiller() override { return *SpillerInstance; }
92 void enqueue(LiveInterval *LI) override {
96 LiveInterval *dequeue() override {
99 LiveInterval *LI = Queue.top();
104 unsigned selectOrSplit(LiveInterval &VirtReg,
105 SmallVectorImpl<unsigned> &SplitVRegs) override;
107 /// Perform register allocation.
108 bool runOnMachineFunction(MachineFunction &mf) override;
110 MachineFunctionProperties getRequiredProperties() const override {
111 return MachineFunctionProperties().set(
112 MachineFunctionProperties::Property::NoPHIs);
115 // Helper for spilling all live virtual registers currently unified under preg
116 // that interfere with the most recently queried lvr. Return true if spilling
117 // was successful, and append any new spilled/split intervals to splitLVRs.
118 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
119 SmallVectorImpl<unsigned> &SplitVRegs);
124 char RABasic::ID = 0;
126 } // end anonymous namespace
128 char &llvm::RABasicID = RABasic::ID;
130 INITIALIZE_PASS_BEGIN(RABasic, "regallocbasic", "Basic Register Allocator",
132 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
133 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
134 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
135 INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer)
136 INITIALIZE_PASS_DEPENDENCY(MachineScheduler)
137 INITIALIZE_PASS_DEPENDENCY(LiveStacks)
138 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
139 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
140 INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
141 INITIALIZE_PASS_DEPENDENCY(LiveRegMatrix)
142 INITIALIZE_PASS_END(RABasic, "regallocbasic", "Basic Register Allocator", false,
145 bool RABasic::LRE_CanEraseVirtReg(unsigned VirtReg) {
146 if (VRM->hasPhys(VirtReg)) {
147 LiveInterval &LI = LIS->getInterval(VirtReg);
148 Matrix->unassign(LI);
149 aboutToRemoveInterval(LI);
152 // Unassigned virtreg is probably in the priority queue.
153 // RegAllocBase will erase it after dequeueing.
157 void RABasic::LRE_WillShrinkVirtReg(unsigned VirtReg) {
158 if (!VRM->hasPhys(VirtReg))
161 // Register is assigned, put it back on the queue for reassignment.
162 LiveInterval &LI = LIS->getInterval(VirtReg);
163 Matrix->unassign(LI);
167 RABasic::RABasic(): MachineFunctionPass(ID) {
170 void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
171 AU.setPreservesCFG();
172 AU.addRequired<AAResultsWrapperPass>();
173 AU.addPreserved<AAResultsWrapperPass>();
174 AU.addRequired<LiveIntervals>();
175 AU.addPreserved<LiveIntervals>();
176 AU.addPreserved<SlotIndexes>();
177 AU.addRequired<LiveDebugVariables>();
178 AU.addPreserved<LiveDebugVariables>();
179 AU.addRequired<LiveStacks>();
180 AU.addPreserved<LiveStacks>();
181 AU.addRequired<MachineBlockFrequencyInfo>();
182 AU.addPreserved<MachineBlockFrequencyInfo>();
183 AU.addRequiredID(MachineDominatorsID);
184 AU.addPreservedID(MachineDominatorsID);
185 AU.addRequired<MachineLoopInfo>();
186 AU.addPreserved<MachineLoopInfo>();
187 AU.addRequired<VirtRegMap>();
188 AU.addPreserved<VirtRegMap>();
189 AU.addRequired<LiveRegMatrix>();
190 AU.addPreserved<LiveRegMatrix>();
191 MachineFunctionPass::getAnalysisUsage(AU);
194 void RABasic::releaseMemory() {
195 SpillerInstance.reset();
199 // Spill or split all live virtual registers currently unified under PhysReg
200 // that interfere with VirtReg. The newly spilled or split live intervals are
201 // returned by appending them to SplitVRegs.
202 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
203 SmallVectorImpl<unsigned> &SplitVRegs) {
204 // Record each interference and determine if all are spillable before mutating
205 // either the union or live intervals.
206 SmallVector<LiveInterval*, 8> Intfs;
208 // Collect interferences assigned to any alias of the physical register.
209 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
210 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
211 Q.collectInterferingVRegs();
212 for (unsigned i = Q.interferingVRegs().size(); i; --i) {
213 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
214 if (!Intf->isSpillable() || Intf->weight > VirtReg.weight)
216 Intfs.push_back(Intf);
219 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
220 " interferences with " << VirtReg << "\n");
221 assert(!Intfs.empty() && "expected interference");
223 // Spill each interfering vreg allocated to PhysReg or an alias.
224 for (unsigned i = 0, e = Intfs.size(); i != e; ++i) {
225 LiveInterval &Spill = *Intfs[i];
228 if (!VRM->hasPhys(Spill.reg))
231 // Deallocate the interfering vreg by removing it from the union.
232 // A LiveInterval instance may not be in a union during modification!
233 Matrix->unassign(Spill);
235 // Spill the extracted interval.
236 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats);
237 spiller().spill(LRE);
242 // Driver for the register assignment and splitting heuristics.
243 // Manages iteration over the LiveIntervalUnions.
245 // This is a minimal implementation of register assignment and splitting that
246 // spills whenever we run out of registers.
248 // selectOrSplit can only be called once per live virtual register. We then do a
249 // single interference test for each register the correct class until we find an
250 // available register. So, the number of interference tests in the worst case is
251 // |vregs| * |machineregs|. And since the number of interference tests is
252 // minimal, there is no value in caching them outside the scope of
254 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
255 SmallVectorImpl<unsigned> &SplitVRegs) {
256 // Populate a list of physical register spill candidates.
257 SmallVector<unsigned, 8> PhysRegSpillCands;
259 // Check for an available register in this class.
260 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
261 while (unsigned PhysReg = Order.next()) {
262 // Check for interference in PhysReg
263 switch (Matrix->checkInterference(VirtReg, PhysReg)) {
264 case LiveRegMatrix::IK_Free:
265 // PhysReg is available, allocate it.
268 case LiveRegMatrix::IK_VirtReg:
269 // Only virtual registers in the way, we may be able to spill them.
270 PhysRegSpillCands.push_back(PhysReg);
274 // RegMask or RegUnit interference.
279 // Try to spill another interfering reg with less spill weight.
280 for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
281 PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
282 if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs))
285 assert(!Matrix->checkInterference(VirtReg, *PhysRegI) &&
286 "Interference after spill.");
287 // Tell the caller to allocate to this newly freed physical register.
291 // No other spill candidates were found, so spill the current VirtReg.
292 DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
293 if (!VirtReg.isSpillable())
295 LiveRangeEdit LRE(&VirtReg, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats);
296 spiller().spill(LRE);
298 // The live virtual register requesting allocation was spilled, so tell
299 // the caller not to allocate anything during this round.
303 bool RABasic::runOnMachineFunction(MachineFunction &mf) {
304 DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
305 << "********** Function: "
306 << mf.getName() << '\n');
309 RegAllocBase::init(getAnalysis<VirtRegMap>(),
310 getAnalysis<LiveIntervals>(),
311 getAnalysis<LiveRegMatrix>());
313 calculateSpillWeightsAndHints(*LIS, *MF, VRM,
314 getAnalysis<MachineLoopInfo>(),
315 getAnalysis<MachineBlockFrequencyInfo>());
317 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
322 // Diagnostic output before rewriting
323 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
329 FunctionPass* llvm::createBasicRegisterAllocator()
331 return new RABasic();