1 //===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RAGreedy function pass for register allocation in
13 //===----------------------------------------------------------------------===//
15 #include "AllocationOrder.h"
16 #include "InterferenceCache.h"
17 #include "LiveDebugVariables.h"
18 #include "RegAllocBase.h"
19 #include "SpillPlacement.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/CodeGen/CalcSpillWeights.h"
25 #include "llvm/CodeGen/EdgeBundles.h"
26 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
27 #include "llvm/CodeGen/LiveRangeEdit.h"
28 #include "llvm/CodeGen/LiveRegMatrix.h"
29 #include "llvm/CodeGen/LiveStackAnalysis.h"
30 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
31 #include "llvm/CodeGen/MachineDominators.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineLoopInfo.h"
35 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/CodeGen/RegAllocRegistry.h"
39 #include "llvm/CodeGen/RegisterClassInfo.h"
40 #include "llvm/CodeGen/VirtRegMap.h"
41 #include "llvm/IR/LLVMContext.h"
42 #include "llvm/PassAnalysisSupport.h"
43 #include "llvm/Support/BranchProbability.h"
44 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/Timer.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetSubtargetInfo.h"
55 #define DEBUG_TYPE "regalloc"
57 STATISTIC(NumGlobalSplits, "Number of split global live ranges");
58 STATISTIC(NumLocalSplits, "Number of split local live ranges");
59 STATISTIC(NumEvicted, "Number of interferences evicted");
61 static cl::opt<SplitEditor::ComplementSpillMode> SplitSpillMode(
62 "split-spill-mode", cl::Hidden,
63 cl::desc("Spill mode for splitting live ranges"),
64 cl::values(clEnumValN(SplitEditor::SM_Partition, "default", "Default"),
65 clEnumValN(SplitEditor::SM_Size, "size", "Optimize for size"),
66 clEnumValN(SplitEditor::SM_Speed, "speed", "Optimize for speed")),
67 cl::init(SplitEditor::SM_Speed));
69 static cl::opt<unsigned>
70 LastChanceRecoloringMaxDepth("lcr-max-depth", cl::Hidden,
71 cl::desc("Last chance recoloring max depth"),
74 static cl::opt<unsigned> LastChanceRecoloringMaxInterference(
75 "lcr-max-interf", cl::Hidden,
76 cl::desc("Last chance recoloring maximum number of considered"
77 " interference at a time"),
81 ExhaustiveSearch("exhaustive-register-search", cl::NotHidden,
82 cl::desc("Exhaustive Search for registers bypassing the depth "
83 "and interference cutoffs of last chance recoloring"));
85 static cl::opt<bool> EnableLocalReassignment(
86 "enable-local-reassign", cl::Hidden,
87 cl::desc("Local reassignment can yield better allocation decisions, but "
88 "may be compile time intensive"),
91 static cl::opt<bool> EnableDeferredSpilling(
92 "enable-deferred-spilling", cl::Hidden,
93 cl::desc("Instead of spilling a variable right away, defer the actual "
94 "code insertion to the end of the allocation. That way the "
95 "allocator might still find a suitable coloring for this "
96 "variable because of other evicted variables."),
99 // FIXME: Find a good default for this flag and remove the flag.
100 static cl::opt<unsigned>
101 CSRFirstTimeCost("regalloc-csr-first-time-cost",
102 cl::desc("Cost for first time use of callee-saved register."),
103 cl::init(0), cl::Hidden);
105 static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
106 createGreedyRegisterAllocator);
109 class RAGreedy : public MachineFunctionPass,
111 private LiveRangeEdit::Delegate {
112 // Convenient shortcuts.
113 typedef std::priority_queue<std::pair<unsigned, unsigned> > PQueue;
114 typedef SmallPtrSet<LiveInterval *, 4> SmallLISet;
115 typedef SmallSet<unsigned, 16> SmallVirtRegSet;
120 // Shortcuts to some useful interface.
121 const TargetInstrInfo *TII;
122 const TargetRegisterInfo *TRI;
123 RegisterClassInfo RCI;
126 SlotIndexes *Indexes;
127 MachineBlockFrequencyInfo *MBFI;
128 MachineDominatorTree *DomTree;
129 MachineLoopInfo *Loops;
130 MachineOptimizationRemarkEmitter *ORE;
131 EdgeBundles *Bundles;
132 SpillPlacement *SpillPlacer;
133 LiveDebugVariables *DebugVars;
137 std::unique_ptr<Spiller> SpillerInstance;
139 unsigned NextCascade;
141 // Live ranges pass through a number of stages as we try to allocate them.
142 // Some of the stages may also create new live ranges:
144 // - Region splitting.
145 // - Per-block splitting.
146 // - Local splitting.
149 // Ranges produced by one of the stages skip the previous stages when they are
150 // dequeued. This improves performance because we can skip interference checks
151 // that are unlikely to give any results. It also guarantees that the live
152 // range splitting algorithm terminates, something that is otherwise hard to
154 enum LiveRangeStage {
155 /// Newly created live range that has never been queued.
158 /// Only attempt assignment and eviction. Then requeue as RS_Split.
161 /// Attempt live range splitting if assignment is impossible.
164 /// Attempt more aggressive live range splitting that is guaranteed to make
165 /// progress. This is used for split products that may not be making
169 /// Live range will be spilled. No more splitting will be attempted.
173 /// Live range is in memory. Because of other evictions, it might get moved
174 /// in a register in the end.
177 /// There is nothing more we can do to this live range. Abort compilation
178 /// if it can't be assigned.
182 // Enum CutOffStage to keep a track whether the register allocation failed
183 // because of the cutoffs encountered in last chance recoloring.
184 // Note: This is used as bitmask. New value should be next power of 2.
186 // No cutoffs encountered
189 // lcr-max-depth cutoff encountered
192 // lcr-max-interf cutoff encountered
199 static const char *const StageName[];
202 // RegInfo - Keep additional information about each live range.
204 LiveRangeStage Stage;
206 // Cascade - Eviction loop prevention. See canEvictInterference().
209 RegInfo() : Stage(RS_New), Cascade(0) {}
212 IndexedMap<RegInfo, VirtReg2IndexFunctor> ExtraRegInfo;
214 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
215 return ExtraRegInfo[VirtReg.reg].Stage;
218 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) {
219 ExtraRegInfo.resize(MRI->getNumVirtRegs());
220 ExtraRegInfo[VirtReg.reg].Stage = Stage;
223 template<typename Iterator>
224 void setStage(Iterator Begin, Iterator End, LiveRangeStage NewStage) {
225 ExtraRegInfo.resize(MRI->getNumVirtRegs());
226 for (;Begin != End; ++Begin) {
227 unsigned Reg = *Begin;
228 if (ExtraRegInfo[Reg].Stage == RS_New)
229 ExtraRegInfo[Reg].Stage = NewStage;
233 /// Cost of evicting interference.
234 struct EvictionCost {
235 unsigned BrokenHints; ///< Total number of broken hints.
236 float MaxWeight; ///< Maximum spill weight evicted.
238 EvictionCost(): BrokenHints(0), MaxWeight(0) {}
240 bool isMax() const { return BrokenHints == ~0u; }
242 void setMax() { BrokenHints = ~0u; }
244 void setBrokenHints(unsigned NHints) { BrokenHints = NHints; }
246 bool operator<(const EvictionCost &O) const {
247 return std::tie(BrokenHints, MaxWeight) <
248 std::tie(O.BrokenHints, O.MaxWeight);
253 std::unique_ptr<SplitAnalysis> SA;
254 std::unique_ptr<SplitEditor> SE;
256 /// Cached per-block interference maps
257 InterferenceCache IntfCache;
259 /// All basic blocks where the current register has uses.
260 SmallVector<SpillPlacement::BlockConstraint, 8> SplitConstraints;
262 /// Global live range splitting candidate info.
263 struct GlobalSplitCandidate {
264 // Register intended for assignment, or 0.
267 // SplitKit interval index for this candidate.
270 // Interference for PhysReg.
271 InterferenceCache::Cursor Intf;
273 // Bundles where this candidate should be live.
274 BitVector LiveBundles;
275 SmallVector<unsigned, 8> ActiveBlocks;
277 void reset(InterferenceCache &Cache, unsigned Reg) {
280 Intf.setPhysReg(Cache, Reg);
282 ActiveBlocks.clear();
285 // Set B[i] = C for every live bundle where B[i] was NoCand.
286 unsigned getBundles(SmallVectorImpl<unsigned> &B, unsigned C) {
288 for (int i = LiveBundles.find_first(); i >= 0;
289 i = LiveBundles.find_next(i))
290 if (B[i] == NoCand) {
298 /// Candidate info for each PhysReg in AllocationOrder.
299 /// This vector never shrinks, but grows to the size of the largest register
301 SmallVector<GlobalSplitCandidate, 32> GlobalCand;
303 enum : unsigned { NoCand = ~0u };
305 /// Candidate map. Each edge bundle is assigned to a GlobalCand entry, or to
306 /// NoCand which indicates the stack interval.
307 SmallVector<unsigned, 32> BundleCand;
309 /// Callee-save register cost, calculated once per machine function.
310 BlockFrequency CSRCost;
312 /// Run or not the local reassignment heuristic. This information is
313 /// obtained from the TargetSubtargetInfo.
314 bool EnableLocalReassign;
316 /// Set of broken hints that may be reconciled later because of eviction.
317 SmallSetVector<LiveInterval *, 8> SetOfBrokenHints;
322 /// Return the pass name.
323 StringRef getPassName() const override { return "Greedy Register Allocator"; }
325 /// RAGreedy analysis usage.
326 void getAnalysisUsage(AnalysisUsage &AU) const override;
327 void releaseMemory() override;
328 Spiller &spiller() override { return *SpillerInstance; }
329 void enqueue(LiveInterval *LI) override;
330 LiveInterval *dequeue() override;
331 unsigned selectOrSplit(LiveInterval&, SmallVectorImpl<unsigned>&) override;
332 void aboutToRemoveInterval(LiveInterval &) override;
334 /// Perform register allocation.
335 bool runOnMachineFunction(MachineFunction &mf) override;
337 MachineFunctionProperties getRequiredProperties() const override {
338 return MachineFunctionProperties().set(
339 MachineFunctionProperties::Property::NoPHIs);
345 unsigned selectOrSplitImpl(LiveInterval &, SmallVectorImpl<unsigned> &,
346 SmallVirtRegSet &, unsigned = 0);
348 bool LRE_CanEraseVirtReg(unsigned) override;
349 void LRE_WillShrinkVirtReg(unsigned) override;
350 void LRE_DidCloneVirtReg(unsigned, unsigned) override;
351 void enqueue(PQueue &CurQueue, LiveInterval *LI);
352 LiveInterval *dequeue(PQueue &CurQueue);
354 BlockFrequency calcSpillCost();
355 bool addSplitConstraints(InterferenceCache::Cursor, BlockFrequency&);
356 void addThroughConstraints(InterferenceCache::Cursor, ArrayRef<unsigned>);
357 void growRegion(GlobalSplitCandidate &Cand);
358 BlockFrequency calcGlobalSplitCost(GlobalSplitCandidate&);
359 bool calcCompactRegion(GlobalSplitCandidate&);
360 void splitAroundRegion(LiveRangeEdit&, ArrayRef<unsigned>);
361 void calcGapWeights(unsigned, SmallVectorImpl<float>&);
362 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg);
363 bool shouldEvict(LiveInterval &A, bool, LiveInterval &B, bool);
364 bool canEvictInterference(LiveInterval&, unsigned, bool, EvictionCost&);
365 void evictInterference(LiveInterval&, unsigned,
366 SmallVectorImpl<unsigned>&);
367 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
368 SmallLISet &RecoloringCandidates,
369 const SmallVirtRegSet &FixedRegisters);
371 unsigned tryAssign(LiveInterval&, AllocationOrder&,
372 SmallVectorImpl<unsigned>&);
373 unsigned tryEvict(LiveInterval&, AllocationOrder&,
374 SmallVectorImpl<unsigned>&, unsigned = ~0u);
375 unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
376 SmallVectorImpl<unsigned>&);
377 /// Calculate cost of region splitting.
378 unsigned calculateRegionSplitCost(LiveInterval &VirtReg,
379 AllocationOrder &Order,
380 BlockFrequency &BestCost,
381 unsigned &NumCands, bool IgnoreCSR);
382 /// Perform region splitting.
383 unsigned doRegionSplit(LiveInterval &VirtReg, unsigned BestCand,
385 SmallVectorImpl<unsigned> &NewVRegs);
386 /// Check other options before using a callee-saved register for the first
388 unsigned tryAssignCSRFirstTime(LiveInterval &VirtReg, AllocationOrder &Order,
389 unsigned PhysReg, unsigned &CostPerUseLimit,
390 SmallVectorImpl<unsigned> &NewVRegs);
391 void initializeCSRCost();
392 unsigned tryBlockSplit(LiveInterval&, AllocationOrder&,
393 SmallVectorImpl<unsigned>&);
394 unsigned tryInstructionSplit(LiveInterval&, AllocationOrder&,
395 SmallVectorImpl<unsigned>&);
396 unsigned tryLocalSplit(LiveInterval&, AllocationOrder&,
397 SmallVectorImpl<unsigned>&);
398 unsigned trySplit(LiveInterval&, AllocationOrder&,
399 SmallVectorImpl<unsigned>&);
400 unsigned tryLastChanceRecoloring(LiveInterval &, AllocationOrder &,
401 SmallVectorImpl<unsigned> &,
402 SmallVirtRegSet &, unsigned);
403 bool tryRecoloringCandidates(PQueue &, SmallVectorImpl<unsigned> &,
404 SmallVirtRegSet &, unsigned);
405 void tryHintRecoloring(LiveInterval &);
406 void tryHintsRecoloring();
408 /// Model the information carried by one end of a copy.
410 /// The frequency of the copy.
412 /// The virtual register or physical register.
414 /// Its currently assigned register.
415 /// In case of a physical register Reg == PhysReg.
417 HintInfo(BlockFrequency Freq, unsigned Reg, unsigned PhysReg)
418 : Freq(Freq), Reg(Reg), PhysReg(PhysReg) {}
420 typedef SmallVector<HintInfo, 4> HintsInfo;
421 BlockFrequency getBrokenHintFreq(const HintsInfo &, unsigned);
422 void collectHintInfo(unsigned, HintsInfo &);
424 bool isUnusedCalleeSavedReg(unsigned PhysReg) const;
426 /// Compute and report the number of spills and reloads for a loop.
427 void reportNumberOfSplillsReloads(MachineLoop *L, unsigned &Reloads,
428 unsigned &FoldedReloads, unsigned &Spills,
429 unsigned &FoldedSpills);
431 /// Report the number of spills and reloads for each loop.
432 void reportNumberOfSplillsReloads() {
433 for (MachineLoop *L : *Loops) {
434 unsigned Reloads, FoldedReloads, Spills, FoldedSpills;
435 reportNumberOfSplillsReloads(L, Reloads, FoldedReloads, Spills,
440 } // end anonymous namespace
442 char RAGreedy::ID = 0;
443 char &llvm::RAGreedyID = RAGreedy::ID;
445 INITIALIZE_PASS_BEGIN(RAGreedy, "greedy",
446 "Greedy Register Allocator", false, false)
447 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
448 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
449 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
450 INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer)
451 INITIALIZE_PASS_DEPENDENCY(MachineScheduler)
452 INITIALIZE_PASS_DEPENDENCY(LiveStacks)
453 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
454 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
455 INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
456 INITIALIZE_PASS_DEPENDENCY(LiveRegMatrix)
457 INITIALIZE_PASS_DEPENDENCY(EdgeBundles)
458 INITIALIZE_PASS_DEPENDENCY(SpillPlacement)
459 INITIALIZE_PASS_DEPENDENCY(MachineOptimizationRemarkEmitterPass)
460 INITIALIZE_PASS_END(RAGreedy, "greedy",
461 "Greedy Register Allocator", false, false)
464 const char *const RAGreedy::StageName[] = {
475 // Hysteresis to use when comparing floats.
476 // This helps stabilize decisions based on float comparisons.
477 const float Hysteresis = (2007 / 2048.0f); // 0.97998046875
480 FunctionPass* llvm::createGreedyRegisterAllocator() {
481 return new RAGreedy();
484 RAGreedy::RAGreedy(): MachineFunctionPass(ID) {
487 void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
488 AU.setPreservesCFG();
489 AU.addRequired<MachineBlockFrequencyInfo>();
490 AU.addPreserved<MachineBlockFrequencyInfo>();
491 AU.addRequired<AAResultsWrapperPass>();
492 AU.addPreserved<AAResultsWrapperPass>();
493 AU.addRequired<LiveIntervals>();
494 AU.addPreserved<LiveIntervals>();
495 AU.addRequired<SlotIndexes>();
496 AU.addPreserved<SlotIndexes>();
497 AU.addRequired<LiveDebugVariables>();
498 AU.addPreserved<LiveDebugVariables>();
499 AU.addRequired<LiveStacks>();
500 AU.addPreserved<LiveStacks>();
501 AU.addRequired<MachineDominatorTree>();
502 AU.addPreserved<MachineDominatorTree>();
503 AU.addRequired<MachineLoopInfo>();
504 AU.addPreserved<MachineLoopInfo>();
505 AU.addRequired<VirtRegMap>();
506 AU.addPreserved<VirtRegMap>();
507 AU.addRequired<LiveRegMatrix>();
508 AU.addPreserved<LiveRegMatrix>();
509 AU.addRequired<EdgeBundles>();
510 AU.addRequired<SpillPlacement>();
511 AU.addRequired<MachineOptimizationRemarkEmitterPass>();
512 MachineFunctionPass::getAnalysisUsage(AU);
516 //===----------------------------------------------------------------------===//
517 // LiveRangeEdit delegate methods
518 //===----------------------------------------------------------------------===//
520 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) {
521 if (VRM->hasPhys(VirtReg)) {
522 LiveInterval &LI = LIS->getInterval(VirtReg);
523 Matrix->unassign(LI);
524 aboutToRemoveInterval(LI);
527 // Unassigned virtreg is probably in the priority queue.
528 // RegAllocBase will erase it after dequeueing.
532 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) {
533 if (!VRM->hasPhys(VirtReg))
536 // Register is assigned, put it back on the queue for reassignment.
537 LiveInterval &LI = LIS->getInterval(VirtReg);
538 Matrix->unassign(LI);
542 void RAGreedy::LRE_DidCloneVirtReg(unsigned New, unsigned Old) {
543 // Cloning a register we haven't even heard about yet? Just ignore it.
544 if (!ExtraRegInfo.inBounds(Old))
547 // LRE may clone a virtual register because dead code elimination causes it to
548 // be split into connected components. The new components are much smaller
549 // than the original, so they should get a new chance at being assigned.
550 // same stage as the parent.
551 ExtraRegInfo[Old].Stage = RS_Assign;
552 ExtraRegInfo.grow(New);
553 ExtraRegInfo[New] = ExtraRegInfo[Old];
556 void RAGreedy::releaseMemory() {
557 SpillerInstance.reset();
558 ExtraRegInfo.clear();
562 void RAGreedy::enqueue(LiveInterval *LI) { enqueue(Queue, LI); }
564 void RAGreedy::enqueue(PQueue &CurQueue, LiveInterval *LI) {
565 // Prioritize live ranges by size, assigning larger ranges first.
566 // The queue holds (size, reg) pairs.
567 const unsigned Size = LI->getSize();
568 const unsigned Reg = LI->reg;
569 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
570 "Can only enqueue virtual registers");
573 ExtraRegInfo.grow(Reg);
574 if (ExtraRegInfo[Reg].Stage == RS_New)
575 ExtraRegInfo[Reg].Stage = RS_Assign;
577 if (ExtraRegInfo[Reg].Stage == RS_Split) {
578 // Unsplit ranges that couldn't be allocated immediately are deferred until
579 // everything else has been allocated.
581 } else if (ExtraRegInfo[Reg].Stage == RS_Memory) {
582 // Memory operand should be considered last.
583 // Change the priority such that Memory operand are assigned in
584 // the reverse order that they came in.
585 // TODO: Make this a member variable and probably do something about hints.
586 static unsigned MemOp = 0;
589 // Giant live ranges fall back to the global assignment heuristic, which
590 // prevents excessive spilling in pathological cases.
591 bool ReverseLocal = TRI->reverseLocalAssignment();
592 const TargetRegisterClass &RC = *MRI->getRegClass(Reg);
593 bool ForceGlobal = !ReverseLocal &&
594 (Size / SlotIndex::InstrDist) > (2 * RC.getNumRegs());
596 if (ExtraRegInfo[Reg].Stage == RS_Assign && !ForceGlobal && !LI->empty() &&
597 LIS->intervalIsInOneMBB(*LI)) {
598 // Allocate original local ranges in linear instruction order. Since they
599 // are singly defined, this produces optimal coloring in the absence of
600 // global interference and other constraints.
602 Prio = LI->beginIndex().getInstrDistance(Indexes->getLastIndex());
604 // Allocating bottom up may allow many short LRGs to be assigned first
605 // to one of the cheap registers. This could be much faster for very
606 // large blocks on targets with many physical registers.
607 Prio = Indexes->getZeroIndex().getInstrDistance(LI->endIndex());
609 Prio |= RC.AllocationPriority << 24;
611 // Allocate global and split ranges in long->short order. Long ranges that
612 // don't fit should be spilled (or split) ASAP so they don't create
613 // interference. Mark a bit to prioritize global above local ranges.
614 Prio = (1u << 29) + Size;
616 // Mark a higher bit to prioritize global and local above RS_Split.
619 // Boost ranges that have a physical register hint.
620 if (VRM->hasKnownPreference(Reg))
623 // The virtual register number is a tie breaker for same-sized ranges.
624 // Give lower vreg numbers higher priority to assign them first.
625 CurQueue.push(std::make_pair(Prio, ~Reg));
628 LiveInterval *RAGreedy::dequeue() { return dequeue(Queue); }
630 LiveInterval *RAGreedy::dequeue(PQueue &CurQueue) {
631 if (CurQueue.empty())
633 LiveInterval *LI = &LIS->getInterval(~CurQueue.top().second);
639 //===----------------------------------------------------------------------===//
641 //===----------------------------------------------------------------------===//
643 /// tryAssign - Try to assign VirtReg to an available register.
644 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg,
645 AllocationOrder &Order,
646 SmallVectorImpl<unsigned> &NewVRegs) {
649 while ((PhysReg = Order.next()))
650 if (!Matrix->checkInterference(VirtReg, PhysReg))
652 if (!PhysReg || Order.isHint())
655 // PhysReg is available, but there may be a better choice.
657 // If we missed a simple hint, try to cheaply evict interference from the
658 // preferred register.
659 if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg))
660 if (Order.isHint(Hint)) {
661 DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n');
662 EvictionCost MaxCost;
663 MaxCost.setBrokenHints(1);
664 if (canEvictInterference(VirtReg, Hint, true, MaxCost)) {
665 evictInterference(VirtReg, Hint, NewVRegs);
668 // Record the missed hint, we may be able to recover
669 // at the end if the surrounding allocation changed.
670 SetOfBrokenHints.insert(&VirtReg);
673 // Try to evict interference from a cheaper alternative.
674 unsigned Cost = TRI->getCostPerUse(PhysReg);
676 // Most registers have 0 additional cost.
680 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost
682 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
683 return CheapReg ? CheapReg : PhysReg;
687 //===----------------------------------------------------------------------===//
688 // Interference eviction
689 //===----------------------------------------------------------------------===//
691 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) {
692 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
694 while ((PhysReg = Order.next())) {
695 if (PhysReg == PrevReg)
698 MCRegUnitIterator Units(PhysReg, TRI);
699 for (; Units.isValid(); ++Units) {
700 // Instantiate a "subquery", not to be confused with the Queries array.
701 LiveIntervalUnion::Query subQ(VirtReg, Matrix->getLiveUnions()[*Units]);
702 if (subQ.checkInterference())
705 // If no units have interference, break out with the current PhysReg.
706 if (!Units.isValid())
710 DEBUG(dbgs() << "can reassign: " << VirtReg << " from "
711 << PrintReg(PrevReg, TRI) << " to " << PrintReg(PhysReg, TRI)
716 /// shouldEvict - determine if A should evict the assigned live range B. The
717 /// eviction policy defined by this function together with the allocation order
718 /// defined by enqueue() decides which registers ultimately end up being split
721 /// Cascade numbers are used to prevent infinite loops if this function is a
724 /// @param A The live range to be assigned.
725 /// @param IsHint True when A is about to be assigned to its preferred
727 /// @param B The live range to be evicted.
728 /// @param BreaksHint True when B is already assigned to its preferred register.
729 bool RAGreedy::shouldEvict(LiveInterval &A, bool IsHint,
730 LiveInterval &B, bool BreaksHint) {
731 bool CanSplit = getStage(B) < RS_Spill;
733 // Be fairly aggressive about following hints as long as the evictee can be
735 if (CanSplit && IsHint && !BreaksHint)
738 if (A.weight > B.weight) {
739 DEBUG(dbgs() << "should evict: " << B << " w= " << B.weight << '\n');
745 /// canEvictInterference - Return true if all interferences between VirtReg and
746 /// PhysReg can be evicted.
748 /// @param VirtReg Live range that is about to be assigned.
749 /// @param PhysReg Desired register for assignment.
750 /// @param IsHint True when PhysReg is VirtReg's preferred register.
751 /// @param MaxCost Only look for cheaper candidates and update with new cost
752 /// when returning true.
753 /// @returns True when interference can be evicted cheaper than MaxCost.
754 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg,
755 bool IsHint, EvictionCost &MaxCost) {
756 // It is only possible to evict virtual register interference.
757 if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg)
760 bool IsLocal = LIS->intervalIsInOneMBB(VirtReg);
762 // Find VirtReg's cascade number. This will be unassigned if VirtReg was never
763 // involved in an eviction before. If a cascade number was assigned, deny
764 // evicting anything with the same or a newer cascade number. This prevents
765 // infinite eviction loops.
767 // This works out so a register without a cascade number is allowed to evict
768 // anything, and it can be evicted by anything.
769 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
771 Cascade = NextCascade;
774 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
775 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
776 // If there is 10 or more interferences, chances are one is heavier.
777 if (Q.collectInterferingVRegs(10) >= 10)
780 // Check if any interfering live range is heavier than MaxWeight.
781 for (unsigned i = Q.interferingVRegs().size(); i; --i) {
782 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
783 assert(TargetRegisterInfo::isVirtualRegister(Intf->reg) &&
784 "Only expecting virtual register interference from query");
785 // Never evict spill products. They cannot split or spill.
786 if (getStage(*Intf) == RS_Done)
788 // Once a live range becomes small enough, it is urgent that we find a
789 // register for it. This is indicated by an infinite spill weight. These
790 // urgent live ranges get to evict almost anything.
792 // Also allow urgent evictions of unspillable ranges from a strictly
793 // larger allocation order.
794 bool Urgent = !VirtReg.isSpillable() &&
795 (Intf->isSpillable() ||
796 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) <
797 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg)));
798 // Only evict older cascades or live ranges without a cascade.
799 unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade;
800 if (Cascade <= IntfCascade) {
803 // We permit breaking cascades for urgent evictions. It should be the
804 // last resort, though, so make it really expensive.
805 Cost.BrokenHints += 10;
807 // Would this break a satisfied hint?
808 bool BreaksHint = VRM->hasPreferredPhys(Intf->reg);
809 // Update eviction cost.
810 Cost.BrokenHints += BreaksHint;
811 Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight);
812 // Abort if this would be too expensive.
813 if (!(Cost < MaxCost))
817 // Apply the eviction policy for non-urgent evictions.
818 if (!shouldEvict(VirtReg, IsHint, *Intf, BreaksHint))
820 // If !MaxCost.isMax(), then we're just looking for a cheap register.
821 // Evicting another local live range in this case could lead to suboptimal
823 if (!MaxCost.isMax() && IsLocal && LIS->intervalIsInOneMBB(*Intf) &&
824 (!EnableLocalReassign || !canReassign(*Intf, PhysReg))) {
833 /// evictInterference - Evict any interferring registers that prevent VirtReg
834 /// from being assigned to Physreg. This assumes that canEvictInterference
836 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg,
837 SmallVectorImpl<unsigned> &NewVRegs) {
838 // Make sure that VirtReg has a cascade number, and assign that cascade
839 // number to every evicted register. These live ranges than then only be
840 // evicted by a newer cascade, preventing infinite loops.
841 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
843 Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;
845 DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI)
846 << " interference: Cascade " << Cascade << '\n');
848 // Collect all interfering virtregs first.
849 SmallVector<LiveInterval*, 8> Intfs;
850 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
851 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
852 // We usually have the interfering VRegs cached so collectInterferingVRegs()
853 // should be fast, we may need to recalculate if when different physregs
854 // overlap the same register unit so we had different SubRanges queried
856 Q.collectInterferingVRegs();
857 ArrayRef<LiveInterval*> IVR = Q.interferingVRegs();
858 Intfs.append(IVR.begin(), IVR.end());
861 // Evict them second. This will invalidate the queries.
862 for (unsigned i = 0, e = Intfs.size(); i != e; ++i) {
863 LiveInterval *Intf = Intfs[i];
864 // The same VirtReg may be present in multiple RegUnits. Skip duplicates.
865 if (!VRM->hasPhys(Intf->reg))
867 Matrix->unassign(*Intf);
868 assert((ExtraRegInfo[Intf->reg].Cascade < Cascade ||
869 VirtReg.isSpillable() < Intf->isSpillable()) &&
870 "Cannot decrease cascade number, illegal eviction");
871 ExtraRegInfo[Intf->reg].Cascade = Cascade;
873 NewVRegs.push_back(Intf->reg);
877 /// Returns true if the given \p PhysReg is a callee saved register and has not
878 /// been used for allocation yet.
879 bool RAGreedy::isUnusedCalleeSavedReg(unsigned PhysReg) const {
880 unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg);
884 return !Matrix->isPhysRegUsed(PhysReg);
887 /// tryEvict - Try to evict all interferences for a physreg.
888 /// @param VirtReg Currently unassigned virtual register.
889 /// @param Order Physregs to try.
890 /// @return Physreg to assign VirtReg, or 0.
891 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg,
892 AllocationOrder &Order,
893 SmallVectorImpl<unsigned> &NewVRegs,
894 unsigned CostPerUseLimit) {
895 NamedRegionTimer T("evict", "Evict", TimerGroupName, TimerGroupDescription,
896 TimePassesIsEnabled);
898 // Keep track of the cheapest interference seen so far.
899 EvictionCost BestCost;
901 unsigned BestPhys = 0;
902 unsigned OrderLimit = Order.getOrder().size();
904 // When we are just looking for a reduced cost per use, don't break any
905 // hints, and only evict smaller spill weights.
906 if (CostPerUseLimit < ~0u) {
907 BestCost.BrokenHints = 0;
908 BestCost.MaxWeight = VirtReg.weight;
910 // Check of any registers in RC are below CostPerUseLimit.
911 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg);
912 unsigned MinCost = RegClassInfo.getMinCost(RC);
913 if (MinCost >= CostPerUseLimit) {
914 DEBUG(dbgs() << TRI->getRegClassName(RC) << " minimum cost = " << MinCost
915 << ", no cheaper registers to be found.\n");
919 // It is normal for register classes to have a long tail of registers with
920 // the same cost. We don't need to look at them if they're too expensive.
921 if (TRI->getCostPerUse(Order.getOrder().back()) >= CostPerUseLimit) {
922 OrderLimit = RegClassInfo.getLastCostChange(RC);
923 DEBUG(dbgs() << "Only trying the first " << OrderLimit << " regs.\n");
928 while (unsigned PhysReg = Order.next(OrderLimit)) {
929 if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit)
931 // The first use of a callee-saved register in a function has cost 1.
932 // Don't start using a CSR when the CostPerUseLimit is low.
933 if (CostPerUseLimit == 1 && isUnusedCalleeSavedReg(PhysReg)) {
934 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR "
935 << PrintReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI)
940 if (!canEvictInterference(VirtReg, PhysReg, false, BestCost))
946 // Stop if the hint can be used.
954 evictInterference(VirtReg, BestPhys, NewVRegs);
959 //===----------------------------------------------------------------------===//
961 //===----------------------------------------------------------------------===//
963 /// addSplitConstraints - Fill out the SplitConstraints vector based on the
964 /// interference pattern in Physreg and its aliases. Add the constraints to
965 /// SpillPlacement and return the static cost of this split in Cost, assuming
966 /// that all preferences in SplitConstraints are met.
967 /// Return false if there are no bundles with positive bias.
968 bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf,
969 BlockFrequency &Cost) {
970 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
972 // Reset interference dependent info.
973 SplitConstraints.resize(UseBlocks.size());
974 BlockFrequency StaticCost = 0;
975 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
976 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
977 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
979 BC.Number = BI.MBB->getNumber();
980 Intf.moveToBlock(BC.Number);
981 BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
982 BC.Exit = BI.LiveOut ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
983 BC.ChangesValue = BI.FirstDef.isValid();
985 if (!Intf.hasInterference())
988 // Number of spill code instructions to insert.
991 // Interference for the live-in value.
993 if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number)) {
994 BC.Entry = SpillPlacement::MustSpill;
996 } else if (Intf.first() < BI.FirstInstr) {
997 BC.Entry = SpillPlacement::PrefSpill;
999 } else if (Intf.first() < BI.LastInstr) {
1004 // Interference for the live-out value.
1006 if (Intf.last() >= SA->getLastSplitPoint(BC.Number)) {
1007 BC.Exit = SpillPlacement::MustSpill;
1009 } else if (Intf.last() > BI.LastInstr) {
1010 BC.Exit = SpillPlacement::PrefSpill;
1012 } else if (Intf.last() > BI.FirstInstr) {
1017 // Accumulate the total frequency of inserted spill code.
1019 StaticCost += SpillPlacer->getBlockFrequency(BC.Number);
1023 // Add constraints for use-blocks. Note that these are the only constraints
1024 // that may add a positive bias, it is downhill from here.
1025 SpillPlacer->addConstraints(SplitConstraints);
1026 return SpillPlacer->scanActiveBundles();
1030 /// addThroughConstraints - Add constraints and links to SpillPlacer from the
1031 /// live-through blocks in Blocks.
1032 void RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf,
1033 ArrayRef<unsigned> Blocks) {
1034 const unsigned GroupSize = 8;
1035 SpillPlacement::BlockConstraint BCS[GroupSize];
1036 unsigned TBS[GroupSize];
1037 unsigned B = 0, T = 0;
1039 for (unsigned i = 0; i != Blocks.size(); ++i) {
1040 unsigned Number = Blocks[i];
1041 Intf.moveToBlock(Number);
1043 if (!Intf.hasInterference()) {
1044 assert(T < GroupSize && "Array overflow");
1046 if (++T == GroupSize) {
1047 SpillPlacer->addLinks(makeArrayRef(TBS, T));
1053 assert(B < GroupSize && "Array overflow");
1054 BCS[B].Number = Number;
1056 // Interference for the live-in value.
1057 if (Intf.first() <= Indexes->getMBBStartIdx(Number))
1058 BCS[B].Entry = SpillPlacement::MustSpill;
1060 BCS[B].Entry = SpillPlacement::PrefSpill;
1062 // Interference for the live-out value.
1063 if (Intf.last() >= SA->getLastSplitPoint(Number))
1064 BCS[B].Exit = SpillPlacement::MustSpill;
1066 BCS[B].Exit = SpillPlacement::PrefSpill;
1068 if (++B == GroupSize) {
1069 SpillPlacer->addConstraints(makeArrayRef(BCS, B));
1074 SpillPlacer->addConstraints(makeArrayRef(BCS, B));
1075 SpillPlacer->addLinks(makeArrayRef(TBS, T));
1078 void RAGreedy::growRegion(GlobalSplitCandidate &Cand) {
1079 // Keep track of through blocks that have not been added to SpillPlacer.
1080 BitVector Todo = SA->getThroughBlocks();
1081 SmallVectorImpl<unsigned> &ActiveBlocks = Cand.ActiveBlocks;
1082 unsigned AddedTo = 0;
1084 unsigned Visited = 0;
1088 ArrayRef<unsigned> NewBundles = SpillPlacer->getRecentPositive();
1089 // Find new through blocks in the periphery of PrefRegBundles.
1090 for (int i = 0, e = NewBundles.size(); i != e; ++i) {
1091 unsigned Bundle = NewBundles[i];
1092 // Look at all blocks connected to Bundle in the full graph.
1093 ArrayRef<unsigned> Blocks = Bundles->getBlocks(Bundle);
1094 for (ArrayRef<unsigned>::iterator I = Blocks.begin(), E = Blocks.end();
1096 unsigned Block = *I;
1097 if (!Todo.test(Block))
1100 // This is a new through block. Add it to SpillPlacer later.
1101 ActiveBlocks.push_back(Block);
1107 // Any new blocks to add?
1108 if (ActiveBlocks.size() == AddedTo)
1111 // Compute through constraints from the interference, or assume that all
1112 // through blocks prefer spilling when forming compact regions.
1113 auto NewBlocks = makeArrayRef(ActiveBlocks).slice(AddedTo);
1115 addThroughConstraints(Cand.Intf, NewBlocks);
1117 // Provide a strong negative bias on through blocks to prevent unwanted
1118 // liveness on loop backedges.
1119 SpillPlacer->addPrefSpill(NewBlocks, /* Strong= */ true);
1120 AddedTo = ActiveBlocks.size();
1122 // Perhaps iterating can enable more bundles?
1123 SpillPlacer->iterate();
1125 DEBUG(dbgs() << ", v=" << Visited);
1128 /// calcCompactRegion - Compute the set of edge bundles that should be live
1129 /// when splitting the current live range into compact regions. Compact
1130 /// regions can be computed without looking at interference. They are the
1131 /// regions formed by removing all the live-through blocks from the live range.
1133 /// Returns false if the current live range is already compact, or if the
1134 /// compact regions would form single block regions anyway.
1135 bool RAGreedy::calcCompactRegion(GlobalSplitCandidate &Cand) {
1136 // Without any through blocks, the live range is already compact.
1137 if (!SA->getNumThroughBlocks())
1140 // Compact regions don't correspond to any physreg.
1141 Cand.reset(IntfCache, 0);
1143 DEBUG(dbgs() << "Compact region bundles");
1145 // Use the spill placer to determine the live bundles. GrowRegion pretends
1146 // that all the through blocks have interference when PhysReg is unset.
1147 SpillPlacer->prepare(Cand.LiveBundles);
1149 // The static split cost will be zero since Cand.Intf reports no interference.
1150 BlockFrequency Cost;
1151 if (!addSplitConstraints(Cand.Intf, Cost)) {
1152 DEBUG(dbgs() << ", none.\n");
1157 SpillPlacer->finish();
1159 if (!Cand.LiveBundles.any()) {
1160 DEBUG(dbgs() << ", none.\n");
1165 for (int i = Cand.LiveBundles.find_first(); i>=0;
1166 i = Cand.LiveBundles.find_next(i))
1167 dbgs() << " EB#" << i;
1173 /// calcSpillCost - Compute how expensive it would be to split the live range in
1174 /// SA around all use blocks instead of forming bundle regions.
1175 BlockFrequency RAGreedy::calcSpillCost() {
1176 BlockFrequency Cost = 0;
1177 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1178 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1179 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1180 unsigned Number = BI.MBB->getNumber();
1181 // We normally only need one spill instruction - a load or a store.
1182 Cost += SpillPlacer->getBlockFrequency(Number);
1184 // Unless the value is redefined in the block.
1185 if (BI.LiveIn && BI.LiveOut && BI.FirstDef)
1186 Cost += SpillPlacer->getBlockFrequency(Number);
1191 /// calcGlobalSplitCost - Return the global split cost of following the split
1192 /// pattern in LiveBundles. This cost should be added to the local cost of the
1193 /// interference pattern in SplitConstraints.
1195 BlockFrequency RAGreedy::calcGlobalSplitCost(GlobalSplitCandidate &Cand) {
1196 BlockFrequency GlobalCost = 0;
1197 const BitVector &LiveBundles = Cand.LiveBundles;
1198 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1199 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1200 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1201 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
1202 bool RegIn = LiveBundles[Bundles->getBundle(BC.Number, 0)];
1203 bool RegOut = LiveBundles[Bundles->getBundle(BC.Number, 1)];
1207 Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg);
1209 Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg);
1211 GlobalCost += SpillPlacer->getBlockFrequency(BC.Number);
1214 for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) {
1215 unsigned Number = Cand.ActiveBlocks[i];
1216 bool RegIn = LiveBundles[Bundles->getBundle(Number, 0)];
1217 bool RegOut = LiveBundles[Bundles->getBundle(Number, 1)];
1218 if (!RegIn && !RegOut)
1220 if (RegIn && RegOut) {
1221 // We need double spill code if this block has interference.
1222 Cand.Intf.moveToBlock(Number);
1223 if (Cand.Intf.hasInterference()) {
1224 GlobalCost += SpillPlacer->getBlockFrequency(Number);
1225 GlobalCost += SpillPlacer->getBlockFrequency(Number);
1229 // live-in / stack-out or stack-in live-out.
1230 GlobalCost += SpillPlacer->getBlockFrequency(Number);
1235 /// splitAroundRegion - Split the current live range around the regions
1236 /// determined by BundleCand and GlobalCand.
1238 /// Before calling this function, GlobalCand and BundleCand must be initialized
1239 /// so each bundle is assigned to a valid candidate, or NoCand for the
1240 /// stack-bound bundles. The shared SA/SE SplitAnalysis and SplitEditor
1241 /// objects must be initialized for the current live range, and intervals
1242 /// created for the used candidates.
1244 /// @param LREdit The LiveRangeEdit object handling the current split.
1245 /// @param UsedCands List of used GlobalCand entries. Every BundleCand value
1246 /// must appear in this list.
1247 void RAGreedy::splitAroundRegion(LiveRangeEdit &LREdit,
1248 ArrayRef<unsigned> UsedCands) {
1249 // These are the intervals created for new global ranges. We may create more
1250 // intervals for local ranges.
1251 const unsigned NumGlobalIntvs = LREdit.size();
1252 DEBUG(dbgs() << "splitAroundRegion with " << NumGlobalIntvs << " globals.\n");
1253 assert(NumGlobalIntvs && "No global intervals configured");
1255 // Isolate even single instructions when dealing with a proper sub-class.
1256 // That guarantees register class inflation for the stack interval because it
1258 unsigned Reg = SA->getParent().reg;
1259 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1261 // First handle all the blocks with uses.
1262 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1263 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1264 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1265 unsigned Number = BI.MBB->getNumber();
1266 unsigned IntvIn = 0, IntvOut = 0;
1267 SlotIndex IntfIn, IntfOut;
1269 unsigned CandIn = BundleCand[Bundles->getBundle(Number, 0)];
1270 if (CandIn != NoCand) {
1271 GlobalSplitCandidate &Cand = GlobalCand[CandIn];
1272 IntvIn = Cand.IntvIdx;
1273 Cand.Intf.moveToBlock(Number);
1274 IntfIn = Cand.Intf.first();
1278 unsigned CandOut = BundleCand[Bundles->getBundle(Number, 1)];
1279 if (CandOut != NoCand) {
1280 GlobalSplitCandidate &Cand = GlobalCand[CandOut];
1281 IntvOut = Cand.IntvIdx;
1282 Cand.Intf.moveToBlock(Number);
1283 IntfOut = Cand.Intf.last();
1287 // Create separate intervals for isolated blocks with multiple uses.
1288 if (!IntvIn && !IntvOut) {
1289 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " isolated.\n");
1290 if (SA->shouldSplitSingleBlock(BI, SingleInstrs))
1291 SE->splitSingleBlock(BI);
1295 if (IntvIn && IntvOut)
1296 SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut);
1298 SE->splitRegInBlock(BI, IntvIn, IntfIn);
1300 SE->splitRegOutBlock(BI, IntvOut, IntfOut);
1303 // Handle live-through blocks. The relevant live-through blocks are stored in
1304 // the ActiveBlocks list with each candidate. We need to filter out
1306 BitVector Todo = SA->getThroughBlocks();
1307 for (unsigned c = 0; c != UsedCands.size(); ++c) {
1308 ArrayRef<unsigned> Blocks = GlobalCand[UsedCands[c]].ActiveBlocks;
1309 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
1310 unsigned Number = Blocks[i];
1311 if (!Todo.test(Number))
1315 unsigned IntvIn = 0, IntvOut = 0;
1316 SlotIndex IntfIn, IntfOut;
1318 unsigned CandIn = BundleCand[Bundles->getBundle(Number, 0)];
1319 if (CandIn != NoCand) {
1320 GlobalSplitCandidate &Cand = GlobalCand[CandIn];
1321 IntvIn = Cand.IntvIdx;
1322 Cand.Intf.moveToBlock(Number);
1323 IntfIn = Cand.Intf.first();
1326 unsigned CandOut = BundleCand[Bundles->getBundle(Number, 1)];
1327 if (CandOut != NoCand) {
1328 GlobalSplitCandidate &Cand = GlobalCand[CandOut];
1329 IntvOut = Cand.IntvIdx;
1330 Cand.Intf.moveToBlock(Number);
1331 IntfOut = Cand.Intf.last();
1333 if (!IntvIn && !IntvOut)
1335 SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut);
1341 SmallVector<unsigned, 8> IntvMap;
1342 SE->finish(&IntvMap);
1343 DebugVars->splitRegister(Reg, LREdit.regs(), *LIS);
1345 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1346 unsigned OrigBlocks = SA->getNumLiveBlocks();
1348 // Sort out the new intervals created by splitting. We get four kinds:
1349 // - Remainder intervals should not be split again.
1350 // - Candidate intervals can be assigned to Cand.PhysReg.
1351 // - Block-local splits are candidates for local splitting.
1352 // - DCE leftovers should go back on the queue.
1353 for (unsigned i = 0, e = LREdit.size(); i != e; ++i) {
1354 LiveInterval &Reg = LIS->getInterval(LREdit.get(i));
1356 // Ignore old intervals from DCE.
1357 if (getStage(Reg) != RS_New)
1360 // Remainder interval. Don't try splitting again, spill if it doesn't
1362 if (IntvMap[i] == 0) {
1363 setStage(Reg, RS_Spill);
1367 // Global intervals. Allow repeated splitting as long as the number of live
1368 // blocks is strictly decreasing.
1369 if (IntvMap[i] < NumGlobalIntvs) {
1370 if (SA->countLiveBlocks(&Reg) >= OrigBlocks) {
1371 DEBUG(dbgs() << "Main interval covers the same " << OrigBlocks
1372 << " blocks as original.\n");
1373 // Don't allow repeated splitting as a safe guard against looping.
1374 setStage(Reg, RS_Split2);
1379 // Other intervals are treated as new. This includes local intervals created
1380 // for blocks with multiple uses, and anything created by DCE.
1384 MF->verify(this, "After splitting live range around region");
1387 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1388 SmallVectorImpl<unsigned> &NewVRegs) {
1389 unsigned NumCands = 0;
1390 BlockFrequency BestCost;
1392 // Check if we can split this live range around a compact region.
1393 bool HasCompact = calcCompactRegion(GlobalCand.front());
1395 // Yes, keep GlobalCand[0] as the compact region candidate.
1397 BestCost = BlockFrequency::getMaxFrequency();
1399 // No benefit from the compact region, our fallback will be per-block
1400 // splitting. Make sure we find a solution that is cheaper than spilling.
1401 BestCost = calcSpillCost();
1402 DEBUG(dbgs() << "Cost of isolating all blocks = ";
1403 MBFI->printBlockFreq(dbgs(), BestCost) << '\n');
1407 calculateRegionSplitCost(VirtReg, Order, BestCost, NumCands,
1408 false/*IgnoreCSR*/);
1410 // No solutions found, fall back to single block splitting.
1411 if (!HasCompact && BestCand == NoCand)
1414 return doRegionSplit(VirtReg, BestCand, HasCompact, NewVRegs);
1417 unsigned RAGreedy::calculateRegionSplitCost(LiveInterval &VirtReg,
1418 AllocationOrder &Order,
1419 BlockFrequency &BestCost,
1422 unsigned BestCand = NoCand;
1424 while (unsigned PhysReg = Order.next()) {
1425 if (IgnoreCSR && isUnusedCalleeSavedReg(PhysReg))
1428 // Discard bad candidates before we run out of interference cache cursors.
1429 // This will only affect register classes with a lot of registers (>32).
1430 if (NumCands == IntfCache.getMaxCursors()) {
1431 unsigned WorstCount = ~0u;
1433 for (unsigned i = 0; i != NumCands; ++i) {
1434 if (i == BestCand || !GlobalCand[i].PhysReg)
1436 unsigned Count = GlobalCand[i].LiveBundles.count();
1437 if (Count < WorstCount) {
1443 GlobalCand[Worst] = GlobalCand[NumCands];
1444 if (BestCand == NumCands)
1448 if (GlobalCand.size() <= NumCands)
1449 GlobalCand.resize(NumCands+1);
1450 GlobalSplitCandidate &Cand = GlobalCand[NumCands];
1451 Cand.reset(IntfCache, PhysReg);
1453 SpillPlacer->prepare(Cand.LiveBundles);
1454 BlockFrequency Cost;
1455 if (!addSplitConstraints(Cand.Intf, Cost)) {
1456 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n");
1459 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = ";
1460 MBFI->printBlockFreq(dbgs(), Cost));
1461 if (Cost >= BestCost) {
1463 if (BestCand == NoCand)
1464 dbgs() << " worse than no bundles\n";
1466 dbgs() << " worse than "
1467 << PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n';
1473 SpillPlacer->finish();
1475 // No live bundles, defer to splitSingleBlocks().
1476 if (!Cand.LiveBundles.any()) {
1477 DEBUG(dbgs() << " no bundles.\n");
1481 Cost += calcGlobalSplitCost(Cand);
1483 dbgs() << ", total = "; MBFI->printBlockFreq(dbgs(), Cost)
1485 for (int i = Cand.LiveBundles.find_first(); i>=0;
1486 i = Cand.LiveBundles.find_next(i))
1487 dbgs() << " EB#" << i;
1490 if (Cost < BestCost) {
1491 BestCand = NumCands;
1499 unsigned RAGreedy::doRegionSplit(LiveInterval &VirtReg, unsigned BestCand,
1501 SmallVectorImpl<unsigned> &NewVRegs) {
1502 SmallVector<unsigned, 8> UsedCands;
1503 // Prepare split editor.
1504 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
1505 SE->reset(LREdit, SplitSpillMode);
1507 // Assign all edge bundles to the preferred candidate, or NoCand.
1508 BundleCand.assign(Bundles->getNumBundles(), NoCand);
1510 // Assign bundles for the best candidate region.
1511 if (BestCand != NoCand) {
1512 GlobalSplitCandidate &Cand = GlobalCand[BestCand];
1513 if (unsigned B = Cand.getBundles(BundleCand, BestCand)) {
1514 UsedCands.push_back(BestCand);
1515 Cand.IntvIdx = SE->openIntv();
1516 DEBUG(dbgs() << "Split for " << PrintReg(Cand.PhysReg, TRI) << " in "
1517 << B << " bundles, intv " << Cand.IntvIdx << ".\n");
1522 // Assign bundles for the compact region.
1524 GlobalSplitCandidate &Cand = GlobalCand.front();
1525 assert(!Cand.PhysReg && "Compact region has no physreg");
1526 if (unsigned B = Cand.getBundles(BundleCand, 0)) {
1527 UsedCands.push_back(0);
1528 Cand.IntvIdx = SE->openIntv();
1529 DEBUG(dbgs() << "Split for compact region in " << B << " bundles, intv "
1530 << Cand.IntvIdx << ".\n");
1535 splitAroundRegion(LREdit, UsedCands);
1540 //===----------------------------------------------------------------------===//
1541 // Per-Block Splitting
1542 //===----------------------------------------------------------------------===//
1544 /// tryBlockSplit - Split a global live range around every block with uses. This
1545 /// creates a lot of local live ranges, that will be split by tryLocalSplit if
1546 /// they don't allocate.
1547 unsigned RAGreedy::tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1548 SmallVectorImpl<unsigned> &NewVRegs) {
1549 assert(&SA->getParent() == &VirtReg && "Live range wasn't analyzed");
1550 unsigned Reg = VirtReg.reg;
1551 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1552 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
1553 SE->reset(LREdit, SplitSpillMode);
1554 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1555 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1556 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1557 if (SA->shouldSplitSingleBlock(BI, SingleInstrs))
1558 SE->splitSingleBlock(BI);
1560 // No blocks were split.
1564 // We did split for some blocks.
1565 SmallVector<unsigned, 8> IntvMap;
1566 SE->finish(&IntvMap);
1568 // Tell LiveDebugVariables about the new ranges.
1569 DebugVars->splitRegister(Reg, LREdit.regs(), *LIS);
1571 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1573 // Sort out the new intervals created by splitting. The remainder interval
1574 // goes straight to spilling, the new local ranges get to stay RS_New.
1575 for (unsigned i = 0, e = LREdit.size(); i != e; ++i) {
1576 LiveInterval &LI = LIS->getInterval(LREdit.get(i));
1577 if (getStage(LI) == RS_New && IntvMap[i] == 0)
1578 setStage(LI, RS_Spill);
1582 MF->verify(this, "After splitting live range around basic blocks");
1587 //===----------------------------------------------------------------------===//
1588 // Per-Instruction Splitting
1589 //===----------------------------------------------------------------------===//
1591 /// Get the number of allocatable registers that match the constraints of \p Reg
1592 /// on \p MI and that are also in \p SuperRC.
1593 static unsigned getNumAllocatableRegsForConstraints(
1594 const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC,
1595 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1596 const RegisterClassInfo &RCI) {
1597 assert(SuperRC && "Invalid register class");
1599 const TargetRegisterClass *ConstrainedRC =
1600 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI,
1601 /* ExploreBundle */ true);
1604 return RCI.getNumAllocatableRegs(ConstrainedRC);
1607 /// tryInstructionSplit - Split a live range around individual instructions.
1608 /// This is normally not worthwhile since the spiller is doing essentially the
1609 /// same thing. However, when the live range is in a constrained register
1610 /// class, it may help to insert copies such that parts of the live range can
1611 /// be moved to a larger register class.
1613 /// This is similar to spilling to a larger register class.
1615 RAGreedy::tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1616 SmallVectorImpl<unsigned> &NewVRegs) {
1617 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg);
1618 // There is no point to this if there are no larger sub-classes.
1619 if (!RegClassInfo.isProperSubClass(CurRC))
1622 // Always enable split spill mode, since we're effectively spilling to a
1624 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
1625 SE->reset(LREdit, SplitEditor::SM_Size);
1627 ArrayRef<SlotIndex> Uses = SA->getUseSlots();
1628 if (Uses.size() <= 1)
1631 DEBUG(dbgs() << "Split around " << Uses.size() << " individual instrs.\n");
1633 const TargetRegisterClass *SuperRC =
1634 TRI->getLargestLegalSuperClass(CurRC, *MF);
1635 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC);
1636 // Split around every non-copy instruction if this split will relax
1637 // the constraints on the virtual register.
1638 // Otherwise, splitting just inserts uncoalescable copies that do not help
1640 for (unsigned i = 0; i != Uses.size(); ++i) {
1641 if (const MachineInstr *MI = Indexes->getInstructionFromIndex(Uses[i]))
1642 if (MI->isFullCopy() ||
1643 SuperRCNumAllocatableRegs ==
1644 getNumAllocatableRegsForConstraints(MI, VirtReg.reg, SuperRC, TII,
1646 DEBUG(dbgs() << " skip:\t" << Uses[i] << '\t' << *MI);
1650 SlotIndex SegStart = SE->enterIntvBefore(Uses[i]);
1651 SlotIndex SegStop = SE->leaveIntvAfter(Uses[i]);
1652 SE->useIntv(SegStart, SegStop);
1655 if (LREdit.empty()) {
1656 DEBUG(dbgs() << "All uses were copies.\n");
1660 SmallVector<unsigned, 8> IntvMap;
1661 SE->finish(&IntvMap);
1662 DebugVars->splitRegister(VirtReg.reg, LREdit.regs(), *LIS);
1663 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1665 // Assign all new registers to RS_Spill. This was the last chance.
1666 setStage(LREdit.begin(), LREdit.end(), RS_Spill);
1671 //===----------------------------------------------------------------------===//
1673 //===----------------------------------------------------------------------===//
1676 /// calcGapWeights - Compute the maximum spill weight that needs to be evicted
1677 /// in order to use PhysReg between two entries in SA->UseSlots.
1679 /// GapWeight[i] represents the gap between UseSlots[i] and UseSlots[i+1].
1681 void RAGreedy::calcGapWeights(unsigned PhysReg,
1682 SmallVectorImpl<float> &GapWeight) {
1683 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
1684 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
1685 ArrayRef<SlotIndex> Uses = SA->getUseSlots();
1686 const unsigned NumGaps = Uses.size()-1;
1688 // Start and end points for the interference check.
1689 SlotIndex StartIdx =
1690 BI.LiveIn ? BI.FirstInstr.getBaseIndex() : BI.FirstInstr;
1692 BI.LiveOut ? BI.LastInstr.getBoundaryIndex() : BI.LastInstr;
1694 GapWeight.assign(NumGaps, 0.0f);
1696 // Add interference from each overlapping register.
1697 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
1698 if (!Matrix->query(const_cast<LiveInterval&>(SA->getParent()), *Units)
1699 .checkInterference())
1702 // We know that VirtReg is a continuous interval from FirstInstr to
1703 // LastInstr, so we don't need InterferenceQuery.
1705 // Interference that overlaps an instruction is counted in both gaps
1706 // surrounding the instruction. The exception is interference before
1707 // StartIdx and after StopIdx.
1709 LiveIntervalUnion::SegmentIter IntI =
1710 Matrix->getLiveUnions()[*Units] .find(StartIdx);
1711 for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) {
1712 // Skip the gaps before IntI.
1713 while (Uses[Gap+1].getBoundaryIndex() < IntI.start())
1714 if (++Gap == NumGaps)
1719 // Update the gaps covered by IntI.
1720 const float weight = IntI.value()->weight;
1721 for (; Gap != NumGaps; ++Gap) {
1722 GapWeight[Gap] = std::max(GapWeight[Gap], weight);
1723 if (Uses[Gap+1].getBaseIndex() >= IntI.stop())
1731 // Add fixed interference.
1732 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
1733 const LiveRange &LR = LIS->getRegUnit(*Units);
1734 LiveRange::const_iterator I = LR.find(StartIdx);
1735 LiveRange::const_iterator E = LR.end();
1737 // Same loop as above. Mark any overlapped gaps as HUGE_VALF.
1738 for (unsigned Gap = 0; I != E && I->start < StopIdx; ++I) {
1739 while (Uses[Gap+1].getBoundaryIndex() < I->start)
1740 if (++Gap == NumGaps)
1745 for (; Gap != NumGaps; ++Gap) {
1746 GapWeight[Gap] = llvm::huge_valf;
1747 if (Uses[Gap+1].getBaseIndex() >= I->end)
1756 /// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
1759 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1760 SmallVectorImpl<unsigned> &NewVRegs) {
1761 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
1762 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
1764 // Note that it is possible to have an interval that is live-in or live-out
1765 // while only covering a single block - A phi-def can use undef values from
1766 // predecessors, and the block could be a single-block loop.
1767 // We don't bother doing anything clever about such a case, we simply assume
1768 // that the interval is continuous from FirstInstr to LastInstr. We should
1769 // make sure that we don't do anything illegal to such an interval, though.
1771 ArrayRef<SlotIndex> Uses = SA->getUseSlots();
1772 if (Uses.size() <= 2)
1774 const unsigned NumGaps = Uses.size()-1;
1777 dbgs() << "tryLocalSplit: ";
1778 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
1779 dbgs() << ' ' << Uses[i];
1783 // If VirtReg is live across any register mask operands, compute a list of
1784 // gaps with register masks.
1785 SmallVector<unsigned, 8> RegMaskGaps;
1786 if (Matrix->checkRegMaskInterference(VirtReg)) {
1787 // Get regmask slots for the whole block.
1788 ArrayRef<SlotIndex> RMS = LIS->getRegMaskSlotsInBlock(BI.MBB->getNumber());
1789 DEBUG(dbgs() << RMS.size() << " regmasks in block:");
1790 // Constrain to VirtReg's live range.
1791 unsigned ri = std::lower_bound(RMS.begin(), RMS.end(),
1792 Uses.front().getRegSlot()) - RMS.begin();
1793 unsigned re = RMS.size();
1794 for (unsigned i = 0; i != NumGaps && ri != re; ++i) {
1795 // Look for Uses[i] <= RMS <= Uses[i+1].
1796 assert(!SlotIndex::isEarlierInstr(RMS[ri], Uses[i]));
1797 if (SlotIndex::isEarlierInstr(Uses[i+1], RMS[ri]))
1799 // Skip a regmask on the same instruction as the last use. It doesn't
1800 // overlap the live range.
1801 if (SlotIndex::isSameInstr(Uses[i+1], RMS[ri]) && i+1 == NumGaps)
1803 DEBUG(dbgs() << ' ' << RMS[ri] << ':' << Uses[i] << '-' << Uses[i+1]);
1804 RegMaskGaps.push_back(i);
1805 // Advance ri to the next gap. A regmask on one of the uses counts in
1807 while (ri != re && SlotIndex::isEarlierInstr(RMS[ri], Uses[i+1]))
1810 DEBUG(dbgs() << '\n');
1813 // Since we allow local split results to be split again, there is a risk of
1814 // creating infinite loops. It is tempting to require that the new live
1815 // ranges have less instructions than the original. That would guarantee
1816 // convergence, but it is too strict. A live range with 3 instructions can be
1817 // split 2+3 (including the COPY), and we want to allow that.
1819 // Instead we use these rules:
1821 // 1. Allow any split for ranges with getStage() < RS_Split2. (Except for the
1822 // noop split, of course).
1823 // 2. Require progress be made for ranges with getStage() == RS_Split2. All
1824 // the new ranges must have fewer instructions than before the split.
1825 // 3. New ranges with the same number of instructions are marked RS_Split2,
1826 // smaller ranges are marked RS_New.
1828 // These rules allow a 3 -> 2+3 split once, which we need. They also prevent
1829 // excessive splitting and infinite loops.
1831 bool ProgressRequired = getStage(VirtReg) >= RS_Split2;
1833 // Best split candidate.
1834 unsigned BestBefore = NumGaps;
1835 unsigned BestAfter = 0;
1838 const float blockFreq =
1839 SpillPlacer->getBlockFrequency(BI.MBB->getNumber()).getFrequency() *
1840 (1.0f / MBFI->getEntryFreq());
1841 SmallVector<float, 8> GapWeight;
1844 while (unsigned PhysReg = Order.next()) {
1845 // Keep track of the largest spill weight that would need to be evicted in
1846 // order to make use of PhysReg between UseSlots[i] and UseSlots[i+1].
1847 calcGapWeights(PhysReg, GapWeight);
1849 // Remove any gaps with regmask clobbers.
1850 if (Matrix->checkRegMaskInterference(VirtReg, PhysReg))
1851 for (unsigned i = 0, e = RegMaskGaps.size(); i != e; ++i)
1852 GapWeight[RegMaskGaps[i]] = llvm::huge_valf;
1854 // Try to find the best sequence of gaps to close.
1855 // The new spill weight must be larger than any gap interference.
1857 // We will split before Uses[SplitBefore] and after Uses[SplitAfter].
1858 unsigned SplitBefore = 0, SplitAfter = 1;
1860 // MaxGap should always be max(GapWeight[SplitBefore..SplitAfter-1]).
1861 // It is the spill weight that needs to be evicted.
1862 float MaxGap = GapWeight[0];
1865 // Live before/after split?
1866 const bool LiveBefore = SplitBefore != 0 || BI.LiveIn;
1867 const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut;
1869 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' '
1870 << Uses[SplitBefore] << '-' << Uses[SplitAfter]
1871 << " i=" << MaxGap);
1873 // Stop before the interval gets so big we wouldn't be making progress.
1874 if (!LiveBefore && !LiveAfter) {
1875 DEBUG(dbgs() << " all\n");
1878 // Should the interval be extended or shrunk?
1881 // How many gaps would the new range have?
1882 unsigned NewGaps = LiveBefore + SplitAfter - SplitBefore + LiveAfter;
1884 // Legally, without causing looping?
1885 bool Legal = !ProgressRequired || NewGaps < NumGaps;
1887 if (Legal && MaxGap < llvm::huge_valf) {
1888 // Estimate the new spill weight. Each instruction reads or writes the
1889 // register. Conservatively assume there are no read-modify-write
1892 // Try to guess the size of the new interval.
1893 const float EstWeight = normalizeSpillWeight(
1894 blockFreq * (NewGaps + 1),
1895 Uses[SplitBefore].distance(Uses[SplitAfter]) +
1896 (LiveBefore + LiveAfter) * SlotIndex::InstrDist,
1898 // Would this split be possible to allocate?
1899 // Never allocate all gaps, we wouldn't be making progress.
1900 DEBUG(dbgs() << " w=" << EstWeight);
1901 if (EstWeight * Hysteresis >= MaxGap) {
1903 float Diff = EstWeight - MaxGap;
1904 if (Diff > BestDiff) {
1905 DEBUG(dbgs() << " (best)");
1906 BestDiff = Hysteresis * Diff;
1907 BestBefore = SplitBefore;
1908 BestAfter = SplitAfter;
1915 if (++SplitBefore < SplitAfter) {
1916 DEBUG(dbgs() << " shrink\n");
1917 // Recompute the max when necessary.
1918 if (GapWeight[SplitBefore - 1] >= MaxGap) {
1919 MaxGap = GapWeight[SplitBefore];
1920 for (unsigned i = SplitBefore + 1; i != SplitAfter; ++i)
1921 MaxGap = std::max(MaxGap, GapWeight[i]);
1928 // Try to extend the interval.
1929 if (SplitAfter >= NumGaps) {
1930 DEBUG(dbgs() << " end\n");
1934 DEBUG(dbgs() << " extend\n");
1935 MaxGap = std::max(MaxGap, GapWeight[SplitAfter++]);
1939 // Didn't find any candidates?
1940 if (BestBefore == NumGaps)
1943 DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore]
1944 << '-' << Uses[BestAfter] << ", " << BestDiff
1945 << ", " << (BestAfter - BestBefore + 1) << " instrs\n");
1947 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
1951 SlotIndex SegStart = SE->enterIntvBefore(Uses[BestBefore]);
1952 SlotIndex SegStop = SE->leaveIntvAfter(Uses[BestAfter]);
1953 SE->useIntv(SegStart, SegStop);
1954 SmallVector<unsigned, 8> IntvMap;
1955 SE->finish(&IntvMap);
1956 DebugVars->splitRegister(VirtReg.reg, LREdit.regs(), *LIS);
1958 // If the new range has the same number of instructions as before, mark it as
1959 // RS_Split2 so the next split will be forced to make progress. Otherwise,
1960 // leave the new intervals as RS_New so they can compete.
1961 bool LiveBefore = BestBefore != 0 || BI.LiveIn;
1962 bool LiveAfter = BestAfter != NumGaps || BI.LiveOut;
1963 unsigned NewGaps = LiveBefore + BestAfter - BestBefore + LiveAfter;
1964 if (NewGaps >= NumGaps) {
1965 DEBUG(dbgs() << "Tagging non-progress ranges: ");
1966 assert(!ProgressRequired && "Didn't make progress when it was required.");
1967 for (unsigned i = 0, e = IntvMap.size(); i != e; ++i)
1968 if (IntvMap[i] == 1) {
1969 setStage(LIS->getInterval(LREdit.get(i)), RS_Split2);
1970 DEBUG(dbgs() << PrintReg(LREdit.get(i)));
1972 DEBUG(dbgs() << '\n');
1979 //===----------------------------------------------------------------------===//
1980 // Live Range Splitting
1981 //===----------------------------------------------------------------------===//
1983 /// trySplit - Try to split VirtReg or one of its interferences, making it
1985 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
1986 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
1987 SmallVectorImpl<unsigned>&NewVRegs) {
1988 // Ranges must be Split2 or less.
1989 if (getStage(VirtReg) >= RS_Spill)
1992 // Local intervals are handled separately.
1993 if (LIS->intervalIsInOneMBB(VirtReg)) {
1994 NamedRegionTimer T("local_split", "Local Splitting", TimerGroupName,
1995 TimerGroupDescription, TimePassesIsEnabled);
1996 SA->analyze(&VirtReg);
1997 unsigned PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs);
1998 if (PhysReg || !NewVRegs.empty())
2000 return tryInstructionSplit(VirtReg, Order, NewVRegs);
2003 NamedRegionTimer T("global_split", "Global Splitting", TimerGroupName,
2004 TimerGroupDescription, TimePassesIsEnabled);
2006 SA->analyze(&VirtReg);
2008 // FIXME: SplitAnalysis may repair broken live ranges coming from the
2009 // coalescer. That may cause the range to become allocatable which means that
2010 // tryRegionSplit won't be making progress. This check should be replaced with
2011 // an assertion when the coalescer is fixed.
2012 if (SA->didRepairRange()) {
2013 // VirtReg has changed, so all cached queries are invalid.
2014 Matrix->invalidateVirtRegs();
2015 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
2019 // First try to split around a region spanning multiple blocks. RS_Split2
2020 // ranges already made dubious progress with region splitting, so they go
2021 // straight to single block splitting.
2022 if (getStage(VirtReg) < RS_Split2) {
2023 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
2024 if (PhysReg || !NewVRegs.empty())
2028 // Then isolate blocks.
2029 return tryBlockSplit(VirtReg, Order, NewVRegs);
2032 //===----------------------------------------------------------------------===//
2033 // Last Chance Recoloring
2034 //===----------------------------------------------------------------------===//
2036 /// mayRecolorAllInterferences - Check if the virtual registers that
2037 /// interfere with \p VirtReg on \p PhysReg (or one of its aliases) may be
2038 /// recolored to free \p PhysReg.
2039 /// When true is returned, \p RecoloringCandidates has been augmented with all
2040 /// the live intervals that need to be recolored in order to free \p PhysReg
2042 /// \p FixedRegisters contains all the virtual registers that cannot be
2045 RAGreedy::mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
2046 SmallLISet &RecoloringCandidates,
2047 const SmallVirtRegSet &FixedRegisters) {
2048 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg);
2050 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
2051 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
2052 // If there is LastChanceRecoloringMaxInterference or more interferences,
2053 // chances are one would not be recolorable.
2054 if (Q.collectInterferingVRegs(LastChanceRecoloringMaxInterference) >=
2055 LastChanceRecoloringMaxInterference && !ExhaustiveSearch) {
2056 DEBUG(dbgs() << "Early abort: too many interferences.\n");
2057 CutOffInfo |= CO_Interf;
2060 for (unsigned i = Q.interferingVRegs().size(); i; --i) {
2061 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
2062 // If Intf is done and sit on the same register class as VirtReg,
2063 // it would not be recolorable as it is in the same state as VirtReg.
2064 if ((getStage(*Intf) == RS_Done &&
2065 MRI->getRegClass(Intf->reg) == CurRC) ||
2066 FixedRegisters.count(Intf->reg)) {
2067 DEBUG(dbgs() << "Early abort: the inteference is not recolorable.\n");
2070 RecoloringCandidates.insert(Intf);
2076 /// tryLastChanceRecoloring - Try to assign a color to \p VirtReg by recoloring
2077 /// its interferences.
2078 /// Last chance recoloring chooses a color for \p VirtReg and recolors every
2079 /// virtual register that was using it. The recoloring process may recursively
2080 /// use the last chance recoloring. Therefore, when a virtual register has been
2081 /// assigned a color by this mechanism, it is marked as Fixed, i.e., it cannot
2082 /// be last-chance-recolored again during this recoloring "session".
2085 /// vA can use {R1, R2 }
2086 /// vB can use { R2, R3}
2087 /// vC can use {R1 }
2088 /// Where vA, vB, and vC cannot be split anymore (they are reloads for
2089 /// instance) and they all interfere.
2091 /// vA is assigned R1
2092 /// vB is assigned R2
2093 /// vC tries to evict vA but vA is already done.
2094 /// Regular register allocation fails.
2096 /// Last chance recoloring kicks in:
2097 /// vC does as if vA was evicted => vC uses R1.
2098 /// vC is marked as fixed.
2099 /// vA needs to find a color.
2100 /// None are available.
2101 /// vA cannot evict vC: vC is a fixed virtual register now.
2102 /// vA does as if vB was evicted => vA uses R2.
2103 /// vB needs to find a color.
2104 /// R3 is available.
2105 /// Recoloring => vC = R1, vA = R2, vB = R3
2107 /// \p Order defines the preferred allocation order for \p VirtReg.
2108 /// \p NewRegs will contain any new virtual register that have been created
2109 /// (split, spill) during the process and that must be assigned.
2110 /// \p FixedRegisters contains all the virtual registers that cannot be
2112 /// \p Depth gives the current depth of the last chance recoloring.
2113 /// \return a physical register that can be used for VirtReg or ~0u if none
2115 unsigned RAGreedy::tryLastChanceRecoloring(LiveInterval &VirtReg,
2116 AllocationOrder &Order,
2117 SmallVectorImpl<unsigned> &NewVRegs,
2118 SmallVirtRegSet &FixedRegisters,
2120 DEBUG(dbgs() << "Try last chance recoloring for " << VirtReg << '\n');
2121 // Ranges must be Done.
2122 assert((getStage(VirtReg) >= RS_Done || !VirtReg.isSpillable()) &&
2123 "Last chance recoloring should really be last chance");
2124 // Set the max depth to LastChanceRecoloringMaxDepth.
2125 // We may want to reconsider that if we end up with a too large search space
2126 // for target with hundreds of registers.
2127 // Indeed, in that case we may want to cut the search space earlier.
2128 if (Depth >= LastChanceRecoloringMaxDepth && !ExhaustiveSearch) {
2129 DEBUG(dbgs() << "Abort because max depth has been reached.\n");
2130 CutOffInfo |= CO_Depth;
2134 // Set of Live intervals that will need to be recolored.
2135 SmallLISet RecoloringCandidates;
2136 // Record the original mapping virtual register to physical register in case
2137 // the recoloring fails.
2138 DenseMap<unsigned, unsigned> VirtRegToPhysReg;
2139 // Mark VirtReg as fixed, i.e., it will not be recolored pass this point in
2140 // this recoloring "session".
2141 FixedRegisters.insert(VirtReg.reg);
2142 SmallVector<unsigned, 4> CurrentNewVRegs;
2145 while (unsigned PhysReg = Order.next()) {
2146 DEBUG(dbgs() << "Try to assign: " << VirtReg << " to "
2147 << PrintReg(PhysReg, TRI) << '\n');
2148 RecoloringCandidates.clear();
2149 VirtRegToPhysReg.clear();
2150 CurrentNewVRegs.clear();
2152 // It is only possible to recolor virtual register interference.
2153 if (Matrix->checkInterference(VirtReg, PhysReg) >
2154 LiveRegMatrix::IK_VirtReg) {
2155 DEBUG(dbgs() << "Some inteferences are not with virtual registers.\n");
2160 // Early give up on this PhysReg if it is obvious we cannot recolor all
2161 // the interferences.
2162 if (!mayRecolorAllInterferences(PhysReg, VirtReg, RecoloringCandidates,
2164 DEBUG(dbgs() << "Some inteferences cannot be recolored.\n");
2168 // RecoloringCandidates contains all the virtual registers that interfer
2169 // with VirtReg on PhysReg (or one of its aliases).
2170 // Enqueue them for recoloring and perform the actual recoloring.
2171 PQueue RecoloringQueue;
2172 for (SmallLISet::iterator It = RecoloringCandidates.begin(),
2173 EndIt = RecoloringCandidates.end();
2174 It != EndIt; ++It) {
2175 unsigned ItVirtReg = (*It)->reg;
2176 enqueue(RecoloringQueue, *It);
2177 assert(VRM->hasPhys(ItVirtReg) &&
2178 "Interferences are supposed to be with allocated vairables");
2180 // Record the current allocation.
2181 VirtRegToPhysReg[ItVirtReg] = VRM->getPhys(ItVirtReg);
2182 // unset the related struct.
2183 Matrix->unassign(**It);
2186 // Do as if VirtReg was assigned to PhysReg so that the underlying
2187 // recoloring has the right information about the interferes and
2188 // available colors.
2189 Matrix->assign(VirtReg, PhysReg);
2191 // Save the current recoloring state.
2192 // If we cannot recolor all the interferences, we will have to start again
2193 // at this point for the next physical register.
2194 SmallVirtRegSet SaveFixedRegisters(FixedRegisters);
2195 if (tryRecoloringCandidates(RecoloringQueue, CurrentNewVRegs,
2196 FixedRegisters, Depth)) {
2197 // Push the queued vregs into the main queue.
2198 for (unsigned NewVReg : CurrentNewVRegs)
2199 NewVRegs.push_back(NewVReg);
2200 // Do not mess up with the global assignment process.
2201 // I.e., VirtReg must be unassigned.
2202 Matrix->unassign(VirtReg);
2206 DEBUG(dbgs() << "Fail to assign: " << VirtReg << " to "
2207 << PrintReg(PhysReg, TRI) << '\n');
2209 // The recoloring attempt failed, undo the changes.
2210 FixedRegisters = SaveFixedRegisters;
2211 Matrix->unassign(VirtReg);
2213 // For a newly created vreg which is also in RecoloringCandidates,
2214 // don't add it to NewVRegs because its physical register will be restored
2215 // below. Other vregs in CurrentNewVRegs are created by calling
2216 // selectOrSplit and should be added into NewVRegs.
2217 for (SmallVectorImpl<unsigned>::iterator Next = CurrentNewVRegs.begin(),
2218 End = CurrentNewVRegs.end();
2219 Next != End; ++Next) {
2220 if (RecoloringCandidates.count(&LIS->getInterval(*Next)))
2222 NewVRegs.push_back(*Next);
2225 for (SmallLISet::iterator It = RecoloringCandidates.begin(),
2226 EndIt = RecoloringCandidates.end();
2227 It != EndIt; ++It) {
2228 unsigned ItVirtReg = (*It)->reg;
2229 if (VRM->hasPhys(ItVirtReg))
2230 Matrix->unassign(**It);
2231 unsigned ItPhysReg = VirtRegToPhysReg[ItVirtReg];
2232 Matrix->assign(**It, ItPhysReg);
2236 // Last chance recoloring did not worked either, give up.
2240 /// tryRecoloringCandidates - Try to assign a new color to every register
2241 /// in \RecoloringQueue.
2242 /// \p NewRegs will contain any new virtual register created during the
2243 /// recoloring process.
2244 /// \p FixedRegisters[in/out] contains all the registers that have been
2246 /// \return true if all virtual registers in RecoloringQueue were successfully
2247 /// recolored, false otherwise.
2248 bool RAGreedy::tryRecoloringCandidates(PQueue &RecoloringQueue,
2249 SmallVectorImpl<unsigned> &NewVRegs,
2250 SmallVirtRegSet &FixedRegisters,
2252 while (!RecoloringQueue.empty()) {
2253 LiveInterval *LI = dequeue(RecoloringQueue);
2254 DEBUG(dbgs() << "Try to recolor: " << *LI << '\n');
2256 PhysReg = selectOrSplitImpl(*LI, NewVRegs, FixedRegisters, Depth + 1);
2257 // When splitting happens, the live-range may actually be empty.
2258 // In that case, this is okay to continue the recoloring even
2259 // if we did not find an alternative color for it. Indeed,
2260 // there will not be anything to color for LI in the end.
2261 if (PhysReg == ~0u || (!PhysReg && !LI->empty()))
2265 assert(LI->empty() && "Only empty live-range do not require a register");
2266 DEBUG(dbgs() << "Recoloring of " << *LI << " succeeded. Empty LI.\n");
2269 DEBUG(dbgs() << "Recoloring of " << *LI
2270 << " succeeded with: " << PrintReg(PhysReg, TRI) << '\n');
2272 Matrix->assign(*LI, PhysReg);
2273 FixedRegisters.insert(LI->reg);
2278 //===----------------------------------------------------------------------===//
2280 //===----------------------------------------------------------------------===//
2282 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
2283 SmallVectorImpl<unsigned> &NewVRegs) {
2284 CutOffInfo = CO_None;
2285 LLVMContext &Ctx = MF->getFunction()->getContext();
2286 SmallVirtRegSet FixedRegisters;
2287 unsigned Reg = selectOrSplitImpl(VirtReg, NewVRegs, FixedRegisters);
2288 if (Reg == ~0U && (CutOffInfo != CO_None)) {
2289 uint8_t CutOffEncountered = CutOffInfo & (CO_Depth | CO_Interf);
2290 if (CutOffEncountered == CO_Depth)
2291 Ctx.emitError("register allocation failed: maximum depth for recoloring "
2292 "reached. Use -fexhaustive-register-search to skip "
2294 else if (CutOffEncountered == CO_Interf)
2295 Ctx.emitError("register allocation failed: maximum interference for "
2296 "recoloring reached. Use -fexhaustive-register-search "
2298 else if (CutOffEncountered == (CO_Depth | CO_Interf))
2299 Ctx.emitError("register allocation failed: maximum interference and "
2300 "depth for recoloring reached. Use "
2301 "-fexhaustive-register-search to skip cutoffs");
2306 /// Using a CSR for the first time has a cost because it causes push|pop
2307 /// to be added to prologue|epilogue. Splitting a cold section of the live
2308 /// range can have lower cost than using the CSR for the first time;
2309 /// Spilling a live range in the cold path can have lower cost than using
2310 /// the CSR for the first time. Returns the physical register if we decide
2311 /// to use the CSR; otherwise return 0.
2312 unsigned RAGreedy::tryAssignCSRFirstTime(LiveInterval &VirtReg,
2313 AllocationOrder &Order,
2315 unsigned &CostPerUseLimit,
2316 SmallVectorImpl<unsigned> &NewVRegs) {
2317 if (getStage(VirtReg) == RS_Spill && VirtReg.isSpillable()) {
2318 // We choose spill over using the CSR for the first time if the spill cost
2319 // is lower than CSRCost.
2320 SA->analyze(&VirtReg);
2321 if (calcSpillCost() >= CSRCost)
2324 // We are going to spill, set CostPerUseLimit to 1 to make sure that
2325 // we will not use a callee-saved register in tryEvict.
2326 CostPerUseLimit = 1;
2329 if (getStage(VirtReg) < RS_Split) {
2330 // We choose pre-splitting over using the CSR for the first time if
2331 // the cost of splitting is lower than CSRCost.
2332 SA->analyze(&VirtReg);
2333 unsigned NumCands = 0;
2334 BlockFrequency BestCost = CSRCost; // Don't modify CSRCost.
2335 unsigned BestCand = calculateRegionSplitCost(VirtReg, Order, BestCost,
2336 NumCands, true /*IgnoreCSR*/);
2337 if (BestCand == NoCand)
2338 // Use the CSR if we can't find a region split below CSRCost.
2341 // Perform the actual pre-splitting.
2342 doRegionSplit(VirtReg, BestCand, false/*HasCompact*/, NewVRegs);
2348 void RAGreedy::aboutToRemoveInterval(LiveInterval &LI) {
2349 // Do not keep invalid information around.
2350 SetOfBrokenHints.remove(&LI);
2353 void RAGreedy::initializeCSRCost() {
2354 // We use the larger one out of the command-line option and the value report
2356 CSRCost = BlockFrequency(
2357 std::max((unsigned)CSRFirstTimeCost, TRI->getCSRFirstUseCost()));
2358 if (!CSRCost.getFrequency())
2361 // Raw cost is relative to Entry == 2^14; scale it appropriately.
2362 uint64_t ActualEntry = MBFI->getEntryFreq();
2367 uint64_t FixedEntry = 1 << 14;
2368 if (ActualEntry < FixedEntry)
2369 CSRCost *= BranchProbability(ActualEntry, FixedEntry);
2370 else if (ActualEntry <= UINT32_MAX)
2371 // Invert the fraction and divide.
2372 CSRCost /= BranchProbability(FixedEntry, ActualEntry);
2374 // Can't use BranchProbability in general, since it takes 32-bit numbers.
2375 CSRCost = CSRCost.getFrequency() * (ActualEntry / FixedEntry);
2378 /// \brief Collect the hint info for \p Reg.
2379 /// The results are stored into \p Out.
2380 /// \p Out is not cleared before being populated.
2381 void RAGreedy::collectHintInfo(unsigned Reg, HintsInfo &Out) {
2382 for (const MachineInstr &Instr : MRI->reg_nodbg_instructions(Reg)) {
2383 if (!Instr.isFullCopy())
2385 // Look for the other end of the copy.
2386 unsigned OtherReg = Instr.getOperand(0).getReg();
2387 if (OtherReg == Reg) {
2388 OtherReg = Instr.getOperand(1).getReg();
2389 if (OtherReg == Reg)
2392 // Get the current assignment.
2393 unsigned OtherPhysReg = TargetRegisterInfo::isPhysicalRegister(OtherReg)
2395 : VRM->getPhys(OtherReg);
2396 // Push the collected information.
2397 Out.push_back(HintInfo(MBFI->getBlockFreq(Instr.getParent()), OtherReg,
2402 /// \brief Using the given \p List, compute the cost of the broken hints if
2403 /// \p PhysReg was used.
2404 /// \return The cost of \p List for \p PhysReg.
2405 BlockFrequency RAGreedy::getBrokenHintFreq(const HintsInfo &List,
2407 BlockFrequency Cost = 0;
2408 for (const HintInfo &Info : List) {
2409 if (Info.PhysReg != PhysReg)
2415 /// \brief Using the register assigned to \p VirtReg, try to recolor
2416 /// all the live ranges that are copy-related with \p VirtReg.
2417 /// The recoloring is then propagated to all the live-ranges that have
2418 /// been recolored and so on, until no more copies can be coalesced or
2419 /// it is not profitable.
2420 /// For a given live range, profitability is determined by the sum of the
2421 /// frequencies of the non-identity copies it would introduce with the old
2422 /// and new register.
2423 void RAGreedy::tryHintRecoloring(LiveInterval &VirtReg) {
2424 // We have a broken hint, check if it is possible to fix it by
2425 // reusing PhysReg for the copy-related live-ranges. Indeed, we evicted
2426 // some register and PhysReg may be available for the other live-ranges.
2427 SmallSet<unsigned, 4> Visited;
2428 SmallVector<unsigned, 2> RecoloringCandidates;
2430 unsigned Reg = VirtReg.reg;
2431 unsigned PhysReg = VRM->getPhys(Reg);
2432 // Start the recoloring algorithm from the input live-interval, then
2433 // it will propagate to the ones that are copy-related with it.
2434 Visited.insert(Reg);
2435 RecoloringCandidates.push_back(Reg);
2437 DEBUG(dbgs() << "Trying to reconcile hints for: " << PrintReg(Reg, TRI) << '('
2438 << PrintReg(PhysReg, TRI) << ")\n");
2441 Reg = RecoloringCandidates.pop_back_val();
2443 // We cannot recolor physcal register.
2444 if (TargetRegisterInfo::isPhysicalRegister(Reg))
2447 assert(VRM->hasPhys(Reg) && "We have unallocated variable!!");
2449 // Get the live interval mapped with this virtual register to be able
2450 // to check for the interference with the new color.
2451 LiveInterval &LI = LIS->getInterval(Reg);
2452 unsigned CurrPhys = VRM->getPhys(Reg);
2453 // Check that the new color matches the register class constraints and
2454 // that it is free for this live range.
2455 if (CurrPhys != PhysReg && (!MRI->getRegClass(Reg)->contains(PhysReg) ||
2456 Matrix->checkInterference(LI, PhysReg)))
2459 DEBUG(dbgs() << PrintReg(Reg, TRI) << '(' << PrintReg(CurrPhys, TRI)
2460 << ") is recolorable.\n");
2462 // Gather the hint info.
2464 collectHintInfo(Reg, Info);
2465 // Check if recoloring the live-range will increase the cost of the
2466 // non-identity copies.
2467 if (CurrPhys != PhysReg) {
2468 DEBUG(dbgs() << "Checking profitability:\n");
2469 BlockFrequency OldCopiesCost = getBrokenHintFreq(Info, CurrPhys);
2470 BlockFrequency NewCopiesCost = getBrokenHintFreq(Info, PhysReg);
2471 DEBUG(dbgs() << "Old Cost: " << OldCopiesCost.getFrequency()
2472 << "\nNew Cost: " << NewCopiesCost.getFrequency() << '\n');
2473 if (OldCopiesCost < NewCopiesCost) {
2474 DEBUG(dbgs() << "=> Not profitable.\n");
2477 // At this point, the cost is either cheaper or equal. If it is
2478 // equal, we consider this is profitable because it may expose
2479 // more recoloring opportunities.
2480 DEBUG(dbgs() << "=> Profitable.\n");
2481 // Recolor the live-range.
2482 Matrix->unassign(LI);
2483 Matrix->assign(LI, PhysReg);
2485 // Push all copy-related live-ranges to keep reconciling the broken
2487 for (const HintInfo &HI : Info) {
2488 if (Visited.insert(HI.Reg).second)
2489 RecoloringCandidates.push_back(HI.Reg);
2491 } while (!RecoloringCandidates.empty());
2494 /// \brief Try to recolor broken hints.
2495 /// Broken hints may be repaired by recoloring when an evicted variable
2496 /// freed up a register for a larger live-range.
2497 /// Consider the following example:
2505 /// Let us assume b gets split:
2515 /// Because of how the allocation work, b, c, and d may be assigned different
2516 /// colors. Now, if a gets evicted later:
2526 /// e = ld SpillSlot
2528 /// This is likely that we can assign the same register for b, c, and d,
2529 /// getting rid of 2 copies.
2530 void RAGreedy::tryHintsRecoloring() {
2531 for (LiveInterval *LI : SetOfBrokenHints) {
2532 assert(TargetRegisterInfo::isVirtualRegister(LI->reg) &&
2533 "Recoloring is possible only for virtual registers");
2534 // Some dead defs may be around (e.g., because of debug uses).
2536 if (!VRM->hasPhys(LI->reg))
2538 tryHintRecoloring(*LI);
2542 unsigned RAGreedy::selectOrSplitImpl(LiveInterval &VirtReg,
2543 SmallVectorImpl<unsigned> &NewVRegs,
2544 SmallVirtRegSet &FixedRegisters,
2546 unsigned CostPerUseLimit = ~0u;
2547 // First try assigning a free register.
2548 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
2549 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs)) {
2550 // When NewVRegs is not empty, we may have made decisions such as evicting
2551 // a virtual register, go with the earlier decisions and use the physical
2553 if (CSRCost.getFrequency() && isUnusedCalleeSavedReg(PhysReg) &&
2555 unsigned CSRReg = tryAssignCSRFirstTime(VirtReg, Order, PhysReg,
2556 CostPerUseLimit, NewVRegs);
2557 if (CSRReg || !NewVRegs.empty())
2558 // Return now if we decide to use a CSR or create new vregs due to
2565 LiveRangeStage Stage = getStage(VirtReg);
2566 DEBUG(dbgs() << StageName[Stage]
2567 << " Cascade " << ExtraRegInfo[VirtReg.reg].Cascade << '\n');
2569 // Try to evict a less worthy live range, but only for ranges from the primary
2570 // queue. The RS_Split ranges already failed to do this, and they should not
2571 // get a second chance until they have been split.
2572 if (Stage != RS_Split)
2573 if (unsigned PhysReg =
2574 tryEvict(VirtReg, Order, NewVRegs, CostPerUseLimit)) {
2575 unsigned Hint = MRI->getSimpleHint(VirtReg.reg);
2576 // If VirtReg has a hint and that hint is broken record this
2577 // virtual register as a recoloring candidate for broken hint.
2578 // Indeed, since we evicted a variable in its neighborhood it is
2579 // likely we can at least partially recolor some of the
2580 // copy-related live-ranges.
2581 if (Hint && Hint != PhysReg)
2582 SetOfBrokenHints.insert(&VirtReg);
2586 assert((NewVRegs.empty() || Depth) && "Cannot append to existing NewVRegs");
2588 // The first time we see a live range, don't try to split or spill.
2589 // Wait until the second time, when all smaller ranges have been allocated.
2590 // This gives a better picture of the interference to split around.
2591 if (Stage < RS_Split) {
2592 setStage(VirtReg, RS_Split);
2593 DEBUG(dbgs() << "wait for second round\n");
2594 NewVRegs.push_back(VirtReg.reg);
2598 if (Stage < RS_Spill) {
2599 // Try splitting VirtReg or interferences.
2600 unsigned NewVRegSizeBefore = NewVRegs.size();
2601 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
2602 if (PhysReg || (NewVRegs.size() - NewVRegSizeBefore))
2606 // If we couldn't allocate a register from spilling, there is probably some
2607 // invalid inline assembly. The base class wil report it.
2608 if (Stage >= RS_Done || !VirtReg.isSpillable())
2609 return tryLastChanceRecoloring(VirtReg, Order, NewVRegs, FixedRegisters,
2612 // Finally spill VirtReg itself.
2613 if (EnableDeferredSpilling && getStage(VirtReg) < RS_Memory) {
2614 // TODO: This is experimental and in particular, we do not model
2615 // the live range splitting done by spilling correctly.
2616 // We would need a deep integration with the spiller to do the
2617 // right thing here. Anyway, that is still good for early testing.
2618 setStage(VirtReg, RS_Memory);
2619 DEBUG(dbgs() << "Do as if this register is in memory\n");
2620 NewVRegs.push_back(VirtReg.reg);
2622 NamedRegionTimer T("spill", "Spiller", TimerGroupName,
2623 TimerGroupDescription, TimePassesIsEnabled);
2624 LiveRangeEdit LRE(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
2625 spiller().spill(LRE);
2626 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Done);
2629 MF->verify(this, "After spilling");
2632 // The live virtual register requesting allocation was spilled, so tell
2633 // the caller not to allocate anything during this round.
2637 void RAGreedy::reportNumberOfSplillsReloads(MachineLoop *L, unsigned &Reloads,
2638 unsigned &FoldedReloads,
2640 unsigned &FoldedSpills) {
2646 // Sum up the spill and reloads in subloops.
2647 for (MachineLoop *SubLoop : *L) {
2648 unsigned SubReloads;
2649 unsigned SubFoldedReloads;
2651 unsigned SubFoldedSpills;
2653 reportNumberOfSplillsReloads(SubLoop, SubReloads, SubFoldedReloads,
2654 SubSpills, SubFoldedSpills);
2655 Reloads += SubReloads;
2656 FoldedReloads += SubFoldedReloads;
2657 Spills += SubSpills;
2658 FoldedSpills += SubFoldedSpills;
2661 const MachineFrameInfo &MFI = MF->getFrameInfo();
2662 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
2665 for (MachineBasicBlock *MBB : L->getBlocks())
2666 // Handle blocks that were not included in subloops.
2667 if (Loops->getLoopFor(MBB) == L)
2668 for (MachineInstr &MI : *MBB) {
2669 const MachineMemOperand *MMO;
2671 if (TII->isLoadFromStackSlot(MI, FI) && MFI.isSpillSlotObjectIndex(FI))
2673 else if (TII->hasLoadFromStackSlot(MI, MMO, FI) &&
2674 MFI.isSpillSlotObjectIndex(FI))
2676 else if (TII->isStoreToStackSlot(MI, FI) &&
2677 MFI.isSpillSlotObjectIndex(FI))
2679 else if (TII->hasStoreToStackSlot(MI, MMO, FI) &&
2680 MFI.isSpillSlotObjectIndex(FI))
2684 if (Reloads || FoldedReloads || Spills || FoldedSpills) {
2685 using namespace ore;
2686 MachineOptimizationRemarkMissed R(DEBUG_TYPE, "LoopSpillReload",
2687 L->getStartLoc(), L->getHeader());
2689 R << NV("NumSpills", Spills) << " spills ";
2691 R << NV("NumFoldedSpills", FoldedSpills) << " folded spills ";
2693 R << NV("NumReloads", Reloads) << " reloads ";
2695 R << NV("NumFoldedReloads", FoldedReloads) << " folded reloads ";
2696 ORE->emit(R << "generated in loop");
2700 bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
2701 DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
2702 << "********** Function: " << mf.getName() << '\n');
2705 TRI = MF->getSubtarget().getRegisterInfo();
2706 TII = MF->getSubtarget().getInstrInfo();
2707 RCI.runOnMachineFunction(mf);
2709 EnableLocalReassign = EnableLocalReassignment ||
2710 MF->getSubtarget().enableRALocalReassignment(
2711 MF->getTarget().getOptLevel());
2714 MF->verify(this, "Before greedy register allocator");
2716 RegAllocBase::init(getAnalysis<VirtRegMap>(),
2717 getAnalysis<LiveIntervals>(),
2718 getAnalysis<LiveRegMatrix>());
2719 Indexes = &getAnalysis<SlotIndexes>();
2720 MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
2721 DomTree = &getAnalysis<MachineDominatorTree>();
2722 ORE = &getAnalysis<MachineOptimizationRemarkEmitterPass>().getORE();
2723 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
2724 Loops = &getAnalysis<MachineLoopInfo>();
2725 Bundles = &getAnalysis<EdgeBundles>();
2726 SpillPlacer = &getAnalysis<SpillPlacement>();
2727 DebugVars = &getAnalysis<LiveDebugVariables>();
2728 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
2730 initializeCSRCost();
2732 calculateSpillWeightsAndHints(*LIS, mf, VRM, *Loops, *MBFI);
2736 SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops));
2737 SE.reset(new SplitEditor(*SA, *AA, *LIS, *VRM, *DomTree, *MBFI));
2738 ExtraRegInfo.clear();
2739 ExtraRegInfo.resize(MRI->getNumVirtRegs());
2741 IntfCache.init(MF, Matrix->getLiveUnions(), Indexes, LIS, TRI);
2742 GlobalCand.resize(32); // This will grow as needed.
2743 SetOfBrokenHints.clear();
2746 tryHintsRecoloring();
2748 reportNumberOfSplillsReloads();