1 //===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
11 // register allocator for LLVM. This allocator works by constructing a PBQP
12 // problem representing the register allocation problem under consideration,
13 // solving this using a PBQP solver, and mapping the solution back to a
14 // register assignment. If any variables are selected for spilling then spill
15 // code is inserted and the process repeated.
17 // The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
18 // for register allocation. For more information on PBQP for register
19 // allocation, see the following papers:
21 // (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
22 // PBQP. In Proceedings of the 7th Joint Modular Languages Conference
23 // (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361.
25 // (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular
26 // architectures. In Proceedings of the Joint Conference on Languages,
27 // Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
30 //===----------------------------------------------------------------------===//
32 #include "llvm/CodeGen/RegAllocPBQP.h"
33 #include "RegisterCoalescer.h"
35 #include "llvm/Analysis/AliasAnalysis.h"
36 #include "llvm/CodeGen/CalcSpillWeights.h"
37 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
38 #include "llvm/CodeGen/LiveRangeEdit.h"
39 #include "llvm/CodeGen/LiveStackAnalysis.h"
40 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
41 #include "llvm/CodeGen/MachineDominators.h"
42 #include "llvm/CodeGen/MachineFunctionPass.h"
43 #include "llvm/CodeGen/MachineLoopInfo.h"
44 #include "llvm/CodeGen/MachineRegisterInfo.h"
45 #include "llvm/CodeGen/RegAllocRegistry.h"
46 #include "llvm/CodeGen/VirtRegMap.h"
47 #include "llvm/IR/Module.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/FileSystem.h"
50 #include "llvm/Support/Printable.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/Target/TargetInstrInfo.h"
53 #include "llvm/Target/TargetSubtargetInfo.h"
63 #define DEBUG_TYPE "regalloc"
65 static RegisterRegAlloc
66 RegisterPBQPRepAlloc("pbqp", "PBQP register allocator",
67 createDefaultPBQPRegisterAllocator);
70 PBQPCoalescing("pbqp-coalescing",
71 cl::desc("Attempt coalescing during PBQP register allocation."),
72 cl::init(false), cl::Hidden);
76 PBQPDumpGraphs("pbqp-dump-graphs",
77 cl::desc("Dump graphs for each function/round in the compilation unit."),
78 cl::init(false), cl::Hidden);
84 /// PBQP based allocators solve the register allocation problem by mapping
85 /// register allocation problems to Partitioned Boolean Quadratic
86 /// Programming problems.
87 class RegAllocPBQP : public MachineFunctionPass {
92 /// Construct a PBQP register allocator.
93 RegAllocPBQP(char *cPassID = nullptr)
94 : MachineFunctionPass(ID), customPassID(cPassID) {
95 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
96 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
97 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
98 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
101 /// Return the pass name.
102 const char* getPassName() const override {
103 return "PBQP Register Allocator";
106 /// PBQP analysis usage.
107 void getAnalysisUsage(AnalysisUsage &au) const override;
109 /// Perform register allocation
110 bool runOnMachineFunction(MachineFunction &MF) override;
114 typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
115 typedef std::vector<const LiveInterval*> Node2LIMap;
116 typedef std::vector<unsigned> AllowedSet;
117 typedef std::vector<AllowedSet> AllowedSetMap;
118 typedef std::pair<unsigned, unsigned> RegPair;
119 typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap;
120 typedef std::set<unsigned> RegSet;
124 RegSet VRegsToAlloc, EmptyIntervalVRegs;
126 /// Inst which is a def of an original reg and whose defs are already all
127 /// dead after remat is saved in DeadRemats. The deletion of such inst is
128 /// postponed till all the allocations are done, so its remat expr is
129 /// always available for the remat of all the siblings of the original reg.
130 SmallPtrSet<MachineInstr *, 32> DeadRemats;
132 /// \brief Finds the initial set of vreg intervals to allocate.
133 void findVRegIntervalsToAlloc(const MachineFunction &MF, LiveIntervals &LIS);
135 /// \brief Constructs an initial graph.
136 void initializeGraph(PBQPRAGraph &G, VirtRegMap &VRM, Spiller &VRegSpiller);
138 /// \brief Spill the given VReg.
139 void spillVReg(unsigned VReg, SmallVectorImpl<unsigned> &NewIntervals,
140 MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM,
141 Spiller &VRegSpiller);
143 /// \brief Given a solved PBQP problem maps this solution back to a register
145 bool mapPBQPToRegAlloc(const PBQPRAGraph &G,
146 const PBQP::Solution &Solution,
148 Spiller &VRegSpiller);
150 /// \brief Postprocessing before final spilling. Sets basic block "live in"
152 void finalizeAlloc(MachineFunction &MF, LiveIntervals &LIS,
153 VirtRegMap &VRM) const;
155 void postOptimization(Spiller &VRegSpiller, LiveIntervals &LIS);
158 char RegAllocPBQP::ID = 0;
160 /// @brief Set spill costs for each node in the PBQP reg-alloc graph.
161 class SpillCosts : public PBQPRAConstraint {
163 void apply(PBQPRAGraph &G) override {
164 LiveIntervals &LIS = G.getMetadata().LIS;
166 // A minimum spill costs, so that register constraints can can be set
167 // without normalization in the [0.0:MinSpillCost( interval.
168 const PBQP::PBQPNum MinSpillCost = 10.0;
170 for (auto NId : G.nodeIds()) {
171 PBQP::PBQPNum SpillCost =
172 LIS.getInterval(G.getNodeMetadata(NId).getVReg()).weight;
173 if (SpillCost == 0.0)
174 SpillCost = std::numeric_limits<PBQP::PBQPNum>::min();
176 SpillCost += MinSpillCost;
177 PBQPRAGraph::RawVector NodeCosts(G.getNodeCosts(NId));
178 NodeCosts[PBQP::RegAlloc::getSpillOptionIdx()] = SpillCost;
179 G.setNodeCosts(NId, std::move(NodeCosts));
184 /// @brief Add interference edges between overlapping vregs.
185 class Interference : public PBQPRAConstraint {
188 typedef const PBQP::RegAlloc::AllowedRegVector* AllowedRegVecPtr;
189 typedef std::pair<AllowedRegVecPtr, AllowedRegVecPtr> IKey;
190 typedef DenseMap<IKey, PBQPRAGraph::MatrixPtr> IMatrixCache;
191 typedef DenseSet<IKey> DisjointAllowedRegsCache;
192 typedef std::pair<PBQP::GraphBase::NodeId, PBQP::GraphBase::NodeId> IEdgeKey;
193 typedef DenseSet<IEdgeKey> IEdgeCache;
195 bool haveDisjointAllowedRegs(const PBQPRAGraph &G, PBQPRAGraph::NodeId NId,
196 PBQPRAGraph::NodeId MId,
197 const DisjointAllowedRegsCache &D) const {
198 const auto *NRegs = &G.getNodeMetadata(NId).getAllowedRegs();
199 const auto *MRegs = &G.getNodeMetadata(MId).getAllowedRegs();
205 return D.count(IKey(NRegs, MRegs)) > 0;
207 return D.count(IKey(MRegs, NRegs)) > 0;
210 void setDisjointAllowedRegs(const PBQPRAGraph &G, PBQPRAGraph::NodeId NId,
211 PBQPRAGraph::NodeId MId,
212 DisjointAllowedRegsCache &D) {
213 const auto *NRegs = &G.getNodeMetadata(NId).getAllowedRegs();
214 const auto *MRegs = &G.getNodeMetadata(MId).getAllowedRegs();
216 assert(NRegs != MRegs && "AllowedRegs can not be disjoint with itself");
219 D.insert(IKey(NRegs, MRegs));
221 D.insert(IKey(MRegs, NRegs));
224 // Holds (Interval, CurrentSegmentID, and NodeId). The first two are required
225 // for the fast interference graph construction algorithm. The last is there
226 // to save us from looking up node ids via the VRegToNode map in the graph
228 typedef std::tuple<LiveInterval*, size_t, PBQP::GraphBase::NodeId>
231 static SlotIndex getStartPoint(const IntervalInfo &I) {
232 return std::get<0>(I)->segments[std::get<1>(I)].start;
235 static SlotIndex getEndPoint(const IntervalInfo &I) {
236 return std::get<0>(I)->segments[std::get<1>(I)].end;
239 static PBQP::GraphBase::NodeId getNodeId(const IntervalInfo &I) {
240 return std::get<2>(I);
243 static bool lowestStartPoint(const IntervalInfo &I1,
244 const IntervalInfo &I2) {
245 // Condition reversed because priority queue has the *highest* element at
246 // the front, rather than the lowest.
247 return getStartPoint(I1) > getStartPoint(I2);
250 static bool lowestEndPoint(const IntervalInfo &I1,
251 const IntervalInfo &I2) {
252 SlotIndex E1 = getEndPoint(I1);
253 SlotIndex E2 = getEndPoint(I2);
261 // If two intervals end at the same point, we need a way to break the tie or
262 // the set will assume they're actually equal and refuse to insert a
263 // "duplicate". Just compare the vregs - fast and guaranteed unique.
264 return std::get<0>(I1)->reg < std::get<0>(I2)->reg;
267 static bool isAtLastSegment(const IntervalInfo &I) {
268 return std::get<1>(I) == std::get<0>(I)->size() - 1;
271 static IntervalInfo nextSegment(const IntervalInfo &I) {
272 return std::make_tuple(std::get<0>(I), std::get<1>(I) + 1, std::get<2>(I));
277 void apply(PBQPRAGraph &G) override {
278 // The following is loosely based on the linear scan algorithm introduced in
279 // "Linear Scan Register Allocation" by Poletto and Sarkar. This version
280 // isn't linear, because the size of the active set isn't bound by the
281 // number of registers, but rather the size of the largest clique in the
282 // graph. Still, we expect this to be better than N^2.
283 LiveIntervals &LIS = G.getMetadata().LIS;
285 // Interferenc matrices are incredibly regular - they're only a function of
286 // the allowed sets, so we cache them to avoid the overhead of constructing
287 // and uniquing them.
290 // Finding an edge is expensive in the worst case (O(max_clique(G))). So
291 // cache locally edges we have already seen.
294 // Cache known disjoint allowed registers pairs
295 DisjointAllowedRegsCache D;
297 typedef std::set<IntervalInfo, decltype(&lowestEndPoint)> IntervalSet;
298 typedef std::priority_queue<IntervalInfo, std::vector<IntervalInfo>,
299 decltype(&lowestStartPoint)> IntervalQueue;
300 IntervalSet Active(lowestEndPoint);
301 IntervalQueue Inactive(lowestStartPoint);
303 // Start by building the inactive set.
304 for (auto NId : G.nodeIds()) {
305 unsigned VReg = G.getNodeMetadata(NId).getVReg();
306 LiveInterval &LI = LIS.getInterval(VReg);
307 assert(!LI.empty() && "PBQP graph contains node for empty interval");
308 Inactive.push(std::make_tuple(&LI, 0, NId));
311 while (!Inactive.empty()) {
312 // Tentatively grab the "next" interval - this choice may be overriden
314 IntervalInfo Cur = Inactive.top();
316 // Retire any active intervals that end before Cur starts.
317 IntervalSet::iterator RetireItr = Active.begin();
318 while (RetireItr != Active.end() &&
319 (getEndPoint(*RetireItr) <= getStartPoint(Cur))) {
320 // If this interval has subsequent segments, add the next one to the
322 if (!isAtLastSegment(*RetireItr))
323 Inactive.push(nextSegment(*RetireItr));
327 Active.erase(Active.begin(), RetireItr);
329 // One of the newly retired segments may actually start before the
330 // Cur segment, so re-grab the front of the inactive list.
331 Cur = Inactive.top();
334 // At this point we know that Cur overlaps all active intervals. Add the
335 // interference edges.
336 PBQP::GraphBase::NodeId NId = getNodeId(Cur);
337 for (const auto &A : Active) {
338 PBQP::GraphBase::NodeId MId = getNodeId(A);
340 // Do not add an edge when the nodes' allowed registers do not
341 // intersect: there is obviously no interference.
342 if (haveDisjointAllowedRegs(G, NId, MId, D))
345 // Check that we haven't already added this edge
346 IEdgeKey EK(std::min(NId, MId), std::max(NId, MId));
350 // This is a new edge - add it to the graph.
351 if (!createInterferenceEdge(G, NId, MId, C))
352 setDisjointAllowedRegs(G, NId, MId, D);
357 // Finally, add Cur to the Active set.
364 // Create an Interference edge and add it to the graph, unless it is
365 // a null matrix, meaning the nodes' allowed registers do not have any
366 // interference. This case occurs frequently between integer and floating
367 // point registers for example.
368 // return true iff both nodes interferes.
369 bool createInterferenceEdge(PBQPRAGraph &G,
370 PBQPRAGraph::NodeId NId, PBQPRAGraph::NodeId MId,
373 const TargetRegisterInfo &TRI =
374 *G.getMetadata().MF.getSubtarget().getRegisterInfo();
375 const auto &NRegs = G.getNodeMetadata(NId).getAllowedRegs();
376 const auto &MRegs = G.getNodeMetadata(MId).getAllowedRegs();
378 // Try looking the edge costs up in the IMatrixCache first.
379 IKey K(&NRegs, &MRegs);
380 IMatrixCache::iterator I = C.find(K);
382 G.addEdgeBypassingCostAllocator(NId, MId, I->second);
386 PBQPRAGraph::RawMatrix M(NRegs.size() + 1, MRegs.size() + 1, 0);
387 bool NodesInterfere = false;
388 for (unsigned I = 0; I != NRegs.size(); ++I) {
389 unsigned PRegN = NRegs[I];
390 for (unsigned J = 0; J != MRegs.size(); ++J) {
391 unsigned PRegM = MRegs[J];
392 if (TRI.regsOverlap(PRegN, PRegM)) {
393 M[I + 1][J + 1] = std::numeric_limits<PBQP::PBQPNum>::infinity();
394 NodesInterfere = true;
402 PBQPRAGraph::EdgeId EId = G.addEdge(NId, MId, std::move(M));
403 C[K] = G.getEdgeCostsPtr(EId);
410 class Coalescing : public PBQPRAConstraint {
412 void apply(PBQPRAGraph &G) override {
413 MachineFunction &MF = G.getMetadata().MF;
414 MachineBlockFrequencyInfo &MBFI = G.getMetadata().MBFI;
415 CoalescerPair CP(*MF.getSubtarget().getRegisterInfo());
417 // Scan the machine function and add a coalescing cost whenever CoalescerPair
419 for (const auto &MBB : MF) {
420 for (const auto &MI : MBB) {
422 // Skip not-coalescable or already coalesced copies.
423 if (!CP.setRegisters(&MI) || CP.getSrcReg() == CP.getDstReg())
426 unsigned DstReg = CP.getDstReg();
427 unsigned SrcReg = CP.getSrcReg();
429 const float Scale = 1.0f / MBFI.getEntryFreq();
430 PBQP::PBQPNum CBenefit = MBFI.getBlockFreq(&MBB).getFrequency() * Scale;
433 if (!MF.getRegInfo().isAllocatable(DstReg))
436 PBQPRAGraph::NodeId NId = G.getMetadata().getNodeIdForVReg(SrcReg);
438 const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed =
439 G.getNodeMetadata(NId).getAllowedRegs();
441 unsigned PRegOpt = 0;
442 while (PRegOpt < Allowed.size() && Allowed[PRegOpt] != DstReg)
445 if (PRegOpt < Allowed.size()) {
446 PBQPRAGraph::RawVector NewCosts(G.getNodeCosts(NId));
447 NewCosts[PRegOpt + 1] -= CBenefit;
448 G.setNodeCosts(NId, std::move(NewCosts));
451 PBQPRAGraph::NodeId N1Id = G.getMetadata().getNodeIdForVReg(DstReg);
452 PBQPRAGraph::NodeId N2Id = G.getMetadata().getNodeIdForVReg(SrcReg);
453 const PBQPRAGraph::NodeMetadata::AllowedRegVector *Allowed1 =
454 &G.getNodeMetadata(N1Id).getAllowedRegs();
455 const PBQPRAGraph::NodeMetadata::AllowedRegVector *Allowed2 =
456 &G.getNodeMetadata(N2Id).getAllowedRegs();
458 PBQPRAGraph::EdgeId EId = G.findEdge(N1Id, N2Id);
459 if (EId == G.invalidEdgeId()) {
460 PBQPRAGraph::RawMatrix Costs(Allowed1->size() + 1,
461 Allowed2->size() + 1, 0);
462 addVirtRegCoalesce(Costs, *Allowed1, *Allowed2, CBenefit);
463 G.addEdge(N1Id, N2Id, std::move(Costs));
465 if (G.getEdgeNode1Id(EId) == N2Id) {
466 std::swap(N1Id, N2Id);
467 std::swap(Allowed1, Allowed2);
469 PBQPRAGraph::RawMatrix Costs(G.getEdgeCosts(EId));
470 addVirtRegCoalesce(Costs, *Allowed1, *Allowed2, CBenefit);
471 G.updateEdgeCosts(EId, std::move(Costs));
480 void addVirtRegCoalesce(
481 PBQPRAGraph::RawMatrix &CostMat,
482 const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed1,
483 const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed2,
484 PBQP::PBQPNum Benefit) {
485 assert(CostMat.getRows() == Allowed1.size() + 1 && "Size mismatch.");
486 assert(CostMat.getCols() == Allowed2.size() + 1 && "Size mismatch.");
487 for (unsigned I = 0; I != Allowed1.size(); ++I) {
488 unsigned PReg1 = Allowed1[I];
489 for (unsigned J = 0; J != Allowed2.size(); ++J) {
490 unsigned PReg2 = Allowed2[J];
492 CostMat[I + 1][J + 1] -= Benefit;
499 } // End anonymous namespace.
501 // Out-of-line destructor/anchor for PBQPRAConstraint.
502 PBQPRAConstraint::~PBQPRAConstraint() {}
503 void PBQPRAConstraint::anchor() {}
504 void PBQPRAConstraintList::anchor() {}
506 void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
507 au.setPreservesCFG();
508 au.addRequired<AAResultsWrapperPass>();
509 au.addPreserved<AAResultsWrapperPass>();
510 au.addRequired<SlotIndexes>();
511 au.addPreserved<SlotIndexes>();
512 au.addRequired<LiveIntervals>();
513 au.addPreserved<LiveIntervals>();
514 //au.addRequiredID(SplitCriticalEdgesID);
516 au.addRequiredID(*customPassID);
517 au.addRequired<LiveStacks>();
518 au.addPreserved<LiveStacks>();
519 au.addRequired<MachineBlockFrequencyInfo>();
520 au.addPreserved<MachineBlockFrequencyInfo>();
521 au.addRequired<MachineLoopInfo>();
522 au.addPreserved<MachineLoopInfo>();
523 au.addRequired<MachineDominatorTree>();
524 au.addPreserved<MachineDominatorTree>();
525 au.addRequired<VirtRegMap>();
526 au.addPreserved<VirtRegMap>();
527 MachineFunctionPass::getAnalysisUsage(au);
530 void RegAllocPBQP::findVRegIntervalsToAlloc(const MachineFunction &MF,
531 LiveIntervals &LIS) {
532 const MachineRegisterInfo &MRI = MF.getRegInfo();
534 // Iterate over all live ranges.
535 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
536 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
537 if (MRI.reg_nodbg_empty(Reg))
539 LiveInterval &LI = LIS.getInterval(Reg);
541 // If this live interval is non-empty we will use pbqp to allocate it.
542 // Empty intervals we allocate in a simple post-processing stage in
545 VRegsToAlloc.insert(LI.reg);
547 EmptyIntervalVRegs.insert(LI.reg);
552 static bool isACalleeSavedRegister(unsigned reg, const TargetRegisterInfo &TRI,
553 const MachineFunction &MF) {
554 const MCPhysReg *CSR = TRI.getCalleeSavedRegs(&MF);
555 for (unsigned i = 0; CSR[i] != 0; ++i)
556 if (TRI.regsOverlap(reg, CSR[i]))
561 void RegAllocPBQP::initializeGraph(PBQPRAGraph &G, VirtRegMap &VRM,
562 Spiller &VRegSpiller) {
563 MachineFunction &MF = G.getMetadata().MF;
565 LiveIntervals &LIS = G.getMetadata().LIS;
566 const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo();
567 const TargetRegisterInfo &TRI =
568 *G.getMetadata().MF.getSubtarget().getRegisterInfo();
570 std::vector<unsigned> Worklist(VRegsToAlloc.begin(), VRegsToAlloc.end());
572 while (!Worklist.empty()) {
573 unsigned VReg = Worklist.back();
576 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
577 LiveInterval &VRegLI = LIS.getInterval(VReg);
579 // Record any overlaps with regmask operands.
580 BitVector RegMaskOverlaps;
581 LIS.checkRegMaskInterference(VRegLI, RegMaskOverlaps);
583 // Compute an initial allowed set for the current vreg.
584 std::vector<unsigned> VRegAllowed;
585 ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF);
586 for (unsigned I = 0; I != RawPRegOrder.size(); ++I) {
587 unsigned PReg = RawPRegOrder[I];
588 if (MRI.isReserved(PReg))
591 // vregLI crosses a regmask operand that clobbers preg.
592 if (!RegMaskOverlaps.empty() && !RegMaskOverlaps.test(PReg))
595 // vregLI overlaps fixed regunit interference.
596 bool Interference = false;
597 for (MCRegUnitIterator Units(PReg, &TRI); Units.isValid(); ++Units) {
598 if (VRegLI.overlaps(LIS.getRegUnit(*Units))) {
606 // preg is usable for this virtual register.
607 VRegAllowed.push_back(PReg);
610 // Check for vregs that have no allowed registers. These should be
611 // pre-spilled and the new vregs added to the worklist.
612 if (VRegAllowed.empty()) {
613 SmallVector<unsigned, 8> NewVRegs;
614 spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller);
615 Worklist.insert(Worklist.end(), NewVRegs.begin(), NewVRegs.end());
619 PBQPRAGraph::RawVector NodeCosts(VRegAllowed.size() + 1, 0);
621 // Tweak cost of callee saved registers, as using then force spilling and
622 // restoring them. This would only happen in the prologue / epilogue though.
623 for (unsigned i = 0; i != VRegAllowed.size(); ++i)
624 if (isACalleeSavedRegister(VRegAllowed[i], TRI, MF))
625 NodeCosts[1 + i] += 1.0;
627 PBQPRAGraph::NodeId NId = G.addNode(std::move(NodeCosts));
628 G.getNodeMetadata(NId).setVReg(VReg);
629 G.getNodeMetadata(NId).setAllowedRegs(
630 G.getMetadata().getAllowedRegs(std::move(VRegAllowed)));
631 G.getMetadata().setNodeIdForVReg(VReg, NId);
635 void RegAllocPBQP::spillVReg(unsigned VReg,
636 SmallVectorImpl<unsigned> &NewIntervals,
637 MachineFunction &MF, LiveIntervals &LIS,
638 VirtRegMap &VRM, Spiller &VRegSpiller) {
640 VRegsToAlloc.erase(VReg);
641 LiveRangeEdit LRE(&LIS.getInterval(VReg), NewIntervals, MF, LIS, &VRM,
642 nullptr, &DeadRemats);
643 VRegSpiller.spill(LRE);
645 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
647 DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> SPILLED (Cost: "
648 << LRE.getParent().weight << ", New vregs: ");
650 // Copy any newly inserted live intervals into the list of regs to
652 for (LiveRangeEdit::iterator I = LRE.begin(), E = LRE.end();
654 const LiveInterval &LI = LIS.getInterval(*I);
655 assert(!LI.empty() && "Empty spill range.");
656 DEBUG(dbgs() << PrintReg(LI.reg, &TRI) << " ");
657 VRegsToAlloc.insert(LI.reg);
660 DEBUG(dbgs() << ")\n");
663 bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAGraph &G,
664 const PBQP::Solution &Solution,
666 Spiller &VRegSpiller) {
667 MachineFunction &MF = G.getMetadata().MF;
668 LiveIntervals &LIS = G.getMetadata().LIS;
669 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
672 // Set to true if we have any spills
673 bool AnotherRoundNeeded = false;
675 // Clear the existing allocation.
678 // Iterate over the nodes mapping the PBQP solution to a register
680 for (auto NId : G.nodeIds()) {
681 unsigned VReg = G.getNodeMetadata(NId).getVReg();
682 unsigned AllocOption = Solution.getSelection(NId);
684 if (AllocOption != PBQP::RegAlloc::getSpillOptionIdx()) {
685 unsigned PReg = G.getNodeMetadata(NId).getAllowedRegs()[AllocOption - 1];
686 DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> "
687 << TRI.getName(PReg) << "\n");
688 assert(PReg != 0 && "Invalid preg selected.");
689 VRM.assignVirt2Phys(VReg, PReg);
691 // Spill VReg. If this introduces new intervals we'll need another round
693 SmallVector<unsigned, 8> NewVRegs;
694 spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller);
695 AnotherRoundNeeded |= !NewVRegs.empty();
699 return !AnotherRoundNeeded;
702 void RegAllocPBQP::finalizeAlloc(MachineFunction &MF,
704 VirtRegMap &VRM) const {
705 MachineRegisterInfo &MRI = MF.getRegInfo();
707 // First allocate registers for the empty intervals.
708 for (RegSet::const_iterator
709 I = EmptyIntervalVRegs.begin(), E = EmptyIntervalVRegs.end();
711 LiveInterval &LI = LIS.getInterval(*I);
713 unsigned PReg = MRI.getSimpleHint(LI.reg);
716 const TargetRegisterClass &RC = *MRI.getRegClass(LI.reg);
717 PReg = RC.getRawAllocationOrder(MF).front();
720 VRM.assignVirt2Phys(LI.reg, PReg);
724 void RegAllocPBQP::postOptimization(Spiller &VRegSpiller, LiveIntervals &LIS) {
725 VRegSpiller.postOptimization();
726 /// Remove dead defs because of rematerialization.
727 for (auto DeadInst : DeadRemats) {
728 LIS.RemoveMachineInstrFromMaps(*DeadInst);
729 DeadInst->eraseFromParent();
734 static inline float normalizePBQPSpillWeight(float UseDefFreq, unsigned Size,
736 // All intervals have a spill weight that is mostly proportional to the number
737 // of uses, with uses in loops having a bigger weight.
738 return NumInstr * normalizeSpillWeight(UseDefFreq, Size, 1);
741 bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
742 LiveIntervals &LIS = getAnalysis<LiveIntervals>();
743 MachineBlockFrequencyInfo &MBFI =
744 getAnalysis<MachineBlockFrequencyInfo>();
746 VirtRegMap &VRM = getAnalysis<VirtRegMap>();
748 calculateSpillWeightsAndHints(LIS, MF, &VRM, getAnalysis<MachineLoopInfo>(),
749 MBFI, normalizePBQPSpillWeight);
751 std::unique_ptr<Spiller> VRegSpiller(createInlineSpiller(*this, MF, VRM));
753 MF.getRegInfo().freezeReservedRegs(MF);
755 DEBUG(dbgs() << "PBQP Register Allocating for " << MF.getName() << "\n");
757 // Allocator main loop:
759 // * Map current regalloc problem to a PBQP problem
760 // * Solve the PBQP problem
761 // * Map the solution back to a register allocation
762 // * Spill if necessary
764 // This process is continued till no more spills are generated.
766 // Find the vreg intervals in need of allocation.
767 findVRegIntervalsToAlloc(MF, LIS);
770 const Function &F = *MF.getFunction();
771 std::string FullyQualifiedName =
772 F.getParent()->getModuleIdentifier() + "." + F.getName().str();
775 // If there are non-empty intervals allocate them using pbqp.
776 if (!VRegsToAlloc.empty()) {
778 const TargetSubtargetInfo &Subtarget = MF.getSubtarget();
779 std::unique_ptr<PBQPRAConstraintList> ConstraintsRoot =
780 llvm::make_unique<PBQPRAConstraintList>();
781 ConstraintsRoot->addConstraint(llvm::make_unique<SpillCosts>());
782 ConstraintsRoot->addConstraint(llvm::make_unique<Interference>());
784 ConstraintsRoot->addConstraint(llvm::make_unique<Coalescing>());
785 ConstraintsRoot->addConstraint(Subtarget.getCustomPBQPConstraints());
787 bool PBQPAllocComplete = false;
790 while (!PBQPAllocComplete) {
791 DEBUG(dbgs() << " PBQP Regalloc round " << Round << ":\n");
793 PBQPRAGraph G(PBQPRAGraph::GraphMetadata(MF, LIS, MBFI));
794 initializeGraph(G, VRM, *VRegSpiller);
795 ConstraintsRoot->apply(G);
798 if (PBQPDumpGraphs) {
799 std::ostringstream RS;
801 std::string GraphFileName = FullyQualifiedName + "." + RS.str() +
804 raw_fd_ostream OS(GraphFileName, EC, sys::fs::F_Text);
805 DEBUG(dbgs() << "Dumping graph for round " << Round << " to \""
806 << GraphFileName << "\"\n");
811 PBQP::Solution Solution = PBQP::RegAlloc::solve(G);
812 PBQPAllocComplete = mapPBQPToRegAlloc(G, Solution, VRM, *VRegSpiller);
817 // Finalise allocation, allocate empty ranges.
818 finalizeAlloc(MF, LIS, VRM);
819 postOptimization(*VRegSpiller, LIS);
820 VRegsToAlloc.clear();
821 EmptyIntervalVRegs.clear();
823 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << VRM << "\n");
828 /// Create Printable object for node and register info.
829 static Printable PrintNodeInfo(PBQP::RegAlloc::PBQPRAGraph::NodeId NId,
830 const PBQP::RegAlloc::PBQPRAGraph &G) {
831 return Printable([NId, &G](raw_ostream &OS) {
832 const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo();
833 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
834 unsigned VReg = G.getNodeMetadata(NId).getVReg();
835 const char *RegClassName = TRI->getRegClassName(MRI.getRegClass(VReg));
836 OS << NId << " (" << RegClassName << ':' << PrintReg(VReg, TRI) << ')';
840 void PBQP::RegAlloc::PBQPRAGraph::dump(raw_ostream &OS) const {
841 for (auto NId : nodeIds()) {
842 const Vector &Costs = getNodeCosts(NId);
843 assert(Costs.getLength() != 0 && "Empty vector in graph.");
844 OS << PrintNodeInfo(NId, *this) << ": " << Costs << '\n';
848 for (auto EId : edgeIds()) {
849 NodeId N1Id = getEdgeNode1Id(EId);
850 NodeId N2Id = getEdgeNode2Id(EId);
851 assert(N1Id != N2Id && "PBQP graphs should not have self-edges.");
852 const Matrix &M = getEdgeCosts(EId);
853 assert(M.getRows() != 0 && "No rows in matrix.");
854 assert(M.getCols() != 0 && "No cols in matrix.");
855 OS << PrintNodeInfo(N1Id, *this) << ' ' << M.getRows() << " rows / ";
856 OS << PrintNodeInfo(N2Id, *this) << ' ' << M.getCols() << " cols:\n";
861 LLVM_DUMP_METHOD void PBQP::RegAlloc::PBQPRAGraph::dump() const { dump(dbgs()); }
863 void PBQP::RegAlloc::PBQPRAGraph::printDot(raw_ostream &OS) const {
865 for (auto NId : nodeIds()) {
866 OS << " node" << NId << " [ label=\""
867 << PrintNodeInfo(NId, *this) << "\\n"
868 << getNodeCosts(NId) << "\" ]\n";
871 OS << " edge [ len=" << nodeIds().size() << " ]\n";
872 for (auto EId : edgeIds()) {
873 OS << " node" << getEdgeNode1Id(EId)
874 << " -- node" << getEdgeNode2Id(EId)
876 const Matrix &EdgeCosts = getEdgeCosts(EId);
877 for (unsigned i = 0; i < EdgeCosts.getRows(); ++i) {
878 OS << EdgeCosts.getRowAsVector(i) << "\\n";
885 FunctionPass *llvm::createPBQPRegisterAllocator(char *customPassID) {
886 return new RegAllocPBQP(customPassID);
889 FunctionPass* llvm::createDefaultPBQPRegisterAllocator() {
890 return createPBQPRegisterAllocator();