1 //===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
11 // register allocator for LLVM. This allocator works by constructing a PBQP
12 // problem representing the register allocation problem under consideration,
13 // solving this using a PBQP solver, and mapping the solution back to a
14 // register assignment. If any variables are selected for spilling then spill
15 // code is inserted and the process repeated.
17 // The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
18 // for register allocation. For more information on PBQP for register
19 // allocation, see the following papers:
21 // (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
22 // PBQP. In Proceedings of the 7th Joint Modular Languages Conference
23 // (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361.
25 // (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular
26 // architectures. In Proceedings of the Joint Conference on Languages,
27 // Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
30 //===----------------------------------------------------------------------===//
32 #include "llvm/CodeGen/RegAllocPBQP.h"
33 #include "RegisterCoalescer.h"
35 #include "llvm/Analysis/AliasAnalysis.h"
36 #include "llvm/CodeGen/CalcSpillWeights.h"
37 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
38 #include "llvm/CodeGen/LiveRangeEdit.h"
39 #include "llvm/CodeGen/LiveStackAnalysis.h"
40 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
41 #include "llvm/CodeGen/MachineDominators.h"
42 #include "llvm/CodeGen/MachineFunctionPass.h"
43 #include "llvm/CodeGen/MachineLoopInfo.h"
44 #include "llvm/CodeGen/MachineRegisterInfo.h"
45 #include "llvm/CodeGen/RegAllocRegistry.h"
46 #include "llvm/CodeGen/VirtRegMap.h"
47 #include "llvm/IR/Module.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/FileSystem.h"
50 #include "llvm/Support/Printable.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/Target/TargetInstrInfo.h"
53 #include "llvm/Target/TargetSubtargetInfo.h"
63 #define DEBUG_TYPE "regalloc"
65 static RegisterRegAlloc
66 RegisterPBQPRepAlloc("pbqp", "PBQP register allocator",
67 createDefaultPBQPRegisterAllocator);
70 PBQPCoalescing("pbqp-coalescing",
71 cl::desc("Attempt coalescing during PBQP register allocation."),
72 cl::init(false), cl::Hidden);
76 PBQPDumpGraphs("pbqp-dump-graphs",
77 cl::desc("Dump graphs for each function/round in the compilation unit."),
78 cl::init(false), cl::Hidden);
84 /// PBQP based allocators solve the register allocation problem by mapping
85 /// register allocation problems to Partitioned Boolean Quadratic
86 /// Programming problems.
87 class RegAllocPBQP : public MachineFunctionPass {
92 /// Construct a PBQP register allocator.
93 RegAllocPBQP(char *cPassID = nullptr)
94 : MachineFunctionPass(ID), customPassID(cPassID) {
95 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
96 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
97 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
98 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
101 /// Return the pass name.
102 StringRef getPassName() const override { return "PBQP Register Allocator"; }
104 /// PBQP analysis usage.
105 void getAnalysisUsage(AnalysisUsage &au) const override;
107 /// Perform register allocation
108 bool runOnMachineFunction(MachineFunction &MF) override;
110 MachineFunctionProperties getRequiredProperties() const override {
111 return MachineFunctionProperties().set(
112 MachineFunctionProperties::Property::NoPHIs);
117 typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
118 typedef std::vector<const LiveInterval*> Node2LIMap;
119 typedef std::vector<unsigned> AllowedSet;
120 typedef std::vector<AllowedSet> AllowedSetMap;
121 typedef std::pair<unsigned, unsigned> RegPair;
122 typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap;
123 typedef std::set<unsigned> RegSet;
127 RegSet VRegsToAlloc, EmptyIntervalVRegs;
129 /// Inst which is a def of an original reg and whose defs are already all
130 /// dead after remat is saved in DeadRemats. The deletion of such inst is
131 /// postponed till all the allocations are done, so its remat expr is
132 /// always available for the remat of all the siblings of the original reg.
133 SmallPtrSet<MachineInstr *, 32> DeadRemats;
135 /// \brief Finds the initial set of vreg intervals to allocate.
136 void findVRegIntervalsToAlloc(const MachineFunction &MF, LiveIntervals &LIS);
138 /// \brief Constructs an initial graph.
139 void initializeGraph(PBQPRAGraph &G, VirtRegMap &VRM, Spiller &VRegSpiller);
141 /// \brief Spill the given VReg.
142 void spillVReg(unsigned VReg, SmallVectorImpl<unsigned> &NewIntervals,
143 MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM,
144 Spiller &VRegSpiller);
146 /// \brief Given a solved PBQP problem maps this solution back to a register
148 bool mapPBQPToRegAlloc(const PBQPRAGraph &G,
149 const PBQP::Solution &Solution,
151 Spiller &VRegSpiller);
153 /// \brief Postprocessing before final spilling. Sets basic block "live in"
155 void finalizeAlloc(MachineFunction &MF, LiveIntervals &LIS,
156 VirtRegMap &VRM) const;
158 void postOptimization(Spiller &VRegSpiller, LiveIntervals &LIS);
161 char RegAllocPBQP::ID = 0;
163 /// @brief Set spill costs for each node in the PBQP reg-alloc graph.
164 class SpillCosts : public PBQPRAConstraint {
166 void apply(PBQPRAGraph &G) override {
167 LiveIntervals &LIS = G.getMetadata().LIS;
169 // A minimum spill costs, so that register constraints can can be set
170 // without normalization in the [0.0:MinSpillCost( interval.
171 const PBQP::PBQPNum MinSpillCost = 10.0;
173 for (auto NId : G.nodeIds()) {
174 PBQP::PBQPNum SpillCost =
175 LIS.getInterval(G.getNodeMetadata(NId).getVReg()).weight;
176 if (SpillCost == 0.0)
177 SpillCost = std::numeric_limits<PBQP::PBQPNum>::min();
179 SpillCost += MinSpillCost;
180 PBQPRAGraph::RawVector NodeCosts(G.getNodeCosts(NId));
181 NodeCosts[PBQP::RegAlloc::getSpillOptionIdx()] = SpillCost;
182 G.setNodeCosts(NId, std::move(NodeCosts));
187 /// @brief Add interference edges between overlapping vregs.
188 class Interference : public PBQPRAConstraint {
191 typedef const PBQP::RegAlloc::AllowedRegVector* AllowedRegVecPtr;
192 typedef std::pair<AllowedRegVecPtr, AllowedRegVecPtr> IKey;
193 typedef DenseMap<IKey, PBQPRAGraph::MatrixPtr> IMatrixCache;
194 typedef DenseSet<IKey> DisjointAllowedRegsCache;
195 typedef std::pair<PBQP::GraphBase::NodeId, PBQP::GraphBase::NodeId> IEdgeKey;
196 typedef DenseSet<IEdgeKey> IEdgeCache;
198 bool haveDisjointAllowedRegs(const PBQPRAGraph &G, PBQPRAGraph::NodeId NId,
199 PBQPRAGraph::NodeId MId,
200 const DisjointAllowedRegsCache &D) const {
201 const auto *NRegs = &G.getNodeMetadata(NId).getAllowedRegs();
202 const auto *MRegs = &G.getNodeMetadata(MId).getAllowedRegs();
208 return D.count(IKey(NRegs, MRegs)) > 0;
210 return D.count(IKey(MRegs, NRegs)) > 0;
213 void setDisjointAllowedRegs(const PBQPRAGraph &G, PBQPRAGraph::NodeId NId,
214 PBQPRAGraph::NodeId MId,
215 DisjointAllowedRegsCache &D) {
216 const auto *NRegs = &G.getNodeMetadata(NId).getAllowedRegs();
217 const auto *MRegs = &G.getNodeMetadata(MId).getAllowedRegs();
219 assert(NRegs != MRegs && "AllowedRegs can not be disjoint with itself");
222 D.insert(IKey(NRegs, MRegs));
224 D.insert(IKey(MRegs, NRegs));
227 // Holds (Interval, CurrentSegmentID, and NodeId). The first two are required
228 // for the fast interference graph construction algorithm. The last is there
229 // to save us from looking up node ids via the VRegToNode map in the graph
231 typedef std::tuple<LiveInterval*, size_t, PBQP::GraphBase::NodeId>
234 static SlotIndex getStartPoint(const IntervalInfo &I) {
235 return std::get<0>(I)->segments[std::get<1>(I)].start;
238 static SlotIndex getEndPoint(const IntervalInfo &I) {
239 return std::get<0>(I)->segments[std::get<1>(I)].end;
242 static PBQP::GraphBase::NodeId getNodeId(const IntervalInfo &I) {
243 return std::get<2>(I);
246 static bool lowestStartPoint(const IntervalInfo &I1,
247 const IntervalInfo &I2) {
248 // Condition reversed because priority queue has the *highest* element at
249 // the front, rather than the lowest.
250 return getStartPoint(I1) > getStartPoint(I2);
253 static bool lowestEndPoint(const IntervalInfo &I1,
254 const IntervalInfo &I2) {
255 SlotIndex E1 = getEndPoint(I1);
256 SlotIndex E2 = getEndPoint(I2);
264 // If two intervals end at the same point, we need a way to break the tie or
265 // the set will assume they're actually equal and refuse to insert a
266 // "duplicate". Just compare the vregs - fast and guaranteed unique.
267 return std::get<0>(I1)->reg < std::get<0>(I2)->reg;
270 static bool isAtLastSegment(const IntervalInfo &I) {
271 return std::get<1>(I) == std::get<0>(I)->size() - 1;
274 static IntervalInfo nextSegment(const IntervalInfo &I) {
275 return std::make_tuple(std::get<0>(I), std::get<1>(I) + 1, std::get<2>(I));
280 void apply(PBQPRAGraph &G) override {
281 // The following is loosely based on the linear scan algorithm introduced in
282 // "Linear Scan Register Allocation" by Poletto and Sarkar. This version
283 // isn't linear, because the size of the active set isn't bound by the
284 // number of registers, but rather the size of the largest clique in the
285 // graph. Still, we expect this to be better than N^2.
286 LiveIntervals &LIS = G.getMetadata().LIS;
288 // Interferenc matrices are incredibly regular - they're only a function of
289 // the allowed sets, so we cache them to avoid the overhead of constructing
290 // and uniquing them.
293 // Finding an edge is expensive in the worst case (O(max_clique(G))). So
294 // cache locally edges we have already seen.
297 // Cache known disjoint allowed registers pairs
298 DisjointAllowedRegsCache D;
300 typedef std::set<IntervalInfo, decltype(&lowestEndPoint)> IntervalSet;
301 typedef std::priority_queue<IntervalInfo, std::vector<IntervalInfo>,
302 decltype(&lowestStartPoint)> IntervalQueue;
303 IntervalSet Active(lowestEndPoint);
304 IntervalQueue Inactive(lowestStartPoint);
306 // Start by building the inactive set.
307 for (auto NId : G.nodeIds()) {
308 unsigned VReg = G.getNodeMetadata(NId).getVReg();
309 LiveInterval &LI = LIS.getInterval(VReg);
310 assert(!LI.empty() && "PBQP graph contains node for empty interval");
311 Inactive.push(std::make_tuple(&LI, 0, NId));
314 while (!Inactive.empty()) {
315 // Tentatively grab the "next" interval - this choice may be overriden
317 IntervalInfo Cur = Inactive.top();
319 // Retire any active intervals that end before Cur starts.
320 IntervalSet::iterator RetireItr = Active.begin();
321 while (RetireItr != Active.end() &&
322 (getEndPoint(*RetireItr) <= getStartPoint(Cur))) {
323 // If this interval has subsequent segments, add the next one to the
325 if (!isAtLastSegment(*RetireItr))
326 Inactive.push(nextSegment(*RetireItr));
330 Active.erase(Active.begin(), RetireItr);
332 // One of the newly retired segments may actually start before the
333 // Cur segment, so re-grab the front of the inactive list.
334 Cur = Inactive.top();
337 // At this point we know that Cur overlaps all active intervals. Add the
338 // interference edges.
339 PBQP::GraphBase::NodeId NId = getNodeId(Cur);
340 for (const auto &A : Active) {
341 PBQP::GraphBase::NodeId MId = getNodeId(A);
343 // Do not add an edge when the nodes' allowed registers do not
344 // intersect: there is obviously no interference.
345 if (haveDisjointAllowedRegs(G, NId, MId, D))
348 // Check that we haven't already added this edge
349 IEdgeKey EK(std::min(NId, MId), std::max(NId, MId));
353 // This is a new edge - add it to the graph.
354 if (!createInterferenceEdge(G, NId, MId, C))
355 setDisjointAllowedRegs(G, NId, MId, D);
360 // Finally, add Cur to the Active set.
367 // Create an Interference edge and add it to the graph, unless it is
368 // a null matrix, meaning the nodes' allowed registers do not have any
369 // interference. This case occurs frequently between integer and floating
370 // point registers for example.
371 // return true iff both nodes interferes.
372 bool createInterferenceEdge(PBQPRAGraph &G,
373 PBQPRAGraph::NodeId NId, PBQPRAGraph::NodeId MId,
376 const TargetRegisterInfo &TRI =
377 *G.getMetadata().MF.getSubtarget().getRegisterInfo();
378 const auto &NRegs = G.getNodeMetadata(NId).getAllowedRegs();
379 const auto &MRegs = G.getNodeMetadata(MId).getAllowedRegs();
381 // Try looking the edge costs up in the IMatrixCache first.
382 IKey K(&NRegs, &MRegs);
383 IMatrixCache::iterator I = C.find(K);
385 G.addEdgeBypassingCostAllocator(NId, MId, I->second);
389 PBQPRAGraph::RawMatrix M(NRegs.size() + 1, MRegs.size() + 1, 0);
390 bool NodesInterfere = false;
391 for (unsigned I = 0; I != NRegs.size(); ++I) {
392 unsigned PRegN = NRegs[I];
393 for (unsigned J = 0; J != MRegs.size(); ++J) {
394 unsigned PRegM = MRegs[J];
395 if (TRI.regsOverlap(PRegN, PRegM)) {
396 M[I + 1][J + 1] = std::numeric_limits<PBQP::PBQPNum>::infinity();
397 NodesInterfere = true;
405 PBQPRAGraph::EdgeId EId = G.addEdge(NId, MId, std::move(M));
406 C[K] = G.getEdgeCostsPtr(EId);
413 class Coalescing : public PBQPRAConstraint {
415 void apply(PBQPRAGraph &G) override {
416 MachineFunction &MF = G.getMetadata().MF;
417 MachineBlockFrequencyInfo &MBFI = G.getMetadata().MBFI;
418 CoalescerPair CP(*MF.getSubtarget().getRegisterInfo());
420 // Scan the machine function and add a coalescing cost whenever CoalescerPair
422 for (const auto &MBB : MF) {
423 for (const auto &MI : MBB) {
425 // Skip not-coalescable or already coalesced copies.
426 if (!CP.setRegisters(&MI) || CP.getSrcReg() == CP.getDstReg())
429 unsigned DstReg = CP.getDstReg();
430 unsigned SrcReg = CP.getSrcReg();
432 const float Scale = 1.0f / MBFI.getEntryFreq();
433 PBQP::PBQPNum CBenefit = MBFI.getBlockFreq(&MBB).getFrequency() * Scale;
436 if (!MF.getRegInfo().isAllocatable(DstReg))
439 PBQPRAGraph::NodeId NId = G.getMetadata().getNodeIdForVReg(SrcReg);
441 const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed =
442 G.getNodeMetadata(NId).getAllowedRegs();
444 unsigned PRegOpt = 0;
445 while (PRegOpt < Allowed.size() && Allowed[PRegOpt] != DstReg)
448 if (PRegOpt < Allowed.size()) {
449 PBQPRAGraph::RawVector NewCosts(G.getNodeCosts(NId));
450 NewCosts[PRegOpt + 1] -= CBenefit;
451 G.setNodeCosts(NId, std::move(NewCosts));
454 PBQPRAGraph::NodeId N1Id = G.getMetadata().getNodeIdForVReg(DstReg);
455 PBQPRAGraph::NodeId N2Id = G.getMetadata().getNodeIdForVReg(SrcReg);
456 const PBQPRAGraph::NodeMetadata::AllowedRegVector *Allowed1 =
457 &G.getNodeMetadata(N1Id).getAllowedRegs();
458 const PBQPRAGraph::NodeMetadata::AllowedRegVector *Allowed2 =
459 &G.getNodeMetadata(N2Id).getAllowedRegs();
461 PBQPRAGraph::EdgeId EId = G.findEdge(N1Id, N2Id);
462 if (EId == G.invalidEdgeId()) {
463 PBQPRAGraph::RawMatrix Costs(Allowed1->size() + 1,
464 Allowed2->size() + 1, 0);
465 addVirtRegCoalesce(Costs, *Allowed1, *Allowed2, CBenefit);
466 G.addEdge(N1Id, N2Id, std::move(Costs));
468 if (G.getEdgeNode1Id(EId) == N2Id) {
469 std::swap(N1Id, N2Id);
470 std::swap(Allowed1, Allowed2);
472 PBQPRAGraph::RawMatrix Costs(G.getEdgeCosts(EId));
473 addVirtRegCoalesce(Costs, *Allowed1, *Allowed2, CBenefit);
474 G.updateEdgeCosts(EId, std::move(Costs));
483 void addVirtRegCoalesce(
484 PBQPRAGraph::RawMatrix &CostMat,
485 const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed1,
486 const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed2,
487 PBQP::PBQPNum Benefit) {
488 assert(CostMat.getRows() == Allowed1.size() + 1 && "Size mismatch.");
489 assert(CostMat.getCols() == Allowed2.size() + 1 && "Size mismatch.");
490 for (unsigned I = 0; I != Allowed1.size(); ++I) {
491 unsigned PReg1 = Allowed1[I];
492 for (unsigned J = 0; J != Allowed2.size(); ++J) {
493 unsigned PReg2 = Allowed2[J];
495 CostMat[I + 1][J + 1] -= Benefit;
502 } // End anonymous namespace.
504 // Out-of-line destructor/anchor for PBQPRAConstraint.
505 PBQPRAConstraint::~PBQPRAConstraint() {}
506 void PBQPRAConstraint::anchor() {}
507 void PBQPRAConstraintList::anchor() {}
509 void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
510 au.setPreservesCFG();
511 au.addRequired<AAResultsWrapperPass>();
512 au.addPreserved<AAResultsWrapperPass>();
513 au.addRequired<SlotIndexes>();
514 au.addPreserved<SlotIndexes>();
515 au.addRequired<LiveIntervals>();
516 au.addPreserved<LiveIntervals>();
517 //au.addRequiredID(SplitCriticalEdgesID);
519 au.addRequiredID(*customPassID);
520 au.addRequired<LiveStacks>();
521 au.addPreserved<LiveStacks>();
522 au.addRequired<MachineBlockFrequencyInfo>();
523 au.addPreserved<MachineBlockFrequencyInfo>();
524 au.addRequired<MachineLoopInfo>();
525 au.addPreserved<MachineLoopInfo>();
526 au.addRequired<MachineDominatorTree>();
527 au.addPreserved<MachineDominatorTree>();
528 au.addRequired<VirtRegMap>();
529 au.addPreserved<VirtRegMap>();
530 MachineFunctionPass::getAnalysisUsage(au);
533 void RegAllocPBQP::findVRegIntervalsToAlloc(const MachineFunction &MF,
534 LiveIntervals &LIS) {
535 const MachineRegisterInfo &MRI = MF.getRegInfo();
537 // Iterate over all live ranges.
538 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
539 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
540 if (MRI.reg_nodbg_empty(Reg))
542 LiveInterval &LI = LIS.getInterval(Reg);
544 // If this live interval is non-empty we will use pbqp to allocate it.
545 // Empty intervals we allocate in a simple post-processing stage in
548 VRegsToAlloc.insert(LI.reg);
550 EmptyIntervalVRegs.insert(LI.reg);
555 static bool isACalleeSavedRegister(unsigned reg, const TargetRegisterInfo &TRI,
556 const MachineFunction &MF) {
557 const MCPhysReg *CSR = TRI.getCalleeSavedRegs(&MF);
558 for (unsigned i = 0; CSR[i] != 0; ++i)
559 if (TRI.regsOverlap(reg, CSR[i]))
564 void RegAllocPBQP::initializeGraph(PBQPRAGraph &G, VirtRegMap &VRM,
565 Spiller &VRegSpiller) {
566 MachineFunction &MF = G.getMetadata().MF;
568 LiveIntervals &LIS = G.getMetadata().LIS;
569 const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo();
570 const TargetRegisterInfo &TRI =
571 *G.getMetadata().MF.getSubtarget().getRegisterInfo();
573 std::vector<unsigned> Worklist(VRegsToAlloc.begin(), VRegsToAlloc.end());
575 while (!Worklist.empty()) {
576 unsigned VReg = Worklist.back();
579 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
580 LiveInterval &VRegLI = LIS.getInterval(VReg);
582 // Record any overlaps with regmask operands.
583 BitVector RegMaskOverlaps;
584 LIS.checkRegMaskInterference(VRegLI, RegMaskOverlaps);
586 // Compute an initial allowed set for the current vreg.
587 std::vector<unsigned> VRegAllowed;
588 ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF);
589 for (unsigned I = 0; I != RawPRegOrder.size(); ++I) {
590 unsigned PReg = RawPRegOrder[I];
591 if (MRI.isReserved(PReg))
594 // vregLI crosses a regmask operand that clobbers preg.
595 if (!RegMaskOverlaps.empty() && !RegMaskOverlaps.test(PReg))
598 // vregLI overlaps fixed regunit interference.
599 bool Interference = false;
600 for (MCRegUnitIterator Units(PReg, &TRI); Units.isValid(); ++Units) {
601 if (VRegLI.overlaps(LIS.getRegUnit(*Units))) {
609 // preg is usable for this virtual register.
610 VRegAllowed.push_back(PReg);
613 // Check for vregs that have no allowed registers. These should be
614 // pre-spilled and the new vregs added to the worklist.
615 if (VRegAllowed.empty()) {
616 SmallVector<unsigned, 8> NewVRegs;
617 spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller);
618 Worklist.insert(Worklist.end(), NewVRegs.begin(), NewVRegs.end());
622 PBQPRAGraph::RawVector NodeCosts(VRegAllowed.size() + 1, 0);
624 // Tweak cost of callee saved registers, as using then force spilling and
625 // restoring them. This would only happen in the prologue / epilogue though.
626 for (unsigned i = 0; i != VRegAllowed.size(); ++i)
627 if (isACalleeSavedRegister(VRegAllowed[i], TRI, MF))
628 NodeCosts[1 + i] += 1.0;
630 PBQPRAGraph::NodeId NId = G.addNode(std::move(NodeCosts));
631 G.getNodeMetadata(NId).setVReg(VReg);
632 G.getNodeMetadata(NId).setAllowedRegs(
633 G.getMetadata().getAllowedRegs(std::move(VRegAllowed)));
634 G.getMetadata().setNodeIdForVReg(VReg, NId);
638 void RegAllocPBQP::spillVReg(unsigned VReg,
639 SmallVectorImpl<unsigned> &NewIntervals,
640 MachineFunction &MF, LiveIntervals &LIS,
641 VirtRegMap &VRM, Spiller &VRegSpiller) {
643 VRegsToAlloc.erase(VReg);
644 LiveRangeEdit LRE(&LIS.getInterval(VReg), NewIntervals, MF, LIS, &VRM,
645 nullptr, &DeadRemats);
646 VRegSpiller.spill(LRE);
648 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
650 DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> SPILLED (Cost: "
651 << LRE.getParent().weight << ", New vregs: ");
653 // Copy any newly inserted live intervals into the list of regs to
655 for (LiveRangeEdit::iterator I = LRE.begin(), E = LRE.end();
657 const LiveInterval &LI = LIS.getInterval(*I);
658 assert(!LI.empty() && "Empty spill range.");
659 DEBUG(dbgs() << PrintReg(LI.reg, &TRI) << " ");
660 VRegsToAlloc.insert(LI.reg);
663 DEBUG(dbgs() << ")\n");
666 bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAGraph &G,
667 const PBQP::Solution &Solution,
669 Spiller &VRegSpiller) {
670 MachineFunction &MF = G.getMetadata().MF;
671 LiveIntervals &LIS = G.getMetadata().LIS;
672 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
675 // Set to true if we have any spills
676 bool AnotherRoundNeeded = false;
678 // Clear the existing allocation.
681 // Iterate over the nodes mapping the PBQP solution to a register
683 for (auto NId : G.nodeIds()) {
684 unsigned VReg = G.getNodeMetadata(NId).getVReg();
685 unsigned AllocOption = Solution.getSelection(NId);
687 if (AllocOption != PBQP::RegAlloc::getSpillOptionIdx()) {
688 unsigned PReg = G.getNodeMetadata(NId).getAllowedRegs()[AllocOption - 1];
689 DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> "
690 << TRI.getName(PReg) << "\n");
691 assert(PReg != 0 && "Invalid preg selected.");
692 VRM.assignVirt2Phys(VReg, PReg);
694 // Spill VReg. If this introduces new intervals we'll need another round
696 SmallVector<unsigned, 8> NewVRegs;
697 spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller);
698 AnotherRoundNeeded |= !NewVRegs.empty();
702 return !AnotherRoundNeeded;
705 void RegAllocPBQP::finalizeAlloc(MachineFunction &MF,
707 VirtRegMap &VRM) const {
708 MachineRegisterInfo &MRI = MF.getRegInfo();
710 // First allocate registers for the empty intervals.
711 for (RegSet::const_iterator
712 I = EmptyIntervalVRegs.begin(), E = EmptyIntervalVRegs.end();
714 LiveInterval &LI = LIS.getInterval(*I);
716 unsigned PReg = MRI.getSimpleHint(LI.reg);
719 const TargetRegisterClass &RC = *MRI.getRegClass(LI.reg);
720 PReg = RC.getRawAllocationOrder(MF).front();
723 VRM.assignVirt2Phys(LI.reg, PReg);
727 void RegAllocPBQP::postOptimization(Spiller &VRegSpiller, LiveIntervals &LIS) {
728 VRegSpiller.postOptimization();
729 /// Remove dead defs because of rematerialization.
730 for (auto DeadInst : DeadRemats) {
731 LIS.RemoveMachineInstrFromMaps(*DeadInst);
732 DeadInst->eraseFromParent();
737 static inline float normalizePBQPSpillWeight(float UseDefFreq, unsigned Size,
739 // All intervals have a spill weight that is mostly proportional to the number
740 // of uses, with uses in loops having a bigger weight.
741 return NumInstr * normalizeSpillWeight(UseDefFreq, Size, 1);
744 bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
745 LiveIntervals &LIS = getAnalysis<LiveIntervals>();
746 MachineBlockFrequencyInfo &MBFI =
747 getAnalysis<MachineBlockFrequencyInfo>();
749 VirtRegMap &VRM = getAnalysis<VirtRegMap>();
751 calculateSpillWeightsAndHints(LIS, MF, &VRM, getAnalysis<MachineLoopInfo>(),
752 MBFI, normalizePBQPSpillWeight);
754 std::unique_ptr<Spiller> VRegSpiller(createInlineSpiller(*this, MF, VRM));
756 MF.getRegInfo().freezeReservedRegs(MF);
758 DEBUG(dbgs() << "PBQP Register Allocating for " << MF.getName() << "\n");
760 // Allocator main loop:
762 // * Map current regalloc problem to a PBQP problem
763 // * Solve the PBQP problem
764 // * Map the solution back to a register allocation
765 // * Spill if necessary
767 // This process is continued till no more spills are generated.
769 // Find the vreg intervals in need of allocation.
770 findVRegIntervalsToAlloc(MF, LIS);
773 const Function &F = *MF.getFunction();
774 std::string FullyQualifiedName =
775 F.getParent()->getModuleIdentifier() + "." + F.getName().str();
778 // If there are non-empty intervals allocate them using pbqp.
779 if (!VRegsToAlloc.empty()) {
781 const TargetSubtargetInfo &Subtarget = MF.getSubtarget();
782 std::unique_ptr<PBQPRAConstraintList> ConstraintsRoot =
783 llvm::make_unique<PBQPRAConstraintList>();
784 ConstraintsRoot->addConstraint(llvm::make_unique<SpillCosts>());
785 ConstraintsRoot->addConstraint(llvm::make_unique<Interference>());
787 ConstraintsRoot->addConstraint(llvm::make_unique<Coalescing>());
788 ConstraintsRoot->addConstraint(Subtarget.getCustomPBQPConstraints());
790 bool PBQPAllocComplete = false;
793 while (!PBQPAllocComplete) {
794 DEBUG(dbgs() << " PBQP Regalloc round " << Round << ":\n");
796 PBQPRAGraph G(PBQPRAGraph::GraphMetadata(MF, LIS, MBFI));
797 initializeGraph(G, VRM, *VRegSpiller);
798 ConstraintsRoot->apply(G);
801 if (PBQPDumpGraphs) {
802 std::ostringstream RS;
804 std::string GraphFileName = FullyQualifiedName + "." + RS.str() +
807 raw_fd_ostream OS(GraphFileName, EC, sys::fs::F_Text);
808 DEBUG(dbgs() << "Dumping graph for round " << Round << " to \""
809 << GraphFileName << "\"\n");
814 PBQP::Solution Solution = PBQP::RegAlloc::solve(G);
815 PBQPAllocComplete = mapPBQPToRegAlloc(G, Solution, VRM, *VRegSpiller);
820 // Finalise allocation, allocate empty ranges.
821 finalizeAlloc(MF, LIS, VRM);
822 postOptimization(*VRegSpiller, LIS);
823 VRegsToAlloc.clear();
824 EmptyIntervalVRegs.clear();
826 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << VRM << "\n");
831 /// Create Printable object for node and register info.
832 static Printable PrintNodeInfo(PBQP::RegAlloc::PBQPRAGraph::NodeId NId,
833 const PBQP::RegAlloc::PBQPRAGraph &G) {
834 return Printable([NId, &G](raw_ostream &OS) {
835 const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo();
836 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
837 unsigned VReg = G.getNodeMetadata(NId).getVReg();
838 const char *RegClassName = TRI->getRegClassName(MRI.getRegClass(VReg));
839 OS << NId << " (" << RegClassName << ':' << PrintReg(VReg, TRI) << ')';
843 void PBQP::RegAlloc::PBQPRAGraph::dump(raw_ostream &OS) const {
844 for (auto NId : nodeIds()) {
845 const Vector &Costs = getNodeCosts(NId);
846 assert(Costs.getLength() != 0 && "Empty vector in graph.");
847 OS << PrintNodeInfo(NId, *this) << ": " << Costs << '\n';
851 for (auto EId : edgeIds()) {
852 NodeId N1Id = getEdgeNode1Id(EId);
853 NodeId N2Id = getEdgeNode2Id(EId);
854 assert(N1Id != N2Id && "PBQP graphs should not have self-edges.");
855 const Matrix &M = getEdgeCosts(EId);
856 assert(M.getRows() != 0 && "No rows in matrix.");
857 assert(M.getCols() != 0 && "No cols in matrix.");
858 OS << PrintNodeInfo(N1Id, *this) << ' ' << M.getRows() << " rows / ";
859 OS << PrintNodeInfo(N2Id, *this) << ' ' << M.getCols() << " cols:\n";
864 LLVM_DUMP_METHOD void PBQP::RegAlloc::PBQPRAGraph::dump() const { dump(dbgs()); }
866 void PBQP::RegAlloc::PBQPRAGraph::printDot(raw_ostream &OS) const {
868 for (auto NId : nodeIds()) {
869 OS << " node" << NId << " [ label=\""
870 << PrintNodeInfo(NId, *this) << "\\n"
871 << getNodeCosts(NId) << "\" ]\n";
874 OS << " edge [ len=" << nodeIds().size() << " ]\n";
875 for (auto EId : edgeIds()) {
876 OS << " node" << getEdgeNode1Id(EId)
877 << " -- node" << getEdgeNode2Id(EId)
879 const Matrix &EdgeCosts = getEdgeCosts(EId);
880 for (unsigned i = 0; i < EdgeCosts.getRows(); ++i) {
881 OS << EdgeCosts.getRowAsVector(i) << "\\n";
888 FunctionPass *llvm::createPBQPRegisterAllocator(char *customPassID) {
889 return new RegAllocPBQP(customPassID);
892 FunctionPass* llvm::createDefaultPBQPRegisterAllocator() {
893 return createPBQPRegisterAllocator();