1 //===- RegisterCoalescer.cpp - Generic Register Coalescing Interface ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the generic RegisterCoalescer interface which
11 // is used as the common interface used by all clients and
12 // implementations of register coalescing.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterCoalescer.h"
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/DenseSet.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/SmallPtrSet.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/Analysis/AliasAnalysis.h"
25 #include "llvm/CodeGen/LiveInterval.h"
26 #include "llvm/CodeGen/LiveIntervals.h"
27 #include "llvm/CodeGen/LiveRangeEdit.h"
28 #include "llvm/CodeGen/MachineBasicBlock.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineInstr.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineLoopInfo.h"
34 #include "llvm/CodeGen/MachineOperand.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/RegisterClassInfo.h"
38 #include "llvm/CodeGen/SlotIndexes.h"
39 #include "llvm/CodeGen/TargetInstrInfo.h"
40 #include "llvm/CodeGen/TargetOpcodes.h"
41 #include "llvm/CodeGen/TargetRegisterInfo.h"
42 #include "llvm/CodeGen/TargetSubtargetInfo.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/MC/LaneBitmask.h"
45 #include "llvm/MC/MCInstrDesc.h"
46 #include "llvm/MC/MCRegisterInfo.h"
47 #include "llvm/Pass.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Compiler.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/raw_ostream.h"
63 #define DEBUG_TYPE "regalloc"
65 STATISTIC(numJoins , "Number of interval joins performed");
66 STATISTIC(numCrossRCs , "Number of cross class joins performed");
67 STATISTIC(numCommutes , "Number of instruction commuting performed");
68 STATISTIC(numExtends , "Number of copies extended");
69 STATISTIC(NumReMats , "Number of instructions re-materialized");
70 STATISTIC(NumInflated , "Number of register classes inflated");
71 STATISTIC(NumLaneConflicts, "Number of dead lane conflicts tested");
72 STATISTIC(NumLaneResolves, "Number of dead lane conflicts resolved");
73 STATISTIC(NumShrinkToUses, "Number of shrinkToUses called");
75 static cl::opt<bool> EnableJoining("join-liveintervals",
76 cl::desc("Coalesce copies (default=true)"),
77 cl::init(true), cl::Hidden);
79 static cl::opt<bool> UseTerminalRule("terminal-rule",
80 cl::desc("Apply the terminal rule"),
81 cl::init(false), cl::Hidden);
83 /// Temporary flag to test critical edge unsplitting.
85 EnableJoinSplits("join-splitedges",
86 cl::desc("Coalesce copies on split edges (default=subtarget)"), cl::Hidden);
88 /// Temporary flag to test global copy optimization.
89 static cl::opt<cl::boolOrDefault>
90 EnableGlobalCopies("join-globalcopies",
91 cl::desc("Coalesce copies that span blocks (default=subtarget)"),
92 cl::init(cl::BOU_UNSET), cl::Hidden);
95 VerifyCoalescing("verify-coalescing",
96 cl::desc("Verify machine instrs before and after register coalescing"),
99 static cl::opt<unsigned> LateRematUpdateThreshold(
100 "late-remat-update-threshold", cl::Hidden,
101 cl::desc("During rematerialization for a copy, if the def instruction has "
102 "many other copy uses to be rematerialized, delay the multiple "
103 "separate live interval update work and do them all at once after "
104 "all those rematerialization are done. It will save a lot of "
110 class RegisterCoalescer : public MachineFunctionPass,
111 private LiveRangeEdit::Delegate {
113 MachineRegisterInfo* MRI;
114 const TargetRegisterInfo* TRI;
115 const TargetInstrInfo* TII;
117 const MachineLoopInfo* Loops;
119 RegisterClassInfo RegClassInfo;
121 /// A LaneMask to remember on which subregister live ranges we need to call
122 /// shrinkToUses() later.
123 LaneBitmask ShrinkMask;
125 /// True if the main range of the currently coalesced intervals should be
126 /// checked for smaller live intervals.
127 bool ShrinkMainRange;
129 /// True if the coalescer should aggressively coalesce global copies
130 /// in favor of keeping local copies.
131 bool JoinGlobalCopies;
133 /// True if the coalescer should aggressively coalesce fall-thru
134 /// blocks exclusively containing copies.
137 /// Copy instructions yet to be coalesced.
138 SmallVector<MachineInstr*, 8> WorkList;
139 SmallVector<MachineInstr*, 8> LocalWorkList;
141 /// Set of instruction pointers that have been erased, and
142 /// that may be present in WorkList.
143 SmallPtrSet<MachineInstr*, 8> ErasedInstrs;
145 /// Dead instructions that are about to be deleted.
146 SmallVector<MachineInstr*, 8> DeadDefs;
148 /// Virtual registers to be considered for register class inflation.
149 SmallVector<unsigned, 8> InflateRegs;
151 /// The collection of live intervals which should have been updated
152 /// immediately after rematerialiation but delayed until
153 /// lateLiveIntervalUpdate is called.
154 DenseSet<unsigned> ToBeUpdated;
156 /// Recursively eliminate dead defs in DeadDefs.
157 void eliminateDeadDefs();
159 /// LiveRangeEdit callback for eliminateDeadDefs().
160 void LRE_WillEraseInstruction(MachineInstr *MI) override;
162 /// Coalesce the LocalWorkList.
163 void coalesceLocals();
165 /// Join compatible live intervals
166 void joinAllIntervals();
168 /// Coalesce copies in the specified MBB, putting
169 /// copies that cannot yet be coalesced into WorkList.
170 void copyCoalesceInMBB(MachineBasicBlock *MBB);
172 /// Tries to coalesce all copies in CurrList. Returns true if any progress
174 bool copyCoalesceWorkList(MutableArrayRef<MachineInstr*> CurrList);
176 /// If one def has many copy like uses, and those copy uses are all
177 /// rematerialized, the live interval update needed for those
178 /// rematerializations will be delayed and done all at once instead
179 /// of being done multiple times. This is to save compile cost because
180 /// live interval update is costly.
181 void lateLiveIntervalUpdate();
183 /// Attempt to join intervals corresponding to SrcReg/DstReg, which are the
184 /// src/dst of the copy instruction CopyMI. This returns true if the copy
185 /// was successfully coalesced away. If it is not currently possible to
186 /// coalesce this interval, but it may be possible if other things get
187 /// coalesced, then it returns true by reference in 'Again'.
188 bool joinCopy(MachineInstr *CopyMI, bool &Again);
190 /// Attempt to join these two intervals. On failure, this
191 /// returns false. The output "SrcInt" will not have been modified, so we
192 /// can use this information below to update aliases.
193 bool joinIntervals(CoalescerPair &CP);
195 /// Attempt joining two virtual registers. Return true on success.
196 bool joinVirtRegs(CoalescerPair &CP);
198 /// Attempt joining with a reserved physreg.
199 bool joinReservedPhysReg(CoalescerPair &CP);
201 /// Add the LiveRange @p ToMerge as a subregister liverange of @p LI.
202 /// Subranges in @p LI which only partially interfere with the desired
203 /// LaneMask are split as necessary. @p LaneMask are the lanes that
204 /// @p ToMerge will occupy in the coalescer register. @p LI has its subrange
205 /// lanemasks already adjusted to the coalesced register.
206 void mergeSubRangeInto(LiveInterval &LI, const LiveRange &ToMerge,
207 LaneBitmask LaneMask, CoalescerPair &CP);
209 /// Join the liveranges of two subregisters. Joins @p RRange into
210 /// @p LRange, @p RRange may be invalid afterwards.
211 void joinSubRegRanges(LiveRange &LRange, LiveRange &RRange,
212 LaneBitmask LaneMask, const CoalescerPair &CP);
214 /// We found a non-trivially-coalescable copy. If the source value number is
215 /// defined by a copy from the destination reg see if we can merge these two
216 /// destination reg valno# into a single value number, eliminating a copy.
217 /// This returns true if an interval was modified.
218 bool adjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
220 /// Return true if there are definitions of IntB
221 /// other than BValNo val# that can reach uses of AValno val# of IntA.
222 bool hasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
223 VNInfo *AValNo, VNInfo *BValNo);
225 /// We found a non-trivially-coalescable copy.
226 /// If the source value number is defined by a commutable instruction and
227 /// its other operand is coalesced to the copy dest register, see if we
228 /// can transform the copy into a noop by commuting the definition.
229 /// This returns a pair of two flags:
230 /// - the first element is true if an interval was modified,
231 /// - the second element is true if the destination interval needs
232 /// to be shrunk after deleting the copy.
233 std::pair<bool,bool> removeCopyByCommutingDef(const CoalescerPair &CP,
234 MachineInstr *CopyMI);
236 /// We found a copy which can be moved to its less frequent predecessor.
237 bool removePartialRedundancy(const CoalescerPair &CP, MachineInstr &CopyMI);
239 /// If the source of a copy is defined by a
240 /// trivial computation, replace the copy by rematerialize the definition.
241 bool reMaterializeTrivialDef(const CoalescerPair &CP, MachineInstr *CopyMI,
244 /// Return true if a copy involving a physreg should be joined.
245 bool canJoinPhys(const CoalescerPair &CP);
247 /// Replace all defs and uses of SrcReg to DstReg and update the subregister
248 /// number if it is not zero. If DstReg is a physical register and the
249 /// existing subregister number of the def / use being updated is not zero,
250 /// make sure to set it to the correct physical subregister.
251 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
253 /// If the given machine operand reads only undefined lanes add an undef
255 /// This can happen when undef uses were previously concealed by a copy
256 /// which we coalesced. Example:
257 /// %0:sub0<def,read-undef> = ...
258 /// %1 = COPY %0 <-- Coalescing COPY reveals undef
259 /// = use %1:sub1 <-- hidden undef use
260 void addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
261 MachineOperand &MO, unsigned SubRegIdx);
263 /// Handle copies of undef values. If the undef value is an incoming
264 /// PHI value, it will convert @p CopyMI to an IMPLICIT_DEF.
265 /// Returns nullptr if @p CopyMI was not in any way eliminable. Otherwise,
266 /// it returns @p CopyMI (which could be an IMPLICIT_DEF at this point).
267 MachineInstr *eliminateUndefCopy(MachineInstr *CopyMI);
269 /// Check whether or not we should apply the terminal rule on the
270 /// destination (Dst) of \p Copy.
271 /// When the terminal rule applies, Copy is not profitable to
273 /// Dst is terminal if it has exactly one affinity (Dst, Src) and
274 /// at least one interference (Dst, Dst2). If Dst is terminal, the
275 /// terminal rule consists in checking that at least one of
276 /// interfering node, say Dst2, has an affinity of equal or greater
278 /// In that case, Dst2 and Dst will not be able to be both coalesced
279 /// with Src. Since Dst2 exposes more coalescing opportunities than
280 /// Dst, we can drop \p Copy.
281 bool applyTerminalRule(const MachineInstr &Copy) const;
283 /// Wrapper method for \see LiveIntervals::shrinkToUses.
284 /// This method does the proper fixing of the live-ranges when the afore
285 /// mentioned method returns true.
286 void shrinkToUses(LiveInterval *LI,
287 SmallVectorImpl<MachineInstr * > *Dead = nullptr) {
289 if (LIS->shrinkToUses(LI, Dead)) {
290 /// Check whether or not \p LI is composed by multiple connected
291 /// components and if that is the case, fix that.
292 SmallVector<LiveInterval*, 8> SplitLIs;
293 LIS->splitSeparateComponents(*LI, SplitLIs);
297 /// Wrapper Method to do all the necessary work when an Instruction is
299 /// Optimizations should use this to make sure that deleted instructions
300 /// are always accounted for.
301 void deleteInstr(MachineInstr* MI) {
302 ErasedInstrs.insert(MI);
303 LIS->RemoveMachineInstrFromMaps(*MI);
304 MI->eraseFromParent();
308 static char ID; ///< Class identification, replacement for typeinfo
310 RegisterCoalescer() : MachineFunctionPass(ID) {
311 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
314 void getAnalysisUsage(AnalysisUsage &AU) const override;
316 void releaseMemory() override;
318 /// This is the pass entry point.
319 bool runOnMachineFunction(MachineFunction&) override;
321 /// Implement the dump method.
322 void print(raw_ostream &O, const Module* = nullptr) const override;
325 } // end anonymous namespace
327 char RegisterCoalescer::ID = 0;
329 char &llvm::RegisterCoalescerID = RegisterCoalescer::ID;
331 INITIALIZE_PASS_BEGIN(RegisterCoalescer, "simple-register-coalescing",
332 "Simple Register Coalescing", false, false)
333 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
334 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
335 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
336 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
337 INITIALIZE_PASS_END(RegisterCoalescer, "simple-register-coalescing",
338 "Simple Register Coalescing", false, false)
340 static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI,
341 unsigned &Src, unsigned &Dst,
342 unsigned &SrcSub, unsigned &DstSub) {
344 Dst = MI->getOperand(0).getReg();
345 DstSub = MI->getOperand(0).getSubReg();
346 Src = MI->getOperand(1).getReg();
347 SrcSub = MI->getOperand(1).getSubReg();
348 } else if (MI->isSubregToReg()) {
349 Dst = MI->getOperand(0).getReg();
350 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(),
351 MI->getOperand(3).getImm());
352 Src = MI->getOperand(2).getReg();
353 SrcSub = MI->getOperand(2).getSubReg();
359 /// Return true if this block should be vacated by the coalescer to eliminate
360 /// branches. The important cases to handle in the coalescer are critical edges
361 /// split during phi elimination which contain only copies. Simple blocks that
362 /// contain non-branches should also be vacated, but this can be handled by an
363 /// earlier pass similar to early if-conversion.
364 static bool isSplitEdge(const MachineBasicBlock *MBB) {
365 if (MBB->pred_size() != 1 || MBB->succ_size() != 1)
368 for (const auto &MI : *MBB) {
369 if (!MI.isCopyLike() && !MI.isUnconditionalBranch())
375 bool CoalescerPair::setRegisters(const MachineInstr *MI) {
379 Flipped = CrossClass = false;
381 unsigned Src, Dst, SrcSub, DstSub;
382 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
384 Partial = SrcSub || DstSub;
386 // If one register is a physreg, it must be Dst.
387 if (TargetRegisterInfo::isPhysicalRegister(Src)) {
388 if (TargetRegisterInfo::isPhysicalRegister(Dst))
391 std::swap(SrcSub, DstSub);
395 const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
397 if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
398 // Eliminate DstSub on a physreg.
400 Dst = TRI.getSubReg(Dst, DstSub);
401 if (!Dst) return false;
405 // Eliminate SrcSub by picking a corresponding Dst superregister.
407 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
408 if (!Dst) return false;
409 } else if (!MRI.getRegClass(Src)->contains(Dst)) {
413 // Both registers are virtual.
414 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
415 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
417 // Both registers have subreg indices.
418 if (SrcSub && DstSub) {
419 // Copies between different sub-registers are never coalescable.
420 if (Src == Dst && SrcSub != DstSub)
423 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
428 // SrcReg will be merged with a sub-register of DstReg.
430 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
432 // DstReg will be merged with a sub-register of SrcReg.
434 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
436 // This is a straight copy without sub-registers.
437 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
440 // The combined constraint may be impossible to satisfy.
444 // Prefer SrcReg to be a sub-register of DstReg.
445 // FIXME: Coalescer should support subregs symmetrically.
446 if (DstIdx && !SrcIdx) {
448 std::swap(SrcIdx, DstIdx);
452 CrossClass = NewRC != DstRC || NewRC != SrcRC;
454 // Check our invariants
455 assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual");
456 assert(!(TargetRegisterInfo::isPhysicalRegister(Dst) && DstSub) &&
457 "Cannot have a physical SubIdx");
463 bool CoalescerPair::flip() {
464 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
466 std::swap(SrcReg, DstReg);
467 std::swap(SrcIdx, DstIdx);
472 bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
475 unsigned Src, Dst, SrcSub, DstSub;
476 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
479 // Find the virtual register that is SrcReg.
482 std::swap(SrcSub, DstSub);
483 } else if (Src != SrcReg) {
487 // Now check that Dst matches DstReg.
488 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
489 if (!TargetRegisterInfo::isPhysicalRegister(Dst))
491 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state.");
492 // DstSub could be set for a physreg from INSERT_SUBREG.
494 Dst = TRI.getSubReg(Dst, DstSub);
497 return DstReg == Dst;
498 // This is a partial register copy. Check that the parts match.
499 return TRI.getSubReg(DstReg, SrcSub) == Dst;
501 // DstReg is virtual.
504 // Registers match, do the subregisters line up?
505 return TRI.composeSubRegIndices(SrcIdx, SrcSub) ==
506 TRI.composeSubRegIndices(DstIdx, DstSub);
510 void RegisterCoalescer::getAnalysisUsage(AnalysisUsage &AU) const {
511 AU.setPreservesCFG();
512 AU.addRequired<AAResultsWrapperPass>();
513 AU.addRequired<LiveIntervals>();
514 AU.addPreserved<LiveIntervals>();
515 AU.addPreserved<SlotIndexes>();
516 AU.addRequired<MachineLoopInfo>();
517 AU.addPreserved<MachineLoopInfo>();
518 AU.addPreservedID(MachineDominatorsID);
519 MachineFunctionPass::getAnalysisUsage(AU);
522 void RegisterCoalescer::eliminateDeadDefs() {
523 SmallVector<unsigned, 8> NewRegs;
524 LiveRangeEdit(nullptr, NewRegs, *MF, *LIS,
525 nullptr, this).eliminateDeadDefs(DeadDefs);
528 void RegisterCoalescer::LRE_WillEraseInstruction(MachineInstr *MI) {
529 // MI may be in WorkList. Make sure we don't visit it.
530 ErasedInstrs.insert(MI);
533 bool RegisterCoalescer::adjustCopiesBackFrom(const CoalescerPair &CP,
534 MachineInstr *CopyMI) {
535 assert(!CP.isPartial() && "This doesn't work for partial copies.");
536 assert(!CP.isPhys() && "This doesn't work for physreg copies.");
539 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
541 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
542 SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
544 // We have a non-trivially-coalescable copy with IntA being the source and
545 // IntB being the dest, thus this defines a value number in IntB. If the
546 // source value number (in IntA) is defined by a copy from B, see if we can
547 // merge these two pieces of B into a single value number, eliminating a copy.
552 // B1 = A3 <- this copy
554 // In this case, B0 can be extended to where the B1 copy lives, allowing the
555 // B1 value number to be replaced with B0 (which simplifies the B
558 // BValNo is a value number in B that is defined by a copy from A. 'B1' in
559 // the example above.
560 LiveInterval::iterator BS = IntB.FindSegmentContaining(CopyIdx);
561 if (BS == IntB.end()) return false;
562 VNInfo *BValNo = BS->valno;
564 // Get the location that B is defined at. Two options: either this value has
565 // an unknown definition point or it is defined at CopyIdx. If unknown, we
567 if (BValNo->def != CopyIdx) return false;
569 // AValNo is the value number in A that defines the copy, A3 in the example.
570 SlotIndex CopyUseIdx = CopyIdx.getRegSlot(true);
571 LiveInterval::iterator AS = IntA.FindSegmentContaining(CopyUseIdx);
572 // The live segment might not exist after fun with physreg coalescing.
573 if (AS == IntA.end()) return false;
574 VNInfo *AValNo = AS->valno;
576 // If AValNo is defined as a copy from IntB, we can potentially process this.
577 // Get the instruction that defines this value number.
578 MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def);
579 // Don't allow any partial copies, even if isCoalescable() allows them.
580 if (!CP.isCoalescable(ACopyMI) || !ACopyMI->isFullCopy())
583 // Get the Segment in IntB that this value number starts with.
584 LiveInterval::iterator ValS =
585 IntB.FindSegmentContaining(AValNo->def.getPrevSlot());
586 if (ValS == IntB.end())
589 // Make sure that the end of the live segment is inside the same block as
591 MachineInstr *ValSEndInst =
592 LIS->getInstructionFromIndex(ValS->end.getPrevSlot());
593 if (!ValSEndInst || ValSEndInst->getParent() != CopyMI->getParent())
596 // Okay, we now know that ValS ends in the same block that the CopyMI
597 // live-range starts. If there are no intervening live segments between them
598 // in IntB, we can merge them.
599 if (ValS+1 != BS) return false;
601 LLVM_DEBUG(dbgs() << "Extending: " << printReg(IntB.reg, TRI));
603 SlotIndex FillerStart = ValS->end, FillerEnd = BS->start;
604 // We are about to delete CopyMI, so need to remove it as the 'instruction
605 // that defines this value #'. Update the valnum with the new defining
607 BValNo->def = FillerStart;
609 // Okay, we can merge them. We need to insert a new liverange:
610 // [ValS.end, BS.begin) of either value number, then we merge the
611 // two value numbers.
612 IntB.addSegment(LiveInterval::Segment(FillerStart, FillerEnd, BValNo));
614 // Okay, merge "B1" into the same value number as "B0".
615 if (BValNo != ValS->valno)
616 IntB.MergeValueNumberInto(BValNo, ValS->valno);
618 // Do the same for the subregister segments.
619 for (LiveInterval::SubRange &S : IntB.subranges()) {
620 // Check for SubRange Segments of the form [1234r,1234d:0) which can be
621 // removed to prevent creating bogus SubRange Segments.
622 LiveInterval::iterator SS = S.FindSegmentContaining(CopyIdx);
623 if (SS != S.end() && SlotIndex::isSameInstr(SS->start, SS->end)) {
624 S.removeSegment(*SS, true);
627 VNInfo *SubBValNo = S.getVNInfoAt(CopyIdx);
628 S.addSegment(LiveInterval::Segment(FillerStart, FillerEnd, SubBValNo));
629 VNInfo *SubValSNo = S.getVNInfoAt(AValNo->def.getPrevSlot());
630 if (SubBValNo != SubValSNo)
631 S.MergeValueNumberInto(SubBValNo, SubValSNo);
634 LLVM_DEBUG(dbgs() << " result = " << IntB << '\n');
636 // If the source instruction was killing the source register before the
637 // merge, unset the isKill marker given the live range has been extended.
638 int UIdx = ValSEndInst->findRegisterUseOperandIdx(IntB.reg, true);
640 ValSEndInst->getOperand(UIdx).setIsKill(false);
644 CopyMI->substituteRegister(IntA.reg, IntB.reg, 0, *TRI);
645 // If the copy instruction was killing the destination register or any
646 // subrange before the merge trim the live range.
647 bool RecomputeLiveRange = AS->end == CopyIdx;
648 if (!RecomputeLiveRange) {
649 for (LiveInterval::SubRange &S : IntA.subranges()) {
650 LiveInterval::iterator SS = S.FindSegmentContaining(CopyUseIdx);
651 if (SS != S.end() && SS->end == CopyIdx) {
652 RecomputeLiveRange = true;
657 if (RecomputeLiveRange)
664 bool RegisterCoalescer::hasOtherReachingDefs(LiveInterval &IntA,
668 // If AValNo has PHI kills, conservatively assume that IntB defs can reach
670 if (LIS->hasPHIKill(IntA, AValNo))
673 for (LiveRange::Segment &ASeg : IntA.segments) {
674 if (ASeg.valno != AValNo) continue;
675 LiveInterval::iterator BI =
676 std::upper_bound(IntB.begin(), IntB.end(), ASeg.start);
677 if (BI != IntB.begin())
679 for (; BI != IntB.end() && ASeg.end >= BI->start; ++BI) {
680 if (BI->valno == BValNo)
682 if (BI->start <= ASeg.start && BI->end > ASeg.start)
684 if (BI->start > ASeg.start && BI->start < ASeg.end)
691 /// Copy segments with value number @p SrcValNo from liverange @p Src to live
692 /// range @Dst and use value number @p DstValNo there.
693 static std::pair<bool,bool>
694 addSegmentsWithValNo(LiveRange &Dst, VNInfo *DstValNo, const LiveRange &Src,
695 const VNInfo *SrcValNo) {
696 bool Changed = false;
697 bool MergedWithDead = false;
698 for (const LiveRange::Segment &S : Src.segments) {
699 if (S.valno != SrcValNo)
701 // This is adding a segment from Src that ends in a copy that is about
702 // to be removed. This segment is going to be merged with a pre-existing
703 // segment in Dst. This works, except in cases when the corresponding
704 // segment in Dst is dead. For example: adding [192r,208r:1) from Src
705 // to [208r,208d:1) in Dst would create [192r,208d:1) in Dst.
706 // Recognized such cases, so that the segments can be shrunk.
707 LiveRange::Segment Added = LiveRange::Segment(S.start, S.end, DstValNo);
708 LiveRange::Segment &Merged = *Dst.addSegment(Added);
709 if (Merged.end.isDead())
710 MergedWithDead = true;
713 return std::make_pair(Changed, MergedWithDead);
717 RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
718 MachineInstr *CopyMI) {
719 assert(!CP.isPhys());
722 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
724 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
726 // We found a non-trivially-coalescable copy with IntA being the source and
727 // IntB being the dest, thus this defines a value number in IntB. If the
728 // source value number (in IntA) is defined by a commutable instruction and
729 // its other operand is coalesced to the copy dest register, see if we can
730 // transform the copy into a noop by commuting the definition. For example,
732 // A3 = op A2 killed B0
734 // B1 = A3 <- this copy
736 // = op A3 <- more uses
740 // B2 = op B0 killed A2
742 // B1 = B2 <- now an identity copy
744 // = op B2 <- more uses
746 // BValNo is a value number in B that is defined by a copy from A. 'B1' in
747 // the example above.
748 SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
749 VNInfo *BValNo = IntB.getVNInfoAt(CopyIdx);
750 assert(BValNo != nullptr && BValNo->def == CopyIdx);
752 // AValNo is the value number in A that defines the copy, A3 in the example.
753 VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getRegSlot(true));
754 assert(AValNo && !AValNo->isUnused() && "COPY source not live");
755 if (AValNo->isPHIDef())
756 return { false, false };
757 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
759 return { false, false };
760 if (!DefMI->isCommutable())
761 return { false, false };
762 // If DefMI is a two-address instruction then commuting it will change the
763 // destination register.
764 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
765 assert(DefIdx != -1);
767 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
768 return { false, false };
770 // FIXME: The code below tries to commute 'UseOpIdx' operand with some other
771 // commutable operand which is expressed by 'CommuteAnyOperandIndex'value
772 // passed to the method. That _other_ operand is chosen by
773 // the findCommutedOpIndices() method.
775 // That is obviously an area for improvement in case of instructions having
776 // more than 2 operands. For example, if some instruction has 3 commutable
777 // operands then all possible variants (i.e. op#1<->op#2, op#1<->op#3,
778 // op#2<->op#3) of commute transformation should be considered/tried here.
779 unsigned NewDstIdx = TargetInstrInfo::CommuteAnyOperandIndex;
780 if (!TII->findCommutedOpIndices(*DefMI, UseOpIdx, NewDstIdx))
781 return { false, false };
783 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
784 unsigned NewReg = NewDstMO.getReg();
785 if (NewReg != IntB.reg || !IntB.Query(AValNo->def).isKill())
786 return { false, false };
788 // Make sure there are no other definitions of IntB that would reach the
789 // uses which the new definition can reach.
790 if (hasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
791 return { false, false };
793 // If some of the uses of IntA.reg is already coalesced away, return false.
794 // It's not possible to determine whether it's safe to perform the coalescing.
795 for (MachineOperand &MO : MRI->use_nodbg_operands(IntA.reg)) {
796 MachineInstr *UseMI = MO.getParent();
797 unsigned OpNo = &MO - &UseMI->getOperand(0);
798 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI);
799 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
800 if (US == IntA.end() || US->valno != AValNo)
802 // If this use is tied to a def, we can't rewrite the register.
803 if (UseMI->isRegTiedToDefOperand(OpNo))
804 return { false, false };
807 LLVM_DEBUG(dbgs() << "\tremoveCopyByCommutingDef: " << AValNo->def << '\t'
810 // At this point we have decided that it is legal to do this
811 // transformation. Start by commuting the instruction.
812 MachineBasicBlock *MBB = DefMI->getParent();
813 MachineInstr *NewMI =
814 TII->commuteInstruction(*DefMI, false, UseOpIdx, NewDstIdx);
816 return { false, false };
817 if (TargetRegisterInfo::isVirtualRegister(IntA.reg) &&
818 TargetRegisterInfo::isVirtualRegister(IntB.reg) &&
819 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
820 return { false, false };
821 if (NewMI != DefMI) {
822 LIS->ReplaceMachineInstrInMaps(*DefMI, *NewMI);
823 MachineBasicBlock::iterator Pos = DefMI;
824 MBB->insert(Pos, NewMI);
828 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
837 // Update uses of IntA of the specific Val# with IntB.
838 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(IntA.reg),
840 UI != UE; /* ++UI is below because of possible MI removal */) {
841 MachineOperand &UseMO = *UI;
845 MachineInstr *UseMI = UseMO.getParent();
846 if (UseMI->isDebugValue()) {
847 // FIXME These don't have an instruction index. Not clear we have enough
848 // info to decide whether to do this replacement or not. For now do it.
849 UseMO.setReg(NewReg);
852 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true);
853 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
854 assert(US != IntA.end() && "Use must be live");
855 if (US->valno != AValNo)
857 // Kill flags are no longer accurate. They are recomputed after RA.
858 UseMO.setIsKill(false);
859 if (TargetRegisterInfo::isPhysicalRegister(NewReg))
860 UseMO.substPhysReg(NewReg, *TRI);
862 UseMO.setReg(NewReg);
865 if (!UseMI->isCopy())
867 if (UseMI->getOperand(0).getReg() != IntB.reg ||
868 UseMI->getOperand(0).getSubReg())
871 // This copy will become a noop. If it's defining a new val#, merge it into
873 SlotIndex DefIdx = UseIdx.getRegSlot();
874 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
877 LLVM_DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
878 assert(DVNI->def == DefIdx);
879 BValNo = IntB.MergeValueNumberInto(DVNI, BValNo);
880 for (LiveInterval::SubRange &S : IntB.subranges()) {
881 VNInfo *SubDVNI = S.getVNInfoAt(DefIdx);
884 VNInfo *SubBValNo = S.getVNInfoAt(CopyIdx);
885 assert(SubBValNo->def == CopyIdx);
886 S.MergeValueNumberInto(SubDVNI, SubBValNo);
892 // Extend BValNo by merging in IntA live segments of AValNo. Val# definition
894 bool ShrinkB = false;
895 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
896 if (IntA.hasSubRanges() || IntB.hasSubRanges()) {
897 if (!IntA.hasSubRanges()) {
898 LaneBitmask Mask = MRI->getMaxLaneMaskForVReg(IntA.reg);
899 IntA.createSubRangeFrom(Allocator, Mask, IntA);
900 } else if (!IntB.hasSubRanges()) {
901 LaneBitmask Mask = MRI->getMaxLaneMaskForVReg(IntB.reg);
902 IntB.createSubRangeFrom(Allocator, Mask, IntB);
904 SlotIndex AIdx = CopyIdx.getRegSlot(true);
906 for (LiveInterval::SubRange &SA : IntA.subranges()) {
907 VNInfo *ASubValNo = SA.getVNInfoAt(AIdx);
908 assert(ASubValNo != nullptr);
909 MaskA |= SA.LaneMask;
911 IntB.refineSubRanges(Allocator, SA.LaneMask,
912 [&Allocator,&SA,CopyIdx,ASubValNo,&ShrinkB]
913 (LiveInterval::SubRange &SR) {
914 VNInfo *BSubValNo = SR.empty()
915 ? SR.getNextValue(CopyIdx, Allocator)
916 : SR.getVNInfoAt(CopyIdx);
917 assert(BSubValNo != nullptr);
918 auto P = addSegmentsWithValNo(SR, BSubValNo, SA, ASubValNo);
921 BSubValNo->def = ASubValNo->def;
924 // Go over all subranges of IntB that have not been covered by IntA,
925 // and delete the segments starting at CopyIdx. This can happen if
926 // IntA has undef lanes that are defined in IntB.
927 for (LiveInterval::SubRange &SB : IntB.subranges()) {
928 if ((SB.LaneMask & MaskA).any())
930 if (LiveRange::Segment *S = SB.getSegmentContaining(CopyIdx))
931 if (S->start.getBaseIndex() == CopyIdx.getBaseIndex())
932 SB.removeSegment(*S, true);
936 BValNo->def = AValNo->def;
937 auto P = addSegmentsWithValNo(IntB, BValNo, IntA, AValNo);
939 LLVM_DEBUG(dbgs() << "\t\textended: " << IntB << '\n');
941 LIS->removeVRegDefAt(IntA, AValNo->def);
943 LLVM_DEBUG(dbgs() << "\t\ttrimmed: " << IntA << '\n');
945 return { true, ShrinkB };
948 /// For copy B = A in BB2, if A is defined by A = B in BB0 which is a
949 /// predecessor of BB2, and if B is not redefined on the way from A = B
950 /// in BB2 to B = A in BB2, B = A in BB2 is partially redundant if the
951 /// execution goes through the path from BB0 to BB2. We may move B = A
952 /// to the predecessor without such reversed copy.
953 /// So we will transform the program from:
971 /// A special case is when BB0 and BB2 are the same BB which is the only
981 /// We may hoist B = A from BB0/BB2 to BB1.
983 /// The major preconditions for correctness to remove such partial
984 /// redundancy include:
985 /// 1. A in B = A in BB2 is defined by a PHI in BB2, and one operand of
986 /// the PHI is defined by the reversed copy A = B in BB0.
987 /// 2. No B is referenced from the start of BB2 to B = A.
988 /// 3. No B is defined from A = B to the end of BB0.
989 /// 4. BB1 has only one successor.
991 /// 2 and 4 implicitly ensure B is not live at the end of BB1.
992 /// 4 guarantees BB2 is hotter than BB1, so we can only move a copy to a
993 /// colder place, which not only prevent endless loop, but also make sure
994 /// the movement of copy is beneficial.
995 bool RegisterCoalescer::removePartialRedundancy(const CoalescerPair &CP,
996 MachineInstr &CopyMI) {
997 assert(!CP.isPhys());
998 if (!CopyMI.isFullCopy())
1001 MachineBasicBlock &MBB = *CopyMI.getParent();
1005 if (MBB.pred_size() != 2)
1008 LiveInterval &IntA =
1009 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
1010 LiveInterval &IntB =
1011 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
1013 // A is defined by PHI at the entry of MBB.
1014 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(true);
1015 VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx);
1016 assert(AValNo && !AValNo->isUnused() && "COPY source not live");
1017 if (!AValNo->isPHIDef())
1020 // No B is referenced before CopyMI in MBB.
1021 if (IntB.overlaps(LIS->getMBBStartIdx(&MBB), CopyIdx))
1024 // MBB has two predecessors: one contains A = B so no copy will be inserted
1025 // for it. The other one will have a copy moved from MBB.
1026 bool FoundReverseCopy = false;
1027 MachineBasicBlock *CopyLeftBB = nullptr;
1028 for (MachineBasicBlock *Pred : MBB.predecessors()) {
1029 VNInfo *PVal = IntA.getVNInfoBefore(LIS->getMBBEndIdx(Pred));
1030 MachineInstr *DefMI = LIS->getInstructionFromIndex(PVal->def);
1031 if (!DefMI || !DefMI->isFullCopy()) {
1035 // Check DefMI is a reverse copy and it is in BB Pred.
1036 if (DefMI->getOperand(0).getReg() != IntA.reg ||
1037 DefMI->getOperand(1).getReg() != IntB.reg ||
1038 DefMI->getParent() != Pred) {
1042 // If there is any other def of B after DefMI and before the end of Pred,
1043 // we need to keep the copy of B = A at the end of Pred if we remove
1045 bool ValB_Changed = false;
1046 for (auto VNI : IntB.valnos) {
1047 if (VNI->isUnused())
1049 if (PVal->def < VNI->def && VNI->def < LIS->getMBBEndIdx(Pred)) {
1050 ValB_Changed = true;
1058 FoundReverseCopy = true;
1061 // If no reverse copy is found in predecessors, nothing to do.
1062 if (!FoundReverseCopy)
1065 // If CopyLeftBB is nullptr, it means every predecessor of MBB contains
1066 // reverse copy, CopyMI can be removed trivially if only IntA/IntB is updated.
1067 // If CopyLeftBB is not nullptr, move CopyMI from MBB to CopyLeftBB and
1068 // update IntA/IntB.
1070 // If CopyLeftBB is not nullptr, ensure CopyLeftBB has a single succ so
1071 // MBB is hotter than CopyLeftBB.
1072 if (CopyLeftBB && CopyLeftBB->succ_size() > 1)
1075 // Now (almost sure it's) ok to move copy.
1077 // Position in CopyLeftBB where we should insert new copy.
1078 auto InsPos = CopyLeftBB->getFirstTerminator();
1080 // Make sure that B isn't referenced in the terminators (if any) at the end
1081 // of the predecessor since we're about to insert a new definition of B
1083 if (InsPos != CopyLeftBB->end()) {
1084 SlotIndex InsPosIdx = LIS->getInstructionIndex(*InsPos).getRegSlot(true);
1085 if (IntB.overlaps(InsPosIdx, LIS->getMBBEndIdx(CopyLeftBB)))
1089 LLVM_DEBUG(dbgs() << "\tremovePartialRedundancy: Move the copy to "
1090 << printMBBReference(*CopyLeftBB) << '\t' << CopyMI);
1092 // Insert new copy to CopyLeftBB.
1093 MachineInstr *NewCopyMI = BuildMI(*CopyLeftBB, InsPos, CopyMI.getDebugLoc(),
1094 TII->get(TargetOpcode::COPY), IntB.reg)
1096 SlotIndex NewCopyIdx =
1097 LIS->InsertMachineInstrInMaps(*NewCopyMI).getRegSlot();
1098 IntB.createDeadDef(NewCopyIdx, LIS->getVNInfoAllocator());
1099 for (LiveInterval::SubRange &SR : IntB.subranges())
1100 SR.createDeadDef(NewCopyIdx, LIS->getVNInfoAllocator());
1102 // If the newly created Instruction has an address of an instruction that was
1103 // deleted before (object recycled by the allocator) it needs to be removed from
1104 // the deleted list.
1105 ErasedInstrs.erase(NewCopyMI);
1107 LLVM_DEBUG(dbgs() << "\tremovePartialRedundancy: Remove the copy from "
1108 << printMBBReference(MBB) << '\t' << CopyMI);
1112 // Note: This is fine to remove the copy before updating the live-ranges.
1113 // While updating the live-ranges, we only look at slot indices and
1114 // never go back to the instruction.
1115 // Mark instructions as deleted.
1116 deleteInstr(&CopyMI);
1118 // Update the liveness.
1119 SmallVector<SlotIndex, 8> EndPoints;
1120 VNInfo *BValNo = IntB.Query(CopyIdx).valueOutOrDead();
1121 LIS->pruneValue(*static_cast<LiveRange *>(&IntB), CopyIdx.getRegSlot(),
1123 BValNo->markUnused();
1124 // Extend IntB to the EndPoints of its original live interval.
1125 LIS->extendToIndices(IntB, EndPoints);
1127 // Now, do the same for its subranges.
1128 for (LiveInterval::SubRange &SR : IntB.subranges()) {
1130 VNInfo *BValNo = SR.Query(CopyIdx).valueOutOrDead();
1131 assert(BValNo && "All sublanes should be live");
1132 LIS->pruneValue(SR, CopyIdx.getRegSlot(), &EndPoints);
1133 BValNo->markUnused();
1134 // We can have a situation where the result of the original copy is live,
1135 // but is immediately dead in this subrange, e.g. [336r,336d:0). That makes
1136 // the copy appear as an endpoint from pruneValue(), but we don't want it
1137 // to because the copy has been removed. We can go ahead and remove that
1138 // endpoint; there is no other situation here that there could be a use at
1139 // the same place as we know that the copy is a full copy.
1140 for (unsigned I = 0; I != EndPoints.size(); ) {
1141 if (SlotIndex::isSameInstr(EndPoints[I], CopyIdx)) {
1142 EndPoints[I] = EndPoints.back();
1143 EndPoints.pop_back();
1148 LIS->extendToIndices(SR, EndPoints);
1150 // If any dead defs were extended, truncate them.
1151 shrinkToUses(&IntB);
1153 // Finally, update the live-range of IntA.
1154 shrinkToUses(&IntA);
1158 /// Returns true if @p MI defines the full vreg @p Reg, as opposed to just
1159 /// defining a subregister.
1160 static bool definesFullReg(const MachineInstr &MI, unsigned Reg) {
1161 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) &&
1162 "This code cannot handle physreg aliasing");
1163 for (const MachineOperand &Op : MI.operands()) {
1164 if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg)
1166 // Return true if we define the full register or don't care about the value
1167 // inside other subregisters.
1168 if (Op.getSubReg() == 0 || Op.isUndef())
1174 bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
1175 MachineInstr *CopyMI,
1178 unsigned SrcReg = CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg();
1179 unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx();
1180 unsigned DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg();
1181 unsigned DstIdx = CP.isFlipped() ? CP.getSrcIdx() : CP.getDstIdx();
1182 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
1185 LiveInterval &SrcInt = LIS->getInterval(SrcReg);
1186 SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI);
1187 VNInfo *ValNo = SrcInt.Query(CopyIdx).valueIn();
1190 if (ValNo->isPHIDef() || ValNo->isUnused())
1192 MachineInstr *DefMI = LIS->getInstructionFromIndex(ValNo->def);
1195 if (DefMI->isCopyLike()) {
1199 if (!TII->isAsCheapAsAMove(*DefMI))
1201 if (!TII->isTriviallyReMaterializable(*DefMI, AA))
1203 if (!definesFullReg(*DefMI, SrcReg))
1205 bool SawStore = false;
1206 if (!DefMI->isSafeToMove(AA, SawStore))
1208 const MCInstrDesc &MCID = DefMI->getDesc();
1209 if (MCID.getNumDefs() != 1)
1211 // Only support subregister destinations when the def is read-undef.
1212 MachineOperand &DstOperand = CopyMI->getOperand(0);
1213 unsigned CopyDstReg = DstOperand.getReg();
1214 if (DstOperand.getSubReg() && !DstOperand.isUndef())
1217 // If both SrcIdx and DstIdx are set, correct rematerialization would widen
1218 // the register substantially (beyond both source and dest size). This is bad
1219 // for performance since it can cascade through a function, introducing many
1220 // extra spills and fills (e.g. ARM can easily end up copying QQQQPR registers
1221 // around after a few subreg copies).
1222 if (SrcIdx && DstIdx)
1225 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF);
1226 if (!DefMI->isImplicitDef()) {
1227 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1228 unsigned NewDstReg = DstReg;
1230 unsigned NewDstIdx = TRI->composeSubRegIndices(CP.getSrcIdx(),
1231 DefMI->getOperand(0).getSubReg());
1233 NewDstReg = TRI->getSubReg(DstReg, NewDstIdx);
1235 // Finally, make sure that the physical subregister that will be
1236 // constructed later is permitted for the instruction.
1237 if (!DefRC->contains(NewDstReg))
1240 // Theoretically, some stack frame reference could exist. Just make sure
1241 // it hasn't actually happened.
1242 assert(TargetRegisterInfo::isVirtualRegister(DstReg) &&
1243 "Only expect to deal with virtual or physical registers");
1247 DebugLoc DL = CopyMI->getDebugLoc();
1248 MachineBasicBlock *MBB = CopyMI->getParent();
1249 MachineBasicBlock::iterator MII =
1250 std::next(MachineBasicBlock::iterator(CopyMI));
1251 TII->reMaterialize(*MBB, MII, DstReg, SrcIdx, *DefMI, *TRI);
1252 MachineInstr &NewMI = *std::prev(MII);
1253 NewMI.setDebugLoc(DL);
1255 // In a situation like the following:
1256 // %0:subreg = instr ; DefMI, subreg = DstIdx
1257 // %1 = copy %0:subreg ; CopyMI, SrcIdx = 0
1258 // instead of widening %1 to the register class of %0 simply do:
1260 const TargetRegisterClass *NewRC = CP.getNewRC();
1262 MachineOperand &DefMO = NewMI.getOperand(0);
1263 if (DefMO.getSubReg() == DstIdx) {
1264 assert(SrcIdx == 0 && CP.isFlipped()
1265 && "Shouldn't have SrcIdx+DstIdx at this point");
1266 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
1267 const TargetRegisterClass *CommonRC =
1268 TRI->getCommonSubClass(DefRC, DstRC);
1269 if (CommonRC != nullptr) {
1273 DefMO.setIsUndef(false); // Only subregs can have def+undef.
1278 // CopyMI may have implicit operands, save them so that we can transfer them
1279 // over to the newly materialized instruction after CopyMI is removed.
1280 SmallVector<MachineOperand, 4> ImplicitOps;
1281 ImplicitOps.reserve(CopyMI->getNumOperands() -
1282 CopyMI->getDesc().getNumOperands());
1283 for (unsigned I = CopyMI->getDesc().getNumOperands(),
1284 E = CopyMI->getNumOperands();
1286 MachineOperand &MO = CopyMI->getOperand(I);
1288 assert(MO.isImplicit() && "No explicit operands after implicit operands.");
1289 // Discard VReg implicit defs.
1290 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1291 ImplicitOps.push_back(MO);
1295 LIS->ReplaceMachineInstrInMaps(*CopyMI, NewMI);
1296 CopyMI->eraseFromParent();
1297 ErasedInstrs.insert(CopyMI);
1299 // NewMI may have dead implicit defs (E.g. EFLAGS for MOV<bits>r0 on X86).
1300 // We need to remember these so we can add intervals once we insert
1301 // NewMI into SlotIndexes.
1302 SmallVector<unsigned, 4> NewMIImplDefs;
1303 for (unsigned i = NewMI.getDesc().getNumOperands(),
1304 e = NewMI.getNumOperands();
1306 MachineOperand &MO = NewMI.getOperand(i);
1307 if (MO.isReg() && MO.isDef()) {
1308 assert(MO.isImplicit() && MO.isDead() &&
1309 TargetRegisterInfo::isPhysicalRegister(MO.getReg()));
1310 NewMIImplDefs.push_back(MO.getReg());
1314 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
1315 unsigned NewIdx = NewMI.getOperand(0).getSubReg();
1317 if (DefRC != nullptr) {
1319 NewRC = TRI->getMatchingSuperRegClass(NewRC, DefRC, NewIdx);
1321 NewRC = TRI->getCommonSubClass(NewRC, DefRC);
1322 assert(NewRC && "subreg chosen for remat incompatible with instruction");
1324 // Remap subranges to new lanemask and change register class.
1325 LiveInterval &DstInt = LIS->getInterval(DstReg);
1326 for (LiveInterval::SubRange &SR : DstInt.subranges()) {
1327 SR.LaneMask = TRI->composeSubRegIndexLaneMask(DstIdx, SR.LaneMask);
1329 MRI->setRegClass(DstReg, NewRC);
1331 // Update machine operands and add flags.
1332 updateRegDefsUses(DstReg, DstReg, DstIdx);
1333 NewMI.getOperand(0).setSubReg(NewIdx);
1334 // updateRegDefUses can add an "undef" flag to the definition, since
1335 // it will replace DstReg with DstReg.DstIdx. If NewIdx is 0, make
1336 // sure that "undef" is not set.
1338 NewMI.getOperand(0).setIsUndef(false);
1339 // Add dead subregister definitions if we are defining the whole register
1340 // but only part of it is live.
1341 // This could happen if the rematerialization instruction is rematerializing
1342 // more than actually is used in the register.
1343 // An example would be:
1344 // %1 = LOAD CONSTANTS 5, 8 ; Loading both 5 and 8 in different subregs
1345 // ; Copying only part of the register here, but the rest is undef.
1346 // %2:sub_16bit<def, read-undef> = COPY %1:sub_16bit
1348 // ; Materialize all the constants but only using one
1349 // %2 = LOAD_CONSTANTS 5, 8
1351 // at this point for the part that wasn't defined before we could have
1352 // subranges missing the definition.
1353 if (NewIdx == 0 && DstInt.hasSubRanges()) {
1354 SlotIndex CurrIdx = LIS->getInstructionIndex(NewMI);
1355 SlotIndex DefIndex =
1356 CurrIdx.getRegSlot(NewMI.getOperand(0).isEarlyClobber());
1357 LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(DstReg);
1358 VNInfo::Allocator& Alloc = LIS->getVNInfoAllocator();
1359 for (LiveInterval::SubRange &SR : DstInt.subranges()) {
1360 if (!SR.liveAt(DefIndex))
1361 SR.createDeadDef(DefIndex, Alloc);
1362 MaxMask &= ~SR.LaneMask;
1364 if (MaxMask.any()) {
1365 LiveInterval::SubRange *SR = DstInt.createSubRange(Alloc, MaxMask);
1366 SR->createDeadDef(DefIndex, Alloc);
1370 // Make sure that the subrange for resultant undef is removed
1372 // %1:sub1<def,read-undef> = LOAD CONSTANT 1
1375 // %2:sub1<def, read-undef> = LOAD CONSTANT 1
1376 // ; Correct but need to remove the subrange for %2:sub0
1377 // ; as it is now undef
1378 if (NewIdx != 0 && DstInt.hasSubRanges()) {
1379 // The affected subregister segments can be removed.
1380 SlotIndex CurrIdx = LIS->getInstructionIndex(NewMI);
1381 LaneBitmask DstMask = TRI->getSubRegIndexLaneMask(NewIdx);
1382 bool UpdatedSubRanges = false;
1383 for (LiveInterval::SubRange &SR : DstInt.subranges()) {
1384 if ((SR.LaneMask & DstMask).none()) {
1386 << "Removing undefined SubRange "
1387 << PrintLaneMask(SR.LaneMask) << " : " << SR << "\n");
1388 // VNI is in ValNo - remove any segments in this SubRange that have this ValNo
1389 if (VNInfo *RmValNo = SR.getVNInfoAt(CurrIdx.getRegSlot())) {
1390 SR.removeValNo(RmValNo);
1391 UpdatedSubRanges = true;
1395 if (UpdatedSubRanges)
1396 DstInt.removeEmptySubRanges();
1398 } else if (NewMI.getOperand(0).getReg() != CopyDstReg) {
1399 // The New instruction may be defining a sub-register of what's actually
1400 // been asked for. If so it must implicitly define the whole thing.
1401 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
1402 "Only expect virtual or physical registers in remat");
1403 NewMI.getOperand(0).setIsDead(true);
1404 NewMI.addOperand(MachineOperand::CreateReg(
1405 CopyDstReg, true /*IsDef*/, true /*IsImp*/, false /*IsKill*/));
1406 // Record small dead def live-ranges for all the subregisters
1407 // of the destination register.
1408 // Otherwise, variables that live through may miss some
1409 // interferences, thus creating invalid allocation.
1411 // %1 = somedef ; %1 GR8
1412 // %2 = remat ; %2 GR32
1413 // CL = COPY %2.sub_8bit
1414 // = somedef %1 ; %1 GR8
1416 // %1 = somedef ; %1 GR8
1417 // dead ECX = remat ; implicit-def CL
1418 // = somedef %1 ; %1 GR8
1419 // %1 will see the interferences with CL but not with CH since
1420 // no live-ranges would have been created for ECX.
1422 SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
1423 for (MCRegUnitIterator Units(NewMI.getOperand(0).getReg(), TRI);
1424 Units.isValid(); ++Units)
1425 if (LiveRange *LR = LIS->getCachedRegUnit(*Units))
1426 LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
1429 if (NewMI.getOperand(0).getSubReg())
1430 NewMI.getOperand(0).setIsUndef();
1432 // Transfer over implicit operands to the rematerialized instruction.
1433 for (MachineOperand &MO : ImplicitOps)
1434 NewMI.addOperand(MO);
1436 SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
1437 for (unsigned i = 0, e = NewMIImplDefs.size(); i != e; ++i) {
1438 unsigned Reg = NewMIImplDefs[i];
1439 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
1440 if (LiveRange *LR = LIS->getCachedRegUnit(*Units))
1441 LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
1444 LLVM_DEBUG(dbgs() << "Remat: " << NewMI);
1447 // If the virtual SrcReg is completely eliminated, update all DBG_VALUEs
1448 // to describe DstReg instead.
1449 if (MRI->use_nodbg_empty(SrcReg)) {
1450 for (MachineOperand &UseMO : MRI->use_operands(SrcReg)) {
1451 MachineInstr *UseMI = UseMO.getParent();
1452 if (UseMI->isDebugValue()) {
1453 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
1454 UseMO.substPhysReg(DstReg, *TRI);
1456 UseMO.setReg(DstReg);
1457 // Move the debug value directly after the def of the rematerialized
1459 MBB->splice(std::next(NewMI.getIterator()), UseMI->getParent(), UseMI);
1460 LLVM_DEBUG(dbgs() << "\t\tupdated: " << *UseMI);
1465 if (ToBeUpdated.count(SrcReg))
1468 unsigned NumCopyUses = 0;
1469 for (MachineOperand &UseMO : MRI->use_nodbg_operands(SrcReg)) {
1470 if (UseMO.getParent()->isCopyLike())
1473 if (NumCopyUses < LateRematUpdateThreshold) {
1474 // The source interval can become smaller because we removed a use.
1475 shrinkToUses(&SrcInt, &DeadDefs);
1476 if (!DeadDefs.empty())
1477 eliminateDeadDefs();
1479 ToBeUpdated.insert(SrcReg);
1484 MachineInstr *RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI) {
1485 // ProcessImplicitDefs may leave some copies of <undef> values, it only
1486 // removes local variables. When we have a copy like:
1488 // %1 = COPY undef %2
1490 // We delete the copy and remove the corresponding value number from %1.
1491 // Any uses of that value number are marked as <undef>.
1493 // Note that we do not query CoalescerPair here but redo isMoveInstr as the
1494 // CoalescerPair may have a new register class with adjusted subreg indices
1496 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1497 isMoveInstr(*TRI, CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
1499 SlotIndex Idx = LIS->getInstructionIndex(*CopyMI);
1500 const LiveInterval &SrcLI = LIS->getInterval(SrcReg);
1501 // CopyMI is undef iff SrcReg is not live before the instruction.
1502 if (SrcSubIdx != 0 && SrcLI.hasSubRanges()) {
1503 LaneBitmask SrcMask = TRI->getSubRegIndexLaneMask(SrcSubIdx);
1504 for (const LiveInterval::SubRange &SR : SrcLI.subranges()) {
1505 if ((SR.LaneMask & SrcMask).none())
1510 } else if (SrcLI.liveAt(Idx))
1513 // If the undef copy defines a live-out value (i.e. an input to a PHI def),
1514 // then replace it with an IMPLICIT_DEF.
1515 LiveInterval &DstLI = LIS->getInterval(DstReg);
1516 SlotIndex RegIndex = Idx.getRegSlot();
1517 LiveRange::Segment *Seg = DstLI.getSegmentContaining(RegIndex);
1518 assert(Seg != nullptr && "No segment for defining instruction");
1519 if (VNInfo *V = DstLI.getVNInfoAt(Seg->end)) {
1520 if (V->isPHIDef()) {
1521 CopyMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
1522 for (unsigned i = CopyMI->getNumOperands(); i != 0; --i) {
1523 MachineOperand &MO = CopyMI->getOperand(i-1);
1524 if (MO.isReg() && MO.isUse())
1525 CopyMI->RemoveOperand(i-1);
1527 LLVM_DEBUG(dbgs() << "\tReplaced copy of <undef> value with an "
1533 // Remove any DstReg segments starting at the instruction.
1534 LLVM_DEBUG(dbgs() << "\tEliminating copy of <undef> value\n");
1536 // Remove value or merge with previous one in case of a subregister def.
1537 if (VNInfo *PrevVNI = DstLI.getVNInfoAt(Idx)) {
1538 VNInfo *VNI = DstLI.getVNInfoAt(RegIndex);
1539 DstLI.MergeValueNumberInto(VNI, PrevVNI);
1541 // The affected subregister segments can be removed.
1542 LaneBitmask DstMask = TRI->getSubRegIndexLaneMask(DstSubIdx);
1543 for (LiveInterval::SubRange &SR : DstLI.subranges()) {
1544 if ((SR.LaneMask & DstMask).none())
1547 VNInfo *SVNI = SR.getVNInfoAt(RegIndex);
1548 assert(SVNI != nullptr && SlotIndex::isSameInstr(SVNI->def, RegIndex));
1549 SR.removeValNo(SVNI);
1551 DstLI.removeEmptySubRanges();
1553 LIS->removeVRegDefAt(DstLI, RegIndex);
1555 // Mark uses as undef.
1556 for (MachineOperand &MO : MRI->reg_nodbg_operands(DstReg)) {
1557 if (MO.isDef() /*|| MO.isUndef()*/)
1559 const MachineInstr &MI = *MO.getParent();
1560 SlotIndex UseIdx = LIS->getInstructionIndex(MI);
1561 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
1563 if (!UseMask.all() && DstLI.hasSubRanges()) {
1565 for (const LiveInterval::SubRange &SR : DstLI.subranges()) {
1566 if ((SR.LaneMask & UseMask).none())
1568 if (SR.liveAt(UseIdx)) {
1574 isLive = DstLI.liveAt(UseIdx);
1577 MO.setIsUndef(true);
1578 LLVM_DEBUG(dbgs() << "\tnew undef: " << UseIdx << '\t' << MI);
1581 // A def of a subregister may be a use of the other subregisters, so
1582 // deleting a def of a subregister may also remove uses. Since CopyMI
1583 // is still part of the function (but about to be erased), mark all
1584 // defs of DstReg in it as <undef>, so that shrinkToUses would
1586 for (MachineOperand &MO : CopyMI->operands())
1587 if (MO.isReg() && MO.isDef() && MO.getReg() == DstReg)
1588 MO.setIsUndef(true);
1589 LIS->shrinkToUses(&DstLI);
1594 void RegisterCoalescer::addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
1595 MachineOperand &MO, unsigned SubRegIdx) {
1596 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubRegIdx);
1599 bool IsUndef = true;
1600 for (const LiveInterval::SubRange &S : Int.subranges()) {
1601 if ((S.LaneMask & Mask).none())
1603 if (S.liveAt(UseIdx)) {
1609 MO.setIsUndef(true);
1610 // We found out some subregister use is actually reading an undefined
1611 // value. In some cases the whole vreg has become undefined at this
1612 // point so we have to potentially shrink the main range if the
1613 // use was ending a live segment there.
1614 LiveQueryResult Q = Int.Query(UseIdx);
1615 if (Q.valueOut() == nullptr)
1616 ShrinkMainRange = true;
1620 void RegisterCoalescer::updateRegDefsUses(unsigned SrcReg,
1623 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1624 LiveInterval *DstInt = DstIsPhys ? nullptr : &LIS->getInterval(DstReg);
1626 if (DstInt && DstInt->hasSubRanges() && DstReg != SrcReg) {
1627 for (MachineOperand &MO : MRI->reg_operands(DstReg)) {
1628 unsigned SubReg = MO.getSubReg();
1629 if (SubReg == 0 || MO.isUndef())
1631 MachineInstr &MI = *MO.getParent();
1632 if (MI.isDebugValue())
1634 SlotIndex UseIdx = LIS->getInstructionIndex(MI).getRegSlot(true);
1635 addUndefFlag(*DstInt, UseIdx, MO, SubReg);
1639 SmallPtrSet<MachineInstr*, 8> Visited;
1640 for (MachineRegisterInfo::reg_instr_iterator
1641 I = MRI->reg_instr_begin(SrcReg), E = MRI->reg_instr_end();
1643 MachineInstr *UseMI = &*(I++);
1645 // Each instruction can only be rewritten once because sub-register
1646 // composition is not always idempotent. When SrcReg != DstReg, rewriting
1647 // the UseMI operands removes them from the SrcReg use-def chain, but when
1648 // SrcReg is DstReg we could encounter UseMI twice if it has multiple
1649 // operands mentioning the virtual register.
1650 if (SrcReg == DstReg && !Visited.insert(UseMI).second)
1653 SmallVector<unsigned,8> Ops;
1655 std::tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
1657 // If SrcReg wasn't read, it may still be the case that DstReg is live-in
1658 // because SrcReg is a sub-register.
1659 if (DstInt && !Reads && SubIdx && !UseMI->isDebugValue())
1660 Reads = DstInt->liveAt(LIS->getInstructionIndex(*UseMI));
1662 // Replace SrcReg with DstReg in all UseMI operands.
1663 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
1664 MachineOperand &MO = UseMI->getOperand(Ops[i]);
1666 // Adjust <undef> flags in case of sub-register joins. We don't want to
1667 // turn a full def into a read-modify-write sub-register def and vice
1669 if (SubIdx && MO.isDef())
1670 MO.setIsUndef(!Reads);
1672 // A subreg use of a partially undef (super) register may be a complete
1673 // undef use now and then has to be marked that way.
1674 if (SubIdx != 0 && MO.isUse() && MRI->shouldTrackSubRegLiveness(DstReg)) {
1675 if (!DstInt->hasSubRanges()) {
1676 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
1677 LaneBitmask Mask = MRI->getMaxLaneMaskForVReg(DstInt->reg);
1678 DstInt->createSubRangeFrom(Allocator, Mask, *DstInt);
1680 SlotIndex MIIdx = UseMI->isDebugValue()
1681 ? LIS->getSlotIndexes()->getIndexBefore(*UseMI)
1682 : LIS->getInstructionIndex(*UseMI);
1683 SlotIndex UseIdx = MIIdx.getRegSlot(true);
1684 addUndefFlag(*DstInt, UseIdx, MO, SubIdx);
1688 MO.substPhysReg(DstReg, *TRI);
1690 MO.substVirtReg(DstReg, SubIdx, *TRI);
1694 dbgs() << "\t\tupdated: ";
1695 if (!UseMI->isDebugValue())
1696 dbgs() << LIS->getInstructionIndex(*UseMI) << "\t";
1702 bool RegisterCoalescer::canJoinPhys(const CoalescerPair &CP) {
1703 // Always join simple intervals that are defined by a single copy from a
1704 // reserved register. This doesn't increase register pressure, so it is
1705 // always beneficial.
1706 if (!MRI->isReserved(CP.getDstReg())) {
1707 LLVM_DEBUG(dbgs() << "\tCan only merge into reserved registers.\n");
1711 LiveInterval &JoinVInt = LIS->getInterval(CP.getSrcReg());
1712 if (JoinVInt.containsOneValue())
1716 dbgs() << "\tCannot join complex intervals into reserved register.\n");
1720 bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
1722 LLVM_DEBUG(dbgs() << LIS->getInstructionIndex(*CopyMI) << '\t' << *CopyMI);
1724 CoalescerPair CP(*TRI);
1725 if (!CP.setRegisters(CopyMI)) {
1726 LLVM_DEBUG(dbgs() << "\tNot coalescable.\n");
1730 if (CP.getNewRC()) {
1731 auto SrcRC = MRI->getRegClass(CP.getSrcReg());
1732 auto DstRC = MRI->getRegClass(CP.getDstReg());
1733 unsigned SrcIdx = CP.getSrcIdx();
1734 unsigned DstIdx = CP.getDstIdx();
1735 if (CP.isFlipped()) {
1736 std::swap(SrcIdx, DstIdx);
1737 std::swap(SrcRC, DstRC);
1739 if (!TRI->shouldCoalesce(CopyMI, SrcRC, SrcIdx, DstRC, DstIdx,
1740 CP.getNewRC(), *LIS)) {
1741 LLVM_DEBUG(dbgs() << "\tSubtarget bailed on coalescing.\n");
1746 // Dead code elimination. This really should be handled by MachineDCE, but
1747 // sometimes dead copies slip through, and we can't generate invalid live
1749 if (!CP.isPhys() && CopyMI->allDefsAreDead()) {
1750 LLVM_DEBUG(dbgs() << "\tCopy is dead.\n");
1751 DeadDefs.push_back(CopyMI);
1752 eliminateDeadDefs();
1756 // Eliminate undefs.
1758 // If this is an IMPLICIT_DEF, leave it alone, but don't try to coalesce.
1759 if (MachineInstr *UndefMI = eliminateUndefCopy(CopyMI)) {
1760 if (UndefMI->isImplicitDef())
1762 deleteInstr(CopyMI);
1763 return false; // Not coalescable.
1767 // Coalesced copies are normally removed immediately, but transformations
1768 // like removeCopyByCommutingDef() can inadvertently create identity copies.
1769 // When that happens, just join the values and remove the copy.
1770 if (CP.getSrcReg() == CP.getDstReg()) {
1771 LiveInterval &LI = LIS->getInterval(CP.getSrcReg());
1772 LLVM_DEBUG(dbgs() << "\tCopy already coalesced: " << LI << '\n');
1773 const SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI);
1774 LiveQueryResult LRQ = LI.Query(CopyIdx);
1775 if (VNInfo *DefVNI = LRQ.valueDefined()) {
1776 VNInfo *ReadVNI = LRQ.valueIn();
1777 assert(ReadVNI && "No value before copy and no <undef> flag.");
1778 assert(ReadVNI != DefVNI && "Cannot read and define the same value.");
1779 LI.MergeValueNumberInto(DefVNI, ReadVNI);
1781 // Process subregister liveranges.
1782 for (LiveInterval::SubRange &S : LI.subranges()) {
1783 LiveQueryResult SLRQ = S.Query(CopyIdx);
1784 if (VNInfo *SDefVNI = SLRQ.valueDefined()) {
1785 VNInfo *SReadVNI = SLRQ.valueIn();
1786 S.MergeValueNumberInto(SDefVNI, SReadVNI);
1789 LLVM_DEBUG(dbgs() << "\tMerged values: " << LI << '\n');
1791 deleteInstr(CopyMI);
1795 // Enforce policies.
1797 LLVM_DEBUG(dbgs() << "\tConsidering merging "
1798 << printReg(CP.getSrcReg(), TRI) << " with "
1799 << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n');
1800 if (!canJoinPhys(CP)) {
1801 // Before giving up coalescing, if definition of source is defined by
1802 // trivial computation, try rematerializing it.
1804 if (reMaterializeTrivialDef(CP, CopyMI, IsDefCopy))
1807 Again = true; // May be possible to coalesce later.
1811 // When possible, let DstReg be the larger interval.
1812 if (!CP.isPartial() && LIS->getInterval(CP.getSrcReg()).size() >
1813 LIS->getInterval(CP.getDstReg()).size())
1817 dbgs() << "\tConsidering merging to "
1818 << TRI->getRegClassName(CP.getNewRC()) << " with ";
1819 if (CP.getDstIdx() && CP.getSrcIdx())
1820 dbgs() << printReg(CP.getDstReg()) << " in "
1821 << TRI->getSubRegIndexName(CP.getDstIdx()) << " and "
1822 << printReg(CP.getSrcReg()) << " in "
1823 << TRI->getSubRegIndexName(CP.getSrcIdx()) << '\n';
1825 dbgs() << printReg(CP.getSrcReg(), TRI) << " in "
1826 << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n';
1830 ShrinkMask = LaneBitmask::getNone();
1831 ShrinkMainRange = false;
1833 // Okay, attempt to join these two intervals. On failure, this returns false.
1834 // Otherwise, if one of the intervals being joined is a physreg, this method
1835 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1836 // been modified, so we can use this information below to update aliases.
1837 if (!joinIntervals(CP)) {
1838 // Coalescing failed.
1840 // If definition of source is defined by trivial computation, try
1841 // rematerializing it.
1843 if (reMaterializeTrivialDef(CP, CopyMI, IsDefCopy))
1846 // If we can eliminate the copy without merging the live segments, do so
1848 if (!CP.isPartial() && !CP.isPhys()) {
1849 bool Changed = adjustCopiesBackFrom(CP, CopyMI);
1850 bool Shrink = false;
1852 std::tie(Changed, Shrink) = removeCopyByCommutingDef(CP, CopyMI);
1854 deleteInstr(CopyMI);
1856 unsigned DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg();
1857 LiveInterval &DstLI = LIS->getInterval(DstReg);
1858 shrinkToUses(&DstLI);
1859 LLVM_DEBUG(dbgs() << "\t\tshrunk: " << DstLI << '\n');
1861 LLVM_DEBUG(dbgs() << "\tTrivial!\n");
1866 // Try and see if we can partially eliminate the copy by moving the copy to
1868 if (!CP.isPartial() && !CP.isPhys())
1869 if (removePartialRedundancy(CP, *CopyMI))
1872 // Otherwise, we are unable to join the intervals.
1873 LLVM_DEBUG(dbgs() << "\tInterference!\n");
1874 Again = true; // May be possible to coalesce later.
1878 // Coalescing to a virtual register that is of a sub-register class of the
1879 // other. Make sure the resulting register is set to the right register class.
1880 if (CP.isCrossClass()) {
1882 MRI->setRegClass(CP.getDstReg(), CP.getNewRC());
1885 // Removing sub-register copies can ease the register class constraints.
1886 // Make sure we attempt to inflate the register class of DstReg.
1887 if (!CP.isPhys() && RegClassInfo.isProperSubClass(CP.getNewRC()))
1888 InflateRegs.push_back(CP.getDstReg());
1890 // CopyMI has been erased by joinIntervals at this point. Remove it from
1891 // ErasedInstrs since copyCoalesceWorkList() won't add a successful join back
1892 // to the work list. This keeps ErasedInstrs from growing needlessly.
1893 ErasedInstrs.erase(CopyMI);
1895 // Rewrite all SrcReg operands to DstReg.
1896 // Also update DstReg operands to include DstIdx if it is set.
1898 updateRegDefsUses(CP.getDstReg(), CP.getDstReg(), CP.getDstIdx());
1899 updateRegDefsUses(CP.getSrcReg(), CP.getDstReg(), CP.getSrcIdx());
1901 // Shrink subregister ranges if necessary.
1902 if (ShrinkMask.any()) {
1903 LiveInterval &LI = LIS->getInterval(CP.getDstReg());
1904 for (LiveInterval::SubRange &S : LI.subranges()) {
1905 if ((S.LaneMask & ShrinkMask).none())
1907 LLVM_DEBUG(dbgs() << "Shrink LaneUses (Lane " << PrintLaneMask(S.LaneMask)
1909 LIS->shrinkToUses(S, LI.reg);
1911 LI.removeEmptySubRanges();
1914 // CP.getSrcReg()'s live interval has been merged into CP.getDstReg's live
1915 // interval. Since CP.getSrcReg() is in ToBeUpdated set and its live interval
1916 // is not up-to-date, need to update the merged live interval here.
1917 if (ToBeUpdated.count(CP.getSrcReg()))
1918 ShrinkMainRange = true;
1920 if (ShrinkMainRange) {
1921 LiveInterval &LI = LIS->getInterval(CP.getDstReg());
1925 // SrcReg is guaranteed to be the register whose live interval that is
1927 LIS->removeInterval(CP.getSrcReg());
1929 // Update regalloc hint.
1930 TRI->updateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
1933 dbgs() << "\tSuccess: " << printReg(CP.getSrcReg(), TRI, CP.getSrcIdx())
1934 << " -> " << printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n';
1935 dbgs() << "\tResult = ";
1937 dbgs() << printReg(CP.getDstReg(), TRI);
1939 dbgs() << LIS->getInterval(CP.getDstReg());
1947 bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
1948 unsigned DstReg = CP.getDstReg();
1949 unsigned SrcReg = CP.getSrcReg();
1950 assert(CP.isPhys() && "Must be a physreg copy");
1951 assert(MRI->isReserved(DstReg) && "Not a reserved register");
1952 LiveInterval &RHS = LIS->getInterval(SrcReg);
1953 LLVM_DEBUG(dbgs() << "\t\tRHS = " << RHS << '\n');
1955 assert(RHS.containsOneValue() && "Invalid join with reserved register");
1957 // Optimization for reserved registers like ESP. We can only merge with a
1958 // reserved physreg if RHS has a single value that is a copy of DstReg.
1959 // The live range of the reserved register will look like a set of dead defs
1960 // - we don't properly track the live range of reserved registers.
1962 // Deny any overlapping intervals. This depends on all the reserved
1963 // register live ranges to look like dead defs.
1964 if (!MRI->isConstantPhysReg(DstReg)) {
1965 for (MCRegUnitIterator UI(DstReg, TRI); UI.isValid(); ++UI) {
1966 // Abort if not all the regunits are reserved.
1967 for (MCRegUnitRootIterator RI(*UI, TRI); RI.isValid(); ++RI) {
1968 if (!MRI->isReserved(*RI))
1971 if (RHS.overlaps(LIS->getRegUnit(*UI))) {
1972 LLVM_DEBUG(dbgs() << "\t\tInterference: " << printRegUnit(*UI, TRI)
1978 // We must also check for overlaps with regmask clobbers.
1979 BitVector RegMaskUsable;
1980 if (LIS->checkRegMaskInterference(RHS, RegMaskUsable) &&
1981 !RegMaskUsable.test(DstReg)) {
1982 LLVM_DEBUG(dbgs() << "\t\tRegMask interference\n");
1987 // Skip any value computations, we are not adding new values to the
1988 // reserved register. Also skip merging the live ranges, the reserved
1989 // register live range doesn't need to be accurate as long as all the
1992 // Delete the identity copy.
1993 MachineInstr *CopyMI;
1994 if (CP.isFlipped()) {
1995 // Physreg is copied into vreg
1996 // %y = COPY %physreg_x
1997 // ... //< no other def of %x here
2002 CopyMI = MRI->getVRegDef(SrcReg);
2004 // VReg is copied into physreg:
2006 // ... //< no other def or use of %y here
2007 // %y = COPY %physreg_x
2011 if (!MRI->hasOneNonDBGUse(SrcReg)) {
2012 LLVM_DEBUG(dbgs() << "\t\tMultiple vreg uses!\n");
2016 if (!LIS->intervalIsInOneMBB(RHS)) {
2017 LLVM_DEBUG(dbgs() << "\t\tComplex control flow!\n");
2021 MachineInstr &DestMI = *MRI->getVRegDef(SrcReg);
2022 CopyMI = &*MRI->use_instr_nodbg_begin(SrcReg);
2023 SlotIndex CopyRegIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
2024 SlotIndex DestRegIdx = LIS->getInstructionIndex(DestMI).getRegSlot();
2026 if (!MRI->isConstantPhysReg(DstReg)) {
2027 // We checked above that there are no interfering defs of the physical
2028 // register. However, for this case, where we intend to move up the def of
2029 // the physical register, we also need to check for interfering uses.
2030 SlotIndexes *Indexes = LIS->getSlotIndexes();
2031 for (SlotIndex SI = Indexes->getNextNonNullIndex(DestRegIdx);
2032 SI != CopyRegIdx; SI = Indexes->getNextNonNullIndex(SI)) {
2033 MachineInstr *MI = LIS->getInstructionFromIndex(SI);
2034 if (MI->readsRegister(DstReg, TRI)) {
2035 LLVM_DEBUG(dbgs() << "\t\tInterference (read): " << *MI);
2041 // We're going to remove the copy which defines a physical reserved
2042 // register, so remove its valno, etc.
2043 LLVM_DEBUG(dbgs() << "\t\tRemoving phys reg def of "
2044 << printReg(DstReg, TRI) << " at " << CopyRegIdx << "\n");
2046 LIS->removePhysRegDefAt(DstReg, CopyRegIdx);
2047 // Create a new dead def at the new def location.
2048 for (MCRegUnitIterator UI(DstReg, TRI); UI.isValid(); ++UI) {
2049 LiveRange &LR = LIS->getRegUnit(*UI);
2050 LR.createDeadDef(DestRegIdx, LIS->getVNInfoAllocator());
2054 deleteInstr(CopyMI);
2056 // We don't track kills for reserved registers.
2057 MRI->clearKillFlags(CP.getSrcReg());
2062 //===----------------------------------------------------------------------===//
2063 // Interference checking and interval joining
2064 //===----------------------------------------------------------------------===//
2066 // In the easiest case, the two live ranges being joined are disjoint, and
2067 // there is no interference to consider. It is quite common, though, to have
2068 // overlapping live ranges, and we need to check if the interference can be
2071 // The live range of a single SSA value forms a sub-tree of the dominator tree.
2072 // This means that two SSA values overlap if and only if the def of one value
2073 // is contained in the live range of the other value. As a special case, the
2074 // overlapping values can be defined at the same index.
2076 // The interference from an overlapping def can be resolved in these cases:
2078 // 1. Coalescable copies. The value is defined by a copy that would become an
2079 // identity copy after joining SrcReg and DstReg. The copy instruction will
2080 // be removed, and the value will be merged with the source value.
2082 // There can be several copies back and forth, causing many values to be
2083 // merged into one. We compute a list of ultimate values in the joined live
2084 // range as well as a mappings from the old value numbers.
2086 // 2. IMPLICIT_DEF. This instruction is only inserted to ensure all PHI
2087 // predecessors have a live out value. It doesn't cause real interference,
2088 // and can be merged into the value it overlaps. Like a coalescable copy, it
2089 // can be erased after joining.
2091 // 3. Copy of external value. The overlapping def may be a copy of a value that
2092 // is already in the other register. This is like a coalescable copy, but
2093 // the live range of the source register must be trimmed after erasing the
2094 // copy instruction:
2097 // %dst = COPY %ext <-- Remove this COPY, trim the live range of %ext.
2099 // 4. Clobbering undefined lanes. Vector registers are sometimes built by
2100 // defining one lane at a time:
2102 // %dst:ssub0<def,read-undef> = FOO
2104 // %dst:ssub1 = COPY %src
2106 // The live range of %src overlaps the %dst value defined by FOO, but
2107 // merging %src into %dst:ssub1 is only going to clobber the ssub1 lane
2108 // which was undef anyway.
2110 // The value mapping is more complicated in this case. The final live range
2111 // will have different value numbers for both FOO and BAR, but there is no
2112 // simple mapping from old to new values. It may even be necessary to add
2115 // 5. Clobbering dead lanes. A def may clobber a lane of a vector register that
2116 // is live, but never read. This can happen because we don't compute
2117 // individual live ranges per lane.
2121 // %dst:ssub1 = COPY %src
2123 // This kind of interference is only resolved locally. If the clobbered
2124 // lane value escapes the block, the join is aborted.
2128 /// Track information about values in a single virtual register about to be
2129 /// joined. Objects of this class are always created in pairs - one for each
2130 /// side of the CoalescerPair (or one for each lane of a side of the coalescer
2133 /// Live range we work on.
2136 /// (Main) register we work on.
2139 /// Reg (and therefore the values in this liverange) will end up as
2140 /// subregister SubIdx in the coalesced register. Either CP.DstIdx or
2142 const unsigned SubIdx;
2144 /// The LaneMask that this liverange will occupy the coalesced register. May
2145 /// be smaller than the lanemask produced by SubIdx when merging subranges.
2146 const LaneBitmask LaneMask;
2148 /// This is true when joining sub register ranges, false when joining main
2150 const bool SubRangeJoin;
2152 /// Whether the current LiveInterval tracks subregister liveness.
2153 const bool TrackSubRegLiveness;
2155 /// Values that will be present in the final live range.
2156 SmallVectorImpl<VNInfo*> &NewVNInfo;
2158 const CoalescerPair &CP;
2160 SlotIndexes *Indexes;
2161 const TargetRegisterInfo *TRI;
2163 /// Value number assignments. Maps value numbers in LI to entries in
2164 /// NewVNInfo. This is suitable for passing to LiveInterval::join().
2165 SmallVector<int, 8> Assignments;
2167 /// Conflict resolution for overlapping values.
2168 enum ConflictResolution {
2169 /// No overlap, simply keep this value.
2172 /// Merge this value into OtherVNI and erase the defining instruction.
2173 /// Used for IMPLICIT_DEF, coalescable copies, and copies from external
2177 /// Merge this value into OtherVNI but keep the defining instruction.
2178 /// This is for the special case where OtherVNI is defined by the same
2182 /// Keep this value, and have it replace OtherVNI where possible. This
2183 /// complicates value mapping since OtherVNI maps to two different values
2184 /// before and after this def.
2185 /// Used when clobbering undefined or dead lanes.
2188 /// Unresolved conflict. Visit later when all values have been mapped.
2191 /// Unresolvable conflict. Abort the join.
2195 /// Per-value info for LI. The lane bit masks are all relative to the final
2196 /// joined register, so they can be compared directly between SrcReg and
2199 ConflictResolution Resolution = CR_Keep;
2201 /// Lanes written by this def, 0 for unanalyzed values.
2202 LaneBitmask WriteLanes;
2204 /// Lanes with defined values in this register. Other lanes are undef and
2205 /// safe to clobber.
2206 LaneBitmask ValidLanes;
2208 /// Value in LI being redefined by this def.
2209 VNInfo *RedefVNI = nullptr;
2211 /// Value in the other live range that overlaps this def, if any.
2212 VNInfo *OtherVNI = nullptr;
2214 /// Is this value an IMPLICIT_DEF that can be erased?
2216 /// IMPLICIT_DEF values should only exist at the end of a basic block that
2217 /// is a predecessor to a phi-value. These IMPLICIT_DEF instructions can be
2218 /// safely erased if they are overlapping a live value in the other live
2221 /// Weird control flow graphs and incomplete PHI handling in
2222 /// ProcessImplicitDefs can very rarely create IMPLICIT_DEF values with
2223 /// longer live ranges. Such IMPLICIT_DEF values should be treated like
2225 bool ErasableImplicitDef = false;
2227 /// True when the live range of this value will be pruned because of an
2228 /// overlapping CR_Replace value in the other live range.
2229 bool Pruned = false;
2231 /// True once Pruned above has been computed.
2232 bool PrunedComputed = false;
2234 /// True if this value is determined to be identical to OtherVNI
2235 /// (in valuesIdentical). This is used with CR_Erase where the erased
2236 /// copy is redundant, i.e. the source value is already the same as
2237 /// the destination. In such cases the subranges need to be updated
2238 /// properly. See comment at pruneSubRegValues for more info.
2239 bool Identical = false;
2243 bool isAnalyzed() const { return WriteLanes.any(); }
2246 /// One entry per value number in LI.
2247 SmallVector<Val, 8> Vals;
2249 /// Compute the bitmask of lanes actually written by DefMI.
2250 /// Set Redef if there are any partial register definitions that depend on the
2251 /// previous value of the register.
2252 LaneBitmask computeWriteLanes(const MachineInstr *DefMI, bool &Redef) const;
2254 /// Find the ultimate value that VNI was copied from.
2255 std::pair<const VNInfo*,unsigned> followCopyChain(const VNInfo *VNI) const;
2257 bool valuesIdentical(VNInfo *Value0, VNInfo *Value1, const JoinVals &Other) const;
2259 /// Analyze ValNo in this live range, and set all fields of Vals[ValNo].
2260 /// Return a conflict resolution when possible, but leave the hard cases as
2262 /// Recursively calls computeAssignment() on this and Other, guaranteeing that
2263 /// both OtherVNI and RedefVNI have been analyzed and mapped before returning.
2264 /// The recursion always goes upwards in the dominator tree, making loops
2266 ConflictResolution analyzeValue(unsigned ValNo, JoinVals &Other);
2268 /// Compute the value assignment for ValNo in RI.
2269 /// This may be called recursively by analyzeValue(), but never for a ValNo on
2271 void computeAssignment(unsigned ValNo, JoinVals &Other);
2273 /// Assuming ValNo is going to clobber some valid lanes in Other.LR, compute
2274 /// the extent of the tainted lanes in the block.
2276 /// Multiple values in Other.LR can be affected since partial redefinitions
2277 /// can preserve previously tainted lanes.
2279 /// 1 %dst = VLOAD <-- Define all lanes in %dst
2280 /// 2 %src = FOO <-- ValNo to be joined with %dst:ssub0
2281 /// 3 %dst:ssub1 = BAR <-- Partial redef doesn't clear taint in ssub0
2282 /// 4 %dst:ssub0 = COPY %src <-- Conflict resolved, ssub0 wasn't read
2284 /// For each ValNo in Other that is affected, add an (EndIndex, TaintedLanes)
2285 /// entry to TaintedVals.
2287 /// Returns false if the tainted lanes extend beyond the basic block.
2289 taintExtent(unsigned ValNo, LaneBitmask TaintedLanes, JoinVals &Other,
2290 SmallVectorImpl<std::pair<SlotIndex, LaneBitmask>> &TaintExtent);
2292 /// Return true if MI uses any of the given Lanes from Reg.
2293 /// This does not include partial redefinitions of Reg.
2294 bool usesLanes(const MachineInstr &MI, unsigned, unsigned, LaneBitmask) const;
2296 /// Determine if ValNo is a copy of a value number in LR or Other.LR that will
2299 /// %dst = COPY %src
2300 /// %src = COPY %dst <-- This value to be pruned.
2301 /// %dst = COPY %src <-- This value is a copy of a pruned value.
2302 bool isPrunedValue(unsigned ValNo, JoinVals &Other);
2305 JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, LaneBitmask LaneMask,
2306 SmallVectorImpl<VNInfo*> &newVNInfo, const CoalescerPair &cp,
2307 LiveIntervals *lis, const TargetRegisterInfo *TRI, bool SubRangeJoin,
2308 bool TrackSubRegLiveness)
2309 : LR(LR), Reg(Reg), SubIdx(SubIdx), LaneMask(LaneMask),
2310 SubRangeJoin(SubRangeJoin), TrackSubRegLiveness(TrackSubRegLiveness),
2311 NewVNInfo(newVNInfo), CP(cp), LIS(lis), Indexes(LIS->getSlotIndexes()),
2312 TRI(TRI), Assignments(LR.getNumValNums(), -1), Vals(LR.getNumValNums()) {}
2314 /// Analyze defs in LR and compute a value mapping in NewVNInfo.
2315 /// Returns false if any conflicts were impossible to resolve.
2316 bool mapValues(JoinVals &Other);
2318 /// Try to resolve conflicts that require all values to be mapped.
2319 /// Returns false if any conflicts were impossible to resolve.
2320 bool resolveConflicts(JoinVals &Other);
2322 /// Prune the live range of values in Other.LR where they would conflict with
2323 /// CR_Replace values in LR. Collect end points for restoring the live range
2325 void pruneValues(JoinVals &Other, SmallVectorImpl<SlotIndex> &EndPoints,
2328 /// Removes subranges starting at copies that get removed. This sometimes
2329 /// happens when undefined subranges are copied around. These ranges contain
2330 /// no useful information and can be removed.
2331 void pruneSubRegValues(LiveInterval &LI, LaneBitmask &ShrinkMask);
2333 /// Pruning values in subranges can lead to removing segments in these
2334 /// subranges started by IMPLICIT_DEFs. The corresponding segments in
2335 /// the main range also need to be removed. This function will mark
2336 /// the corresponding values in the main range as pruned, so that
2337 /// eraseInstrs can do the final cleanup.
2338 /// The parameter @p LI must be the interval whose main range is the
2340 void pruneMainSegments(LiveInterval &LI, bool &ShrinkMainRange);
2342 /// Erase any machine instructions that have been coalesced away.
2343 /// Add erased instructions to ErasedInstrs.
2344 /// Add foreign virtual registers to ShrinkRegs if their live range ended at
2345 /// the erased instrs.
2346 void eraseInstrs(SmallPtrSetImpl<MachineInstr*> &ErasedInstrs,
2347 SmallVectorImpl<unsigned> &ShrinkRegs,
2348 LiveInterval *LI = nullptr);
2350 /// Remove liverange defs at places where implicit defs will be removed.
2351 void removeImplicitDefs();
2353 /// Get the value assignments suitable for passing to LiveInterval::join.
2354 const int *getAssignments() const { return Assignments.data(); }
2357 } // end anonymous namespace
2359 LaneBitmask JoinVals::computeWriteLanes(const MachineInstr *DefMI, bool &Redef)
2362 for (const MachineOperand &MO : DefMI->operands()) {
2363 if (!MO.isReg() || MO.getReg() != Reg || !MO.isDef())
2365 L |= TRI->getSubRegIndexLaneMask(
2366 TRI->composeSubRegIndices(SubIdx, MO.getSubReg()));
2373 std::pair<const VNInfo*, unsigned> JoinVals::followCopyChain(
2374 const VNInfo *VNI) const {
2375 unsigned TrackReg = Reg;
2377 while (!VNI->isPHIDef()) {
2378 SlotIndex Def = VNI->def;
2379 MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
2380 assert(MI && "No defining instruction");
2381 if (!MI->isFullCopy())
2382 return std::make_pair(VNI, TrackReg);
2383 unsigned SrcReg = MI->getOperand(1).getReg();
2384 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
2385 return std::make_pair(VNI, TrackReg);
2387 const LiveInterval &LI = LIS->getInterval(SrcReg);
2388 const VNInfo *ValueIn;
2389 // No subrange involved.
2390 if (!SubRangeJoin || !LI.hasSubRanges()) {
2391 LiveQueryResult LRQ = LI.Query(Def);
2392 ValueIn = LRQ.valueIn();
2394 // Query subranges. Ensure that all matching ones take us to the same def
2395 // (allowing some of them to be undef).
2397 for (const LiveInterval::SubRange &S : LI.subranges()) {
2398 // Transform lanemask to a mask in the joined live interval.
2399 LaneBitmask SMask = TRI->composeSubRegIndexLaneMask(SubIdx, S.LaneMask);
2400 if ((SMask & LaneMask).none())
2402 LiveQueryResult LRQ = S.Query(Def);
2404 ValueIn = LRQ.valueIn();
2407 if (LRQ.valueIn() && ValueIn != LRQ.valueIn())
2408 return std::make_pair(VNI, TrackReg);
2411 if (ValueIn == nullptr) {
2412 // Reaching an undefined value is legitimate, for example:
2414 // 1 undef %0.sub1 = ... ;; %0.sub0 == undef
2415 // 2 %1 = COPY %0 ;; %1 is defined here.
2416 // 3 %0 = COPY %1 ;; Now %0.sub0 has a definition,
2417 // ;; but it's equivalent to "undef".
2418 return std::make_pair(nullptr, SrcReg);
2423 return std::make_pair(VNI, TrackReg);
2426 bool JoinVals::valuesIdentical(VNInfo *Value0, VNInfo *Value1,
2427 const JoinVals &Other) const {
2428 const VNInfo *Orig0;
2430 std::tie(Orig0, Reg0) = followCopyChain(Value0);
2431 if (Orig0 == Value1 && Reg0 == Other.Reg)
2434 const VNInfo *Orig1;
2436 std::tie(Orig1, Reg1) = Other.followCopyChain(Value1);
2437 // If both values are undefined, and the source registers are the same
2438 // register, the values are identical. Filter out cases where only one
2439 // value is defined.
2440 if (Orig0 == nullptr || Orig1 == nullptr)
2441 return Orig0 == Orig1 && Reg0 == Reg1;
2443 // The values are equal if they are defined at the same place and use the
2444 // same register. Note that we cannot compare VNInfos directly as some of
2445 // them might be from a copy created in mergeSubRangeInto() while the other
2446 // is from the original LiveInterval.
2447 return Orig0->def == Orig1->def && Reg0 == Reg1;
2450 JoinVals::ConflictResolution
2451 JoinVals::analyzeValue(unsigned ValNo, JoinVals &Other) {
2452 Val &V = Vals[ValNo];
2453 assert(!V.isAnalyzed() && "Value has already been analyzed!");
2454 VNInfo *VNI = LR.getValNumInfo(ValNo);
2455 if (VNI->isUnused()) {
2456 V.WriteLanes = LaneBitmask::getAll();
2460 // Get the instruction defining this value, compute the lanes written.
2461 const MachineInstr *DefMI = nullptr;
2462 if (VNI->isPHIDef()) {
2463 // Conservatively assume that all lanes in a PHI are valid.
2464 LaneBitmask Lanes = SubRangeJoin ? LaneBitmask::getLane(0)
2465 : TRI->getSubRegIndexLaneMask(SubIdx);
2466 V.ValidLanes = V.WriteLanes = Lanes;
2468 DefMI = Indexes->getInstructionFromIndex(VNI->def);
2469 assert(DefMI != nullptr);
2471 // We don't care about the lanes when joining subregister ranges.
2472 V.WriteLanes = V.ValidLanes = LaneBitmask::getLane(0);
2473 if (DefMI->isImplicitDef()) {
2474 V.ValidLanes = LaneBitmask::getNone();
2475 V.ErasableImplicitDef = true;
2479 V.ValidLanes = V.WriteLanes = computeWriteLanes(DefMI, Redef);
2481 // If this is a read-modify-write instruction, there may be more valid
2482 // lanes than the ones written by this instruction.
2483 // This only covers partial redef operands. DefMI may have normal use
2484 // operands reading the register. They don't contribute valid lanes.
2486 // This adds ssub1 to the set of valid lanes in %src:
2490 // This leaves only ssub1 valid, making any other lanes undef:
2492 // %src:ssub1<def,read-undef> = FOO %src:ssub2
2494 // The <read-undef> flag on the def operand means that old lane values are
2497 V.RedefVNI = LR.Query(VNI->def).valueIn();
2498 assert((TrackSubRegLiveness || V.RedefVNI) &&
2499 "Instruction is reading nonexistent value");
2500 if (V.RedefVNI != nullptr) {
2501 computeAssignment(V.RedefVNI->id, Other);
2502 V.ValidLanes |= Vals[V.RedefVNI->id].ValidLanes;
2506 // An IMPLICIT_DEF writes undef values.
2507 if (DefMI->isImplicitDef()) {
2508 // We normally expect IMPLICIT_DEF values to be live only until the end
2509 // of their block. If the value is really live longer and gets pruned in
2510 // another block, this flag is cleared again.
2512 // Clearing the valid lanes is deferred until it is sure this can be
2514 V.ErasableImplicitDef = true;
2519 // Find the value in Other that overlaps VNI->def, if any.
2520 LiveQueryResult OtherLRQ = Other.LR.Query(VNI->def);
2522 // It is possible that both values are defined by the same instruction, or
2523 // the values are PHIs defined in the same block. When that happens, the two
2524 // values should be merged into one, but not into any preceding value.
2525 // The first value defined or visited gets CR_Keep, the other gets CR_Merge.
2526 if (VNInfo *OtherVNI = OtherLRQ.valueDefined()) {
2527 assert(SlotIndex::isSameInstr(VNI->def, OtherVNI->def) && "Broken LRQ");
2529 // One value stays, the other is merged. Keep the earlier one, or the first
2531 if (OtherVNI->def < VNI->def)
2532 Other.computeAssignment(OtherVNI->id, *this);
2533 else if (VNI->def < OtherVNI->def && OtherLRQ.valueIn()) {
2534 // This is an early-clobber def overlapping a live-in value in the other
2535 // register. Not mergeable.
2536 V.OtherVNI = OtherLRQ.valueIn();
2537 return CR_Impossible;
2539 V.OtherVNI = OtherVNI;
2540 Val &OtherV = Other.Vals[OtherVNI->id];
2541 // Keep this value, check for conflicts when analyzing OtherVNI.
2542 if (!OtherV.isAnalyzed())
2544 // Both sides have been analyzed now.
2545 // Allow overlapping PHI values. Any real interference would show up in a
2546 // predecessor, the PHI itself can't introduce any conflicts.
2547 if (VNI->isPHIDef())
2549 if ((V.ValidLanes & OtherV.ValidLanes).any())
2550 // Overlapping lanes can't be resolved.
2551 return CR_Impossible;
2556 // No simultaneous def. Is Other live at the def?
2557 V.OtherVNI = OtherLRQ.valueIn();
2559 // No overlap, no conflict.
2562 assert(!SlotIndex::isSameInstr(VNI->def, V.OtherVNI->def) && "Broken LRQ");
2564 // We have overlapping values, or possibly a kill of Other.
2565 // Recursively compute assignments up the dominator tree.
2566 Other.computeAssignment(V.OtherVNI->id, *this);
2567 Val &OtherV = Other.Vals[V.OtherVNI->id];
2569 if (OtherV.ErasableImplicitDef) {
2570 // Check if OtherV is an IMPLICIT_DEF that extends beyond its basic block.
2571 // This shouldn't normally happen, but ProcessImplicitDefs can leave such
2572 // IMPLICIT_DEF instructions behind, and there is nothing wrong with it
2575 // When it happens, treat that IMPLICIT_DEF as a normal value, and don't try
2576 // to erase the IMPLICIT_DEF instruction.
2578 DefMI->getParent() != Indexes->getMBBFromIndex(V.OtherVNI->def)) {
2579 LLVM_DEBUG(dbgs() << "IMPLICIT_DEF defined at " << V.OtherVNI->def
2581 << printMBBReference(*DefMI->getParent())
2582 << ", keeping it.\n");
2583 OtherV.ErasableImplicitDef = false;
2585 // We deferred clearing these lanes in case we needed to save them
2586 OtherV.ValidLanes &= ~OtherV.WriteLanes;
2590 // Allow overlapping PHI values. Any real interference would show up in a
2591 // predecessor, the PHI itself can't introduce any conflicts.
2592 if (VNI->isPHIDef())
2595 // Check for simple erasable conflicts.
2596 if (DefMI->isImplicitDef()) {
2597 // We need the def for the subregister if there is nothing else live at the
2598 // subrange at this point.
2599 if (TrackSubRegLiveness
2600 && (V.WriteLanes & (OtherV.ValidLanes | OtherV.WriteLanes)).none())
2605 // Include the non-conflict where DefMI is a coalescable copy that kills
2606 // OtherVNI. We still want the copy erased and value numbers merged.
2607 if (CP.isCoalescable(DefMI)) {
2608 // Some of the lanes copied from OtherVNI may be undef, making them undef
2610 V.ValidLanes &= ~V.WriteLanes | OtherV.ValidLanes;
2614 // This may not be a real conflict if DefMI simply kills Other and defines
2616 if (OtherLRQ.isKill() && OtherLRQ.endPoint() <= VNI->def)
2619 // Handle the case where VNI and OtherVNI can be proven to be identical:
2621 // %other = COPY %ext
2622 // %this = COPY %ext <-- Erase this copy
2624 if (DefMI->isFullCopy() && !CP.isPartial() &&
2625 valuesIdentical(VNI, V.OtherVNI, Other)) {
2630 // The remaining checks apply to the lanes, which aren't tracked here. This
2631 // was already decided to be OK via the following CR_Replace condition.
2636 // If the lanes written by this instruction were all undef in OtherVNI, it is
2637 // still safe to join the live ranges. This can't be done with a simple value
2638 // mapping, though - OtherVNI will map to multiple values:
2640 // 1 %dst:ssub0 = FOO <-- OtherVNI
2641 // 2 %src = BAR <-- VNI
2642 // 3 %dst:ssub1 = COPY killed %src <-- Eliminate this copy.
2643 // 4 BAZ killed %dst
2644 // 5 QUUX killed %src
2646 // Here OtherVNI will map to itself in [1;2), but to VNI in [2;5). CR_Replace
2647 // handles this complex value mapping.
2648 if ((V.WriteLanes & OtherV.ValidLanes).none())
2651 // If the other live range is killed by DefMI and the live ranges are still
2652 // overlapping, it must be because we're looking at an early clobber def:
2654 // %dst<def,early-clobber> = ASM killed %src
2656 // In this case, it is illegal to merge the two live ranges since the early
2657 // clobber def would clobber %src before it was read.
2658 if (OtherLRQ.isKill()) {
2659 // This case where the def doesn't overlap the kill is handled above.
2660 assert(VNI->def.isEarlyClobber() &&
2661 "Only early clobber defs can overlap a kill");
2662 return CR_Impossible;
2665 // VNI is clobbering live lanes in OtherVNI, but there is still the
2666 // possibility that no instructions actually read the clobbered lanes.
2667 // If we're clobbering all the lanes in OtherVNI, at least one must be read.
2668 // Otherwise Other.RI wouldn't be live here.
2669 if ((TRI->getSubRegIndexLaneMask(Other.SubIdx) & ~V.WriteLanes).none())
2670 return CR_Impossible;
2672 // We need to verify that no instructions are reading the clobbered lanes. To
2673 // save compile time, we'll only check that locally. Don't allow the tainted
2674 // value to escape the basic block.
2675 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
2676 if (OtherLRQ.endPoint() >= Indexes->getMBBEndIdx(MBB))
2677 return CR_Impossible;
2679 // There are still some things that could go wrong besides clobbered lanes
2680 // being read, for example OtherVNI may be only partially redefined in MBB,
2681 // and some clobbered lanes could escape the block. Save this analysis for
2682 // resolveConflicts() when all values have been mapped. We need to know
2683 // RedefVNI and WriteLanes for any later defs in MBB, and we can't compute
2684 // that now - the recursive analyzeValue() calls must go upwards in the
2686 return CR_Unresolved;
2689 void JoinVals::computeAssignment(unsigned ValNo, JoinVals &Other) {
2690 Val &V = Vals[ValNo];
2691 if (V.isAnalyzed()) {
2692 // Recursion should always move up the dominator tree, so ValNo is not
2693 // supposed to reappear before it has been assigned.
2694 assert(Assignments[ValNo] != -1 && "Bad recursion?");
2697 switch ((V.Resolution = analyzeValue(ValNo, Other))) {
2700 // Merge this ValNo into OtherVNI.
2701 assert(V.OtherVNI && "OtherVNI not assigned, can't merge.");
2702 assert(Other.Vals[V.OtherVNI->id].isAnalyzed() && "Missing recursion");
2703 Assignments[ValNo] = Other.Assignments[V.OtherVNI->id];
2704 LLVM_DEBUG(dbgs() << "\t\tmerge " << printReg(Reg) << ':' << ValNo << '@'
2705 << LR.getValNumInfo(ValNo)->def << " into "
2706 << printReg(Other.Reg) << ':' << V.OtherVNI->id << '@'
2707 << V.OtherVNI->def << " --> @"
2708 << NewVNInfo[Assignments[ValNo]]->def << '\n');
2711 case CR_Unresolved: {
2712 // The other value is going to be pruned if this join is successful.
2713 assert(V.OtherVNI && "OtherVNI not assigned, can't prune");
2714 Val &OtherV = Other.Vals[V.OtherVNI->id];
2715 // We cannot erase an IMPLICIT_DEF if we don't have valid values for all
2717 if (OtherV.ErasableImplicitDef &&
2718 TrackSubRegLiveness &&
2719 (OtherV.WriteLanes & ~V.ValidLanes).any()) {
2720 LLVM_DEBUG(dbgs() << "Cannot erase implicit_def with missing values\n");
2722 OtherV.ErasableImplicitDef = false;
2723 // The valid lanes written by the implicit_def were speculatively cleared
2724 // before, so make this more conservative. It may be better to track this,
2725 // I haven't found a testcase where it matters.
2726 OtherV.ValidLanes = LaneBitmask::getAll();
2729 OtherV.Pruned = true;
2733 // This value number needs to go in the final joined live range.
2734 Assignments[ValNo] = NewVNInfo.size();
2735 NewVNInfo.push_back(LR.getValNumInfo(ValNo));
2740 bool JoinVals::mapValues(JoinVals &Other) {
2741 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
2742 computeAssignment(i, Other);
2743 if (Vals[i].Resolution == CR_Impossible) {
2744 LLVM_DEBUG(dbgs() << "\t\tinterference at " << printReg(Reg) << ':' << i
2745 << '@' << LR.getValNumInfo(i)->def << '\n');
2753 taintExtent(unsigned ValNo, LaneBitmask TaintedLanes, JoinVals &Other,
2754 SmallVectorImpl<std::pair<SlotIndex, LaneBitmask>> &TaintExtent) {
2755 VNInfo *VNI = LR.getValNumInfo(ValNo);
2756 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
2757 SlotIndex MBBEnd = Indexes->getMBBEndIdx(MBB);
2759 // Scan Other.LR from VNI.def to MBBEnd.
2760 LiveInterval::iterator OtherI = Other.LR.find(VNI->def);
2761 assert(OtherI != Other.LR.end() && "No conflict?");
2763 // OtherI is pointing to a tainted value. Abort the join if the tainted
2764 // lanes escape the block.
2765 SlotIndex End = OtherI->end;
2766 if (End >= MBBEnd) {
2767 LLVM_DEBUG(dbgs() << "\t\ttaints global " << printReg(Other.Reg) << ':'
2768 << OtherI->valno->id << '@' << OtherI->start << '\n');
2771 LLVM_DEBUG(dbgs() << "\t\ttaints local " << printReg(Other.Reg) << ':'
2772 << OtherI->valno->id << '@' << OtherI->start << " to "
2774 // A dead def is not a problem.
2777 TaintExtent.push_back(std::make_pair(End, TaintedLanes));
2779 // Check for another def in the MBB.
2780 if (++OtherI == Other.LR.end() || OtherI->start >= MBBEnd)
2783 // Lanes written by the new def are no longer tainted.
2784 const Val &OV = Other.Vals[OtherI->valno->id];
2785 TaintedLanes &= ~OV.WriteLanes;
2788 } while (TaintedLanes.any());
2792 bool JoinVals::usesLanes(const MachineInstr &MI, unsigned Reg, unsigned SubIdx,
2793 LaneBitmask Lanes) const {
2794 if (MI.isDebugInstr())
2796 for (const MachineOperand &MO : MI.operands()) {
2797 if (!MO.isReg() || MO.isDef() || MO.getReg() != Reg)
2801 unsigned S = TRI->composeSubRegIndices(SubIdx, MO.getSubReg());
2802 if ((Lanes & TRI->getSubRegIndexLaneMask(S)).any())
2808 bool JoinVals::resolveConflicts(JoinVals &Other) {
2809 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
2811 assert(V.Resolution != CR_Impossible && "Unresolvable conflict");
2812 if (V.Resolution != CR_Unresolved)
2814 LLVM_DEBUG(dbgs() << "\t\tconflict at " << printReg(Reg) << ':' << i << '@'
2815 << LR.getValNumInfo(i)->def << '\n');
2820 assert(V.OtherVNI && "Inconsistent conflict resolution.");
2821 VNInfo *VNI = LR.getValNumInfo(i);
2822 const Val &OtherV = Other.Vals[V.OtherVNI->id];
2824 // VNI is known to clobber some lanes in OtherVNI. If we go ahead with the
2825 // join, those lanes will be tainted with a wrong value. Get the extent of
2826 // the tainted lanes.
2827 LaneBitmask TaintedLanes = V.WriteLanes & OtherV.ValidLanes;
2828 SmallVector<std::pair<SlotIndex, LaneBitmask>, 8> TaintExtent;
2829 if (!taintExtent(i, TaintedLanes, Other, TaintExtent))
2830 // Tainted lanes would extend beyond the basic block.
2833 assert(!TaintExtent.empty() && "There should be at least one conflict.");
2835 // Now look at the instructions from VNI->def to TaintExtent (inclusive).
2836 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
2837 MachineBasicBlock::iterator MI = MBB->begin();
2838 if (!VNI->isPHIDef()) {
2839 MI = Indexes->getInstructionFromIndex(VNI->def);
2840 // No need to check the instruction defining VNI for reads.
2843 assert(!SlotIndex::isSameInstr(VNI->def, TaintExtent.front().first) &&
2844 "Interference ends on VNI->def. Should have been handled earlier");
2845 MachineInstr *LastMI =
2846 Indexes->getInstructionFromIndex(TaintExtent.front().first);
2847 assert(LastMI && "Range must end at a proper instruction");
2848 unsigned TaintNum = 0;
2850 assert(MI != MBB->end() && "Bad LastMI");
2851 if (usesLanes(*MI, Other.Reg, Other.SubIdx, TaintedLanes)) {
2852 LLVM_DEBUG(dbgs() << "\t\ttainted lanes used by: " << *MI);
2855 // LastMI is the last instruction to use the current value.
2856 if (&*MI == LastMI) {
2857 if (++TaintNum == TaintExtent.size())
2859 LastMI = Indexes->getInstructionFromIndex(TaintExtent[TaintNum].first);
2860 assert(LastMI && "Range must end at a proper instruction");
2861 TaintedLanes = TaintExtent[TaintNum].second;
2866 // The tainted lanes are unused.
2867 V.Resolution = CR_Replace;
2873 bool JoinVals::isPrunedValue(unsigned ValNo, JoinVals &Other) {
2874 Val &V = Vals[ValNo];
2875 if (V.Pruned || V.PrunedComputed)
2878 if (V.Resolution != CR_Erase && V.Resolution != CR_Merge)
2881 // Follow copies up the dominator tree and check if any intermediate value
2883 V.PrunedComputed = true;
2884 V.Pruned = Other.isPrunedValue(V.OtherVNI->id, *this);
2888 void JoinVals::pruneValues(JoinVals &Other,
2889 SmallVectorImpl<SlotIndex> &EndPoints,
2890 bool changeInstrs) {
2891 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
2892 SlotIndex Def = LR.getValNumInfo(i)->def;
2893 switch (Vals[i].Resolution) {
2897 // This value takes precedence over the value in Other.LR.
2898 LIS->pruneValue(Other.LR, Def, &EndPoints);
2899 // Check if we're replacing an IMPLICIT_DEF value. The IMPLICIT_DEF
2900 // instructions are only inserted to provide a live-out value for PHI
2901 // predecessors, so the instruction should simply go away once its value
2902 // has been replaced.
2903 Val &OtherV = Other.Vals[Vals[i].OtherVNI->id];
2904 bool EraseImpDef = OtherV.ErasableImplicitDef &&
2905 OtherV.Resolution == CR_Keep;
2906 if (!Def.isBlock()) {
2908 // Remove <def,read-undef> flags. This def is now a partial redef.
2909 // Also remove dead flags since the joined live range will
2910 // continue past this instruction.
2911 for (MachineOperand &MO :
2912 Indexes->getInstructionFromIndex(Def)->operands()) {
2913 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg) {
2914 if (MO.getSubReg() != 0 && MO.isUndef() && !EraseImpDef)
2915 MO.setIsUndef(false);
2916 MO.setIsDead(false);
2920 // This value will reach instructions below, but we need to make sure
2921 // the live range also reaches the instruction at Def.
2923 EndPoints.push_back(Def);
2925 LLVM_DEBUG(dbgs() << "\t\tpruned " << printReg(Other.Reg) << " at " << Def
2926 << ": " << Other.LR << '\n');
2931 if (isPrunedValue(i, Other)) {
2932 // This value is ultimately a copy of a pruned value in LR or Other.LR.
2933 // We can no longer trust the value mapping computed by
2934 // computeAssignment(), the value that was originally copied could have
2936 LIS->pruneValue(LR, Def, &EndPoints);
2937 LLVM_DEBUG(dbgs() << "\t\tpruned all of " << printReg(Reg) << " at "
2938 << Def << ": " << LR << '\n');
2943 llvm_unreachable("Unresolved conflicts");
2948 /// Consider the following situation when coalescing the copy between
2949 /// %31 and %45 at 800. (The vertical lines represent live range segments.)
2951 /// Main range Subrange 0004 (sub2)
2953 /// 544 %45 = COPY %28 + +
2956 /// 624 = %45.sub2 | v2 | v2
2957 /// 800 %31 = COPY %45 + + + +
2959 /// 816 %31.sub1 = ... + |
2960 /// 880 %30 = COPY %31 | v1 +
2961 /// 928 %45 = COPY %30 | + +
2962 /// | | v0 | v0 <--+
2963 /// 992B ; backedge -> bb.1 | + + |
2964 /// 1040 = %31.sub0 + |
2965 /// This value must remain
2968 /// Assuming that %31 is coalesced into %45, the copy at 928 becomes
2969 /// redundant, since it copies the value from %45 back into it. The
2970 /// conflict resolution for the main range determines that %45.v0 is
2971 /// to be erased, which is ok since %31.v1 is identical to it.
2972 /// The problem happens with the subrange for sub2: it has to be live
2973 /// on exit from the block, but since 928 was actually a point of
2974 /// definition of %45.sub2, %45.sub2 was not live immediately prior
2975 /// to that definition. As a result, when 928 was erased, the value v0
2976 /// for %45.sub2 was pruned in pruneSubRegValues. Consequently, an
2977 /// IMPLICIT_DEF was inserted as a "backedge" definition for %45.sub2,
2978 /// providing an incorrect value to the use at 624.
2980 /// Since the main-range values %31.v1 and %45.v0 were proved to be
2981 /// identical, the corresponding values in subranges must also be the
2982 /// same. A redundant copy is removed because it's not needed, and not
2983 /// because it copied an undefined value, so any liveness that originated
2984 /// from that copy cannot disappear. When pruning a value that started
2985 /// at the removed copy, the corresponding identical value must be
2986 /// extended to replace it.
2987 void JoinVals::pruneSubRegValues(LiveInterval &LI, LaneBitmask &ShrinkMask) {
2988 // Look for values being erased.
2989 bool DidPrune = false;
2990 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
2992 // We should trigger in all cases in which eraseInstrs() does something.
2993 // match what eraseInstrs() is doing, print a message so
2994 if (V.Resolution != CR_Erase &&
2995 (V.Resolution != CR_Keep || !V.ErasableImplicitDef || !V.Pruned))
2998 // Check subranges at the point where the copy will be removed.
2999 SlotIndex Def = LR.getValNumInfo(i)->def;
3002 OtherDef = V.OtherVNI->def;
3004 // Print message so mismatches with eraseInstrs() can be diagnosed.
3005 LLVM_DEBUG(dbgs() << "\t\tExpecting instruction removal at " << Def
3007 for (LiveInterval::SubRange &S : LI.subranges()) {
3008 LiveQueryResult Q = S.Query(Def);
3010 // If a subrange starts at the copy then an undefined value has been
3011 // copied and we must remove that subrange value as well.
3012 VNInfo *ValueOut = Q.valueOutOrDead();
3013 if (ValueOut != nullptr && Q.valueIn() == nullptr) {
3014 LLVM_DEBUG(dbgs() << "\t\tPrune sublane " << PrintLaneMask(S.LaneMask)
3015 << " at " << Def << "\n");
3016 SmallVector<SlotIndex,8> EndPoints;
3017 LIS->pruneValue(S, Def, &EndPoints);
3019 // Mark value number as unused.
3020 ValueOut->markUnused();
3022 if (V.Identical && S.Query(OtherDef).valueOut()) {
3023 // If V is identical to V.OtherVNI (and S was live at OtherDef),
3024 // then we can't simply prune V from S. V needs to be replaced
3026 LIS->extendToIndices(S, EndPoints);
3030 // If a subrange ends at the copy, then a value was copied but only
3031 // partially used later. Shrink the subregister range appropriately.
3032 if (Q.valueIn() != nullptr && Q.valueOut() == nullptr) {
3033 LLVM_DEBUG(dbgs() << "\t\tDead uses at sublane "
3034 << PrintLaneMask(S.LaneMask) << " at " << Def
3036 ShrinkMask |= S.LaneMask;
3041 LI.removeEmptySubRanges();
3044 /// Check if any of the subranges of @p LI contain a definition at @p Def.
3045 static bool isDefInSubRange(LiveInterval &LI, SlotIndex Def) {
3046 for (LiveInterval::SubRange &SR : LI.subranges()) {
3047 if (VNInfo *VNI = SR.Query(Def).valueOutOrDead())
3048 if (VNI->def == Def)
3054 void JoinVals::pruneMainSegments(LiveInterval &LI, bool &ShrinkMainRange) {
3055 assert(&static_cast<LiveRange&>(LI) == &LR);
3057 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
3058 if (Vals[i].Resolution != CR_Keep)
3060 VNInfo *VNI = LR.getValNumInfo(i);
3061 if (VNI->isUnused() || VNI->isPHIDef() || isDefInSubRange(LI, VNI->def))
3063 Vals[i].Pruned = true;
3064 ShrinkMainRange = true;
3068 void JoinVals::removeImplicitDefs() {
3069 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
3071 if (V.Resolution != CR_Keep || !V.ErasableImplicitDef || !V.Pruned)
3074 VNInfo *VNI = LR.getValNumInfo(i);
3076 LR.removeValNo(VNI);
3080 void JoinVals::eraseInstrs(SmallPtrSetImpl<MachineInstr*> &ErasedInstrs,
3081 SmallVectorImpl<unsigned> &ShrinkRegs,
3083 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
3084 // Get the def location before markUnused() below invalidates it.
3085 SlotIndex Def = LR.getValNumInfo(i)->def;
3086 switch (Vals[i].Resolution) {
3088 // If an IMPLICIT_DEF value is pruned, it doesn't serve a purpose any
3089 // longer. The IMPLICIT_DEF instructions are only inserted by
3090 // PHIElimination to guarantee that all PHI predecessors have a value.
3091 if (!Vals[i].ErasableImplicitDef || !Vals[i].Pruned)
3093 // Remove value number i from LR.
3094 // For intervals with subranges, removing a segment from the main range
3095 // may require extending the previous segment: for each definition of
3096 // a subregister, there will be a corresponding def in the main range.
3097 // That def may fall in the middle of a segment from another subrange.
3098 // In such cases, removing this def from the main range must be
3099 // complemented by extending the main range to account for the liveness
3100 // of the other subrange.
3101 VNInfo *VNI = LR.getValNumInfo(i);
3102 SlotIndex Def = VNI->def;
3103 // The new end point of the main range segment to be extended.
3105 if (LI != nullptr) {
3106 LiveRange::iterator I = LR.FindSegmentContaining(Def);
3107 assert(I != LR.end());
3108 // Do not extend beyond the end of the segment being removed.
3109 // The segment may have been pruned in preparation for joining
3114 LR.removeValNo(VNI);
3115 // Note that this VNInfo is reused and still referenced in NewVNInfo,
3116 // make it appear like an unused value number.
3119 if (LI != nullptr && LI->hasSubRanges()) {
3120 assert(static_cast<LiveRange*>(LI) == &LR);
3121 // Determine the end point based on the subrange information:
3122 // minimum of (earliest def of next segment,
3123 // latest end point of containing segment)
3125 for (LiveInterval::SubRange &SR : LI->subranges()) {
3126 LiveRange::iterator I = SR.find(Def);
3130 ED = ED.isValid() ? std::min(ED, I->start) : I->start;
3132 LE = LE.isValid() ? std::max(LE, I->end) : I->end;
3135 NewEnd = std::min(NewEnd, LE);
3137 NewEnd = std::min(NewEnd, ED);
3139 // We only want to do the extension if there was a subrange that
3140 // was live across Def.
3142 LiveRange::iterator S = LR.find(Def);
3143 if (S != LR.begin())
3144 std::prev(S)->end = NewEnd;
3148 dbgs() << "\t\tremoved " << i << '@' << Def << ": " << LR << '\n';
3150 dbgs() << "\t\t LHS = " << *LI << '\n';
3156 MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
3157 assert(MI && "No instruction to erase");
3159 unsigned Reg = MI->getOperand(1).getReg();
3160 if (TargetRegisterInfo::isVirtualRegister(Reg) &&
3161 Reg != CP.getSrcReg() && Reg != CP.getDstReg())
3162 ShrinkRegs.push_back(Reg);
3164 ErasedInstrs.insert(MI);
3165 LLVM_DEBUG(dbgs() << "\t\terased:\t" << Def << '\t' << *MI);
3166 LIS->RemoveMachineInstrFromMaps(*MI);
3167 MI->eraseFromParent();
3176 void RegisterCoalescer::joinSubRegRanges(LiveRange &LRange, LiveRange &RRange,
3177 LaneBitmask LaneMask,
3178 const CoalescerPair &CP) {
3179 SmallVector<VNInfo*, 16> NewVNInfo;
3180 JoinVals RHSVals(RRange, CP.getSrcReg(), CP.getSrcIdx(), LaneMask,
3181 NewVNInfo, CP, LIS, TRI, true, true);
3182 JoinVals LHSVals(LRange, CP.getDstReg(), CP.getDstIdx(), LaneMask,
3183 NewVNInfo, CP, LIS, TRI, true, true);
3185 // Compute NewVNInfo and resolve conflicts (see also joinVirtRegs())
3186 // We should be able to resolve all conflicts here as we could successfully do
3187 // it on the mainrange already. There is however a problem when multiple
3188 // ranges get mapped to the "overflow" lane mask bit which creates unexpected
3190 if (!LHSVals.mapValues(RHSVals) || !RHSVals.mapValues(LHSVals)) {
3191 // We already determined that it is legal to merge the intervals, so this
3192 // should never fail.
3193 llvm_unreachable("*** Couldn't join subrange!\n");
3195 if (!LHSVals.resolveConflicts(RHSVals) ||
3196 !RHSVals.resolveConflicts(LHSVals)) {
3197 // We already determined that it is legal to merge the intervals, so this
3198 // should never fail.
3199 llvm_unreachable("*** Couldn't join subrange!\n");
3202 // The merging algorithm in LiveInterval::join() can't handle conflicting
3203 // value mappings, so we need to remove any live ranges that overlap a
3204 // CR_Replace resolution. Collect a set of end points that can be used to
3205 // restore the live range after joining.
3206 SmallVector<SlotIndex, 8> EndPoints;
3207 LHSVals.pruneValues(RHSVals, EndPoints, false);
3208 RHSVals.pruneValues(LHSVals, EndPoints, false);
3210 LHSVals.removeImplicitDefs();
3211 RHSVals.removeImplicitDefs();
3216 // Join RRange into LHS.
3217 LRange.join(RRange, LHSVals.getAssignments(), RHSVals.getAssignments(),
3220 LLVM_DEBUG(dbgs() << "\t\tjoined lanes: " << PrintLaneMask(LaneMask)
3221 << ' ' << LRange << "\n");
3222 if (EndPoints.empty())
3225 // Recompute the parts of the live range we had to remove because of
3226 // CR_Replace conflicts.
3228 dbgs() << "\t\trestoring liveness to " << EndPoints.size() << " points: ";
3229 for (unsigned i = 0, n = EndPoints.size(); i != n; ++i) {
3230 dbgs() << EndPoints[i];
3234 dbgs() << ": " << LRange << '\n';
3236 LIS->extendToIndices(LRange, EndPoints);
3239 void RegisterCoalescer::mergeSubRangeInto(LiveInterval &LI,
3240 const LiveRange &ToMerge,
3241 LaneBitmask LaneMask,
3242 CoalescerPair &CP) {
3243 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
3244 LI.refineSubRanges(Allocator, LaneMask,
3245 [this,&Allocator,&ToMerge,&CP](LiveInterval::SubRange &SR) {
3247 SR.assign(ToMerge, Allocator);
3249 // joinSubRegRange() destroys the merged range, so we need a copy.
3250 LiveRange RangeCopy(ToMerge, Allocator);
3251 joinSubRegRanges(SR, RangeCopy, SR.LaneMask, CP);
3256 bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) {
3257 SmallVector<VNInfo*, 16> NewVNInfo;
3258 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
3259 LiveInterval &LHS = LIS->getInterval(CP.getDstReg());
3260 bool TrackSubRegLiveness = MRI->shouldTrackSubRegLiveness(*CP.getNewRC());
3261 JoinVals RHSVals(RHS, CP.getSrcReg(), CP.getSrcIdx(), LaneBitmask::getNone(),
3262 NewVNInfo, CP, LIS, TRI, false, TrackSubRegLiveness);
3263 JoinVals LHSVals(LHS, CP.getDstReg(), CP.getDstIdx(), LaneBitmask::getNone(),
3264 NewVNInfo, CP, LIS, TRI, false, TrackSubRegLiveness);
3266 LLVM_DEBUG(dbgs() << "\t\tRHS = " << RHS << "\n\t\tLHS = " << LHS << '\n');
3268 // First compute NewVNInfo and the simple value mappings.
3269 // Detect impossible conflicts early.
3270 if (!LHSVals.mapValues(RHSVals) || !RHSVals.mapValues(LHSVals))
3273 // Some conflicts can only be resolved after all values have been mapped.
3274 if (!LHSVals.resolveConflicts(RHSVals) || !RHSVals.resolveConflicts(LHSVals))
3277 // All clear, the live ranges can be merged.
3278 if (RHS.hasSubRanges() || LHS.hasSubRanges()) {
3279 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
3281 // Transform lanemasks from the LHS to masks in the coalesced register and
3282 // create initial subranges if necessary.
3283 unsigned DstIdx = CP.getDstIdx();
3284 if (!LHS.hasSubRanges()) {
3285 LaneBitmask Mask = DstIdx == 0 ? CP.getNewRC()->getLaneMask()
3286 : TRI->getSubRegIndexLaneMask(DstIdx);
3287 // LHS must support subregs or we wouldn't be in this codepath.
3289 LHS.createSubRangeFrom(Allocator, Mask, LHS);
3290 } else if (DstIdx != 0) {
3291 // Transform LHS lanemasks to new register class if necessary.
3292 for (LiveInterval::SubRange &R : LHS.subranges()) {
3293 LaneBitmask Mask = TRI->composeSubRegIndexLaneMask(DstIdx, R.LaneMask);
3297 LLVM_DEBUG(dbgs() << "\t\tLHST = " << printReg(CP.getDstReg()) << ' ' << LHS
3300 // Determine lanemasks of RHS in the coalesced register and merge subranges.
3301 unsigned SrcIdx = CP.getSrcIdx();
3302 if (!RHS.hasSubRanges()) {
3303 LaneBitmask Mask = SrcIdx == 0 ? CP.getNewRC()->getLaneMask()
3304 : TRI->getSubRegIndexLaneMask(SrcIdx);
3305 mergeSubRangeInto(LHS, RHS, Mask, CP);
3307 // Pair up subranges and merge.
3308 for (LiveInterval::SubRange &R : RHS.subranges()) {
3309 LaneBitmask Mask = TRI->composeSubRegIndexLaneMask(SrcIdx, R.LaneMask);
3310 mergeSubRangeInto(LHS, R, Mask, CP);
3313 LLVM_DEBUG(dbgs() << "\tJoined SubRanges " << LHS << "\n");
3315 // Pruning implicit defs from subranges may result in the main range
3316 // having stale segments.
3317 LHSVals.pruneMainSegments(LHS, ShrinkMainRange);
3319 LHSVals.pruneSubRegValues(LHS, ShrinkMask);
3320 RHSVals.pruneSubRegValues(LHS, ShrinkMask);
3323 // The merging algorithm in LiveInterval::join() can't handle conflicting
3324 // value mappings, so we need to remove any live ranges that overlap a
3325 // CR_Replace resolution. Collect a set of end points that can be used to
3326 // restore the live range after joining.
3327 SmallVector<SlotIndex, 8> EndPoints;
3328 LHSVals.pruneValues(RHSVals, EndPoints, true);
3329 RHSVals.pruneValues(LHSVals, EndPoints, true);
3331 // Erase COPY and IMPLICIT_DEF instructions. This may cause some external
3332 // registers to require trimming.
3333 SmallVector<unsigned, 8> ShrinkRegs;
3334 LHSVals.eraseInstrs(ErasedInstrs, ShrinkRegs, &LHS);
3335 RHSVals.eraseInstrs(ErasedInstrs, ShrinkRegs);
3336 while (!ShrinkRegs.empty())
3337 shrinkToUses(&LIS->getInterval(ShrinkRegs.pop_back_val()));
3339 // Join RHS into LHS.
3340 LHS.join(RHS, LHSVals.getAssignments(), RHSVals.getAssignments(), NewVNInfo);
3342 // Kill flags are going to be wrong if the live ranges were overlapping.
3343 // Eventually, we should simply clear all kill flags when computing live
3344 // ranges. They are reinserted after register allocation.
3345 MRI->clearKillFlags(LHS.reg);
3346 MRI->clearKillFlags(RHS.reg);
3348 if (!EndPoints.empty()) {
3349 // Recompute the parts of the live range we had to remove because of
3350 // CR_Replace conflicts.
3352 dbgs() << "\t\trestoring liveness to " << EndPoints.size() << " points: ";
3353 for (unsigned i = 0, n = EndPoints.size(); i != n; ++i) {
3354 dbgs() << EndPoints[i];
3358 dbgs() << ": " << LHS << '\n';
3360 LIS->extendToIndices((LiveRange&)LHS, EndPoints);
3366 bool RegisterCoalescer::joinIntervals(CoalescerPair &CP) {
3367 return CP.isPhys() ? joinReservedPhysReg(CP) : joinVirtRegs(CP);
3372 /// Information concerning MBB coalescing priority.
3373 struct MBBPriorityInfo {
3374 MachineBasicBlock *MBB;
3378 MBBPriorityInfo(MachineBasicBlock *mbb, unsigned depth, bool issplit)
3379 : MBB(mbb), Depth(depth), IsSplit(issplit) {}
3382 } // end anonymous namespace
3384 /// C-style comparator that sorts first based on the loop depth of the basic
3385 /// block (the unsigned), and then on the MBB number.
3387 /// EnableGlobalCopies assumes that the primary sort key is loop depth.
3388 static int compareMBBPriority(const MBBPriorityInfo *LHS,
3389 const MBBPriorityInfo *RHS) {
3390 // Deeper loops first
3391 if (LHS->Depth != RHS->Depth)
3392 return LHS->Depth > RHS->Depth ? -1 : 1;
3394 // Try to unsplit critical edges next.
3395 if (LHS->IsSplit != RHS->IsSplit)
3396 return LHS->IsSplit ? -1 : 1;
3398 // Prefer blocks that are more connected in the CFG. This takes care of
3399 // the most difficult copies first while intervals are short.
3400 unsigned cl = LHS->MBB->pred_size() + LHS->MBB->succ_size();
3401 unsigned cr = RHS->MBB->pred_size() + RHS->MBB->succ_size();
3403 return cl > cr ? -1 : 1;
3405 // As a last resort, sort by block number.
3406 return LHS->MBB->getNumber() < RHS->MBB->getNumber() ? -1 : 1;
3409 /// \returns true if the given copy uses or defines a local live range.
3410 static bool isLocalCopy(MachineInstr *Copy, const LiveIntervals *LIS) {
3411 if (!Copy->isCopy())
3414 if (Copy->getOperand(1).isUndef())
3417 unsigned SrcReg = Copy->getOperand(1).getReg();
3418 unsigned DstReg = Copy->getOperand(0).getReg();
3419 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)
3420 || TargetRegisterInfo::isPhysicalRegister(DstReg))
3423 return LIS->intervalIsInOneMBB(LIS->getInterval(SrcReg))
3424 || LIS->intervalIsInOneMBB(LIS->getInterval(DstReg));
3427 void RegisterCoalescer::lateLiveIntervalUpdate() {
3428 for (unsigned reg : ToBeUpdated) {
3429 if (!LIS->hasInterval(reg))
3431 LiveInterval &LI = LIS->getInterval(reg);
3432 shrinkToUses(&LI, &DeadDefs);
3433 if (!DeadDefs.empty())
3434 eliminateDeadDefs();
3436 ToBeUpdated.clear();
3439 bool RegisterCoalescer::
3440 copyCoalesceWorkList(MutableArrayRef<MachineInstr*> CurrList) {
3441 bool Progress = false;
3442 for (unsigned i = 0, e = CurrList.size(); i != e; ++i) {
3445 // Skip instruction pointers that have already been erased, for example by
3446 // dead code elimination.
3447 if (ErasedInstrs.count(CurrList[i])) {
3448 CurrList[i] = nullptr;
3452 bool Success = joinCopy(CurrList[i], Again);
3453 Progress |= Success;
3454 if (Success || !Again)
3455 CurrList[i] = nullptr;
3460 /// Check if DstReg is a terminal node.
3461 /// I.e., it does not have any affinity other than \p Copy.
3462 static bool isTerminalReg(unsigned DstReg, const MachineInstr &Copy,
3463 const MachineRegisterInfo *MRI) {
3464 assert(Copy.isCopyLike());
3465 // Check if the destination of this copy as any other affinity.
3466 for (const MachineInstr &MI : MRI->reg_nodbg_instructions(DstReg))
3467 if (&MI != &Copy && MI.isCopyLike())
3472 bool RegisterCoalescer::applyTerminalRule(const MachineInstr &Copy) const {
3473 assert(Copy.isCopyLike());
3474 if (!UseTerminalRule)
3476 unsigned DstReg, DstSubReg, SrcReg, SrcSubReg;
3477 isMoveInstr(*TRI, &Copy, SrcReg, DstReg, SrcSubReg, DstSubReg);
3478 // Check if the destination of this copy has any other affinity.
3479 if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||
3480 // If SrcReg is a physical register, the copy won't be coalesced.
3481 // Ignoring it may have other side effect (like missing
3482 // rematerialization). So keep it.
3483 TargetRegisterInfo::isPhysicalRegister(SrcReg) ||
3484 !isTerminalReg(DstReg, Copy, MRI))
3487 // DstReg is a terminal node. Check if it interferes with any other
3488 // copy involving SrcReg.
3489 const MachineBasicBlock *OrigBB = Copy.getParent();
3490 const LiveInterval &DstLI = LIS->getInterval(DstReg);
3491 for (const MachineInstr &MI : MRI->reg_nodbg_instructions(SrcReg)) {
3492 // Technically we should check if the weight of the new copy is
3493 // interesting compared to the other one and update the weight
3494 // of the copies accordingly. However, this would only work if
3495 // we would gather all the copies first then coalesce, whereas
3496 // right now we interleave both actions.
3497 // For now, just consider the copies that are in the same block.
3498 if (&MI == &Copy || !MI.isCopyLike() || MI.getParent() != OrigBB)
3500 unsigned OtherReg, OtherSubReg, OtherSrcReg, OtherSrcSubReg;
3501 isMoveInstr(*TRI, &Copy, OtherSrcReg, OtherReg, OtherSrcSubReg,
3503 if (OtherReg == SrcReg)
3504 OtherReg = OtherSrcReg;
3505 // Check if OtherReg is a non-terminal.
3506 if (TargetRegisterInfo::isPhysicalRegister(OtherReg) ||
3507 isTerminalReg(OtherReg, MI, MRI))
3509 // Check that OtherReg interfere with DstReg.
3510 if (LIS->getInterval(OtherReg).overlaps(DstLI)) {
3511 LLVM_DEBUG(dbgs() << "Apply terminal rule for: " << printReg(DstReg)
3520 RegisterCoalescer::copyCoalesceInMBB(MachineBasicBlock *MBB) {
3521 LLVM_DEBUG(dbgs() << MBB->getName() << ":\n");
3523 // Collect all copy-like instructions in MBB. Don't start coalescing anything
3524 // yet, it might invalidate the iterator.
3525 const unsigned PrevSize = WorkList.size();
3526 if (JoinGlobalCopies) {
3527 SmallVector<MachineInstr*, 2> LocalTerminals;
3528 SmallVector<MachineInstr*, 2> GlobalTerminals;
3529 // Coalesce copies bottom-up to coalesce local defs before local uses. They
3530 // are not inherently easier to resolve, but slightly preferable until we
3531 // have local live range splitting. In particular this is required by
3532 // cmp+jmp macro fusion.
3533 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
3535 if (!MII->isCopyLike())
3537 bool ApplyTerminalRule = applyTerminalRule(*MII);
3538 if (isLocalCopy(&(*MII), LIS)) {
3539 if (ApplyTerminalRule)
3540 LocalTerminals.push_back(&(*MII));
3542 LocalWorkList.push_back(&(*MII));
3544 if (ApplyTerminalRule)
3545 GlobalTerminals.push_back(&(*MII));
3547 WorkList.push_back(&(*MII));
3550 // Append the copies evicted by the terminal rule at the end of the list.
3551 LocalWorkList.append(LocalTerminals.begin(), LocalTerminals.end());
3552 WorkList.append(GlobalTerminals.begin(), GlobalTerminals.end());
3555 SmallVector<MachineInstr*, 2> Terminals;
3556 for (MachineInstr &MII : *MBB)
3557 if (MII.isCopyLike()) {
3558 if (applyTerminalRule(MII))
3559 Terminals.push_back(&MII);
3561 WorkList.push_back(&MII);
3563 // Append the copies evicted by the terminal rule at the end of the list.
3564 WorkList.append(Terminals.begin(), Terminals.end());
3566 // Try coalescing the collected copies immediately, and remove the nulls.
3567 // This prevents the WorkList from getting too large since most copies are
3568 // joinable on the first attempt.
3569 MutableArrayRef<MachineInstr*>
3570 CurrList(WorkList.begin() + PrevSize, WorkList.end());
3571 if (copyCoalesceWorkList(CurrList))
3572 WorkList.erase(std::remove(WorkList.begin() + PrevSize, WorkList.end(),
3573 nullptr), WorkList.end());
3576 void RegisterCoalescer::coalesceLocals() {
3577 copyCoalesceWorkList(LocalWorkList);
3578 for (unsigned j = 0, je = LocalWorkList.size(); j != je; ++j) {
3579 if (LocalWorkList[j])
3580 WorkList.push_back(LocalWorkList[j]);
3582 LocalWorkList.clear();
3585 void RegisterCoalescer::joinAllIntervals() {
3586 LLVM_DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
3587 assert(WorkList.empty() && LocalWorkList.empty() && "Old data still around.");
3589 std::vector<MBBPriorityInfo> MBBs;
3590 MBBs.reserve(MF->size());
3591 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
3592 MachineBasicBlock *MBB = &*I;
3593 MBBs.push_back(MBBPriorityInfo(MBB, Loops->getLoopDepth(MBB),
3594 JoinSplitEdges && isSplitEdge(MBB)));
3596 array_pod_sort(MBBs.begin(), MBBs.end(), compareMBBPriority);
3598 // Coalesce intervals in MBB priority order.
3599 unsigned CurrDepth = std::numeric_limits<unsigned>::max();
3600 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
3601 // Try coalescing the collected local copies for deeper loops.
3602 if (JoinGlobalCopies && MBBs[i].Depth < CurrDepth) {
3604 CurrDepth = MBBs[i].Depth;
3606 copyCoalesceInMBB(MBBs[i].MBB);
3608 lateLiveIntervalUpdate();
3611 // Joining intervals can allow other intervals to be joined. Iteratively join
3612 // until we make no progress.
3613 while (copyCoalesceWorkList(WorkList))
3615 lateLiveIntervalUpdate();
3618 void RegisterCoalescer::releaseMemory() {
3619 ErasedInstrs.clear();
3622 InflateRegs.clear();
3625 bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
3627 MRI = &fn.getRegInfo();
3628 const TargetSubtargetInfo &STI = fn.getSubtarget();
3629 TRI = STI.getRegisterInfo();
3630 TII = STI.getInstrInfo();
3631 LIS = &getAnalysis<LiveIntervals>();
3632 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
3633 Loops = &getAnalysis<MachineLoopInfo>();
3634 if (EnableGlobalCopies == cl::BOU_UNSET)
3635 JoinGlobalCopies = STI.enableJoinGlobalCopies();
3637 JoinGlobalCopies = (EnableGlobalCopies == cl::BOU_TRUE);
3639 // The MachineScheduler does not currently require JoinSplitEdges. This will
3640 // either be enabled unconditionally or replaced by a more general live range
3641 // splitting optimization.
3642 JoinSplitEdges = EnableJoinSplits;
3644 LLVM_DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
3645 << "********** Function: " << MF->getName() << '\n');
3647 if (VerifyCoalescing)
3648 MF->verify(this, "Before register coalescing");
3650 RegClassInfo.runOnMachineFunction(fn);
3652 // Join (coalesce) intervals if requested.
3656 // After deleting a lot of copies, register classes may be less constrained.
3657 // Removing sub-register operands may allow GR32_ABCD -> GR32 and DPR_VFP2 ->
3659 array_pod_sort(InflateRegs.begin(), InflateRegs.end());
3660 InflateRegs.erase(std::unique(InflateRegs.begin(), InflateRegs.end()),
3662 LLVM_DEBUG(dbgs() << "Trying to inflate " << InflateRegs.size()
3664 for (unsigned i = 0, e = InflateRegs.size(); i != e; ++i) {
3665 unsigned Reg = InflateRegs[i];
3666 if (MRI->reg_nodbg_empty(Reg))
3668 if (MRI->recomputeRegClass(Reg)) {
3669 LLVM_DEBUG(dbgs() << printReg(Reg) << " inflated to "
3670 << TRI->getRegClassName(MRI->getRegClass(Reg)) << '\n');
3673 LiveInterval &LI = LIS->getInterval(Reg);
3674 if (LI.hasSubRanges()) {
3675 // If the inflated register class does not support subregisters anymore
3676 // remove the subranges.
3677 if (!MRI->shouldTrackSubRegLiveness(Reg)) {
3678 LI.clearSubRanges();
3681 LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
3682 // If subranges are still supported, then the same subregs
3683 // should still be supported.
3684 for (LiveInterval::SubRange &S : LI.subranges()) {
3685 assert((S.LaneMask & ~MaxMask).none());
3694 if (VerifyCoalescing)
3695 MF->verify(this, "After register coalescing");
3699 void RegisterCoalescer::print(raw_ostream &O, const Module* m) const {