1 //===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// \file This implements the ScheduleDAGInstrs class, which implements
11 /// re-scheduling of MachineInstrs.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
16 #include "llvm/ADT/IntEqClasses.h"
17 #include "llvm/ADT/SmallPtrSet.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/ValueTracking.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineMemOperand.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/CodeGen/RegisterPressure.h"
29 #include "llvm/CodeGen/ScheduleDFS.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/Type.h"
32 #include "llvm/IR/Operator.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/Format.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetRegisterInfo.h"
40 #include "llvm/Target/TargetSubtargetInfo.h"
44 #define DEBUG_TYPE "misched"
46 static cl::opt<bool> EnableAASchedMI("enable-aa-sched-mi", cl::Hidden,
47 cl::ZeroOrMore, cl::init(false),
48 cl::desc("Enable use of AA during MI DAG construction"));
50 static cl::opt<bool> UseTBAA("use-tbaa-in-sched-mi", cl::Hidden,
51 cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"));
53 // Note: the two options below might be used in tuning compile time vs
54 // output quality. Setting HugeRegion so large that it will never be
55 // reached means best-effort, but may be slow.
57 // When Stores and Loads maps (or NonAliasStores and NonAliasLoads)
58 // together hold this many SUs, a reduction of maps will be done.
59 static cl::opt<unsigned> HugeRegion("dag-maps-huge-region", cl::Hidden,
60 cl::init(1000), cl::desc("The limit to use while constructing the DAG "
61 "prior to scheduling, at which point a trade-off "
62 "is made to avoid excessive compile time."));
64 static cl::opt<unsigned> ReductionSize(
65 "dag-maps-reduction-size", cl::Hidden,
66 cl::desc("A huge scheduling region will have maps reduced by this many "
67 "nodes at a time. Defaults to HugeRegion / 2."));
69 static unsigned getReductionSize() {
70 // Always reduce a huge region with half of the elements, except
71 // when user sets this number explicitly.
72 if (ReductionSize.getNumOccurrences() == 0)
73 return HugeRegion / 2;
77 static void dumpSUList(ScheduleDAGInstrs::SUList &L) {
78 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
80 for (const SUnit *su : L) {
81 dbgs() << "SU(" << su->NodeNum << ")";
89 ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
90 const MachineLoopInfo *mli,
92 : ScheduleDAG(mf), MLI(mli), MFI(mf.getFrameInfo()),
93 RemoveKillFlags(RemoveKillFlags), CanHandleTerminators(false),
94 TrackLaneMasks(false), AAForDep(nullptr), BarrierChain(nullptr),
95 UnknownValue(UndefValue::get(
96 Type::getVoidTy(mf.getFunction()->getContext()))),
97 FirstDbgValue(nullptr) {
100 const TargetSubtargetInfo &ST = mf.getSubtarget();
101 SchedModel.init(ST.getSchedModel(), &ST, TII);
104 /// This is the function that does the work of looking through basic
105 /// ptrtoint+arithmetic+inttoptr sequences.
106 static const Value *getUnderlyingObjectFromInt(const Value *V) {
108 if (const Operator *U = dyn_cast<Operator>(V)) {
109 // If we find a ptrtoint, we can transfer control back to the
110 // regular getUnderlyingObjectFromInt.
111 if (U->getOpcode() == Instruction::PtrToInt)
112 return U->getOperand(0);
113 // If we find an add of a constant, a multiplied value, or a phi, it's
114 // likely that the other operand will lead us to the base
115 // object. We don't have to worry about the case where the
116 // object address is somehow being computed by the multiply,
117 // because our callers only care when the result is an
118 // identifiable object.
119 if (U->getOpcode() != Instruction::Add ||
120 (!isa<ConstantInt>(U->getOperand(1)) &&
121 Operator::getOpcode(U->getOperand(1)) != Instruction::Mul &&
122 !isa<PHINode>(U->getOperand(1))))
124 V = U->getOperand(0);
128 assert(V->getType()->isIntegerTy() && "Unexpected operand type!");
132 /// This is a wrapper around GetUnderlyingObjects and adds support for basic
133 /// ptrtoint+arithmetic+inttoptr sequences.
134 static void getUnderlyingObjects(const Value *V,
135 SmallVectorImpl<Value *> &Objects,
136 const DataLayout &DL) {
137 SmallPtrSet<const Value *, 16> Visited;
138 SmallVector<const Value *, 4> Working(1, V);
140 V = Working.pop_back_val();
142 SmallVector<Value *, 4> Objs;
143 GetUnderlyingObjects(const_cast<Value *>(V), Objs, DL);
145 for (Value *V : Objs) {
146 if (!Visited.insert(V).second)
148 if (Operator::getOpcode(V) == Instruction::IntToPtr) {
150 getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0));
151 if (O->getType()->isPointerTy()) {
152 Working.push_back(O);
156 Objects.push_back(const_cast<Value *>(V));
158 } while (!Working.empty());
161 /// If this machine instr has memory reference information and it can be tracked
162 /// to a normal reference to a known object, return the Value for that object.
163 static void getUnderlyingObjectsForInstr(const MachineInstr *MI,
164 const MachineFrameInfo &MFI,
165 UnderlyingObjectsVector &Objects,
166 const DataLayout &DL) {
167 auto allMMOsOkay = [&]() {
168 for (const MachineMemOperand *MMO : MI->memoperands()) {
169 if (MMO->isVolatile())
172 if (const PseudoSourceValue *PSV = MMO->getPseudoValue()) {
173 // Function that contain tail calls don't have unique PseudoSourceValue
174 // objects. Two PseudoSourceValues might refer to the same or
175 // overlapping locations. The client code calling this function assumes
176 // this is not the case. So return a conservative answer of no known
178 if (MFI.hasTailCall())
181 // For now, ignore PseudoSourceValues which may alias LLVM IR values
182 // because the code that uses this function has no way to cope with
184 if (PSV->isAliased(&MFI))
187 bool MayAlias = PSV->mayAlias(&MFI);
188 Objects.push_back(UnderlyingObjectsVector::value_type(PSV, MayAlias));
189 } else if (const Value *V = MMO->getValue()) {
190 SmallVector<Value *, 4> Objs;
191 getUnderlyingObjects(V, Objs, DL);
193 for (Value *V : Objs) {
194 if (!isIdentifiedObject(V))
197 Objects.push_back(UnderlyingObjectsVector::value_type(V, true));
209 void ScheduleDAGInstrs::startBlock(MachineBasicBlock *bb) {
213 void ScheduleDAGInstrs::finishBlock() {
214 // Subclasses should no longer refer to the old block.
218 void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb,
219 MachineBasicBlock::iterator begin,
220 MachineBasicBlock::iterator end,
221 unsigned regioninstrs) {
222 assert(bb == BB && "startBlock should set BB");
225 NumRegionInstrs = regioninstrs;
228 void ScheduleDAGInstrs::exitRegion() {
232 void ScheduleDAGInstrs::addSchedBarrierDeps() {
233 MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : nullptr;
234 ExitSU.setInstr(ExitMI);
235 // Add dependencies on the defs and uses of the instruction.
237 for (const MachineOperand &MO : ExitMI->operands()) {
238 if (!MO.isReg() || MO.isDef()) continue;
239 unsigned Reg = MO.getReg();
240 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
241 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
242 } else if (TargetRegisterInfo::isVirtualRegister(Reg) && MO.readsReg()) {
243 addVRegUseDeps(&ExitSU, ExitMI->getOperandNo(&MO));
247 if (!ExitMI || (!ExitMI->isCall() && !ExitMI->isBarrier())) {
248 // For others, e.g. fallthrough, conditional branch, assume the exit
249 // uses all the registers that are livein to the successor blocks.
250 for (const MachineBasicBlock *Succ : BB->successors()) {
251 for (const auto &LI : Succ->liveins()) {
252 if (!Uses.contains(LI.PhysReg))
253 Uses.insert(PhysRegSUOper(&ExitSU, -1, LI.PhysReg));
259 /// MO is an operand of SU's instruction that defines a physical register. Adds
260 /// data dependencies from SU to any uses of the physical register.
261 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
262 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
263 assert(MO.isDef() && "expect physreg def");
265 // Ask the target if address-backscheduling is desirable, and if so how much.
266 const TargetSubtargetInfo &ST = MF.getSubtarget();
268 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
269 Alias.isValid(); ++Alias) {
270 if (!Uses.contains(*Alias))
272 for (Reg2SUnitsMap::iterator I = Uses.find(*Alias); I != Uses.end(); ++I) {
273 SUnit *UseSU = I->SU;
277 // Adjust the dependence latency using operand def/use information,
278 // then allow the target to perform its own adjustments.
279 int UseOp = I->OpIdx;
280 MachineInstr *RegUse = nullptr;
283 Dep = SDep(SU, SDep::Artificial);
285 // Set the hasPhysRegDefs only for physreg defs that have a use within
286 // the scheduling region.
287 SU->hasPhysRegDefs = true;
288 Dep = SDep(SU, SDep::Data, *Alias);
289 RegUse = UseSU->getInstr();
292 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse,
295 ST.adjustSchedDependency(SU, UseSU, Dep);
301 /// \brief Adds register dependencies (data, anti, and output) from this SUnit
302 /// to following instructions in the same scheduling region that depend the
303 /// physical register referenced at OperIdx.
304 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
305 MachineInstr *MI = SU->getInstr();
306 MachineOperand &MO = MI->getOperand(OperIdx);
307 unsigned Reg = MO.getReg();
308 // We do not need to track any dependencies for constant registers.
309 if (MRI.isConstantPhysReg(Reg))
312 // Optionally add output and anti dependencies. For anti
313 // dependencies we use a latency of 0 because for a multi-issue
314 // target we want to allow the defining instruction to issue
315 // in the same cycle as the using instruction.
316 // TODO: Using a latency of 1 here for output dependencies assumes
317 // there's no cost for reusing registers.
318 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
319 for (MCRegAliasIterator Alias(Reg, TRI, true); Alias.isValid(); ++Alias) {
320 if (!Defs.contains(*Alias))
322 for (Reg2SUnitsMap::iterator I = Defs.find(*Alias); I != Defs.end(); ++I) {
323 SUnit *DefSU = I->SU;
324 if (DefSU == &ExitSU)
327 (Kind != SDep::Output || !MO.isDead() ||
328 !DefSU->getInstr()->registerDefIsDead(*Alias))) {
329 if (Kind == SDep::Anti)
330 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias));
332 SDep Dep(SU, Kind, /*Reg=*/*Alias);
334 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
342 SU->hasPhysRegUses = true;
343 // Either insert a new Reg2SUnits entry with an empty SUnits list, or
344 // retrieve the existing SUnits list for this register's uses.
345 // Push this SUnit on the use list.
346 Uses.insert(PhysRegSUOper(SU, OperIdx, Reg));
350 addPhysRegDataDeps(SU, OperIdx);
352 // clear this register's use list
353 if (Uses.contains(Reg))
358 } else if (SU->isCall) {
359 // Calls will not be reordered because of chain dependencies (see
360 // below). Since call operands are dead, calls may continue to be added
361 // to the DefList making dependence checking quadratic in the size of
362 // the block. Instead, we leave only one call at the back of the
364 Reg2SUnitsMap::RangePair P = Defs.equal_range(Reg);
365 Reg2SUnitsMap::iterator B = P.first;
366 Reg2SUnitsMap::iterator I = P.second;
367 for (bool isBegin = I == B; !isBegin; /* empty */) {
368 isBegin = (--I) == B;
375 // Defs are pushed in the order they are visited and never reordered.
376 Defs.insert(PhysRegSUOper(SU, OperIdx, Reg));
380 LaneBitmask ScheduleDAGInstrs::getLaneMaskForMO(const MachineOperand &MO) const
382 unsigned Reg = MO.getReg();
383 // No point in tracking lanemasks if we don't have interesting subregisters.
384 const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
385 if (!RC.HasDisjunctSubRegs)
386 return LaneBitmask::getAll();
388 unsigned SubReg = MO.getSubReg();
390 return RC.getLaneMask();
391 return TRI->getSubRegIndexLaneMask(SubReg);
394 /// Adds register output and data dependencies from this SUnit to instructions
395 /// that occur later in the same scheduling region if they read from or write to
396 /// the virtual register defined at OperIdx.
398 /// TODO: Hoist loop induction variable increments. This has to be
399 /// reevaluated. Generally, IV scheduling should be done before coalescing.
400 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
401 MachineInstr *MI = SU->getInstr();
402 MachineOperand &MO = MI->getOperand(OperIdx);
403 unsigned Reg = MO.getReg();
405 LaneBitmask DefLaneMask;
406 LaneBitmask KillLaneMask;
407 if (TrackLaneMasks) {
408 bool IsKill = MO.getSubReg() == 0 || MO.isUndef();
409 DefLaneMask = getLaneMaskForMO(MO);
410 // If we have a <read-undef> flag, none of the lane values comes from an
411 // earlier instruction.
412 KillLaneMask = IsKill ? LaneBitmask::getAll() : DefLaneMask;
414 // Clear undef flag, we'll re-add it later once we know which subregister
416 MO.setIsUndef(false);
418 DefLaneMask = LaneBitmask::getAll();
419 KillLaneMask = LaneBitmask::getAll();
423 assert(CurrentVRegUses.find(Reg) == CurrentVRegUses.end() &&
424 "Dead defs should have no uses");
426 // Add data dependence to all uses we found so far.
427 const TargetSubtargetInfo &ST = MF.getSubtarget();
428 for (VReg2SUnitOperIdxMultiMap::iterator I = CurrentVRegUses.find(Reg),
429 E = CurrentVRegUses.end(); I != E; /*empty*/) {
430 LaneBitmask LaneMask = I->LaneMask;
431 // Ignore uses of other lanes.
432 if ((LaneMask & KillLaneMask).none()) {
437 if ((LaneMask & DefLaneMask).any()) {
438 SUnit *UseSU = I->SU;
439 MachineInstr *Use = UseSU->getInstr();
440 SDep Dep(SU, SDep::Data, Reg);
441 Dep.setLatency(SchedModel.computeOperandLatency(MI, OperIdx, Use,
443 ST.adjustSchedDependency(SU, UseSU, Dep);
447 LaneMask &= ~KillLaneMask;
448 // If we found a Def for all lanes of this use, remove it from the list.
449 if (LaneMask.any()) {
450 I->LaneMask = LaneMask;
453 I = CurrentVRegUses.erase(I);
457 // Shortcut: Singly defined vregs do not have output/anti dependencies.
458 if (MRI.hasOneDef(Reg))
461 // Add output dependence to the next nearest defs of this vreg.
463 // Unless this definition is dead, the output dependence should be
464 // transitively redundant with antidependencies from this definition's
465 // uses. We're conservative for now until we have a way to guarantee the uses
466 // are not eliminated sometime during scheduling. The output dependence edge
467 // is also useful if output latency exceeds def-use latency.
468 LaneBitmask LaneMask = DefLaneMask;
469 for (VReg2SUnit &V2SU : make_range(CurrentVRegDefs.find(Reg),
470 CurrentVRegDefs.end())) {
471 // Ignore defs for other lanes.
472 if ((V2SU.LaneMask & LaneMask).none())
474 // Add an output dependence.
475 SUnit *DefSU = V2SU.SU;
476 // Ignore additional defs of the same lanes in one instruction. This can
477 // happen because lanemasks are shared for targets with too many
478 // subregisters. We also use some representration tricks/hacks where we
479 // add super-register defs/uses, to imply that although we only access parts
480 // of the reg we care about the full one.
483 SDep Dep(SU, SDep::Output, Reg);
485 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
488 // Update current definition. This can get tricky if the def was about a
489 // bigger lanemask before. We then have to shrink it and create a new
490 // VReg2SUnit for the non-overlapping part.
491 LaneBitmask OverlapMask = V2SU.LaneMask & LaneMask;
492 LaneBitmask NonOverlapMask = V2SU.LaneMask & ~LaneMask;
494 V2SU.LaneMask = OverlapMask;
495 if (NonOverlapMask.any())
496 CurrentVRegDefs.insert(VReg2SUnit(Reg, NonOverlapMask, DefSU));
498 // If there was no CurrentVRegDefs entry for some lanes yet, create one.
500 CurrentVRegDefs.insert(VReg2SUnit(Reg, LaneMask, SU));
503 /// \brief Adds a register data dependency if the instruction that defines the
504 /// virtual register used at OperIdx is mapped to an SUnit. Add a register
505 /// antidependency from this SUnit to instructions that occur later in the same
506 /// scheduling region if they write the virtual register.
508 /// TODO: Handle ExitSU "uses" properly.
509 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
510 const MachineInstr *MI = SU->getInstr();
511 const MachineOperand &MO = MI->getOperand(OperIdx);
512 unsigned Reg = MO.getReg();
514 // Remember the use. Data dependencies will be added when we find the def.
515 LaneBitmask LaneMask = TrackLaneMasks ? getLaneMaskForMO(MO)
516 : LaneBitmask::getAll();
517 CurrentVRegUses.insert(VReg2SUnitOperIdx(Reg, LaneMask, OperIdx, SU));
519 // Add antidependences to the following defs of the vreg.
520 for (VReg2SUnit &V2SU : make_range(CurrentVRegDefs.find(Reg),
521 CurrentVRegDefs.end())) {
522 // Ignore defs for unrelated lanes.
523 LaneBitmask PrevDefLaneMask = V2SU.LaneMask;
524 if ((PrevDefLaneMask & LaneMask).none())
529 V2SU.SU->addPred(SDep(SU, SDep::Anti, Reg));
533 /// Returns true if MI is an instruction we are unable to reason about
534 /// (like a call or something with unmodeled side effects).
535 static inline bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) {
536 return MI->isCall() || MI->hasUnmodeledSideEffects() ||
537 (MI->hasOrderedMemoryRef() && !MI->isDereferenceableInvariantLoad(AA));
540 void ScheduleDAGInstrs::addChainDependency (SUnit *SUa, SUnit *SUb,
542 if (SUa->getInstr()->mayAlias(AAForDep, *SUb->getInstr(), UseTBAA)) {
543 SDep Dep(SUa, SDep::MayAliasMem);
544 Dep.setLatency(Latency);
549 /// \brief Creates an SUnit for each real instruction, numbered in top-down
550 /// topological order. The instruction order A < B, implies that no edge exists
553 /// Map each real instruction to its SUnit.
555 /// After initSUnits, the SUnits vector cannot be resized and the scheduler may
556 /// hang onto SUnit pointers. We may relax this in the future by using SUnit IDs
557 /// instead of pointers.
559 /// MachineScheduler relies on initSUnits numbering the nodes by their order in
560 /// the original instruction list.
561 void ScheduleDAGInstrs::initSUnits() {
562 // We'll be allocating one SUnit for each real instruction in the region,
563 // which is contained within a basic block.
564 SUnits.reserve(NumRegionInstrs);
566 for (MachineInstr &MI : llvm::make_range(RegionBegin, RegionEnd)) {
567 if (MI.isDebugValue())
570 SUnit *SU = newSUnit(&MI);
571 MISUnitMap[&MI] = SU;
573 SU->isCall = MI.isCall();
574 SU->isCommutable = MI.isCommutable();
576 // Assign the Latency field of SU using target-provided information.
577 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
579 // If this SUnit uses a reserved or unbuffered resource, mark it as such.
581 // Reserved resources block an instruction from issuing and stall the
582 // entire pipeline. These are identified by BufferSize=0.
584 // Unbuffered resources prevent execution of subsequent instructions that
585 // require the same resources. This is used for in-order execution pipelines
586 // within an out-of-order core. These are identified by BufferSize=1.
587 if (SchedModel.hasInstrSchedModel()) {
588 const MCSchedClassDesc *SC = getSchedClass(SU);
589 for (const MCWriteProcResEntry &PRE :
590 make_range(SchedModel.getWriteProcResBegin(SC),
591 SchedModel.getWriteProcResEnd(SC))) {
592 switch (SchedModel.getProcResource(PRE.ProcResourceIdx)->BufferSize) {
594 SU->hasReservedResource = true;
597 SU->isUnbuffered = true;
607 class ScheduleDAGInstrs::Value2SUsMap : public MapVector<ValueType, SUList> {
608 /// Current total number of SUs in map.
611 /// 1 for loads, 0 for stores. (see comment in SUList)
612 unsigned TrueMemOrderLatency;
615 Value2SUsMap(unsigned lat = 0) : NumNodes(0), TrueMemOrderLatency(lat) {}
617 /// To keep NumNodes up to date, insert() is used instead of
618 /// this operator w/ push_back().
619 ValueType &operator[](const SUList &Key) {
620 llvm_unreachable("Don't use. Use insert() instead."); };
622 /// Adds SU to the SUList of V. If Map grows huge, reduce its size by calling
624 void inline insert(SUnit *SU, ValueType V) {
625 MapVector::operator[](V).push_back(SU);
629 /// Clears the list of SUs mapped to V.
630 void inline clearList(ValueType V) {
631 iterator Itr = find(V);
633 assert (NumNodes >= Itr->second.size());
634 NumNodes -= Itr->second.size();
640 /// Clears map from all contents.
642 MapVector<ValueType, SUList>::clear();
646 unsigned inline size() const { return NumNodes; }
648 /// Counts the number of SUs in this map after a reduction.
649 void reComputeSize(void) {
651 for (auto &I : *this)
652 NumNodes += I.second.size();
655 unsigned inline getTrueMemOrderLatency() const {
656 return TrueMemOrderLatency;
662 void ScheduleDAGInstrs::addChainDependencies(SUnit *SU,
663 Value2SUsMap &Val2SUsMap) {
664 for (auto &I : Val2SUsMap)
665 addChainDependencies(SU, I.second,
666 Val2SUsMap.getTrueMemOrderLatency());
669 void ScheduleDAGInstrs::addChainDependencies(SUnit *SU,
670 Value2SUsMap &Val2SUsMap,
672 Value2SUsMap::iterator Itr = Val2SUsMap.find(V);
673 if (Itr != Val2SUsMap.end())
674 addChainDependencies(SU, Itr->second,
675 Val2SUsMap.getTrueMemOrderLatency());
678 void ScheduleDAGInstrs::addBarrierChain(Value2SUsMap &map) {
679 assert (BarrierChain != nullptr);
681 for (auto &I : map) {
682 SUList &sus = I.second;
684 SU->addPredBarrier(BarrierChain);
689 void ScheduleDAGInstrs::insertBarrierChain(Value2SUsMap &map) {
690 assert (BarrierChain != nullptr);
692 // Go through all lists of SUs.
693 for (Value2SUsMap::iterator I = map.begin(), EE = map.end(); I != EE;) {
694 Value2SUsMap::iterator CurrItr = I++;
695 SUList &sus = CurrItr->second;
696 SUList::iterator SUItr = sus.begin(), SUEE = sus.end();
697 for (; SUItr != SUEE; ++SUItr) {
698 // Stop on BarrierChain or any instruction above it.
699 if ((*SUItr)->NodeNum <= BarrierChain->NodeNum)
702 (*SUItr)->addPredBarrier(BarrierChain);
705 // Remove also the BarrierChain from list if present.
706 if (SUItr != SUEE && *SUItr == BarrierChain)
709 // Remove all SUs that are now successors of BarrierChain.
710 if (SUItr != sus.begin())
711 sus.erase(sus.begin(), SUItr);
714 // Remove all entries with empty su lists.
715 map.remove_if([&](std::pair<ValueType, SUList> &mapEntry) {
716 return (mapEntry.second.empty()); });
718 // Recompute the size of the map (NumNodes).
722 void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
723 RegPressureTracker *RPTracker,
724 PressureDiffs *PDiffs,
726 bool TrackLaneMasks) {
727 const TargetSubtargetInfo &ST = MF.getSubtarget();
728 bool UseAA = EnableAASchedMI.getNumOccurrences() > 0 ? EnableAASchedMI
730 AAForDep = UseAA ? AA : nullptr;
732 BarrierChain = nullptr;
734 this->TrackLaneMasks = TrackLaneMasks;
736 ScheduleDAG::clearDAG();
738 // Create an SUnit for each real instruction.
742 PDiffs->init(SUnits.size());
744 // We build scheduling units by walking a block's instruction list
745 // from bottom to top.
747 // Each MIs' memory operand(s) is analyzed to a list of underlying
748 // objects. The SU is then inserted in the SUList(s) mapped from the
749 // Value(s). Each Value thus gets mapped to lists of SUs depending
750 // on it, stores and loads kept separately. Two SUs are trivially
751 // non-aliasing if they both depend on only identified Values and do
752 // not share any common Value.
753 Value2SUsMap Stores, Loads(1 /*TrueMemOrderLatency*/);
755 // Certain memory accesses are known to not alias any SU in Stores
756 // or Loads, and have therefore their own 'NonAlias'
757 // domain. E.g. spill / reload instructions never alias LLVM I/R
758 // Values. It would be nice to assume that this type of memory
759 // accesses always have a proper memory operand modelling, and are
760 // therefore never unanalyzable, but this is conservatively not
762 Value2SUsMap NonAliasStores, NonAliasLoads(1 /*TrueMemOrderLatency*/);
764 // Remove any stale debug info; sometimes BuildSchedGraph is called again
765 // without emitting the info from the previous call.
767 FirstDbgValue = nullptr;
769 assert(Defs.empty() && Uses.empty() &&
770 "Only BuildGraph should update Defs/Uses");
771 Defs.setUniverse(TRI->getNumRegs());
772 Uses.setUniverse(TRI->getNumRegs());
774 assert(CurrentVRegDefs.empty() && "nobody else should use CurrentVRegDefs");
775 assert(CurrentVRegUses.empty() && "nobody else should use CurrentVRegUses");
776 unsigned NumVirtRegs = MRI.getNumVirtRegs();
777 CurrentVRegDefs.setUniverse(NumVirtRegs);
778 CurrentVRegUses.setUniverse(NumVirtRegs);
780 // Model data dependencies between instructions being scheduled and the
782 addSchedBarrierDeps();
784 // Walk the list of instructions, from bottom moving up.
785 MachineInstr *DbgMI = nullptr;
786 for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
788 MachineInstr &MI = *std::prev(MII);
790 DbgValues.push_back(std::make_pair(DbgMI, &MI));
794 if (MI.isDebugValue()) {
798 SUnit *SU = MISUnitMap[&MI];
799 assert(SU && "No SUnit mapped to this MI");
802 RegisterOperands RegOpers;
803 RegOpers.collect(MI, *TRI, MRI, TrackLaneMasks, false);
804 if (TrackLaneMasks) {
805 SlotIndex SlotIdx = LIS->getInstructionIndex(MI);
806 RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx);
808 if (PDiffs != nullptr)
809 PDiffs->addInstruction(SU->NodeNum, RegOpers, MRI);
811 RPTracker->recedeSkipDebugValues();
812 assert(&*RPTracker->getPos() == &MI && "RPTracker in sync");
813 RPTracker->recede(RegOpers);
817 (CanHandleTerminators || (!MI.isTerminator() && !MI.isPosition())) &&
818 "Cannot schedule terminators or labels!");
820 // Add register-based dependencies (data, anti, and output).
821 // For some instructions (calls, returns, inline-asm, etc.) there can
822 // be explicit uses and implicit defs, in which case the use will appear
823 // on the operand list before the def. Do two passes over the operand
824 // list to make sure that defs are processed before any uses.
825 bool HasVRegDef = false;
826 for (unsigned j = 0, n = MI.getNumOperands(); j != n; ++j) {
827 const MachineOperand &MO = MI.getOperand(j);
828 if (!MO.isReg() || !MO.isDef())
830 unsigned Reg = MO.getReg();
831 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
832 addPhysRegDeps(SU, j);
833 } else if (TargetRegisterInfo::isVirtualRegister(Reg)) {
835 addVRegDefDeps(SU, j);
838 // Now process all uses.
839 for (unsigned j = 0, n = MI.getNumOperands(); j != n; ++j) {
840 const MachineOperand &MO = MI.getOperand(j);
841 // Only look at use operands.
842 // We do not need to check for MO.readsReg() here because subsequent
843 // subregister defs will get output dependence edges and need no
844 // additional use dependencies.
845 if (!MO.isReg() || !MO.isUse())
847 unsigned Reg = MO.getReg();
848 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
849 addPhysRegDeps(SU, j);
850 } else if (TargetRegisterInfo::isVirtualRegister(Reg) && MO.readsReg()) {
851 addVRegUseDeps(SU, j);
855 // If we haven't seen any uses in this scheduling region, create a
856 // dependence edge to ExitSU to model the live-out latency. This is required
857 // for vreg defs with no in-region use, and prefetches with no vreg def.
859 // FIXME: NumDataSuccs would be more precise than NumSuccs here. This
860 // check currently relies on being called before adding chain deps.
861 if (SU->NumSuccs == 0 && SU->Latency > 1 && (HasVRegDef || MI.mayLoad())) {
862 SDep Dep(SU, SDep::Artificial);
863 Dep.setLatency(SU->Latency - 1);
867 // Add memory dependencies (Note: isStoreToStackSlot and
868 // isLoadFromStackSLot are not usable after stack slots are lowered to
869 // actual addresses).
871 // This is a barrier event that acts as a pivotal node in the DAG.
872 if (isGlobalMemoryObject(AA, &MI)) {
874 // Become the barrier chain.
876 BarrierChain->addPredBarrier(SU);
879 DEBUG(dbgs() << "Global memory object and new barrier chain: SU("
880 << BarrierChain->NodeNum << ").\n";);
882 // Add dependencies against everything below it and clear maps.
883 addBarrierChain(Stores);
884 addBarrierChain(Loads);
885 addBarrierChain(NonAliasStores);
886 addBarrierChain(NonAliasLoads);
891 // If it's not a store or a variant load, we're done.
892 if (!MI.mayStore() &&
893 !(MI.mayLoad() && !MI.isDereferenceableInvariantLoad(AA)))
896 // Always add dependecy edge to BarrierChain if present.
898 BarrierChain->addPredBarrier(SU);
900 // Find the underlying objects for MI. The Objs vector is either
901 // empty, or filled with the Values of memory locations which this
902 // SU depends on. An empty vector means the memory location is
903 // unknown, and may alias anything.
904 UnderlyingObjectsVector Objs;
905 getUnderlyingObjectsForInstr(&MI, MFI, Objs, MF.getDataLayout());
909 // An unknown store depends on all stores and loads.
910 addChainDependencies(SU, Stores);
911 addChainDependencies(SU, NonAliasStores);
912 addChainDependencies(SU, Loads);
913 addChainDependencies(SU, NonAliasLoads);
915 // Map this store to 'UnknownValue'.
916 Stores.insert(SU, UnknownValue);
918 // Add precise dependencies against all previously seen memory
919 // accesses mapped to the same Value(s).
920 for (const UnderlyingObject &UnderlObj : Objs) {
921 ValueType V = UnderlObj.getValue();
922 bool ThisMayAlias = UnderlObj.mayAlias();
924 // Add dependencies to previous stores and loads mapped to V.
925 addChainDependencies(SU, (ThisMayAlias ? Stores : NonAliasStores), V);
926 addChainDependencies(SU, (ThisMayAlias ? Loads : NonAliasLoads), V);
928 // Update the store map after all chains have been added to avoid adding
929 // self-loop edge if multiple underlying objects are present.
930 for (const UnderlyingObject &UnderlObj : Objs) {
931 ValueType V = UnderlObj.getValue();
932 bool ThisMayAlias = UnderlObj.mayAlias();
934 // Map this store to V.
935 (ThisMayAlias ? Stores : NonAliasStores).insert(SU, V);
937 // The store may have dependencies to unanalyzable loads and
939 addChainDependencies(SU, Loads, UnknownValue);
940 addChainDependencies(SU, Stores, UnknownValue);
942 } else { // SU is a load.
944 // An unknown load depends on all stores.
945 addChainDependencies(SU, Stores);
946 addChainDependencies(SU, NonAliasStores);
948 Loads.insert(SU, UnknownValue);
950 for (const UnderlyingObject &UnderlObj : Objs) {
951 ValueType V = UnderlObj.getValue();
952 bool ThisMayAlias = UnderlObj.mayAlias();
954 // Add precise dependencies against all previously seen stores
955 // mapping to the same Value(s).
956 addChainDependencies(SU, (ThisMayAlias ? Stores : NonAliasStores), V);
958 // Map this load to V.
959 (ThisMayAlias ? Loads : NonAliasLoads).insert(SU, V);
961 // The load may have dependencies to unanalyzable stores.
962 addChainDependencies(SU, Stores, UnknownValue);
966 // Reduce maps if they grow huge.
967 if (Stores.size() + Loads.size() >= HugeRegion) {
968 DEBUG(dbgs() << "Reducing Stores and Loads maps.\n";);
969 reduceHugeMemNodeMaps(Stores, Loads, getReductionSize());
971 if (NonAliasStores.size() + NonAliasLoads.size() >= HugeRegion) {
972 DEBUG(dbgs() << "Reducing NonAliasStores and NonAliasLoads maps.\n";);
973 reduceHugeMemNodeMaps(NonAliasStores, NonAliasLoads, getReductionSize());
978 FirstDbgValue = DbgMI;
982 CurrentVRegDefs.clear();
983 CurrentVRegUses.clear();
986 raw_ostream &llvm::operator<<(raw_ostream &OS, const PseudoSourceValue* PSV) {
987 PSV->printCustom(OS);
991 void ScheduleDAGInstrs::Value2SUsMap::dump() {
992 for (auto &Itr : *this) {
993 if (Itr.first.is<const Value*>()) {
994 const Value *V = Itr.first.get<const Value*>();
995 if (isa<UndefValue>(V))
998 V->printAsOperand(dbgs());
1000 else if (Itr.first.is<const PseudoSourceValue*>())
1001 dbgs() << Itr.first.get<const PseudoSourceValue*>();
1003 llvm_unreachable("Unknown Value type.");
1006 dumpSUList(Itr.second);
1010 void ScheduleDAGInstrs::reduceHugeMemNodeMaps(Value2SUsMap &stores,
1011 Value2SUsMap &loads, unsigned N) {
1012 DEBUG(dbgs() << "Before reduction:\nStoring SUnits:\n";
1014 dbgs() << "Loading SUnits:\n";
1017 // Insert all SU's NodeNums into a vector and sort it.
1018 std::vector<unsigned> NodeNums;
1019 NodeNums.reserve(stores.size() + loads.size());
1020 for (auto &I : stores)
1021 for (auto *SU : I.second)
1022 NodeNums.push_back(SU->NodeNum);
1023 for (auto &I : loads)
1024 for (auto *SU : I.second)
1025 NodeNums.push_back(SU->NodeNum);
1026 std::sort(NodeNums.begin(), NodeNums.end());
1028 // The N last elements in NodeNums will be removed, and the SU with
1029 // the lowest NodeNum of them will become the new BarrierChain to
1030 // let the not yet seen SUs have a dependency to the removed SUs.
1031 assert (N <= NodeNums.size());
1032 SUnit *newBarrierChain = &SUnits[*(NodeNums.end() - N)];
1034 // The aliasing and non-aliasing maps reduce independently of each
1035 // other, but share a common BarrierChain. Check if the
1036 // newBarrierChain is above the former one. If it is not, it may
1037 // introduce a loop to use newBarrierChain, so keep the old one.
1038 if (newBarrierChain->NodeNum < BarrierChain->NodeNum) {
1039 BarrierChain->addPredBarrier(newBarrierChain);
1040 BarrierChain = newBarrierChain;
1041 DEBUG(dbgs() << "Inserting new barrier chain: SU("
1042 << BarrierChain->NodeNum << ").\n";);
1045 DEBUG(dbgs() << "Keeping old barrier chain: SU("
1046 << BarrierChain->NodeNum << ").\n";);
1049 BarrierChain = newBarrierChain;
1051 insertBarrierChain(stores);
1052 insertBarrierChain(loads);
1054 DEBUG(dbgs() << "After reduction:\nStoring SUnits:\n";
1056 dbgs() << "Loading SUnits:\n";
1060 void ScheduleDAGInstrs::startBlockForKills(MachineBasicBlock *BB) {
1061 // Start with no live registers.
1064 // Examine the live-in regs of all successors.
1065 for (const MachineBasicBlock *Succ : BB->successors()) {
1066 for (const auto &LI : Succ->liveins()) {
1067 // Repeat, for reg and all subregs.
1068 for (MCSubRegIterator SubRegs(LI.PhysReg, TRI, /*IncludeSelf=*/true);
1069 SubRegs.isValid(); ++SubRegs)
1070 LiveRegs.set(*SubRegs);
1075 /// \brief If we change a kill flag on the bundle instruction implicit register
1076 /// operands, then we also need to propagate that to any instructions inside
1077 /// the bundle which had the same kill state.
1078 static void toggleBundleKillFlag(MachineInstr *MI, unsigned Reg,
1080 const TargetRegisterInfo *TRI) {
1081 if (MI->getOpcode() != TargetOpcode::BUNDLE)
1084 // Walk backwards from the last instruction in the bundle to the first.
1085 // Once we set a kill flag on an instruction, we bail out, as otherwise we
1086 // might set it on too many operands. We will clear as many flags as we
1088 MachineBasicBlock::instr_iterator Begin = MI->getIterator();
1089 MachineBasicBlock::instr_iterator End = getBundleEnd(Begin);
1090 while (Begin != End) {
1092 if ((--End)->addRegisterKilled(Reg, TRI, /* addIfNotFound= */ false))
1095 (--End)->clearRegisterKills(Reg, TRI);
1099 void ScheduleDAGInstrs::toggleKillFlag(MachineInstr &MI, MachineOperand &MO) {
1103 // Setting kill flag...
1106 toggleBundleKillFlag(&MI, MO.getReg(), true, TRI);
1110 // If MO itself is live, clear the kill flag...
1111 if (LiveRegs.test(MO.getReg())) {
1112 MO.setIsKill(false);
1113 toggleBundleKillFlag(&MI, MO.getReg(), false, TRI);
1117 // If any subreg of MO is live, then create an imp-def for that
1118 // subreg and keep MO marked as killed.
1119 MO.setIsKill(false);
1120 toggleBundleKillFlag(&MI, MO.getReg(), false, TRI);
1121 bool AllDead = true;
1122 const unsigned SuperReg = MO.getReg();
1123 MachineInstrBuilder MIB(MF, &MI);
1124 for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) {
1125 if (LiveRegs.test(*SubRegs)) {
1126 MIB.addReg(*SubRegs, RegState::ImplicitDefine);
1133 toggleBundleKillFlag(&MI, MO.getReg(), true, TRI);
1137 void ScheduleDAGInstrs::fixupKills(MachineBasicBlock *MBB) {
1138 // FIXME: Reuse the LivePhysRegs utility for this.
1139 DEBUG(dbgs() << "Fixup kills for BB#" << MBB->getNumber() << '\n');
1141 LiveRegs.resize(TRI->getNumRegs());
1142 BitVector killedRegs(TRI->getNumRegs());
1144 startBlockForKills(MBB);
1146 // Examine block from end to start...
1147 unsigned Count = MBB->size();
1148 for (MachineBasicBlock::iterator I = MBB->end(), E = MBB->begin();
1150 MachineInstr &MI = *--I;
1151 if (MI.isDebugValue())
1154 // Update liveness. Registers that are defed but not used in this
1155 // instruction are now dead. Mark register and all subregs as they
1156 // are completely defined.
1157 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1158 MachineOperand &MO = MI.getOperand(i);
1160 LiveRegs.clearBitsNotInMask(MO.getRegMask());
1161 if (!MO.isReg()) continue;
1162 unsigned Reg = MO.getReg();
1163 if (Reg == 0) continue;
1164 if (!MO.isDef()) continue;
1165 // Ignore two-addr defs.
1166 if (MI.isRegTiedToUseOperand(i)) continue;
1168 // Repeat for reg and all subregs.
1169 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1170 SubRegs.isValid(); ++SubRegs)
1171 LiveRegs.reset(*SubRegs);
1174 // Examine all used registers and set/clear kill flag. When a
1175 // register is used multiple times we only set the kill flag on
1176 // the first use. Don't set kill flags on undef operands.
1179 // toggleKillFlag can append new operands (implicit defs), so using
1180 // a range-based loop is not safe. The new operands will be appended
1181 // at the end of the operand list and they don't need to be visited,
1182 // so iterating until the currently last operand is ok.
1183 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1184 MachineOperand &MO = MI.getOperand(i);
1185 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
1186 unsigned Reg = MO.getReg();
1187 if ((Reg == 0) || MRI.isReserved(Reg)) continue;
1190 if (!killedRegs.test(Reg)) {
1192 // A register is not killed if any subregs are live...
1193 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
1194 if (LiveRegs.test(*SubRegs)) {
1200 // If subreg is not live, then register is killed if it became
1201 // live in this instruction
1203 kill = !LiveRegs.test(Reg);
1206 if (MO.isKill() != kill) {
1207 DEBUG(dbgs() << "Fixing " << MO << " in ");
1208 toggleKillFlag(MI, MO);
1211 if (MI.getOpcode() == TargetOpcode::BUNDLE) {
1212 MachineBasicBlock::instr_iterator Begin = MI.getIterator();
1213 MachineBasicBlock::instr_iterator End = getBundleEnd(Begin);
1214 while (++Begin != End)
1215 DEBUG(Begin->dump());
1220 killedRegs.set(Reg);
1223 // Mark any used register (that is not using undef) and subregs as
1225 for (const MachineOperand &MO : MI.operands()) {
1226 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
1227 unsigned Reg = MO.getReg();
1228 if ((Reg == 0) || MRI.isReserved(Reg)) continue;
1230 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1231 SubRegs.isValid(); ++SubRegs)
1232 LiveRegs.set(*SubRegs);
1237 void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
1238 // Cannot completely remove virtual function even in release mode.
1239 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1240 SU->getInstr()->dump();
1244 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
1246 raw_string_ostream oss(s);
1249 else if (SU == &ExitSU)
1252 SU->getInstr()->print(oss, /*SkipOpers=*/true);
1256 /// Return the basic block label. It is not necessarilly unique because a block
1257 /// contains multiple scheduling regions. But it is fine for visualization.
1258 std::string ScheduleDAGInstrs::getDAGName() const {
1259 return "dag." + BB->getFullName();
1262 //===----------------------------------------------------------------------===//
1263 // SchedDFSResult Implementation
1264 //===----------------------------------------------------------------------===//
1267 /// Internal state used to compute SchedDFSResult.
1268 class SchedDFSImpl {
1271 /// Join DAG nodes into equivalence classes by their subtree.
1272 IntEqClasses SubtreeClasses;
1273 /// List PredSU, SuccSU pairs that represent data edges between subtrees.
1274 std::vector<std::pair<const SUnit*, const SUnit*> > ConnectionPairs;
1278 unsigned ParentNodeID; ///< Parent node (member of the parent subtree).
1279 unsigned SubInstrCount; ///< Instr count in this tree only, not children.
1281 RootData(unsigned id): NodeID(id),
1282 ParentNodeID(SchedDFSResult::InvalidSubtreeID),
1285 unsigned getSparseSetIndex() const { return NodeID; }
1288 SparseSet<RootData> RootSet;
1291 SchedDFSImpl(SchedDFSResult &r): R(r), SubtreeClasses(R.DFSNodeData.size()) {
1292 RootSet.setUniverse(R.DFSNodeData.size());
1295 /// Returns true if this node been visited by the DFS traversal.
1297 /// During visitPostorderNode the Node's SubtreeID is assigned to the Node
1298 /// ID. Later, SubtreeID is updated but remains valid.
1299 bool isVisited(const SUnit *SU) const {
1300 return R.DFSNodeData[SU->NodeNum].SubtreeID
1301 != SchedDFSResult::InvalidSubtreeID;
1304 /// Initializes this node's instruction count. We don't need to flag the node
1305 /// visited until visitPostorder because the DAG cannot have cycles.
1306 void visitPreorder(const SUnit *SU) {
1307 R.DFSNodeData[SU->NodeNum].InstrCount =
1308 SU->getInstr()->isTransient() ? 0 : 1;
1311 /// Called once for each node after all predecessors are visited. Revisit this
1312 /// node's predecessors and potentially join them now that we know the ILP of
1313 /// the other predecessors.
1314 void visitPostorderNode(const SUnit *SU) {
1315 // Mark this node as the root of a subtree. It may be joined with its
1316 // successors later.
1317 R.DFSNodeData[SU->NodeNum].SubtreeID = SU->NodeNum;
1318 RootData RData(SU->NodeNum);
1319 RData.SubInstrCount = SU->getInstr()->isTransient() ? 0 : 1;
1321 // If any predecessors are still in their own subtree, they either cannot be
1322 // joined or are large enough to remain separate. If this parent node's
1323 // total instruction count is not greater than a child subtree by at least
1324 // the subtree limit, then try to join it now since splitting subtrees is
1325 // only useful if multiple high-pressure paths are possible.
1326 unsigned InstrCount = R.DFSNodeData[SU->NodeNum].InstrCount;
1327 for (const SDep &PredDep : SU->Preds) {
1328 if (PredDep.getKind() != SDep::Data)
1330 unsigned PredNum = PredDep.getSUnit()->NodeNum;
1331 if ((InstrCount - R.DFSNodeData[PredNum].InstrCount) < R.SubtreeLimit)
1332 joinPredSubtree(PredDep, SU, /*CheckLimit=*/false);
1334 // Either link or merge the TreeData entry from the child to the parent.
1335 if (R.DFSNodeData[PredNum].SubtreeID == PredNum) {
1336 // If the predecessor's parent is invalid, this is a tree edge and the
1337 // current node is the parent.
1338 if (RootSet[PredNum].ParentNodeID == SchedDFSResult::InvalidSubtreeID)
1339 RootSet[PredNum].ParentNodeID = SU->NodeNum;
1341 else if (RootSet.count(PredNum)) {
1342 // The predecessor is not a root, but is still in the root set. This
1343 // must be the new parent that it was just joined to. Note that
1344 // RootSet[PredNum].ParentNodeID may either be invalid or may still be
1345 // set to the original parent.
1346 RData.SubInstrCount += RootSet[PredNum].SubInstrCount;
1347 RootSet.erase(PredNum);
1350 RootSet[SU->NodeNum] = RData;
1353 /// \brief Called once for each tree edge after calling visitPostOrderNode on
1354 /// the predecessor. Increment the parent node's instruction count and
1355 /// preemptively join this subtree to its parent's if it is small enough.
1356 void visitPostorderEdge(const SDep &PredDep, const SUnit *Succ) {
1357 R.DFSNodeData[Succ->NodeNum].InstrCount
1358 += R.DFSNodeData[PredDep.getSUnit()->NodeNum].InstrCount;
1359 joinPredSubtree(PredDep, Succ);
1362 /// Adds a connection for cross edges.
1363 void visitCrossEdge(const SDep &PredDep, const SUnit *Succ) {
1364 ConnectionPairs.push_back(std::make_pair(PredDep.getSUnit(), Succ));
1367 /// Sets each node's subtree ID to the representative ID and record
1368 /// connections between trees.
1370 SubtreeClasses.compress();
1371 R.DFSTreeData.resize(SubtreeClasses.getNumClasses());
1372 assert(SubtreeClasses.getNumClasses() == RootSet.size()
1373 && "number of roots should match trees");
1374 for (const RootData &Root : RootSet) {
1375 unsigned TreeID = SubtreeClasses[Root.NodeID];
1376 if (Root.ParentNodeID != SchedDFSResult::InvalidSubtreeID)
1377 R.DFSTreeData[TreeID].ParentTreeID = SubtreeClasses[Root.ParentNodeID];
1378 R.DFSTreeData[TreeID].SubInstrCount = Root.SubInstrCount;
1379 // Note that SubInstrCount may be greater than InstrCount if we joined
1380 // subtrees across a cross edge. InstrCount will be attributed to the
1381 // original parent, while SubInstrCount will be attributed to the joined
1384 R.SubtreeConnections.resize(SubtreeClasses.getNumClasses());
1385 R.SubtreeConnectLevels.resize(SubtreeClasses.getNumClasses());
1386 DEBUG(dbgs() << R.getNumSubtrees() << " subtrees:\n");
1387 for (unsigned Idx = 0, End = R.DFSNodeData.size(); Idx != End; ++Idx) {
1388 R.DFSNodeData[Idx].SubtreeID = SubtreeClasses[Idx];
1389 DEBUG(dbgs() << " SU(" << Idx << ") in tree "
1390 << R.DFSNodeData[Idx].SubtreeID << '\n');
1392 for (const std::pair<const SUnit*, const SUnit*> &P : ConnectionPairs) {
1393 unsigned PredTree = SubtreeClasses[P.first->NodeNum];
1394 unsigned SuccTree = SubtreeClasses[P.second->NodeNum];
1395 if (PredTree == SuccTree)
1397 unsigned Depth = P.first->getDepth();
1398 addConnection(PredTree, SuccTree, Depth);
1399 addConnection(SuccTree, PredTree, Depth);
1404 /// Joins the predecessor subtree with the successor that is its DFS parent.
1405 /// Applies some heuristics before joining.
1406 bool joinPredSubtree(const SDep &PredDep, const SUnit *Succ,
1407 bool CheckLimit = true) {
1408 assert(PredDep.getKind() == SDep::Data && "Subtrees are for data edges");
1410 // Check if the predecessor is already joined.
1411 const SUnit *PredSU = PredDep.getSUnit();
1412 unsigned PredNum = PredSU->NodeNum;
1413 if (R.DFSNodeData[PredNum].SubtreeID != PredNum)
1416 // Four is the magic number of successors before a node is considered a
1418 unsigned NumDataSucs = 0;
1419 for (const SDep &SuccDep : PredSU->Succs) {
1420 if (SuccDep.getKind() == SDep::Data) {
1421 if (++NumDataSucs >= 4)
1425 if (CheckLimit && R.DFSNodeData[PredNum].InstrCount > R.SubtreeLimit)
1427 R.DFSNodeData[PredNum].SubtreeID = Succ->NodeNum;
1428 SubtreeClasses.join(Succ->NodeNum, PredNum);
1432 /// Called by finalize() to record a connection between trees.
1433 void addConnection(unsigned FromTree, unsigned ToTree, unsigned Depth) {
1438 SmallVectorImpl<SchedDFSResult::Connection> &Connections =
1439 R.SubtreeConnections[FromTree];
1440 for (SchedDFSResult::Connection &C : Connections) {
1441 if (C.TreeID == ToTree) {
1442 C.Level = std::max(C.Level, Depth);
1446 Connections.push_back(SchedDFSResult::Connection(ToTree, Depth));
1447 FromTree = R.DFSTreeData[FromTree].ParentTreeID;
1448 } while (FromTree != SchedDFSResult::InvalidSubtreeID);
1451 } // end namespace llvm
1454 /// Manage the stack used by a reverse depth-first search over the DAG.
1455 class SchedDAGReverseDFS {
1456 std::vector<std::pair<const SUnit*, SUnit::const_pred_iterator> > DFSStack;
1458 bool isComplete() const { return DFSStack.empty(); }
1460 void follow(const SUnit *SU) {
1461 DFSStack.push_back(std::make_pair(SU, SU->Preds.begin()));
1463 void advance() { ++DFSStack.back().second; }
1465 const SDep *backtrack() {
1466 DFSStack.pop_back();
1467 return DFSStack.empty() ? nullptr : std::prev(DFSStack.back().second);
1470 const SUnit *getCurr() const { return DFSStack.back().first; }
1472 SUnit::const_pred_iterator getPred() const { return DFSStack.back().second; }
1474 SUnit::const_pred_iterator getPredEnd() const {
1475 return getCurr()->Preds.end();
1480 static bool hasDataSucc(const SUnit *SU) {
1481 for (const SDep &SuccDep : SU->Succs) {
1482 if (SuccDep.getKind() == SDep::Data &&
1483 !SuccDep.getSUnit()->isBoundaryNode())
1489 /// Computes an ILP metric for all nodes in the subDAG reachable via depth-first
1490 /// search from this root.
1491 void SchedDFSResult::compute(ArrayRef<SUnit> SUnits) {
1493 llvm_unreachable("Top-down ILP metric is unimplemnted");
1495 SchedDFSImpl Impl(*this);
1496 for (const SUnit &SU : SUnits) {
1497 if (Impl.isVisited(&SU) || hasDataSucc(&SU))
1500 SchedDAGReverseDFS DFS;
1501 Impl.visitPreorder(&SU);
1504 // Traverse the leftmost path as far as possible.
1505 while (DFS.getPred() != DFS.getPredEnd()) {
1506 const SDep &PredDep = *DFS.getPred();
1508 // Ignore non-data edges.
1509 if (PredDep.getKind() != SDep::Data
1510 || PredDep.getSUnit()->isBoundaryNode()) {
1513 // An already visited edge is a cross edge, assuming an acyclic DAG.
1514 if (Impl.isVisited(PredDep.getSUnit())) {
1515 Impl.visitCrossEdge(PredDep, DFS.getCurr());
1518 Impl.visitPreorder(PredDep.getSUnit());
1519 DFS.follow(PredDep.getSUnit());
1521 // Visit the top of the stack in postorder and backtrack.
1522 const SUnit *Child = DFS.getCurr();
1523 const SDep *PredDep = DFS.backtrack();
1524 Impl.visitPostorderNode(Child);
1526 Impl.visitPostorderEdge(*PredDep, DFS.getCurr());
1527 if (DFS.isComplete())
1534 /// The root of the given SubtreeID was just scheduled. For all subtrees
1535 /// connected to this tree, record the depth of the connection so that the
1536 /// nearest connected subtrees can be prioritized.
1537 void SchedDFSResult::scheduleTree(unsigned SubtreeID) {
1538 for (const Connection &C : SubtreeConnections[SubtreeID]) {
1539 SubtreeConnectLevels[C.TreeID] =
1540 std::max(SubtreeConnectLevels[C.TreeID], C.Level);
1541 DEBUG(dbgs() << " Tree: " << C.TreeID
1542 << " @" << SubtreeConnectLevels[C.TreeID] << '\n');
1546 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1547 LLVM_DUMP_METHOD void ILPValue::print(raw_ostream &OS) const {
1548 OS << InstrCount << " / " << Length << " = ";
1552 OS << format("%g", ((double)InstrCount / Length));
1555 LLVM_DUMP_METHOD void ILPValue::dump() const {
1556 dbgs() << *this << '\n';
1562 raw_ostream &operator<<(raw_ostream &OS, const ILPValue &Val) {
1567 } // end namespace llvm