1 //===-- FastISel.cpp - Implementation of the FastISel class ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/ADT/Optional.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/Analysis/BranchProbabilityInfo.h"
45 #include "llvm/Analysis/Loads.h"
46 #include "llvm/Analysis/TargetLibraryInfo.h"
47 #include "llvm/CodeGen/Analysis.h"
48 #include "llvm/CodeGen/FastISel.h"
49 #include "llvm/CodeGen/FunctionLoweringInfo.h"
50 #include "llvm/CodeGen/MachineFrameInfo.h"
51 #include "llvm/CodeGen/MachineInstrBuilder.h"
52 #include "llvm/CodeGen/MachineModuleInfo.h"
53 #include "llvm/CodeGen/MachineRegisterInfo.h"
54 #include "llvm/CodeGen/StackMaps.h"
55 #include "llvm/IR/DataLayout.h"
56 #include "llvm/IR/DebugInfo.h"
57 #include "llvm/IR/Function.h"
58 #include "llvm/IR/GetElementPtrTypeIterator.h"
59 #include "llvm/IR/GlobalVariable.h"
60 #include "llvm/IR/Instructions.h"
61 #include "llvm/IR/IntrinsicInst.h"
62 #include "llvm/IR/Mangler.h"
63 #include "llvm/IR/Operator.h"
64 #include "llvm/Support/Debug.h"
65 #include "llvm/Support/ErrorHandling.h"
66 #include "llvm/Support/raw_ostream.h"
67 #include "llvm/Target/TargetInstrInfo.h"
68 #include "llvm/Target/TargetLowering.h"
69 #include "llvm/Target/TargetMachine.h"
70 #include "llvm/Target/TargetSubtargetInfo.h"
73 #define DEBUG_TYPE "isel"
75 STATISTIC(NumFastIselSuccessIndependent, "Number of insts selected by "
76 "target-independent selector");
77 STATISTIC(NumFastIselSuccessTarget, "Number of insts selected by "
78 "target-specific selector");
79 STATISTIC(NumFastIselDead, "Number of dead insts removed on failure");
81 void FastISel::ArgListEntry::setAttributes(ImmutableCallSite *CS,
83 IsSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt);
84 IsZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt);
85 IsInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg);
86 IsSRet = CS->paramHasAttr(AttrIdx, Attribute::StructRet);
87 IsNest = CS->paramHasAttr(AttrIdx, Attribute::Nest);
88 IsByVal = CS->paramHasAttr(AttrIdx, Attribute::ByVal);
89 IsInAlloca = CS->paramHasAttr(AttrIdx, Attribute::InAlloca);
90 IsReturned = CS->paramHasAttr(AttrIdx, Attribute::Returned);
91 IsSwiftSelf = CS->paramHasAttr(AttrIdx, Attribute::SwiftSelf);
92 IsSwiftError = CS->paramHasAttr(AttrIdx, Attribute::SwiftError);
93 Alignment = CS->getParamAlignment(AttrIdx);
96 /// Set the current block to which generated machine instructions will be
97 /// appended, and clear the local CSE map.
98 void FastISel::startNewBlock() {
99 LocalValueMap.clear();
101 // Instructions are appended to FuncInfo.MBB. If the basic block already
102 // contains labels or copies, use the last instruction as the last local
104 EmitStartPt = nullptr;
105 if (!FuncInfo.MBB->empty())
106 EmitStartPt = &FuncInfo.MBB->back();
107 LastLocalValue = EmitStartPt;
110 bool FastISel::lowerArguments() {
111 if (!FuncInfo.CanLowerReturn)
112 // Fallback to SDISel argument lowering code to deal with sret pointer
116 if (!fastLowerArguments())
119 // Enter arguments into ValueMap for uses in non-entry BBs.
120 for (Function::const_arg_iterator I = FuncInfo.Fn->arg_begin(),
121 E = FuncInfo.Fn->arg_end();
123 DenseMap<const Value *, unsigned>::iterator VI = LocalValueMap.find(&*I);
124 assert(VI != LocalValueMap.end() && "Missed an argument?");
125 FuncInfo.ValueMap[&*I] = VI->second;
130 void FastISel::flushLocalValueMap() {
131 LocalValueMap.clear();
132 LastLocalValue = EmitStartPt;
134 SavedInsertPt = FuncInfo.InsertPt;
137 bool FastISel::hasTrivialKill(const Value *V) {
138 // Don't consider constants or arguments to have trivial kills.
139 const Instruction *I = dyn_cast<Instruction>(V);
143 // No-op casts are trivially coalesced by fast-isel.
144 if (const auto *Cast = dyn_cast<CastInst>(I))
145 if (Cast->isNoopCast(DL.getIntPtrType(Cast->getContext())) &&
146 !hasTrivialKill(Cast->getOperand(0)))
149 // Even the value might have only one use in the LLVM IR, it is possible that
150 // FastISel might fold the use into another instruction and now there is more
151 // than one use at the Machine Instruction level.
152 unsigned Reg = lookUpRegForValue(V);
153 if (Reg && !MRI.use_empty(Reg))
156 // GEPs with all zero indices are trivially coalesced by fast-isel.
157 if (const auto *GEP = dyn_cast<GetElementPtrInst>(I))
158 if (GEP->hasAllZeroIndices() && !hasTrivialKill(GEP->getOperand(0)))
161 // Only instructions with a single use in the same basic block are considered
162 // to have trivial kills.
163 return I->hasOneUse() &&
164 !(I->getOpcode() == Instruction::BitCast ||
165 I->getOpcode() == Instruction::PtrToInt ||
166 I->getOpcode() == Instruction::IntToPtr) &&
167 cast<Instruction>(*I->user_begin())->getParent() == I->getParent();
170 unsigned FastISel::getRegForValue(const Value *V) {
171 EVT RealVT = TLI.getValueType(DL, V->getType(), /*AllowUnknown=*/true);
172 // Don't handle non-simple values in FastISel.
173 if (!RealVT.isSimple())
176 // Ignore illegal types. We must do this before looking up the value
177 // in ValueMap because Arguments are given virtual registers regardless
178 // of whether FastISel can handle them.
179 MVT VT = RealVT.getSimpleVT();
180 if (!TLI.isTypeLegal(VT)) {
181 // Handle integer promotions, though, because they're common and easy.
182 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
183 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
188 // Look up the value to see if we already have a register for it.
189 unsigned Reg = lookUpRegForValue(V);
193 // In bottom-up mode, just create the virtual register which will be used
194 // to hold the value. It will be materialized later.
195 if (isa<Instruction>(V) &&
196 (!isa<AllocaInst>(V) ||
197 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V))))
198 return FuncInfo.InitializeRegForValue(V);
200 SavePoint SaveInsertPt = enterLocalValueArea();
202 // Materialize the value in a register. Emit any instructions in the
204 Reg = materializeRegForValue(V, VT);
206 leaveLocalValueArea(SaveInsertPt);
211 unsigned FastISel::materializeConstant(const Value *V, MVT VT) {
213 if (const auto *CI = dyn_cast<ConstantInt>(V)) {
214 if (CI->getValue().getActiveBits() <= 64)
215 Reg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
216 } else if (isa<AllocaInst>(V))
217 Reg = fastMaterializeAlloca(cast<AllocaInst>(V));
218 else if (isa<ConstantPointerNull>(V))
219 // Translate this as an integer zero so that it can be
220 // local-CSE'd with actual integer zeros.
221 Reg = getRegForValue(
222 Constant::getNullValue(DL.getIntPtrType(V->getContext())));
223 else if (const auto *CF = dyn_cast<ConstantFP>(V)) {
224 if (CF->isNullValue())
225 Reg = fastMaterializeFloatZero(CF);
227 // Try to emit the constant directly.
228 Reg = fastEmit_f(VT, VT, ISD::ConstantFP, CF);
231 // Try to emit the constant by using an integer constant with a cast.
232 const APFloat &Flt = CF->getValueAPF();
233 EVT IntVT = TLI.getPointerTy(DL);
236 uint32_t IntBitWidth = IntVT.getSizeInBits();
238 (void)Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
239 APFloat::rmTowardZero, &isExact);
241 APInt IntVal(IntBitWidth, x);
243 unsigned IntegerReg =
244 getRegForValue(ConstantInt::get(V->getContext(), IntVal));
246 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg,
250 } else if (const auto *Op = dyn_cast<Operator>(V)) {
251 if (!selectOperator(Op, Op->getOpcode()))
252 if (!isa<Instruction>(Op) ||
253 !fastSelectInstruction(cast<Instruction>(Op)))
255 Reg = lookUpRegForValue(Op);
256 } else if (isa<UndefValue>(V)) {
257 Reg = createResultReg(TLI.getRegClassFor(VT));
258 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
259 TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
264 /// Helper for getRegForValue. This function is called when the value isn't
265 /// already available in a register and must be materialized with new
267 unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) {
269 // Give the target-specific code a try first.
270 if (isa<Constant>(V))
271 Reg = fastMaterializeConstant(cast<Constant>(V));
273 // If target-specific code couldn't or didn't want to handle the value, then
274 // give target-independent code a try.
276 Reg = materializeConstant(V, VT);
278 // Don't cache constant materializations in the general ValueMap.
279 // To do so would require tracking what uses they dominate.
281 LocalValueMap[V] = Reg;
282 LastLocalValue = MRI.getVRegDef(Reg);
287 unsigned FastISel::lookUpRegForValue(const Value *V) {
288 // Look up the value to see if we already have a register for it. We
289 // cache values defined by Instructions across blocks, and other values
290 // only locally. This is because Instructions already have the SSA
291 // def-dominates-use requirement enforced.
292 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V);
293 if (I != FuncInfo.ValueMap.end())
295 return LocalValueMap[V];
298 void FastISel::updateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) {
299 if (!isa<Instruction>(I)) {
300 LocalValueMap[I] = Reg;
304 unsigned &AssignedReg = FuncInfo.ValueMap[I];
305 if (AssignedReg == 0)
306 // Use the new register.
308 else if (Reg != AssignedReg) {
309 // Arrange for uses of AssignedReg to be replaced by uses of Reg.
310 for (unsigned i = 0; i < NumRegs; i++)
311 FuncInfo.RegFixups[AssignedReg + i] = Reg + i;
317 std::pair<unsigned, bool> FastISel::getRegForGEPIndex(const Value *Idx) {
318 unsigned IdxN = getRegForValue(Idx);
320 // Unhandled operand. Halt "fast" selection and bail.
321 return std::pair<unsigned, bool>(0, false);
323 bool IdxNIsKill = hasTrivialKill(Idx);
325 // If the index is smaller or larger than intptr_t, truncate or extend it.
326 MVT PtrVT = TLI.getPointerTy(DL);
327 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
328 if (IdxVT.bitsLT(PtrVT)) {
329 IdxN = fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN,
332 } else if (IdxVT.bitsGT(PtrVT)) {
334 fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN, IdxNIsKill);
337 return std::pair<unsigned, bool>(IdxN, IdxNIsKill);
340 void FastISel::recomputeInsertPt() {
341 if (getLastLocalValue()) {
342 FuncInfo.InsertPt = getLastLocalValue();
343 FuncInfo.MBB = FuncInfo.InsertPt->getParent();
346 FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI();
348 // Now skip past any EH_LABELs, which must remain at the beginning.
349 while (FuncInfo.InsertPt != FuncInfo.MBB->end() &&
350 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL)
354 void FastISel::removeDeadCode(MachineBasicBlock::iterator I,
355 MachineBasicBlock::iterator E) {
356 assert(I.isValid() && E.isValid() && std::distance(I, E) > 0 &&
357 "Invalid iterator!");
359 MachineInstr *Dead = &*I;
361 Dead->eraseFromParent();
367 FastISel::SavePoint FastISel::enterLocalValueArea() {
368 MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt;
369 DebugLoc OldDL = DbgLoc;
372 SavePoint SP = {OldInsertPt, OldDL};
376 void FastISel::leaveLocalValueArea(SavePoint OldInsertPt) {
377 if (FuncInfo.InsertPt != FuncInfo.MBB->begin())
378 LastLocalValue = &*std::prev(FuncInfo.InsertPt);
380 // Restore the previous insert position.
381 FuncInfo.InsertPt = OldInsertPt.InsertPt;
382 DbgLoc = OldInsertPt.DL;
385 bool FastISel::selectBinaryOp(const User *I, unsigned ISDOpcode) {
386 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
387 if (VT == MVT::Other || !VT.isSimple())
388 // Unhandled type. Halt "fast" selection and bail.
391 // We only handle legal types. For example, on x86-32 the instruction
392 // selector contains all of the 64-bit instructions from x86-64,
393 // under the assumption that i64 won't be used if the target doesn't
395 if (!TLI.isTypeLegal(VT)) {
396 // MVT::i1 is special. Allow AND, OR, or XOR because they
397 // don't require additional zeroing, which makes them easy.
398 if (VT == MVT::i1 && (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
399 ISDOpcode == ISD::XOR))
400 VT = TLI.getTypeToTransformTo(I->getContext(), VT);
405 // Check if the first operand is a constant, and handle it as "ri". At -O0,
406 // we don't have anything that canonicalizes operand order.
407 if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(0)))
408 if (isa<Instruction>(I) && cast<Instruction>(I)->isCommutative()) {
409 unsigned Op1 = getRegForValue(I->getOperand(1));
412 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
415 fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, Op1IsKill,
416 CI->getZExtValue(), VT.getSimpleVT());
420 // We successfully emitted code for the given LLVM Instruction.
421 updateValueMap(I, ResultReg);
425 unsigned Op0 = getRegForValue(I->getOperand(0));
426 if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
428 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
430 // Check if the second operand is a constant and handle it appropriately.
431 if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
432 uint64_t Imm = CI->getSExtValue();
434 // Transform "sdiv exact X, 8" -> "sra X, 3".
435 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
436 cast<BinaryOperator>(I)->isExact() && isPowerOf2_64(Imm)) {
438 ISDOpcode = ISD::SRA;
441 // Transform "urem x, pow2" -> "and x, pow2-1".
442 if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) &&
443 isPowerOf2_64(Imm)) {
445 ISDOpcode = ISD::AND;
448 unsigned ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
449 Op0IsKill, Imm, VT.getSimpleVT());
453 // We successfully emitted code for the given LLVM Instruction.
454 updateValueMap(I, ResultReg);
458 unsigned Op1 = getRegForValue(I->getOperand(1));
459 if (!Op1) // Unhandled operand. Halt "fast" selection and bail.
461 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
463 // Now we have both operands in registers. Emit the instruction.
464 unsigned ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
465 ISDOpcode, Op0, Op0IsKill, Op1, Op1IsKill);
467 // Target-specific code wasn't able to find a machine opcode for
468 // the given ISD opcode and type. Halt "fast" selection and bail.
471 // We successfully emitted code for the given LLVM Instruction.
472 updateValueMap(I, ResultReg);
476 bool FastISel::selectGetElementPtr(const User *I) {
477 unsigned N = getRegForValue(I->getOperand(0));
478 if (!N) // Unhandled operand. Halt "fast" selection and bail.
480 bool NIsKill = hasTrivialKill(I->getOperand(0));
482 // Keep a running tab of the total offset to coalesce multiple N = N + Offset
483 // into a single N = N + TotalOffset.
484 uint64_t TotalOffs = 0;
485 // FIXME: What's a good SWAG number for MaxOffs?
486 uint64_t MaxOffs = 2048;
487 MVT VT = TLI.getPointerTy(DL);
488 for (gep_type_iterator GTI = gep_type_begin(I), E = gep_type_end(I);
490 const Value *Idx = GTI.getOperand();
491 if (StructType *StTy = GTI.getStructTypeOrNull()) {
492 uint64_t Field = cast<ConstantInt>(Idx)->getZExtValue();
495 TotalOffs += DL.getStructLayout(StTy)->getElementOffset(Field);
496 if (TotalOffs >= MaxOffs) {
497 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
498 if (!N) // Unhandled operand. Halt "fast" selection and bail.
505 Type *Ty = GTI.getIndexedType();
507 // If this is a constant subscript, handle it quickly.
508 if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
512 uint64_t IdxN = CI->getValue().sextOrTrunc(64).getSExtValue();
513 TotalOffs += DL.getTypeAllocSize(Ty) * IdxN;
514 if (TotalOffs >= MaxOffs) {
515 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
516 if (!N) // Unhandled operand. Halt "fast" selection and bail.
524 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
525 if (!N) // Unhandled operand. Halt "fast" selection and bail.
531 // N = N + Idx * ElementSize;
532 uint64_t ElementSize = DL.getTypeAllocSize(Ty);
533 std::pair<unsigned, bool> Pair = getRegForGEPIndex(Idx);
534 unsigned IdxN = Pair.first;
535 bool IdxNIsKill = Pair.second;
536 if (!IdxN) // Unhandled operand. Halt "fast" selection and bail.
539 if (ElementSize != 1) {
540 IdxN = fastEmit_ri_(VT, ISD::MUL, IdxN, IdxNIsKill, ElementSize, VT);
541 if (!IdxN) // Unhandled operand. Halt "fast" selection and bail.
545 N = fastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill);
546 if (!N) // Unhandled operand. Halt "fast" selection and bail.
551 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
552 if (!N) // Unhandled operand. Halt "fast" selection and bail.
556 // We successfully emitted code for the given LLVM Instruction.
557 updateValueMap(I, N);
561 bool FastISel::addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
562 const CallInst *CI, unsigned StartIdx) {
563 for (unsigned i = StartIdx, e = CI->getNumArgOperands(); i != e; ++i) {
564 Value *Val = CI->getArgOperand(i);
565 // Check for constants and encode them with a StackMaps::ConstantOp prefix.
566 if (const auto *C = dyn_cast<ConstantInt>(Val)) {
567 Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
568 Ops.push_back(MachineOperand::CreateImm(C->getSExtValue()));
569 } else if (isa<ConstantPointerNull>(Val)) {
570 Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
571 Ops.push_back(MachineOperand::CreateImm(0));
572 } else if (auto *AI = dyn_cast<AllocaInst>(Val)) {
573 // Values coming from a stack location also require a special encoding,
574 // but that is added later on by the target specific frame index
575 // elimination implementation.
576 auto SI = FuncInfo.StaticAllocaMap.find(AI);
577 if (SI != FuncInfo.StaticAllocaMap.end())
578 Ops.push_back(MachineOperand::CreateFI(SI->second));
582 unsigned Reg = getRegForValue(Val);
585 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
591 bool FastISel::selectStackmap(const CallInst *I) {
592 // void @llvm.experimental.stackmap(i64 <id>, i32 <numShadowBytes>,
593 // [live variables...])
594 assert(I->getCalledFunction()->getReturnType()->isVoidTy() &&
595 "Stackmap cannot return a value.");
597 // The stackmap intrinsic only records the live variables (the arguments
598 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
599 // intrinsic, this won't be lowered to a function call. This means we don't
600 // have to worry about calling conventions and target-specific lowering code.
601 // Instead we perform the call lowering right here.
603 // CALLSEQ_START(0...)
604 // STACKMAP(id, nbytes, ...)
607 SmallVector<MachineOperand, 32> Ops;
609 // Add the <id> and <numBytes> constants.
610 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
611 "Expected a constant integer.");
612 const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
613 Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
615 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos)) &&
616 "Expected a constant integer.");
617 const auto *NumBytes =
618 cast<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos));
619 Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
621 // Push live variables for the stack map (skipping the first two arguments
622 // <id> and <numBytes>).
623 if (!addStackMapLiveVars(Ops, I, 2))
626 // We are not adding any register mask info here, because the stackmap doesn't
629 // Add scratch registers as implicit def and early clobber.
630 CallingConv::ID CC = I->getCallingConv();
631 const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
632 for (unsigned i = 0; ScratchRegs[i]; ++i)
633 Ops.push_back(MachineOperand::CreateReg(
634 ScratchRegs[i], /*IsDef=*/true, /*IsImp=*/true, /*IsKill=*/false,
635 /*IsDead=*/false, /*IsUndef=*/false, /*IsEarlyClobber=*/true));
637 // Issue CALLSEQ_START
638 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
640 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown));
641 const MCInstrDesc &MCID = Builder.getInstr()->getDesc();
642 for (unsigned I = 0, E = MCID.getNumOperands(); I < E; ++I)
646 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
647 TII.get(TargetOpcode::STACKMAP));
648 for (auto const &MO : Ops)
652 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
653 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
657 // Inform the Frame Information that we have a stackmap in this function.
658 FuncInfo.MF->getFrameInfo().setHasStackMap();
663 /// \brief Lower an argument list according to the target calling convention.
665 /// This is a helper for lowering intrinsics that follow a target calling
666 /// convention or require stack pointer adjustment. Only a subset of the
667 /// intrinsic's operands need to participate in the calling convention.
668 bool FastISel::lowerCallOperands(const CallInst *CI, unsigned ArgIdx,
669 unsigned NumArgs, const Value *Callee,
670 bool ForceRetVoidTy, CallLoweringInfo &CLI) {
672 Args.reserve(NumArgs);
674 // Populate the argument list.
675 // Attributes for args start at offset 1, after the return attribute.
676 ImmutableCallSite CS(CI);
677 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
678 ArgI != ArgE; ++ArgI) {
679 Value *V = CI->getOperand(ArgI);
681 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
685 Entry.Ty = V->getType();
686 Entry.setAttributes(&CS, AttrI);
687 Args.push_back(Entry);
690 Type *RetTy = ForceRetVoidTy ? Type::getVoidTy(CI->getType()->getContext())
692 CLI.setCallee(CI->getCallingConv(), RetTy, Callee, std::move(Args), NumArgs);
694 return lowerCallTo(CLI);
697 FastISel::CallLoweringInfo &FastISel::CallLoweringInfo::setCallee(
698 const DataLayout &DL, MCContext &Ctx, CallingConv::ID CC, Type *ResultTy,
699 StringRef Target, ArgListTy &&ArgsList, unsigned FixedArgs) {
700 SmallString<32> MangledName;
701 Mangler::getNameWithPrefix(MangledName, Target, DL);
702 MCSymbol *Sym = Ctx.getOrCreateSymbol(MangledName);
703 return setCallee(CC, ResultTy, Sym, std::move(ArgsList), FixedArgs);
706 bool FastISel::selectPatchpoint(const CallInst *I) {
707 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
712 // [live variables...])
713 CallingConv::ID CC = I->getCallingConv();
714 bool IsAnyRegCC = CC == CallingConv::AnyReg;
715 bool HasDef = !I->getType()->isVoidTy();
716 Value *Callee = I->getOperand(PatchPointOpers::TargetPos)->stripPointerCasts();
718 // Get the real number of arguments participating in the call <numArgs>
719 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NArgPos)) &&
720 "Expected a constant integer.");
721 const auto *NumArgsVal =
722 cast<ConstantInt>(I->getOperand(PatchPointOpers::NArgPos));
723 unsigned NumArgs = NumArgsVal->getZExtValue();
725 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
726 // This includes all meta-operands up to but not including CC.
727 unsigned NumMetaOpers = PatchPointOpers::CCPos;
728 assert(I->getNumArgOperands() >= NumMetaOpers + NumArgs &&
729 "Not enough arguments provided to the patchpoint intrinsic");
731 // For AnyRegCC the arguments are lowered later on manually.
732 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
733 CallLoweringInfo CLI;
734 CLI.setIsPatchPoint();
735 if (!lowerCallOperands(I, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC, CLI))
738 assert(CLI.Call && "No call instruction specified.");
740 SmallVector<MachineOperand, 32> Ops;
742 // Add an explicit result reg if we use the anyreg calling convention.
743 if (IsAnyRegCC && HasDef) {
744 assert(CLI.NumResultRegs == 0 && "Unexpected result register.");
745 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64));
746 CLI.NumResultRegs = 1;
747 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*IsDef=*/true));
750 // Add the <id> and <numBytes> constants.
751 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
752 "Expected a constant integer.");
753 const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
754 Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
756 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos)) &&
757 "Expected a constant integer.");
758 const auto *NumBytes =
759 cast<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos));
760 Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
762 // Add the call target.
763 if (const auto *C = dyn_cast<IntToPtrInst>(Callee)) {
764 uint64_t CalleeConstAddr =
765 cast<ConstantInt>(C->getOperand(0))->getZExtValue();
766 Ops.push_back(MachineOperand::CreateImm(CalleeConstAddr));
767 } else if (const auto *C = dyn_cast<ConstantExpr>(Callee)) {
768 if (C->getOpcode() == Instruction::IntToPtr) {
769 uint64_t CalleeConstAddr =
770 cast<ConstantInt>(C->getOperand(0))->getZExtValue();
771 Ops.push_back(MachineOperand::CreateImm(CalleeConstAddr));
773 llvm_unreachable("Unsupported ConstantExpr.");
774 } else if (const auto *GV = dyn_cast<GlobalValue>(Callee)) {
775 Ops.push_back(MachineOperand::CreateGA(GV, 0));
776 } else if (isa<ConstantPointerNull>(Callee))
777 Ops.push_back(MachineOperand::CreateImm(0));
779 llvm_unreachable("Unsupported callee address.");
781 // Adjust <numArgs> to account for any arguments that have been passed on
782 // the stack instead.
783 unsigned NumCallRegArgs = IsAnyRegCC ? NumArgs : CLI.OutRegs.size();
784 Ops.push_back(MachineOperand::CreateImm(NumCallRegArgs));
786 // Add the calling convention
787 Ops.push_back(MachineOperand::CreateImm((unsigned)CC));
789 // Add the arguments we omitted previously. The register allocator should
790 // place these in any free register.
792 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i) {
793 unsigned Reg = getRegForValue(I->getArgOperand(i));
796 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
800 // Push the arguments from the call instruction.
801 for (auto Reg : CLI.OutRegs)
802 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
804 // Push live variables for the stack map.
805 if (!addStackMapLiveVars(Ops, I, NumMetaOpers + NumArgs))
808 // Push the register mask info.
809 Ops.push_back(MachineOperand::CreateRegMask(
810 TRI.getCallPreservedMask(*FuncInfo.MF, CC)));
812 // Add scratch registers as implicit def and early clobber.
813 const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
814 for (unsigned i = 0; ScratchRegs[i]; ++i)
815 Ops.push_back(MachineOperand::CreateReg(
816 ScratchRegs[i], /*IsDef=*/true, /*IsImp=*/true, /*IsKill=*/false,
817 /*IsDead=*/false, /*IsUndef=*/false, /*IsEarlyClobber=*/true));
819 // Add implicit defs (return values).
820 for (auto Reg : CLI.InRegs)
821 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/true,
824 // Insert the patchpoint instruction before the call generated by the target.
825 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, CLI.Call, DbgLoc,
826 TII.get(TargetOpcode::PATCHPOINT));
831 MIB->setPhysRegsDeadExcept(CLI.InRegs, TRI);
833 // Delete the original call instruction.
834 CLI.Call->eraseFromParent();
836 // Inform the Frame Information that we have a patchpoint in this function.
837 FuncInfo.MF->getFrameInfo().setHasPatchPoint();
839 if (CLI.NumResultRegs)
840 updateValueMap(I, CLI.ResultReg, CLI.NumResultRegs);
844 /// Returns an AttributeSet representing the attributes applied to the return
845 /// value of the given call.
846 static AttributeSet getReturnAttrs(FastISel::CallLoweringInfo &CLI) {
847 SmallVector<Attribute::AttrKind, 2> Attrs;
849 Attrs.push_back(Attribute::SExt);
851 Attrs.push_back(Attribute::ZExt);
853 Attrs.push_back(Attribute::InReg);
855 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
859 bool FastISel::lowerCallTo(const CallInst *CI, const char *SymName,
861 MCContext &Ctx = MF->getContext();
862 SmallString<32> MangledName;
863 Mangler::getNameWithPrefix(MangledName, SymName, DL);
864 MCSymbol *Sym = Ctx.getOrCreateSymbol(MangledName);
865 return lowerCallTo(CI, Sym, NumArgs);
868 bool FastISel::lowerCallTo(const CallInst *CI, MCSymbol *Symbol,
870 ImmutableCallSite CS(CI);
872 FunctionType *FTy = CS.getFunctionType();
873 Type *RetTy = CS.getType();
876 Args.reserve(NumArgs);
878 // Populate the argument list.
879 // Attributes for args start at offset 1, after the return attribute.
880 for (unsigned ArgI = 0; ArgI != NumArgs; ++ArgI) {
881 Value *V = CI->getOperand(ArgI);
883 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
887 Entry.Ty = V->getType();
888 Entry.setAttributes(&CS, ArgI + 1);
889 Args.push_back(Entry);
892 CallLoweringInfo CLI;
893 CLI.setCallee(RetTy, FTy, Symbol, std::move(Args), CS, NumArgs);
895 return lowerCallTo(CLI);
898 bool FastISel::lowerCallTo(CallLoweringInfo &CLI) {
899 // Handle the incoming return values from the call.
901 SmallVector<EVT, 4> RetTys;
902 ComputeValueVTs(TLI, DL, CLI.RetTy, RetTys);
904 SmallVector<ISD::OutputArg, 4> Outs;
905 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, TLI, DL);
907 bool CanLowerReturn = TLI.CanLowerReturn(
908 CLI.CallConv, *FuncInfo.MF, CLI.IsVarArg, Outs, CLI.RetTy->getContext());
910 // FIXME: sret demotion isn't supported yet - bail out.
914 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
916 MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT);
917 unsigned NumRegs = TLI.getNumRegisters(CLI.RetTy->getContext(), VT);
918 for (unsigned i = 0; i != NumRegs; ++i) {
919 ISD::InputArg MyFlags;
920 MyFlags.VT = RegisterVT;
922 MyFlags.Used = CLI.IsReturnValueUsed;
924 MyFlags.Flags.setSExt();
926 MyFlags.Flags.setZExt();
928 MyFlags.Flags.setInReg();
929 CLI.Ins.push_back(MyFlags);
933 // Handle all of the outgoing arguments.
935 for (auto &Arg : CLI.getArgs()) {
936 Type *FinalType = Arg.Ty;
938 FinalType = cast<PointerType>(Arg.Ty)->getElementType();
939 bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
940 FinalType, CLI.CallConv, CLI.IsVarArg);
942 ISD::ArgFlagsTy Flags;
952 Flags.setSwiftSelf();
953 if (Arg.IsSwiftError)
954 Flags.setSwiftError();
957 if (Arg.IsInAlloca) {
959 // Set the byval flag for CCAssignFn callbacks that don't know about
960 // inalloca. This way we can know how many bytes we should've allocated
961 // and how many bytes a callee cleanup function will pop. If we port
962 // inalloca to more targets, we'll have to add custom inalloca handling in
963 // the various CC lowering callbacks.
966 if (Arg.IsByVal || Arg.IsInAlloca) {
967 PointerType *Ty = cast<PointerType>(Arg.Ty);
968 Type *ElementTy = Ty->getElementType();
969 unsigned FrameSize = DL.getTypeAllocSize(ElementTy);
970 // For ByVal, alignment should come from FE. BE will guess if this info is
971 // not there, but there are cases it cannot get right.
972 unsigned FrameAlign = Arg.Alignment;
974 FrameAlign = TLI.getByValTypeAlignment(ElementTy, DL);
975 Flags.setByValSize(FrameSize);
976 Flags.setByValAlign(FrameAlign);
981 Flags.setInConsecutiveRegs();
982 unsigned OriginalAlignment = DL.getABITypeAlignment(Arg.Ty);
983 Flags.setOrigAlign(OriginalAlignment);
985 CLI.OutVals.push_back(Arg.Val);
986 CLI.OutFlags.push_back(Flags);
989 if (!fastLowerCall(CLI))
992 // Set all unused physreg defs as dead.
993 assert(CLI.Call && "No call instruction specified.");
994 CLI.Call->setPhysRegsDeadExcept(CLI.InRegs, TRI);
996 if (CLI.NumResultRegs && CLI.CS)
997 updateValueMap(CLI.CS->getInstruction(), CLI.ResultReg, CLI.NumResultRegs);
1002 bool FastISel::lowerCall(const CallInst *CI) {
1003 ImmutableCallSite CS(CI);
1005 FunctionType *FuncTy = CS.getFunctionType();
1006 Type *RetTy = CS.getType();
1010 Args.reserve(CS.arg_size());
1012 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1017 if (V->getType()->isEmptyTy())
1021 Entry.Ty = V->getType();
1023 // Skip the first return-type Attribute to get to params.
1024 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
1025 Args.push_back(Entry);
1028 // Check if target-independent constraints permit a tail call here.
1029 // Target-dependent constraints are checked within fastLowerCall.
1030 bool IsTailCall = CI->isTailCall();
1031 if (IsTailCall && !isInTailCallPosition(CS, TM))
1034 CallLoweringInfo CLI;
1035 CLI.setCallee(RetTy, FuncTy, CI->getCalledValue(), std::move(Args), CS)
1036 .setTailCall(IsTailCall);
1038 return lowerCallTo(CLI);
1041 bool FastISel::selectCall(const User *I) {
1042 const CallInst *Call = cast<CallInst>(I);
1044 // Handle simple inline asms.
1045 if (const InlineAsm *IA = dyn_cast<InlineAsm>(Call->getCalledValue())) {
1046 // If the inline asm has side effects, then make sure that no local value
1047 // lives across by flushing the local value map.
1048 if (IA->hasSideEffects())
1049 flushLocalValueMap();
1051 // Don't attempt to handle constraints.
1052 if (!IA->getConstraintString().empty())
1055 unsigned ExtraInfo = 0;
1056 if (IA->hasSideEffects())
1057 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
1058 if (IA->isAlignStack())
1059 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
1061 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1062 TII.get(TargetOpcode::INLINEASM))
1063 .addExternalSymbol(IA->getAsmString().c_str())
1068 MachineModuleInfo &MMI = FuncInfo.MF->getMMI();
1069 computeUsesVAFloatArgument(*Call, MMI);
1071 // Handle intrinsic function calls.
1072 if (const auto *II = dyn_cast<IntrinsicInst>(Call))
1073 return selectIntrinsicCall(II);
1075 // Usually, it does not make sense to initialize a value,
1076 // make an unrelated function call and use the value, because
1077 // it tends to be spilled on the stack. So, we move the pointer
1078 // to the last local value to the beginning of the block, so that
1079 // all the values which have already been materialized,
1080 // appear after the call. It also makes sense to skip intrinsics
1081 // since they tend to be inlined.
1082 flushLocalValueMap();
1084 return lowerCall(Call);
1087 bool FastISel::selectIntrinsicCall(const IntrinsicInst *II) {
1088 switch (II->getIntrinsicID()) {
1091 // At -O0 we don't care about the lifetime intrinsics.
1092 case Intrinsic::lifetime_start:
1093 case Intrinsic::lifetime_end:
1094 // The donothing intrinsic does, well, nothing.
1095 case Intrinsic::donothing:
1096 // Neither does the assume intrinsic; it's also OK not to codegen its operand.
1097 case Intrinsic::assume:
1099 case Intrinsic::dbg_declare: {
1100 const DbgDeclareInst *DI = cast<DbgDeclareInst>(II);
1101 assert(DI->getVariable() && "Missing variable");
1102 if (!FuncInfo.MF->getMMI().hasDebugInfo()) {
1103 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1107 const Value *Address = DI->getAddress();
1108 if (!Address || isa<UndefValue>(Address)) {
1109 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1113 unsigned Offset = 0;
1114 Optional<MachineOperand> Op;
1115 if (const auto *Arg = dyn_cast<Argument>(Address))
1116 // Some arguments' frame index is recorded during argument lowering.
1117 Offset = FuncInfo.getArgumentFrameIndex(Arg);
1119 Op = MachineOperand::CreateFI(Offset);
1121 if (unsigned Reg = lookUpRegForValue(Address))
1122 Op = MachineOperand::CreateReg(Reg, false);
1124 // If we have a VLA that has a "use" in a metadata node that's then used
1125 // here but it has no other uses, then we have a problem. E.g.,
1127 // int foo (const int *x) {
1132 // If we assign 'a' a vreg and fast isel later on has to use the selection
1133 // DAG isel, it will want to copy the value to the vreg. However, there are
1134 // no uses, which goes counter to what selection DAG isel expects.
1135 if (!Op && !Address->use_empty() && isa<Instruction>(Address) &&
1136 (!isa<AllocaInst>(Address) ||
1137 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(Address))))
1138 Op = MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address),
1142 assert(DI->getVariable()->isValidLocationForIntrinsic(DbgLoc) &&
1143 "Expected inlined-at fields to agree");
1145 Op->setIsDebug(true);
1146 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1147 TII.get(TargetOpcode::DBG_VALUE), false, Op->getReg(), 0,
1148 DI->getVariable(), DI->getExpression());
1150 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1151 TII.get(TargetOpcode::DBG_VALUE))
1154 .addMetadata(DI->getVariable())
1155 .addMetadata(DI->getExpression());
1157 // We can't yet handle anything else here because it would require
1158 // generating code, thus altering codegen because of debug info.
1159 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1163 case Intrinsic::dbg_value: {
1164 // This form of DBG_VALUE is target-independent.
1165 const DbgValueInst *DI = cast<DbgValueInst>(II);
1166 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1167 const Value *V = DI->getValue();
1168 assert(DI->getVariable()->isValidLocationForIntrinsic(DbgLoc) &&
1169 "Expected inlined-at fields to agree");
1171 // Currently the optimizer can produce this; insert an undef to
1172 // help debugging. Probably the optimizer should not do this.
1173 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1175 .addImm(DI->getOffset())
1176 .addMetadata(DI->getVariable())
1177 .addMetadata(DI->getExpression());
1178 } else if (const auto *CI = dyn_cast<ConstantInt>(V)) {
1179 if (CI->getBitWidth() > 64)
1180 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1182 .addImm(DI->getOffset())
1183 .addMetadata(DI->getVariable())
1184 .addMetadata(DI->getExpression());
1186 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1187 .addImm(CI->getZExtValue())
1188 .addImm(DI->getOffset())
1189 .addMetadata(DI->getVariable())
1190 .addMetadata(DI->getExpression());
1191 } else if (const auto *CF = dyn_cast<ConstantFP>(V)) {
1192 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1194 .addImm(DI->getOffset())
1195 .addMetadata(DI->getVariable())
1196 .addMetadata(DI->getExpression());
1197 } else if (unsigned Reg = lookUpRegForValue(V)) {
1198 // FIXME: This does not handle register-indirect values at offset 0.
1199 bool IsIndirect = DI->getOffset() != 0;
1200 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, IsIndirect, Reg,
1201 DI->getOffset(), DI->getVariable(), DI->getExpression());
1203 // We can't yet handle anything else here because it would require
1204 // generating code, thus altering codegen because of debug info.
1205 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1209 case Intrinsic::objectsize: {
1210 ConstantInt *CI = cast<ConstantInt>(II->getArgOperand(1));
1211 unsigned long long Res = CI->isZero() ? -1ULL : 0;
1212 Constant *ResCI = ConstantInt::get(II->getType(), Res);
1213 unsigned ResultReg = getRegForValue(ResCI);
1216 updateValueMap(II, ResultReg);
1219 case Intrinsic::invariant_group_barrier:
1220 case Intrinsic::expect: {
1221 unsigned ResultReg = getRegForValue(II->getArgOperand(0));
1224 updateValueMap(II, ResultReg);
1227 case Intrinsic::experimental_stackmap:
1228 return selectStackmap(II);
1229 case Intrinsic::experimental_patchpoint_void:
1230 case Intrinsic::experimental_patchpoint_i64:
1231 return selectPatchpoint(II);
1234 return fastLowerIntrinsicCall(II);
1237 bool FastISel::selectCast(const User *I, unsigned Opcode) {
1238 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType());
1239 EVT DstVT = TLI.getValueType(DL, I->getType());
1241 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other ||
1243 // Unhandled type. Halt "fast" selection and bail.
1246 // Check if the destination type is legal.
1247 if (!TLI.isTypeLegal(DstVT))
1250 // Check if the source operand is legal.
1251 if (!TLI.isTypeLegal(SrcVT))
1254 unsigned InputReg = getRegForValue(I->getOperand(0));
1256 // Unhandled operand. Halt "fast" selection and bail.
1259 bool InputRegIsKill = hasTrivialKill(I->getOperand(0));
1261 unsigned ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
1262 Opcode, InputReg, InputRegIsKill);
1266 updateValueMap(I, ResultReg);
1270 bool FastISel::selectBitCast(const User *I) {
1271 // If the bitcast doesn't change the type, just use the operand value.
1272 if (I->getType() == I->getOperand(0)->getType()) {
1273 unsigned Reg = getRegForValue(I->getOperand(0));
1276 updateValueMap(I, Reg);
1280 // Bitcasts of other values become reg-reg copies or BITCAST operators.
1281 EVT SrcEVT = TLI.getValueType(DL, I->getOperand(0)->getType());
1282 EVT DstEVT = TLI.getValueType(DL, I->getType());
1283 if (SrcEVT == MVT::Other || DstEVT == MVT::Other ||
1284 !TLI.isTypeLegal(SrcEVT) || !TLI.isTypeLegal(DstEVT))
1285 // Unhandled type. Halt "fast" selection and bail.
1288 MVT SrcVT = SrcEVT.getSimpleVT();
1289 MVT DstVT = DstEVT.getSimpleVT();
1290 unsigned Op0 = getRegForValue(I->getOperand(0));
1291 if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
1293 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
1295 // First, try to perform the bitcast by inserting a reg-reg copy.
1296 unsigned ResultReg = 0;
1297 if (SrcVT == DstVT) {
1298 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT);
1299 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT);
1300 // Don't attempt a cross-class copy. It will likely fail.
1301 if (SrcClass == DstClass) {
1302 ResultReg = createResultReg(DstClass);
1303 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1304 TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0);
1308 // If the reg-reg copy failed, select a BITCAST opcode.
1310 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
1315 updateValueMap(I, ResultReg);
1319 // Remove local value instructions starting from the instruction after
1320 // SavedLastLocalValue to the current function insert point.
1321 void FastISel::removeDeadLocalValueCode(MachineInstr *SavedLastLocalValue)
1323 MachineInstr *CurLastLocalValue = getLastLocalValue();
1324 if (CurLastLocalValue != SavedLastLocalValue) {
1325 // Find the first local value instruction to be deleted.
1326 // This is the instruction after SavedLastLocalValue if it is non-NULL.
1327 // Otherwise it's the first instruction in the block.
1328 MachineBasicBlock::iterator FirstDeadInst(SavedLastLocalValue);
1329 if (SavedLastLocalValue)
1332 FirstDeadInst = FuncInfo.MBB->getFirstNonPHI();
1333 setLastLocalValue(SavedLastLocalValue);
1334 removeDeadCode(FirstDeadInst, FuncInfo.InsertPt);
1338 bool FastISel::selectInstruction(const Instruction *I) {
1339 MachineInstr *SavedLastLocalValue = getLastLocalValue();
1340 // Just before the terminator instruction, insert instructions to
1341 // feed PHI nodes in successor blocks.
1342 if (isa<TerminatorInst>(I)) {
1343 if (!handlePHINodesInSuccessorBlocks(I->getParent())) {
1344 // PHI node handling may have generated local value instructions,
1345 // even though it failed to handle all PHI nodes.
1346 // We remove these instructions because SelectionDAGISel will generate
1348 removeDeadLocalValueCode(SavedLastLocalValue);
1353 // FastISel does not handle any operand bundles except OB_funclet.
1354 if (ImmutableCallSite CS = ImmutableCallSite(I))
1355 for (unsigned i = 0, e = CS.getNumOperandBundles(); i != e; ++i)
1356 if (CS.getOperandBundleAt(i).getTagID() != LLVMContext::OB_funclet)
1359 DbgLoc = I->getDebugLoc();
1361 SavedInsertPt = FuncInfo.InsertPt;
1363 if (const auto *Call = dyn_cast<CallInst>(I)) {
1364 const Function *F = Call->getCalledFunction();
1367 // As a special case, don't handle calls to builtin library functions that
1368 // may be translated directly to target instructions.
1369 if (F && !F->hasLocalLinkage() && F->hasName() &&
1370 LibInfo->getLibFunc(F->getName(), Func) &&
1371 LibInfo->hasOptimizedCodeGen(Func))
1374 // Don't handle Intrinsic::trap if a trap function is specified.
1375 if (F && F->getIntrinsicID() == Intrinsic::trap &&
1376 Call->hasFnAttr("trap-func-name"))
1380 // First, try doing target-independent selection.
1381 if (!SkipTargetIndependentISel) {
1382 if (selectOperator(I, I->getOpcode())) {
1383 ++NumFastIselSuccessIndependent;
1384 DbgLoc = DebugLoc();
1387 // Remove dead code.
1388 recomputeInsertPt();
1389 if (SavedInsertPt != FuncInfo.InsertPt)
1390 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
1391 SavedInsertPt = FuncInfo.InsertPt;
1393 // Next, try calling the target to attempt to handle the instruction.
1394 if (fastSelectInstruction(I)) {
1395 ++NumFastIselSuccessTarget;
1396 DbgLoc = DebugLoc();
1399 // Remove dead code.
1400 recomputeInsertPt();
1401 if (SavedInsertPt != FuncInfo.InsertPt)
1402 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
1404 DbgLoc = DebugLoc();
1405 // Undo phi node updates, because they will be added again by SelectionDAG.
1406 if (isa<TerminatorInst>(I)) {
1407 // PHI node handling may have generated local value instructions.
1408 // We remove them because SelectionDAGISel will generate them again.
1409 removeDeadLocalValueCode(SavedLastLocalValue);
1410 FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
1415 /// Emit an unconditional branch to the given block, unless it is the immediate
1416 /// (fall-through) successor, and update the CFG.
1417 void FastISel::fastEmitBranch(MachineBasicBlock *MSucc,
1418 const DebugLoc &DbgLoc) {
1419 if (FuncInfo.MBB->getBasicBlock()->size() > 1 &&
1420 FuncInfo.MBB->isLayoutSuccessor(MSucc)) {
1421 // For more accurate line information if this is the only instruction
1422 // in the block then emit it, otherwise we have the unconditional
1423 // fall-through case, which needs no instructions.
1425 // The unconditional branch case.
1426 TII.insertBranch(*FuncInfo.MBB, MSucc, nullptr,
1427 SmallVector<MachineOperand, 0>(), DbgLoc);
1430 auto BranchProbability = FuncInfo.BPI->getEdgeProbability(
1431 FuncInfo.MBB->getBasicBlock(), MSucc->getBasicBlock());
1432 FuncInfo.MBB->addSuccessor(MSucc, BranchProbability);
1434 FuncInfo.MBB->addSuccessorWithoutProb(MSucc);
1437 void FastISel::finishCondBranch(const BasicBlock *BranchBB,
1438 MachineBasicBlock *TrueMBB,
1439 MachineBasicBlock *FalseMBB) {
1440 // Add TrueMBB as successor unless it is equal to the FalseMBB: This can
1441 // happen in degenerate IR and MachineIR forbids to have a block twice in the
1442 // successor/predecessor lists.
1443 if (TrueMBB != FalseMBB) {
1445 auto BranchProbability =
1446 FuncInfo.BPI->getEdgeProbability(BranchBB, TrueMBB->getBasicBlock());
1447 FuncInfo.MBB->addSuccessor(TrueMBB, BranchProbability);
1449 FuncInfo.MBB->addSuccessorWithoutProb(TrueMBB);
1452 fastEmitBranch(FalseMBB, DbgLoc);
1455 /// Emit an FNeg operation.
1456 bool FastISel::selectFNeg(const User *I) {
1457 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
1460 bool OpRegIsKill = hasTrivialKill(I);
1462 // If the target has ISD::FNEG, use it.
1463 EVT VT = TLI.getValueType(DL, I->getType());
1464 unsigned ResultReg = fastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), ISD::FNEG,
1465 OpReg, OpRegIsKill);
1467 updateValueMap(I, ResultReg);
1471 // Bitcast the value to integer, twiddle the sign bit with xor,
1472 // and then bitcast it back to floating-point.
1473 if (VT.getSizeInBits() > 64)
1475 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
1476 if (!TLI.isTypeLegal(IntVT))
1479 unsigned IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
1480 ISD::BITCAST, OpReg, OpRegIsKill);
1484 unsigned IntResultReg = fastEmit_ri_(
1485 IntVT.getSimpleVT(), ISD::XOR, IntReg, /*IsKill=*/true,
1486 UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT());
1490 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST,
1491 IntResultReg, /*IsKill=*/true);
1495 updateValueMap(I, ResultReg);
1499 bool FastISel::selectExtractValue(const User *U) {
1500 const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(U);
1504 // Make sure we only try to handle extracts with a legal result. But also
1505 // allow i1 because it's easy.
1506 EVT RealVT = TLI.getValueType(DL, EVI->getType(), /*AllowUnknown=*/true);
1507 if (!RealVT.isSimple())
1509 MVT VT = RealVT.getSimpleVT();
1510 if (!TLI.isTypeLegal(VT) && VT != MVT::i1)
1513 const Value *Op0 = EVI->getOperand(0);
1514 Type *AggTy = Op0->getType();
1516 // Get the base result register.
1518 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(Op0);
1519 if (I != FuncInfo.ValueMap.end())
1520 ResultReg = I->second;
1521 else if (isa<Instruction>(Op0))
1522 ResultReg = FuncInfo.InitializeRegForValue(Op0);
1524 return false; // fast-isel can't handle aggregate constants at the moment
1526 // Get the actual result register, which is an offset from the base register.
1527 unsigned VTIndex = ComputeLinearIndex(AggTy, EVI->getIndices());
1529 SmallVector<EVT, 4> AggValueVTs;
1530 ComputeValueVTs(TLI, DL, AggTy, AggValueVTs);
1532 for (unsigned i = 0; i < VTIndex; i++)
1533 ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]);
1535 updateValueMap(EVI, ResultReg);
1539 bool FastISel::selectOperator(const User *I, unsigned Opcode) {
1541 case Instruction::Add:
1542 return selectBinaryOp(I, ISD::ADD);
1543 case Instruction::FAdd:
1544 return selectBinaryOp(I, ISD::FADD);
1545 case Instruction::Sub:
1546 return selectBinaryOp(I, ISD::SUB);
1547 case Instruction::FSub:
1548 // FNeg is currently represented in LLVM IR as a special case of FSub.
1549 if (BinaryOperator::isFNeg(I))
1550 return selectFNeg(I);
1551 return selectBinaryOp(I, ISD::FSUB);
1552 case Instruction::Mul:
1553 return selectBinaryOp(I, ISD::MUL);
1554 case Instruction::FMul:
1555 return selectBinaryOp(I, ISD::FMUL);
1556 case Instruction::SDiv:
1557 return selectBinaryOp(I, ISD::SDIV);
1558 case Instruction::UDiv:
1559 return selectBinaryOp(I, ISD::UDIV);
1560 case Instruction::FDiv:
1561 return selectBinaryOp(I, ISD::FDIV);
1562 case Instruction::SRem:
1563 return selectBinaryOp(I, ISD::SREM);
1564 case Instruction::URem:
1565 return selectBinaryOp(I, ISD::UREM);
1566 case Instruction::FRem:
1567 return selectBinaryOp(I, ISD::FREM);
1568 case Instruction::Shl:
1569 return selectBinaryOp(I, ISD::SHL);
1570 case Instruction::LShr:
1571 return selectBinaryOp(I, ISD::SRL);
1572 case Instruction::AShr:
1573 return selectBinaryOp(I, ISD::SRA);
1574 case Instruction::And:
1575 return selectBinaryOp(I, ISD::AND);
1576 case Instruction::Or:
1577 return selectBinaryOp(I, ISD::OR);
1578 case Instruction::Xor:
1579 return selectBinaryOp(I, ISD::XOR);
1581 case Instruction::GetElementPtr:
1582 return selectGetElementPtr(I);
1584 case Instruction::Br: {
1585 const BranchInst *BI = cast<BranchInst>(I);
1587 if (BI->isUnconditional()) {
1588 const BasicBlock *LLVMSucc = BI->getSuccessor(0);
1589 MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc];
1590 fastEmitBranch(MSucc, BI->getDebugLoc());
1594 // Conditional branches are not handed yet.
1595 // Halt "fast" selection and bail.
1599 case Instruction::Unreachable:
1600 if (TM.Options.TrapUnreachable)
1601 return fastEmit_(MVT::Other, MVT::Other, ISD::TRAP) != 0;
1605 case Instruction::Alloca:
1606 // FunctionLowering has the static-sized case covered.
1607 if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I)))
1610 // Dynamic-sized alloca is not handled yet.
1613 case Instruction::Call:
1614 return selectCall(I);
1616 case Instruction::BitCast:
1617 return selectBitCast(I);
1619 case Instruction::FPToSI:
1620 return selectCast(I, ISD::FP_TO_SINT);
1621 case Instruction::ZExt:
1622 return selectCast(I, ISD::ZERO_EXTEND);
1623 case Instruction::SExt:
1624 return selectCast(I, ISD::SIGN_EXTEND);
1625 case Instruction::Trunc:
1626 return selectCast(I, ISD::TRUNCATE);
1627 case Instruction::SIToFP:
1628 return selectCast(I, ISD::SINT_TO_FP);
1630 case Instruction::IntToPtr: // Deliberate fall-through.
1631 case Instruction::PtrToInt: {
1632 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType());
1633 EVT DstVT = TLI.getValueType(DL, I->getType());
1634 if (DstVT.bitsGT(SrcVT))
1635 return selectCast(I, ISD::ZERO_EXTEND);
1636 if (DstVT.bitsLT(SrcVT))
1637 return selectCast(I, ISD::TRUNCATE);
1638 unsigned Reg = getRegForValue(I->getOperand(0));
1641 updateValueMap(I, Reg);
1645 case Instruction::ExtractValue:
1646 return selectExtractValue(I);
1648 case Instruction::PHI:
1649 llvm_unreachable("FastISel shouldn't visit PHI nodes!");
1652 // Unhandled instruction. Halt "fast" selection and bail.
1657 FastISel::FastISel(FunctionLoweringInfo &FuncInfo,
1658 const TargetLibraryInfo *LibInfo,
1659 bool SkipTargetIndependentISel)
1660 : FuncInfo(FuncInfo), MF(FuncInfo.MF), MRI(FuncInfo.MF->getRegInfo()),
1661 MFI(FuncInfo.MF->getFrameInfo()), MCP(*FuncInfo.MF->getConstantPool()),
1662 TM(FuncInfo.MF->getTarget()), DL(MF->getDataLayout()),
1663 TII(*MF->getSubtarget().getInstrInfo()),
1664 TLI(*MF->getSubtarget().getTargetLowering()),
1665 TRI(*MF->getSubtarget().getRegisterInfo()), LibInfo(LibInfo),
1666 SkipTargetIndependentISel(SkipTargetIndependentISel) {}
1668 FastISel::~FastISel() {}
1670 bool FastISel::fastLowerArguments() { return false; }
1672 bool FastISel::fastLowerCall(CallLoweringInfo & /*CLI*/) { return false; }
1674 bool FastISel::fastLowerIntrinsicCall(const IntrinsicInst * /*II*/) {
1678 unsigned FastISel::fastEmit_(MVT, MVT, unsigned) { return 0; }
1680 unsigned FastISel::fastEmit_r(MVT, MVT, unsigned, unsigned /*Op0*/,
1681 bool /*Op0IsKill*/) {
1685 unsigned FastISel::fastEmit_rr(MVT, MVT, unsigned, unsigned /*Op0*/,
1686 bool /*Op0IsKill*/, unsigned /*Op1*/,
1687 bool /*Op1IsKill*/) {
1691 unsigned FastISel::fastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
1695 unsigned FastISel::fastEmit_f(MVT, MVT, unsigned,
1696 const ConstantFP * /*FPImm*/) {
1700 unsigned FastISel::fastEmit_ri(MVT, MVT, unsigned, unsigned /*Op0*/,
1701 bool /*Op0IsKill*/, uint64_t /*Imm*/) {
1705 /// This method is a wrapper of fastEmit_ri. It first tries to emit an
1706 /// instruction with an immediate operand using fastEmit_ri.
1707 /// If that fails, it materializes the immediate into a register and try
1708 /// fastEmit_rr instead.
1709 unsigned FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0,
1710 bool Op0IsKill, uint64_t Imm, MVT ImmType) {
1711 // If this is a multiply by a power of two, emit this as a shift left.
1712 if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) {
1715 } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) {
1716 // div x, 8 -> srl x, 3
1721 // Horrible hack (to be removed), check to make sure shift amounts are
1723 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
1724 Imm >= VT.getSizeInBits())
1727 // First check if immediate type is legal. If not, we can't use the ri form.
1728 unsigned ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
1731 unsigned MaterialReg = fastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
1732 bool IsImmKill = true;
1734 // This is a bit ugly/slow, but failing here means falling out of
1735 // fast-isel, which would be very slow.
1737 IntegerType::get(FuncInfo.Fn->getContext(), VT.getSizeInBits());
1738 MaterialReg = getRegForValue(ConstantInt::get(ITy, Imm));
1741 // FIXME: If the materialized register here has no uses yet then this
1742 // will be the first use and we should be able to mark it as killed.
1743 // However, the local value area for materialising constant expressions
1744 // grows down, not up, which means that any constant expressions we generate
1745 // later which also use 'Imm' could be after this instruction and therefore
1749 return fastEmit_rr(VT, VT, Opcode, Op0, Op0IsKill, MaterialReg, IsImmKill);
1752 unsigned FastISel::createResultReg(const TargetRegisterClass *RC) {
1753 return MRI.createVirtualRegister(RC);
1756 unsigned FastISel::constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
1758 if (TargetRegisterInfo::isVirtualRegister(Op)) {
1759 const TargetRegisterClass *RegClass =
1760 TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF);
1761 if (!MRI.constrainRegClass(Op, RegClass)) {
1762 // If it's not legal to COPY between the register classes, something
1763 // has gone very wrong before we got here.
1764 unsigned NewOp = createResultReg(RegClass);
1765 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1766 TII.get(TargetOpcode::COPY), NewOp).addReg(Op);
1773 unsigned FastISel::fastEmitInst_(unsigned MachineInstOpcode,
1774 const TargetRegisterClass *RC) {
1775 unsigned ResultReg = createResultReg(RC);
1776 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1778 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg);
1782 unsigned FastISel::fastEmitInst_r(unsigned MachineInstOpcode,
1783 const TargetRegisterClass *RC, unsigned Op0,
1785 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1787 unsigned ResultReg = createResultReg(RC);
1788 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1790 if (II.getNumDefs() >= 1)
1791 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1792 .addReg(Op0, getKillRegState(Op0IsKill));
1794 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1795 .addReg(Op0, getKillRegState(Op0IsKill));
1796 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1797 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1803 unsigned FastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
1804 const TargetRegisterClass *RC, unsigned Op0,
1805 bool Op0IsKill, unsigned Op1,
1807 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1809 unsigned ResultReg = createResultReg(RC);
1810 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1811 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1813 if (II.getNumDefs() >= 1)
1814 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1815 .addReg(Op0, getKillRegState(Op0IsKill))
1816 .addReg(Op1, getKillRegState(Op1IsKill));
1818 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1819 .addReg(Op0, getKillRegState(Op0IsKill))
1820 .addReg(Op1, getKillRegState(Op1IsKill));
1821 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1822 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1827 unsigned FastISel::fastEmitInst_rrr(unsigned MachineInstOpcode,
1828 const TargetRegisterClass *RC, unsigned Op0,
1829 bool Op0IsKill, unsigned Op1,
1830 bool Op1IsKill, unsigned Op2,
1832 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1834 unsigned ResultReg = createResultReg(RC);
1835 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1836 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1837 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2);
1839 if (II.getNumDefs() >= 1)
1840 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1841 .addReg(Op0, getKillRegState(Op0IsKill))
1842 .addReg(Op1, getKillRegState(Op1IsKill))
1843 .addReg(Op2, getKillRegState(Op2IsKill));
1845 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1846 .addReg(Op0, getKillRegState(Op0IsKill))
1847 .addReg(Op1, getKillRegState(Op1IsKill))
1848 .addReg(Op2, getKillRegState(Op2IsKill));
1849 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1850 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1855 unsigned FastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
1856 const TargetRegisterClass *RC, unsigned Op0,
1857 bool Op0IsKill, uint64_t Imm) {
1858 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1860 unsigned ResultReg = createResultReg(RC);
1861 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1863 if (II.getNumDefs() >= 1)
1864 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1865 .addReg(Op0, getKillRegState(Op0IsKill))
1868 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1869 .addReg(Op0, getKillRegState(Op0IsKill))
1871 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1872 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1877 unsigned FastISel::fastEmitInst_rii(unsigned MachineInstOpcode,
1878 const TargetRegisterClass *RC, unsigned Op0,
1879 bool Op0IsKill, uint64_t Imm1,
1881 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1883 unsigned ResultReg = createResultReg(RC);
1884 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1886 if (II.getNumDefs() >= 1)
1887 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1888 .addReg(Op0, getKillRegState(Op0IsKill))
1892 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1893 .addReg(Op0, getKillRegState(Op0IsKill))
1896 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1897 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1902 unsigned FastISel::fastEmitInst_f(unsigned MachineInstOpcode,
1903 const TargetRegisterClass *RC,
1904 const ConstantFP *FPImm) {
1905 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1907 unsigned ResultReg = createResultReg(RC);
1909 if (II.getNumDefs() >= 1)
1910 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1913 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1915 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1916 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1921 unsigned FastISel::fastEmitInst_rri(unsigned MachineInstOpcode,
1922 const TargetRegisterClass *RC, unsigned Op0,
1923 bool Op0IsKill, unsigned Op1,
1924 bool Op1IsKill, uint64_t Imm) {
1925 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1927 unsigned ResultReg = createResultReg(RC);
1928 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1929 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1931 if (II.getNumDefs() >= 1)
1932 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1933 .addReg(Op0, getKillRegState(Op0IsKill))
1934 .addReg(Op1, getKillRegState(Op1IsKill))
1937 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1938 .addReg(Op0, getKillRegState(Op0IsKill))
1939 .addReg(Op1, getKillRegState(Op1IsKill))
1941 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1942 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1947 unsigned FastISel::fastEmitInst_i(unsigned MachineInstOpcode,
1948 const TargetRegisterClass *RC, uint64_t Imm) {
1949 unsigned ResultReg = createResultReg(RC);
1950 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1952 if (II.getNumDefs() >= 1)
1953 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1956 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addImm(Imm);
1957 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1958 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1963 unsigned FastISel::fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0,
1964 bool Op0IsKill, uint32_t Idx) {
1965 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1966 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
1967 "Cannot yet extract from physregs");
1968 const TargetRegisterClass *RC = MRI.getRegClass(Op0);
1969 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
1970 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
1971 ResultReg).addReg(Op0, getKillRegState(Op0IsKill), Idx);
1975 /// Emit MachineInstrs to compute the value of Op with all but the least
1976 /// significant bit set to zero.
1977 unsigned FastISel::fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) {
1978 return fastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1);
1981 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
1982 /// Emit code to ensure constants are copied into registers when needed.
1983 /// Remember the virtual registers that need to be added to the Machine PHI
1984 /// nodes as input. We cannot just directly add them, because expansion
1985 /// might result in multiple MBB's for one BB. As such, the start of the
1986 /// BB might correspond to a different MBB than the end.
1987 bool FastISel::handlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
1988 const TerminatorInst *TI = LLVMBB->getTerminator();
1990 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
1991 FuncInfo.OrigNumPHINodesToUpdate = FuncInfo.PHINodesToUpdate.size();
1993 // Check successor nodes' PHI nodes that expect a constant to be available
1995 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
1996 const BasicBlock *SuccBB = TI->getSuccessor(succ);
1997 if (!isa<PHINode>(SuccBB->begin()))
1999 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
2001 // If this terminator has multiple identical successors (common for
2002 // switches), only handle each succ once.
2003 if (!SuccsHandled.insert(SuccMBB).second)
2006 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
2008 // At this point we know that there is a 1-1 correspondence between LLVM PHI
2009 // nodes and Machine PHI nodes, but the incoming operands have not been
2011 for (BasicBlock::const_iterator I = SuccBB->begin();
2012 const auto *PN = dyn_cast<PHINode>(I); ++I) {
2014 // Ignore dead phi's.
2015 if (PN->use_empty())
2018 // Only handle legal types. Two interesting things to note here. First,
2019 // by bailing out early, we may leave behind some dead instructions,
2020 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
2021 // own moves. Second, this check is necessary because FastISel doesn't
2022 // use CreateRegs to create registers, so it always creates
2023 // exactly one register for each non-void instruction.
2024 EVT VT = TLI.getValueType(DL, PN->getType(), /*AllowUnknown=*/true);
2025 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
2026 // Handle integer promotions, though, because they're common and easy.
2027 if (!(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)) {
2028 FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
2033 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
2035 // Set the DebugLoc for the copy. Prefer the location of the operand
2036 // if there is one; use the location of the PHI otherwise.
2037 DbgLoc = PN->getDebugLoc();
2038 if (const auto *Inst = dyn_cast<Instruction>(PHIOp))
2039 DbgLoc = Inst->getDebugLoc();
2041 unsigned Reg = getRegForValue(PHIOp);
2043 FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
2046 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(&*MBBI++, Reg));
2047 DbgLoc = DebugLoc();
2054 bool FastISel::tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst) {
2055 assert(LI->hasOneUse() &&
2056 "tryToFoldLoad expected a LoadInst with a single use");
2057 // We know that the load has a single use, but don't know what it is. If it
2058 // isn't one of the folded instructions, then we can't succeed here. Handle
2059 // this by scanning the single-use users of the load until we get to FoldInst.
2060 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
2062 const Instruction *TheUser = LI->user_back();
2063 while (TheUser != FoldInst && // Scan up until we find FoldInst.
2064 // Stay in the right block.
2065 TheUser->getParent() == FoldInst->getParent() &&
2066 --MaxUsers) { // Don't scan too far.
2067 // If there are multiple or no uses of this instruction, then bail out.
2068 if (!TheUser->hasOneUse())
2071 TheUser = TheUser->user_back();
2074 // If we didn't find the fold instruction, then we failed to collapse the
2076 if (TheUser != FoldInst)
2079 // Don't try to fold volatile loads. Target has to deal with alignment
2081 if (LI->isVolatile())
2084 // Figure out which vreg this is going into. If there is no assigned vreg yet
2085 // then there actually was no reference to it. Perhaps the load is referenced
2086 // by a dead instruction.
2087 unsigned LoadReg = getRegForValue(LI);
2091 // We can't fold if this vreg has no uses or more than one use. Multiple uses
2092 // may mean that the instruction got lowered to multiple MIs, or the use of
2093 // the loaded value ended up being multiple operands of the result.
2094 if (!MRI.hasOneUse(LoadReg))
2097 MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(LoadReg);
2098 MachineInstr *User = RI->getParent();
2100 // Set the insertion point properly. Folding the load can cause generation of
2101 // other random instructions (like sign extends) for addressing modes; make
2102 // sure they get inserted in a logical place before the new instruction.
2103 FuncInfo.InsertPt = User;
2104 FuncInfo.MBB = User->getParent();
2106 // Ask the target to try folding the load.
2107 return tryToFoldLoadIntoMI(User, RI.getOperandNo(), LI);
2110 bool FastISel::canFoldAddIntoGEP(const User *GEP, const Value *Add) {
2112 if (!isa<AddOperator>(Add))
2114 // Type size needs to match.
2115 if (DL.getTypeSizeInBits(GEP->getType()) !=
2116 DL.getTypeSizeInBits(Add->getType()))
2118 // Must be in the same basic block.
2119 if (isa<Instruction>(Add) &&
2120 FuncInfo.MBBMap[cast<Instruction>(Add)->getParent()] != FuncInfo.MBB)
2122 // Must have a constant operand.
2123 return isa<ConstantInt>(cast<AddOperator>(Add)->getOperand(1));
2127 FastISel::createMachineMemOperandFor(const Instruction *I) const {
2131 MachineMemOperand::Flags Flags;
2134 if (const auto *LI = dyn_cast<LoadInst>(I)) {
2135 Alignment = LI->getAlignment();
2136 IsVolatile = LI->isVolatile();
2137 Flags = MachineMemOperand::MOLoad;
2138 Ptr = LI->getPointerOperand();
2139 ValTy = LI->getType();
2140 } else if (const auto *SI = dyn_cast<StoreInst>(I)) {
2141 Alignment = SI->getAlignment();
2142 IsVolatile = SI->isVolatile();
2143 Flags = MachineMemOperand::MOStore;
2144 Ptr = SI->getPointerOperand();
2145 ValTy = SI->getValueOperand()->getType();
2149 bool IsNonTemporal = I->getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2150 bool IsInvariant = I->getMetadata(LLVMContext::MD_invariant_load) != nullptr;
2151 bool IsDereferenceable =
2152 I->getMetadata(LLVMContext::MD_dereferenceable) != nullptr;
2153 const MDNode *Ranges = I->getMetadata(LLVMContext::MD_range);
2156 I->getAAMetadata(AAInfo);
2158 if (Alignment == 0) // Ensure that codegen never sees alignment 0.
2159 Alignment = DL.getABITypeAlignment(ValTy);
2161 unsigned Size = DL.getTypeStoreSize(ValTy);
2164 Flags |= MachineMemOperand::MOVolatile;
2166 Flags |= MachineMemOperand::MONonTemporal;
2167 if (IsDereferenceable)
2168 Flags |= MachineMemOperand::MODereferenceable;
2170 Flags |= MachineMemOperand::MOInvariant;
2172 return FuncInfo.MF->getMachineMemOperand(MachinePointerInfo(Ptr), Flags, Size,
2173 Alignment, AAInfo, Ranges);
2176 CmpInst::Predicate FastISel::optimizeCmpPredicate(const CmpInst *CI) const {
2177 // If both operands are the same, then try to optimize or fold the cmp.
2178 CmpInst::Predicate Predicate = CI->getPredicate();
2179 if (CI->getOperand(0) != CI->getOperand(1))
2182 switch (Predicate) {
2183 default: llvm_unreachable("Invalid predicate!");
2184 case CmpInst::FCMP_FALSE: Predicate = CmpInst::FCMP_FALSE; break;
2185 case CmpInst::FCMP_OEQ: Predicate = CmpInst::FCMP_ORD; break;
2186 case CmpInst::FCMP_OGT: Predicate = CmpInst::FCMP_FALSE; break;
2187 case CmpInst::FCMP_OGE: Predicate = CmpInst::FCMP_ORD; break;
2188 case CmpInst::FCMP_OLT: Predicate = CmpInst::FCMP_FALSE; break;
2189 case CmpInst::FCMP_OLE: Predicate = CmpInst::FCMP_ORD; break;
2190 case CmpInst::FCMP_ONE: Predicate = CmpInst::FCMP_FALSE; break;
2191 case CmpInst::FCMP_ORD: Predicate = CmpInst::FCMP_ORD; break;
2192 case CmpInst::FCMP_UNO: Predicate = CmpInst::FCMP_UNO; break;
2193 case CmpInst::FCMP_UEQ: Predicate = CmpInst::FCMP_TRUE; break;
2194 case CmpInst::FCMP_UGT: Predicate = CmpInst::FCMP_UNO; break;
2195 case CmpInst::FCMP_UGE: Predicate = CmpInst::FCMP_TRUE; break;
2196 case CmpInst::FCMP_ULT: Predicate = CmpInst::FCMP_UNO; break;
2197 case CmpInst::FCMP_ULE: Predicate = CmpInst::FCMP_TRUE; break;
2198 case CmpInst::FCMP_UNE: Predicate = CmpInst::FCMP_UNO; break;
2199 case CmpInst::FCMP_TRUE: Predicate = CmpInst::FCMP_TRUE; break;
2201 case CmpInst::ICMP_EQ: Predicate = CmpInst::FCMP_TRUE; break;
2202 case CmpInst::ICMP_NE: Predicate = CmpInst::FCMP_FALSE; break;
2203 case CmpInst::ICMP_UGT: Predicate = CmpInst::FCMP_FALSE; break;
2204 case CmpInst::ICMP_UGE: Predicate = CmpInst::FCMP_TRUE; break;
2205 case CmpInst::ICMP_ULT: Predicate = CmpInst::FCMP_FALSE; break;
2206 case CmpInst::ICMP_ULE: Predicate = CmpInst::FCMP_TRUE; break;
2207 case CmpInst::ICMP_SGT: Predicate = CmpInst::FCMP_FALSE; break;
2208 case CmpInst::ICMP_SGE: Predicate = CmpInst::FCMP_TRUE; break;
2209 case CmpInst::ICMP_SLT: Predicate = CmpInst::FCMP_FALSE; break;
2210 case CmpInst::ICMP_SLE: Predicate = CmpInst::FCMP_TRUE; break;