1 //===-- FunctionLoweringInfo.cpp ------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating functions from LLVM IR into
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/FunctionLoweringInfo.h"
16 #include "llvm/CodeGen/Analysis.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/TargetFrameLowering.h"
22 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #include "llvm/CodeGen/TargetLowering.h"
24 #include "llvm/CodeGen/TargetRegisterInfo.h"
25 #include "llvm/CodeGen/TargetSubtargetInfo.h"
26 #include "llvm/CodeGen/WasmEHFuncInfo.h"
27 #include "llvm/CodeGen/WinEHFuncInfo.h"
28 #include "llvm/IR/DataLayout.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/Instructions.h"
32 #include "llvm/IR/IntrinsicInst.h"
33 #include "llvm/IR/LLVMContext.h"
34 #include "llvm/IR/Module.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetOptions.h"
43 #define DEBUG_TYPE "function-lowering-info"
45 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
46 /// PHI nodes or outside of the basic block that defines it, or used by a
47 /// switch or atomic instruction, which may expand to multiple basic blocks.
48 static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
49 if (I->use_empty()) return false;
50 if (isa<PHINode>(I)) return true;
51 const BasicBlock *BB = I->getParent();
52 for (const User *U : I->users())
53 if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
59 static ISD::NodeType getPreferredExtendForValue(const Value *V) {
60 // For the users of the source value being used for compare instruction, if
61 // the number of signed predicate is greater than unsigned predicate, we
62 // prefer to use SIGN_EXTEND.
64 // With this optimization, we would be able to reduce some redundant sign or
65 // zero extension instruction, and eventually more machine CSE opportunities
67 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
68 unsigned NumOfSigned = 0, NumOfUnsigned = 0;
69 for (const User *U : V->users()) {
70 if (const auto *CI = dyn_cast<CmpInst>(U)) {
71 NumOfSigned += CI->isSigned();
72 NumOfUnsigned += CI->isUnsigned();
75 if (NumOfSigned > NumOfUnsigned)
76 ExtendKind = ISD::SIGN_EXTEND;
81 void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
85 TLI = MF->getSubtarget().getTargetLowering();
86 RegInfo = &MF->getRegInfo();
87 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
88 unsigned StackAlign = TFI->getStackAlignment();
90 // Check whether the function can return without sret-demotion.
91 SmallVector<ISD::OutputArg, 4> Outs;
92 GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI,
94 CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF,
95 Fn->isVarArg(), Outs, Fn->getContext());
97 // If this personality uses funclets, we need to do a bit more work.
98 DenseMap<const AllocaInst *, TinyPtrVector<int *>> CatchObjects;
99 EHPersonality Personality = classifyEHPersonality(
100 Fn->hasPersonalityFn() ? Fn->getPersonalityFn() : nullptr);
101 if (isFuncletEHPersonality(Personality)) {
102 // Calculate state numbers if we haven't already.
103 WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
104 if (Personality == EHPersonality::MSVC_CXX)
105 calculateWinCXXEHStateNumbers(&fn, EHInfo);
106 else if (isAsynchronousEHPersonality(Personality))
107 calculateSEHStateNumbers(&fn, EHInfo);
108 else if (Personality == EHPersonality::CoreCLR)
109 calculateClrEHStateNumbers(&fn, EHInfo);
111 // Map all BB references in the WinEH data to MBBs.
112 for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
113 for (WinEHHandlerType &H : TBME.HandlerArray) {
114 if (const AllocaInst *AI = H.CatchObj.Alloca)
115 CatchObjects.insert({AI, {}}).first->second.push_back(
116 &H.CatchObj.FrameIndex);
118 H.CatchObj.FrameIndex = INT_MAX;
122 if (Personality == EHPersonality::Wasm_CXX) {
123 WasmEHFuncInfo &EHInfo = *MF->getWasmEHFuncInfo();
124 calculateWasmEHInfo(&fn, EHInfo);
127 // Initialize the mapping of values to registers. This is only set up for
128 // instruction values that are used outside of the block that defines
130 for (const BasicBlock &BB : *Fn) {
131 for (const Instruction &I : BB) {
132 if (const AllocaInst *AI = dyn_cast<AllocaInst>(&I)) {
133 Type *Ty = AI->getAllocatedType();
135 std::max((unsigned)MF->getDataLayout().getPrefTypeAlignment(Ty),
138 // Static allocas can be folded into the initial stack frame
139 // adjustment. For targets that don't realign the stack, don't
140 // do this if there is an extra alignment requirement.
141 if (AI->isStaticAlloca() &&
142 (TFI->isStackRealignable() || (Align <= StackAlign))) {
143 const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize());
144 uint64_t TySize = MF->getDataLayout().getTypeAllocSize(Ty);
146 TySize *= CUI->getZExtValue(); // Get total allocated size.
147 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
148 int FrameIndex = INT_MAX;
149 auto Iter = CatchObjects.find(AI);
150 if (Iter != CatchObjects.end() && TLI->needsFixedCatchObjects()) {
151 FrameIndex = MF->getFrameInfo().CreateFixedObject(
152 TySize, 0, /*Immutable=*/false, /*isAliased=*/true);
153 MF->getFrameInfo().setObjectAlignment(FrameIndex, Align);
156 MF->getFrameInfo().CreateStackObject(TySize, Align, false, AI);
159 StaticAllocaMap[AI] = FrameIndex;
160 // Update the catch handler information.
161 if (Iter != CatchObjects.end()) {
162 for (int *CatchObjPtr : Iter->second)
163 *CatchObjPtr = FrameIndex;
166 // FIXME: Overaligned static allocas should be grouped into
167 // a single dynamic allocation instead of using a separate
168 // stack allocation for each one.
169 if (Align <= StackAlign)
171 // Inform the Frame Information that we have variable-sized objects.
172 MF->getFrameInfo().CreateVariableSizedObject(Align ? Align : 1, AI);
176 // Look for inline asm that clobbers the SP register.
177 if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
178 ImmutableCallSite CS(&I);
179 if (isa<InlineAsm>(CS.getCalledValue())) {
180 unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
181 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
182 std::vector<TargetLowering::AsmOperandInfo> Ops =
183 TLI->ParseConstraints(Fn->getParent()->getDataLayout(), TRI, CS);
184 for (TargetLowering::AsmOperandInfo &Op : Ops) {
185 if (Op.Type == InlineAsm::isClobber) {
186 // Clobbers don't have SDValue operands, hence SDValue().
187 TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
188 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
189 TLI->getRegForInlineAsmConstraint(TRI, Op.ConstraintCode,
191 if (PhysReg.first == SP)
192 MF->getFrameInfo().setHasOpaqueSPAdjustment(true);
198 // Look for calls to the @llvm.va_start intrinsic. We can omit some
199 // prologue boilerplate for variadic functions that don't examine their
201 if (const auto *II = dyn_cast<IntrinsicInst>(&I)) {
202 if (II->getIntrinsicID() == Intrinsic::vastart)
203 MF->getFrameInfo().setHasVAStart(true);
206 // If we have a musttail call in a variadic function, we need to ensure we
207 // forward implicit register parameters.
208 if (const auto *CI = dyn_cast<CallInst>(&I)) {
209 if (CI->isMustTailCall() && Fn->isVarArg())
210 MF->getFrameInfo().setHasMustTailInVarArgFunc(true);
213 // Mark values used outside their block as exported, by allocating
214 // a virtual register for them.
215 if (isUsedOutsideOfDefiningBlock(&I))
216 if (!isa<AllocaInst>(I) || !StaticAllocaMap.count(cast<AllocaInst>(&I)))
217 InitializeRegForValue(&I);
219 // Decide the preferred extend type for a value.
220 PreferredExtendType[&I] = getPreferredExtendForValue(&I);
224 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
225 // also creates the initial PHI MachineInstrs, though none of the input
226 // operands are populated.
227 for (const BasicBlock &BB : *Fn) {
228 // Don't create MachineBasicBlocks for imaginary EH pad blocks. These blocks
229 // are really data, and no instructions can live here.
231 const Instruction *PadInst = BB.getFirstNonPHI();
232 // If this is a non-landingpad EH pad, mark this function as using
234 // FIXME: SEH catchpads do not create EH scope/funclets, so we could avoid
235 // setting this in such cases in order to improve frame layout.
236 if (!isa<LandingPadInst>(PadInst)) {
237 MF->setHasEHScopes(true);
238 MF->setHasEHFunclets(true);
239 MF->getFrameInfo().setHasOpaqueSPAdjustment(true);
241 if (isa<CatchSwitchInst>(PadInst)) {
242 assert(&*BB.begin() == PadInst &&
243 "WinEHPrepare failed to remove PHIs from imaginary BBs");
246 if (isa<FuncletPadInst>(PadInst))
247 assert(&*BB.begin() == PadInst && "WinEHPrepare failed to demote PHIs");
250 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(&BB);
254 // Transfer the address-taken flag. This is necessary because there could
255 // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
256 // the first one should be marked.
257 if (BB.hasAddressTaken())
258 MBB->setHasAddressTaken();
260 // Mark landing pad blocks.
264 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
266 for (const PHINode &PN : BB.phis()) {
271 if (PN.getType()->isEmptyTy())
274 DebugLoc DL = PN.getDebugLoc();
275 unsigned PHIReg = ValueMap[&PN];
276 assert(PHIReg && "PHI node does not have an assigned virtual register!");
278 SmallVector<EVT, 4> ValueVTs;
279 ComputeValueVTs(*TLI, MF->getDataLayout(), PN.getType(), ValueVTs);
280 for (EVT VT : ValueVTs) {
281 unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
282 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
283 for (unsigned i = 0; i != NumRegisters; ++i)
284 BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
285 PHIReg += NumRegisters;
290 if (isFuncletEHPersonality(Personality)) {
291 WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
293 // Map all BB references in the WinEH data to MBBs.
294 for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
295 for (WinEHHandlerType &H : TBME.HandlerArray) {
297 H.Handler = MBBMap[H.Handler.get<const BasicBlock *>()];
300 for (CxxUnwindMapEntry &UME : EHInfo.CxxUnwindMap)
302 UME.Cleanup = MBBMap[UME.Cleanup.get<const BasicBlock *>()];
303 for (SEHUnwindMapEntry &UME : EHInfo.SEHUnwindMap) {
304 const auto *BB = UME.Handler.get<const BasicBlock *>();
305 UME.Handler = MBBMap[BB];
307 for (ClrEHUnwindMapEntry &CME : EHInfo.ClrEHUnwindMap) {
308 const auto *BB = CME.Handler.get<const BasicBlock *>();
309 CME.Handler = MBBMap[BB];
313 else if (Personality == EHPersonality::Wasm_CXX) {
314 WasmEHFuncInfo &EHInfo = *MF->getWasmEHFuncInfo();
315 // Map all BB references in the WinEH data to MBBs.
316 DenseMap<BBOrMBB, BBOrMBB> NewMap;
317 for (auto &KV : EHInfo.EHPadUnwindMap) {
318 const auto *Src = KV.first.get<const BasicBlock *>();
319 const auto *Dst = KV.second.get<const BasicBlock *>();
320 NewMap[MBBMap[Src]] = MBBMap[Dst];
322 EHInfo.EHPadUnwindMap = std::move(NewMap);
324 for (auto &KV : EHInfo.ThrowUnwindMap) {
325 const auto *Src = KV.first.get<const BasicBlock *>();
326 const auto *Dst = KV.second.get<const BasicBlock *>();
327 NewMap[MBBMap[Src]] = MBBMap[Dst];
329 EHInfo.ThrowUnwindMap = std::move(NewMap);
333 /// clear - Clear out all the function-specific state. This returns this
334 /// FunctionLoweringInfo to an empty state, ready to be used for a
335 /// different function.
336 void FunctionLoweringInfo::clear() {
339 VirtReg2Value.clear();
340 StaticAllocaMap.clear();
341 LiveOutRegInfo.clear();
343 ArgDbgValues.clear();
344 ByValArgFrameIndexMap.clear();
346 RegsWithFixups.clear();
347 StatepointStackSlots.clear();
348 StatepointSpillMaps.clear();
349 PreferredExtendType.clear();
352 /// CreateReg - Allocate a single virtual register for the given type.
353 unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
354 return RegInfo->createVirtualRegister(
355 MF->getSubtarget().getTargetLowering()->getRegClassFor(VT));
358 /// CreateRegs - Allocate the appropriate number of virtual registers of
359 /// the correctly promoted or expanded types. Assign these registers
360 /// consecutive vreg numbers and return the first assigned number.
362 /// In the case that the given value has struct or array type, this function
363 /// will assign registers for each member or element.
365 unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
366 const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
368 SmallVector<EVT, 4> ValueVTs;
369 ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
371 unsigned FirstReg = 0;
372 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
373 EVT ValueVT = ValueVTs[Value];
374 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
376 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
377 for (unsigned i = 0; i != NumRegs; ++i) {
378 unsigned R = CreateReg(RegisterVT);
379 if (!FirstReg) FirstReg = R;
385 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
386 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
387 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
388 /// the larger bit width by zero extension. The bit width must be no smaller
389 /// than the LiveOutInfo's existing bit width.
390 const FunctionLoweringInfo::LiveOutInfo *
391 FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) {
392 if (!LiveOutRegInfo.inBounds(Reg))
395 LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
399 if (BitWidth > LOI->Known.getBitWidth()) {
400 LOI->NumSignBits = 1;
401 LOI->Known = LOI->Known.zextOrTrunc(BitWidth);
407 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
408 /// register based on the LiveOutInfo of its operands.
409 void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
410 Type *Ty = PN->getType();
411 if (!Ty->isIntegerTy() || Ty->isVectorTy())
414 SmallVector<EVT, 1> ValueVTs;
415 ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
416 assert(ValueVTs.size() == 1 &&
417 "PHIs with non-vector integer types should have a single VT.");
418 EVT IntVT = ValueVTs[0];
420 if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
422 IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
423 unsigned BitWidth = IntVT.getSizeInBits();
425 unsigned DestReg = ValueMap[PN];
426 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
428 LiveOutRegInfo.grow(DestReg);
429 LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
431 Value *V = PN->getIncomingValue(0);
432 if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
433 DestLOI.NumSignBits = 1;
434 DestLOI.Known = KnownBits(BitWidth);
438 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
439 APInt Val = CI->getValue().zextOrTrunc(BitWidth);
440 DestLOI.NumSignBits = Val.getNumSignBits();
441 DestLOI.Known.Zero = ~Val;
442 DestLOI.Known.One = Val;
444 assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
445 "CopyToReg node was created.");
446 unsigned SrcReg = ValueMap[V];
447 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
448 DestLOI.IsValid = false;
451 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
453 DestLOI.IsValid = false;
459 assert(DestLOI.Known.Zero.getBitWidth() == BitWidth &&
460 DestLOI.Known.One.getBitWidth() == BitWidth &&
461 "Masks should have the same bit width as the type.");
463 for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
464 Value *V = PN->getIncomingValue(i);
465 if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
466 DestLOI.NumSignBits = 1;
467 DestLOI.Known = KnownBits(BitWidth);
471 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
472 APInt Val = CI->getValue().zextOrTrunc(BitWidth);
473 DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
474 DestLOI.Known.Zero &= ~Val;
475 DestLOI.Known.One &= Val;
479 assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
480 "its CopyToReg node was created.");
481 unsigned SrcReg = ValueMap[V];
482 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
483 DestLOI.IsValid = false;
486 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
488 DestLOI.IsValid = false;
491 DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
492 DestLOI.Known.Zero &= SrcLOI->Known.Zero;
493 DestLOI.Known.One &= SrcLOI->Known.One;
497 /// setArgumentFrameIndex - Record frame index for the byval
498 /// argument. This overrides previous frame index entry for this argument,
500 void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
502 ByValArgFrameIndexMap[A] = FI;
505 /// getArgumentFrameIndex - Get frame index for the byval argument.
506 /// If the argument does not have any assigned frame index then 0 is
508 int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
509 auto I = ByValArgFrameIndexMap.find(A);
510 if (I != ByValArgFrameIndexMap.end())
512 LLVM_DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
516 unsigned FunctionLoweringInfo::getCatchPadExceptionPointerVReg(
517 const Value *CPI, const TargetRegisterClass *RC) {
518 MachineRegisterInfo &MRI = MF->getRegInfo();
519 auto I = CatchPadExceptionPointers.insert({CPI, 0});
520 unsigned &VReg = I.first->second;
522 VReg = MRI.createVirtualRegister(RC);
523 assert(VReg && "null vreg in exception pointer table!");
528 FunctionLoweringInfo::getOrCreateSwiftErrorVReg(const MachineBasicBlock *MBB,
530 auto Key = std::make_pair(MBB, Val);
531 auto It = SwiftErrorVRegDefMap.find(Key);
532 // If this is the first use of this swifterror value in this basic block,
533 // create a new virtual register.
534 // After we processed all basic blocks we will satisfy this "upwards exposed
535 // use" by inserting a copy or phi at the beginning of this block.
536 if (It == SwiftErrorVRegDefMap.end()) {
537 auto &DL = MF->getDataLayout();
538 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
539 auto VReg = MF->getRegInfo().createVirtualRegister(RC);
540 SwiftErrorVRegDefMap[Key] = VReg;
541 SwiftErrorVRegUpwardsUse[Key] = VReg;
543 } else return It->second;
546 void FunctionLoweringInfo::setCurrentSwiftErrorVReg(
547 const MachineBasicBlock *MBB, const Value *Val, unsigned VReg) {
548 SwiftErrorVRegDefMap[std::make_pair(MBB, Val)] = VReg;
551 std::pair<unsigned, bool>
552 FunctionLoweringInfo::getOrCreateSwiftErrorVRegDefAt(const Instruction *I) {
553 auto Key = PointerIntPair<const Instruction *, 1, bool>(I, true);
554 auto It = SwiftErrorVRegDefUses.find(Key);
555 if (It == SwiftErrorVRegDefUses.end()) {
556 auto &DL = MF->getDataLayout();
557 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
558 unsigned VReg = MF->getRegInfo().createVirtualRegister(RC);
559 SwiftErrorVRegDefUses[Key] = VReg;
560 return std::make_pair(VReg, true);
562 return std::make_pair(It->second, false);
565 std::pair<unsigned, bool>
566 FunctionLoweringInfo::getOrCreateSwiftErrorVRegUseAt(const Instruction *I, const MachineBasicBlock *MBB, const Value *Val) {
567 auto Key = PointerIntPair<const Instruction *, 1, bool>(I, false);
568 auto It = SwiftErrorVRegDefUses.find(Key);
569 if (It == SwiftErrorVRegDefUses.end()) {
570 unsigned VReg = getOrCreateSwiftErrorVReg(MBB, Val);
571 SwiftErrorVRegDefUses[Key] = VReg;
572 return std::make_pair(VReg, true);
574 return std::make_pair(It->second, false);
578 FunctionLoweringInfo::getValueFromVirtualReg(unsigned Vreg) {
579 if (VirtReg2Value.empty()) {
580 for (auto &P : ValueMap) {
581 VirtReg2Value[P.second] = P.first;
584 return VirtReg2Value[Vreg];