1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the Emit routines for the SelectionDAG class, which creates
11 // MachineInstrs based on the decisions of the SelectionDAG instruction
14 //===----------------------------------------------------------------------===//
16 #include "InstrEmitter.h"
17 #include "SDNodeDbgValue.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/StackMaps.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetSubtargetInfo.h"
33 #define DEBUG_TYPE "instr-emitter"
35 /// MinRCSize - Smallest register class we allow when constraining virtual
36 /// registers. If satisfying all register class constraints would require
37 /// using a smaller register class, emit a COPY to a new virtual register
39 const unsigned MinRCSize = 4;
41 /// CountResults - The results of target nodes have register or immediate
42 /// operands first, then an optional chain, and optional glue operands (which do
43 /// not go into the resulting MachineInstr).
44 unsigned InstrEmitter::CountResults(SDNode *Node) {
45 unsigned N = Node->getNumValues();
46 while (N && Node->getValueType(N - 1) == MVT::Glue)
48 if (N && Node->getValueType(N - 1) == MVT::Other)
49 --N; // Skip over chain result.
53 /// countOperands - The inputs to target nodes have any actual inputs first,
54 /// followed by an optional chain operand, then an optional glue operand.
55 /// Compute the number of actual operands that will go into the resulting
58 /// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
59 /// the chain and glue. These operands may be implicit on the machine instr.
60 static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
61 unsigned &NumImpUses) {
62 unsigned N = Node->getNumOperands();
63 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
65 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
66 --N; // Ignore chain if it exists.
68 // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
69 NumImpUses = N - NumExpUses;
70 for (unsigned I = N; I > NumExpUses; --I) {
71 if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
73 if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
74 if (TargetRegisterInfo::isPhysicalRegister(RN->getReg()))
83 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
84 /// implicit physical register output.
86 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
87 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
89 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
90 // Just use the input register directly!
91 SDValue Op(Node, ResNo);
94 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
95 (void)isNew; // Silence compiler warning.
96 assert(isNew && "Node emitted out of order - early");
100 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
101 // the CopyToReg'd destination register instead of creating a new vreg.
102 bool MatchReg = true;
103 const TargetRegisterClass *UseRC = nullptr;
104 MVT VT = Node->getSimpleValueType(ResNo);
106 // Stick to the preferred register classes for legal types.
107 if (TLI->isTypeLegal(VT))
108 UseRC = TLI->getRegClassFor(VT);
110 if (!IsClone && !IsCloned)
111 for (SDNode *User : Node->uses()) {
113 if (User->getOpcode() == ISD::CopyToReg &&
114 User->getOperand(2).getNode() == Node &&
115 User->getOperand(2).getResNo() == ResNo) {
116 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
117 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
120 } else if (DestReg != SrcReg)
123 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
124 SDValue Op = User->getOperand(i);
125 if (Op.getNode() != Node || Op.getResNo() != ResNo)
127 MVT VT = Node->getSimpleValueType(Op.getResNo());
128 if (VT == MVT::Other || VT == MVT::Glue)
131 if (User->isMachineOpcode()) {
132 const MCInstrDesc &II = TII->get(User->getMachineOpcode());
133 const TargetRegisterClass *RC = nullptr;
134 if (i+II.getNumDefs() < II.getNumOperands()) {
135 RC = TRI->getAllocatableClass(
136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
141 const TargetRegisterClass *ComRC =
142 TRI->getCommonSubClass(UseRC, RC);
143 // If multiple uses expect disjoint register classes, we emit
144 // copies in AddRegisterOperand.
156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
159 // Figure out the register class to create for the destreg.
161 DstRC = MRI->getRegClass(VRBase);
163 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
166 DstRC = TLI->getRegClassFor(VT);
169 // If all uses are reading from the src physical register and copying the
170 // register is either impossible or very expensive, then don't create a copy.
171 if (MatchReg && SrcRC->getCopyCost() < 0) {
174 // Create the reg, emit the copy.
175 VRBase = MRI->createVirtualRegister(DstRC);
176 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
177 VRBase).addReg(SrcReg);
180 SDValue Op(Node, ResNo);
183 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
184 (void)isNew; // Silence compiler warning.
185 assert(isNew && "Node emitted out of order - early");
188 /// getDstOfCopyToRegUse - If the only use of the specified result number of
189 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
190 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
191 unsigned ResNo) const {
192 if (!Node->hasOneUse())
195 SDNode *User = *Node->use_begin();
196 if (User->getOpcode() == ISD::CopyToReg &&
197 User->getOperand(2).getNode() == Node &&
198 User->getOperand(2).getResNo() == ResNo) {
199 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
200 if (TargetRegisterInfo::isVirtualRegister(Reg))
206 void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
207 MachineInstrBuilder &MIB,
208 const MCInstrDesc &II,
209 bool IsClone, bool IsCloned,
210 DenseMap<SDValue, unsigned> &VRBaseMap) {
211 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
212 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
214 unsigned NumResults = CountResults(Node);
215 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
216 // If the specific node value is only used by a CopyToReg and the dest reg
217 // is a vreg in the same register class, use the CopyToReg'd destination
218 // register instead of creating a new vreg.
220 const TargetRegisterClass *RC =
221 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
222 // Always let the value type influence the used register class. The
223 // constraints on the instruction may be too lax to represent the value
224 // type correctly. For example, a 64-bit float (X86::FR64) can't live in
225 // the 32-bit float super-class (X86::FR32).
226 if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
227 const TargetRegisterClass *VTRC =
228 TLI->getRegClassFor(Node->getSimpleValueType(i));
230 VTRC = TRI->getCommonSubClass(RC, VTRC);
235 if (II.OpInfo[i].isOptionalDef()) {
236 // Optional def must be a physical register.
237 unsigned NumResults = CountResults(Node);
238 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
239 assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
240 MIB.addReg(VRBase, RegState::Define);
243 if (!VRBase && !IsClone && !IsCloned)
244 for (SDNode *User : Node->uses()) {
245 if (User->getOpcode() == ISD::CopyToReg &&
246 User->getOperand(2).getNode() == Node &&
247 User->getOperand(2).getResNo() == i) {
248 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
249 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
250 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
253 MIB.addReg(VRBase, RegState::Define);
260 // Create the result registers for this node and add the result regs to
261 // the machine instruction.
263 assert(RC && "Isn't a register operand!");
264 VRBase = MRI->createVirtualRegister(RC);
265 MIB.addReg(VRBase, RegState::Define);
268 // If this def corresponds to a result of the SDNode insert the VRBase into
270 if (i < NumResults) {
274 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
275 (void)isNew; // Silence compiler warning.
276 assert(isNew && "Node emitted out of order - early");
281 /// getVR - Return the virtual register corresponding to the specified result
282 /// of the specified node.
283 unsigned InstrEmitter::getVR(SDValue Op,
284 DenseMap<SDValue, unsigned> &VRBaseMap) {
285 if (Op.isMachineOpcode() &&
286 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
287 // Add an IMPLICIT_DEF instruction before every use.
288 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
289 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
290 // does not include operand register class info.
292 const TargetRegisterClass *RC =
293 TLI->getRegClassFor(Op.getSimpleValueType());
294 VReg = MRI->createVirtualRegister(RC);
296 BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
297 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
301 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
302 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
307 /// AddRegisterOperand - Add the specified register as an operand to the
308 /// specified machine instr. Insert register copies if the register is
309 /// not in the required register class.
311 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
314 const MCInstrDesc *II,
315 DenseMap<SDValue, unsigned> &VRBaseMap,
316 bool IsDebug, bool IsClone, bool IsCloned) {
317 assert(Op.getValueType() != MVT::Other &&
318 Op.getValueType() != MVT::Glue &&
319 "Chain and glue operands should occur at end of operand list!");
320 // Get/emit the operand.
321 unsigned VReg = getVR(Op, VRBaseMap);
322 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
324 const MCInstrDesc &MCID = MIB->getDesc();
325 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
326 MCID.OpInfo[IIOpNum].isOptionalDef();
328 // If the instruction requires a register in a different class, create
329 // a new virtual register and copy the value into it, but first attempt to
330 // shrink VReg's register class within reason. For example, if VReg == GR32
331 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
333 const TargetRegisterClass *DstRC = nullptr;
334 if (IIOpNum < II->getNumOperands())
335 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
336 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
337 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
338 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
339 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
344 // If this value has only one use, that use is a kill. This is a
345 // conservative approximation. InstrEmitter does trivial coalescing
346 // with CopyFromReg nodes, so don't emit kill flags for them.
347 // Avoid kill flags on Schedule cloned nodes, since there will be
349 // Tied operands are never killed, so we need to check that. And that
350 // means we need to determine the index of the operand.
351 bool isKill = Op.hasOneUse() &&
352 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
354 !(IsClone || IsCloned);
356 unsigned Idx = MIB->getNumOperands();
358 MIB->getOperand(Idx-1).isReg() &&
359 MIB->getOperand(Idx-1).isImplicit())
361 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
366 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
367 getDebugRegState(IsDebug));
370 /// AddOperand - Add the specified operand to the specified machine instr. II
371 /// specifies the instruction information for the node, and IIOpNum is the
372 /// operand number (in the II) that we are adding.
373 void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
376 const MCInstrDesc *II,
377 DenseMap<SDValue, unsigned> &VRBaseMap,
378 bool IsDebug, bool IsClone, bool IsCloned) {
379 if (Op.isMachineOpcode()) {
380 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
381 IsDebug, IsClone, IsCloned);
382 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
383 MIB.addImm(C->getSExtValue());
384 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
385 MIB.addFPImm(F->getConstantFPValue());
386 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
387 // Turn additional physreg operands into implicit uses on non-variadic
388 // instructions. This is used by call and return instructions passing
389 // arguments in registers.
390 bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
391 MIB.addReg(R->getReg(), getImplRegState(Imp));
392 } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
393 MIB.addRegMask(RM->getRegMask());
394 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
395 MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
396 TGA->getTargetFlags());
397 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
398 MIB.addMBB(BBNode->getBasicBlock());
399 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
400 MIB.addFrameIndex(FI->getIndex());
401 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
402 MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
403 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
404 int Offset = CP->getOffset();
405 unsigned Align = CP->getAlignment();
406 Type *Type = CP->getType();
407 // MachineConstantPool wants an explicit alignment.
409 Align = MF->getSubtarget().getDataLayout()->getPrefTypeAlignment(Type);
411 // Alignment of vector types. FIXME!
412 Align = MF->getSubtarget().getDataLayout()->getTypeAllocSize(Type);
417 MachineConstantPool *MCP = MF->getConstantPool();
418 if (CP->isMachineConstantPoolEntry())
419 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
421 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
422 MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
423 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
424 MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
425 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
426 MIB.addBlockAddress(BA->getBlockAddress(),
428 BA->getTargetFlags());
429 } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
430 MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
432 assert(Op.getValueType() != MVT::Other &&
433 Op.getValueType() != MVT::Glue &&
434 "Chain and glue operands should occur at end of operand list!");
435 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
436 IsDebug, IsClone, IsCloned);
440 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
441 MVT VT, DebugLoc DL) {
442 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
443 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
445 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
448 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
450 // VReg has been adjusted. It can be used with SubIdx operands now.
454 // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
456 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx);
457 assert(RC && "No legal register class for VT supports that SubIdx");
458 unsigned NewReg = MRI->createVirtualRegister(RC);
459 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
464 /// EmitSubregNode - Generate machine code for subreg nodes.
466 void InstrEmitter::EmitSubregNode(SDNode *Node,
467 DenseMap<SDValue, unsigned> &VRBaseMap,
468 bool IsClone, bool IsCloned) {
470 unsigned Opc = Node->getMachineOpcode();
472 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
473 // the CopyToReg'd destination register instead of creating a new vreg.
474 for (SDNode *User : Node->uses()) {
475 if (User->getOpcode() == ISD::CopyToReg &&
476 User->getOperand(2).getNode() == Node) {
477 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
478 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
485 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
486 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
487 // constraints on the %dst register, COPY can target all legal register
489 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
490 const TargetRegisterClass *TRC =
491 TLI->getRegClassFor(Node->getSimpleValueType(0));
493 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
494 MachineInstr *DefMI = MRI->getVRegDef(VReg);
495 unsigned SrcReg, DstReg, DefSubIdx;
497 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
498 SubIdx == DefSubIdx &&
499 TRC == MRI->getRegClass(SrcReg)) {
501 // r1025 = s/zext r1024, 4
502 // r1026 = extract_subreg r1025, 4
504 // r1026 = copy r1024
505 VRBase = MRI->createVirtualRegister(TRC);
506 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
507 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
508 MRI->clearKillFlags(SrcReg);
510 // VReg may not support a SubIdx sub-register, and we may need to
511 // constrain its register class or issue a COPY to a compatible register
513 VReg = ConstrainForSubReg(VReg, SubIdx,
514 Node->getOperand(0).getSimpleValueType(),
515 Node->getDebugLoc());
517 // Create the destreg if it is missing.
519 VRBase = MRI->createVirtualRegister(TRC);
521 // Create the extract_subreg machine instruction.
522 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
523 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx);
525 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
526 Opc == TargetOpcode::SUBREG_TO_REG) {
527 SDValue N0 = Node->getOperand(0);
528 SDValue N1 = Node->getOperand(1);
529 SDValue N2 = Node->getOperand(2);
530 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
532 // Figure out the register class to create for the destreg. It should be
533 // the largest legal register class supporting SubIdx sub-registers.
534 // RegisterCoalescer will constrain it further if it decides to eliminate
535 // the INSERT_SUBREG instruction.
537 // %dst = INSERT_SUBREG %src, %sub, SubIdx
539 // is lowered by TwoAddressInstructionPass to:
542 // %dst:SubIdx = COPY %sub
544 // There is no constraint on the %src register class.
546 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0));
547 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
548 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
550 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
551 VRBase = MRI->createVirtualRegister(SRC);
553 // Create the insert_subreg or subreg_to_reg machine instruction.
554 MachineInstrBuilder MIB =
555 BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
557 // If creating a subreg_to_reg, then the first input operand
558 // is an implicit value immediate, otherwise it's a register
559 if (Opc == TargetOpcode::SUBREG_TO_REG) {
560 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
561 MIB.addImm(SD->getZExtValue());
563 AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
565 // Add the subregster being inserted
566 AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
569 MBB->insert(InsertPos, MIB);
571 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
574 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
575 (void)isNew; // Silence compiler warning.
576 assert(isNew && "Node emitted out of order - early");
579 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
580 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
581 /// register is constrained to be in a particular register class.
584 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
585 DenseMap<SDValue, unsigned> &VRBaseMap) {
586 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
588 // Create the new VReg in the destination class and emit a copy.
589 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
590 const TargetRegisterClass *DstRC =
591 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
592 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
593 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
594 NewVReg).addReg(VReg);
597 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
598 (void)isNew; // Silence compiler warning.
599 assert(isNew && "Node emitted out of order - early");
602 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
604 void InstrEmitter::EmitRegSequence(SDNode *Node,
605 DenseMap<SDValue, unsigned> &VRBaseMap,
606 bool IsClone, bool IsCloned) {
607 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
608 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
609 unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
610 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
611 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
612 unsigned NumOps = Node->getNumOperands();
613 assert((NumOps & 1) == 1 &&
614 "REG_SEQUENCE must have an odd number of operands!");
615 for (unsigned i = 1; i != NumOps; ++i) {
616 SDValue Op = Node->getOperand(i);
618 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
619 // Skip physical registers as they don't have a vreg to get and we'll
620 // insert copies for them in TwoAddressInstructionPass anyway.
621 if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
622 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
623 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
624 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
625 const TargetRegisterClass *SRC =
626 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
627 if (SRC && SRC != RC) {
628 MRI->setRegClass(NewVReg, SRC);
633 AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
637 MBB->insert(InsertPos, MIB);
639 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
640 (void)isNew; // Silence compiler warning.
641 assert(isNew && "Node emitted out of order - early");
644 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
647 InstrEmitter::EmitDbgValue(SDDbgValue *SD,
648 DenseMap<SDValue, unsigned> &VRBaseMap) {
649 uint64_t Offset = SD->getOffset();
650 MDNode *Var = SD->getVariable();
651 MDNode *Expr = SD->getExpression();
652 DebugLoc DL = SD->getDebugLoc();
654 if (SD->getKind() == SDDbgValue::FRAMEIX) {
655 // Stack address; this needs to be lowered in target-dependent fashion.
656 // EmitTargetCodeForFrameDebugValue is responsible for allocation.
657 return BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
658 .addFrameIndex(SD->getFrameIx())
663 // Otherwise, we're going to create an instruction here.
664 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
665 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
666 if (SD->getKind() == SDDbgValue::SDNODE) {
667 SDNode *Node = SD->getSDNode();
668 SDValue Op = SDValue(Node, SD->getResNo());
669 // It's possible we replaced this SDNode with other(s) and therefore
670 // didn't generate code for it. It's better to catch these cases where
671 // they happen and transfer the debug info, but trying to guarantee that
672 // in all cases would be very fragile; this is a safeguard for any
674 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
675 if (I==VRBaseMap.end())
676 MIB.addReg(0U); // undef
678 AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
679 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
680 } else if (SD->getKind() == SDDbgValue::CONST) {
681 const Value *V = SD->getConst();
682 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
683 if (CI->getBitWidth() > 64)
686 MIB.addImm(CI->getSExtValue());
687 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
690 // Could be an Undef. In any case insert an Undef so we can see what we
695 // Insert an Undef so we can see what we dropped.
699 // Indirect addressing is indicated by an Imm as the second parameter.
700 if (SD->isIndirect())
703 assert(Offset == 0 && "direct value cannot have an offset");
704 MIB.addReg(0U, RegState::Debug);
707 MIB.addMetadata(Var);
708 MIB.addMetadata(Expr);
713 /// EmitMachineNode - Generate machine code for a target-specific node and
714 /// needed dependencies.
717 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
718 DenseMap<SDValue, unsigned> &VRBaseMap) {
719 unsigned Opc = Node->getMachineOpcode();
721 // Handle subreg insert/extract specially
722 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
723 Opc == TargetOpcode::INSERT_SUBREG ||
724 Opc == TargetOpcode::SUBREG_TO_REG) {
725 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
729 // Handle COPY_TO_REGCLASS specially.
730 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
731 EmitCopyToRegClassNode(Node, VRBaseMap);
735 // Handle REG_SEQUENCE specially.
736 if (Opc == TargetOpcode::REG_SEQUENCE) {
737 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
741 if (Opc == TargetOpcode::IMPLICIT_DEF)
742 // We want a unique VR for each IMPLICIT_DEF use.
745 const MCInstrDesc &II = TII->get(Opc);
746 unsigned NumResults = CountResults(Node);
747 unsigned NumDefs = II.getNumDefs();
748 const MCPhysReg *ScratchRegs = nullptr;
750 // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
751 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
752 // Stackmaps do not have arguments and do not preserve their calling
753 // convention. However, to simplify runtime support, they clobber the same
754 // scratch registers as AnyRegCC.
755 unsigned CC = CallingConv::AnyReg;
756 if (Opc == TargetOpcode::PATCHPOINT) {
757 CC = Node->getConstantOperandVal(PatchPointOpers::CCPos);
758 NumDefs = NumResults;
760 ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
763 unsigned NumImpUses = 0;
764 unsigned NodeOperands =
765 countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
766 bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr;
768 unsigned NumMIOperands = NodeOperands + NumResults;
770 assert(NumMIOperands >= II.getNumOperands() &&
771 "Too few operands for a variadic node!");
773 assert(NumMIOperands >= II.getNumOperands() &&
774 NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
776 "#operands for dag node doesn't match .td file!");
779 // Create the new machine instruction.
780 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
782 // Add result register values for things that are defined by this
785 CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
787 // Emit all of the actual operands of this instruction, adding them to the
788 // instruction as appropriate.
789 bool HasOptPRefs = NumDefs > NumResults;
790 assert((!HasOptPRefs || !HasPhysRegOuts) &&
791 "Unable to cope with optional defs and phys regs defs!");
792 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
793 for (unsigned i = NumSkip; i != NodeOperands; ++i)
794 AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
795 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
797 // Add scratch registers as implicit def and early clobber
799 for (unsigned i = 0; ScratchRegs[i]; ++i)
800 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
801 RegState::EarlyClobber);
803 // Transfer all of the memory reference descriptions of this instruction.
804 MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
805 cast<MachineSDNode>(Node)->memoperands_end());
807 // Insert the instruction into position in the block. This needs to
808 // happen before any custom inserter hook is called so that the
809 // hook knows where in the block to insert the replacement code.
810 MBB->insert(InsertPos, MIB);
812 // The MachineInstr may also define physregs instead of virtregs. These
813 // physreg values can reach other instructions in different ways:
815 // 1. When there is a use of a Node value beyond the explicitly defined
816 // virtual registers, we emit a CopyFromReg for one of the implicitly
817 // defined physregs. This only happens when HasPhysRegOuts is true.
819 // 2. A CopyFromReg reading a physreg may be glued to this instruction.
821 // 3. A glued instruction may implicitly use a physreg.
823 // 4. A glued instruction may use a RegisterSDNode operand.
825 // Collect all the used physreg defs, and make sure that any unused physreg
826 // defs are marked as dead.
827 SmallVector<unsigned, 8> UsedRegs;
829 // Additional results must be physical register defs.
830 if (HasPhysRegOuts) {
831 for (unsigned i = NumDefs; i < NumResults; ++i) {
832 unsigned Reg = II.getImplicitDefs()[i - NumDefs];
833 if (!Node->hasAnyUseOfValue(i))
835 // This implicitly defined physreg has a use.
836 UsedRegs.push_back(Reg);
837 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
841 // Scan the glue chain for any used physregs.
842 if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
843 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
844 if (F->getOpcode() == ISD::CopyFromReg) {
845 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
847 } else if (F->getOpcode() == ISD::CopyToReg) {
848 // Skip CopyToReg nodes that are internal to the glue chain.
851 // Collect declared implicit uses.
852 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
853 UsedRegs.append(MCID.getImplicitUses(),
854 MCID.getImplicitUses() + MCID.getNumImplicitUses());
855 // In addition to declared implicit uses, we must also check for
856 // direct RegisterSDNode operands.
857 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
858 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
859 unsigned Reg = R->getReg();
860 if (TargetRegisterInfo::isPhysicalRegister(Reg))
861 UsedRegs.push_back(Reg);
866 // Finally mark unused registers as dead.
867 if (!UsedRegs.empty() || II.getImplicitDefs())
868 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
870 // Run post-isel target hook to adjust this instruction if needed.
871 if (II.hasPostISelHook())
872 TLI->AdjustInstrPostInstrSelection(MIB, Node);
875 /// EmitSpecialNode - Generate machine code for a target-independent node and
876 /// needed dependencies.
878 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
879 DenseMap<SDValue, unsigned> &VRBaseMap) {
880 switch (Node->getOpcode()) {
885 llvm_unreachable("This target-independent node should have been selected!");
886 case ISD::EntryToken:
887 llvm_unreachable("EntryToken should have been excluded from the schedule!");
888 case ISD::MERGE_VALUES:
889 case ISD::TokenFactor: // fall thru
891 case ISD::CopyToReg: {
893 SDValue SrcVal = Node->getOperand(2);
894 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
895 SrcReg = R->getReg();
897 SrcReg = getVR(SrcVal, VRBaseMap);
899 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
900 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
903 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
904 DestReg).addReg(SrcReg);
907 case ISD::CopyFromReg: {
908 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
909 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
912 case ISD::EH_LABEL: {
913 MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel();
914 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
915 TII->get(TargetOpcode::EH_LABEL)).addSym(S);
919 case ISD::LIFETIME_START:
920 case ISD::LIFETIME_END: {
921 unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
922 TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END;
924 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1));
925 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
926 .addFrameIndex(FI->getIndex());
930 case ISD::INLINEASM: {
931 unsigned NumOps = Node->getNumOperands();
932 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
933 --NumOps; // Ignore the glue operand.
935 // Create the inline asm machine instruction.
936 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(),
937 TII->get(TargetOpcode::INLINEASM));
939 // Add the asm string as an external symbol operand.
940 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
941 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
942 MIB.addExternalSymbol(AsmStr);
944 // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
947 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
949 MIB.addImm(ExtraInfo);
951 // Remember to operand index of the group flags.
952 SmallVector<unsigned, 8> GroupIdx;
954 // Add all of the operand registers to the instruction.
955 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
957 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
958 const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
960 GroupIdx.push_back(MIB->getNumOperands());
962 ++i; // Skip the ID value.
964 switch (InlineAsm::getKind(Flags)) {
965 default: llvm_unreachable("Bad flags!");
966 case InlineAsm::Kind_RegDef:
967 for (unsigned j = 0; j != NumVals; ++j, ++i) {
968 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
969 // FIXME: Add dead flags for physical and virtual registers defined.
970 // For now, mark physical register defs as implicit to help fast
971 // regalloc. This makes inline asm look a lot like calls.
972 MIB.addReg(Reg, RegState::Define |
973 getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
976 case InlineAsm::Kind_RegDefEarlyClobber:
977 case InlineAsm::Kind_Clobber:
978 for (unsigned j = 0; j != NumVals; ++j, ++i) {
979 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
980 MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber |
981 getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
984 case InlineAsm::Kind_RegUse: // Use of register.
985 case InlineAsm::Kind_Imm: // Immediate.
986 case InlineAsm::Kind_Mem: // Addressing mode.
987 // The addressing mode has been selected, just add all of the
988 // operands to the machine instruction.
989 for (unsigned j = 0; j != NumVals; ++j, ++i)
990 AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
991 /*IsDebug=*/false, IsClone, IsCloned);
993 // Manually set isTied bits.
994 if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
995 unsigned DefGroup = 0;
996 if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
997 unsigned DefIdx = GroupIdx[DefGroup] + 1;
998 unsigned UseIdx = GroupIdx.back() + 1;
999 for (unsigned j = 0; j != NumVals; ++j)
1000 MIB->tieOperands(DefIdx + j, UseIdx + j);
1007 // Get the mdnode from the asm if it exists and add it to the instruction.
1008 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
1009 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1011 MIB.addMetadata(MD);
1013 MBB->insert(InsertPos, MIB);
1019 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1020 /// at the given position in the given block.
1021 InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
1022 MachineBasicBlock::iterator insertpos)
1023 : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
1024 TII(MF->getSubtarget().getInstrInfo()),
1025 TRI(MF->getSubtarget().getRegisterInfo()),
1026 TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
1027 InsertPos(insertpos) {}