1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/ADT/SetVector.h"
15 #include "llvm/ADT/SmallPtrSet.h"
16 #include "llvm/ADT/SmallSet.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGNodes.h"
23 #include "llvm/IR/CallingConv.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/DebugInfo.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetSubtargetInfo.h"
40 #define DEBUG_TYPE "legalizedag"
44 struct FloatSignAsInt;
46 //===----------------------------------------------------------------------===//
47 /// This takes an arbitrary SelectionDAG as input and
48 /// hacks on it until the target machine can handle it. This involves
49 /// eliminating value sizes the machine cannot handle (promoting small sizes to
50 /// large sizes or splitting up large values into small values) as well as
51 /// eliminating operations the machine cannot handle.
53 /// This code also does a small amount of optimization and recognition of idioms
54 /// as part of its processing. For example, if a target does not support a
55 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
56 /// will attempt merge setcc and brc instructions into brcc's.
58 class SelectionDAGLegalize {
59 const TargetMachine &TM;
60 const TargetLowering &TLI;
63 /// \brief The set of nodes which have already been legalized. We hold a
64 /// reference to it in order to update as necessary on node deletion.
65 SmallPtrSetImpl<SDNode *> &LegalizedNodes;
67 /// \brief A set of all the nodes updated during legalization.
68 SmallSetVector<SDNode *, 16> *UpdatedNodes;
70 EVT getSetCCResultType(EVT VT) const {
71 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
74 // Libcall insertion helpers.
77 SelectionDAGLegalize(SelectionDAG &DAG,
78 SmallPtrSetImpl<SDNode *> &LegalizedNodes,
79 SmallSetVector<SDNode *, 16> *UpdatedNodes = nullptr)
80 : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
81 LegalizedNodes(LegalizedNodes), UpdatedNodes(UpdatedNodes) {}
83 /// \brief Legalizes the given operation.
84 void LegalizeOp(SDNode *Node);
87 SDValue OptimizeFloatStore(StoreSDNode *ST);
89 void LegalizeLoadOps(SDNode *Node);
90 void LegalizeStoreOps(SDNode *Node);
92 /// Some targets cannot handle a variable
93 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
94 /// is necessary to spill the vector being inserted into to memory, perform
95 /// the insert there, and then read the result back.
96 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
98 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx,
101 /// Return a vector shuffle operation which
102 /// performs the same shuffe in terms of order or result bytes, but on a type
103 /// whose vector element type is narrower than the original shuffle type.
104 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
105 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, const SDLoc &dl,
106 SDValue N1, SDValue N2,
107 ArrayRef<int> Mask) const;
109 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
110 bool &NeedInvert, const SDLoc &dl);
112 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
113 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
114 unsigned NumOps, bool isSigned, const SDLoc &dl);
116 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
117 SDNode *Node, bool isSigned);
118 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
119 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
120 RTLIB::Libcall Call_F128,
121 RTLIB::Libcall Call_PPCF128);
122 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
123 RTLIB::Libcall Call_I8,
124 RTLIB::Libcall Call_I16,
125 RTLIB::Libcall Call_I32,
126 RTLIB::Libcall Call_I64,
127 RTLIB::Libcall Call_I128);
128 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
129 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
131 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
133 SDValue ExpandBUILD_VECTOR(SDNode *Node);
134 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
135 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
136 SmallVectorImpl<SDValue> &Results);
137 void getSignAsIntValue(FloatSignAsInt &State, const SDLoc &DL,
138 SDValue Value) const;
139 SDValue modifySignAsInt(const FloatSignAsInt &State, const SDLoc &DL,
140 SDValue NewIntValue) const;
141 SDValue ExpandFCOPYSIGN(SDNode *Node) const;
142 SDValue ExpandFABS(SDNode *Node) const;
143 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
145 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
147 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
150 SDValue ExpandBITREVERSE(SDValue Op, const SDLoc &dl);
151 SDValue ExpandBSWAP(SDValue Op, const SDLoc &dl);
152 SDValue ExpandBitCount(unsigned Opc, SDValue Op, const SDLoc &dl);
154 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
155 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
156 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
158 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
159 SDValue ExpandConstant(ConstantSDNode *CP);
161 // if ExpandNode returns false, LegalizeOp falls back to ConvertNodeToLibcall
162 bool ExpandNode(SDNode *Node);
163 void ConvertNodeToLibcall(SDNode *Node);
164 void PromoteNode(SDNode *Node);
167 // Node replacement helpers
168 void ReplacedNode(SDNode *N) {
169 LegalizedNodes.erase(N);
171 UpdatedNodes->insert(N);
173 void ReplaceNode(SDNode *Old, SDNode *New) {
174 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
175 dbgs() << " with: "; New->dump(&DAG));
177 assert(Old->getNumValues() == New->getNumValues() &&
178 "Replacing one node with another that produces a different number "
180 DAG.ReplaceAllUsesWith(Old, New);
182 UpdatedNodes->insert(New);
185 void ReplaceNode(SDValue Old, SDValue New) {
186 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
187 dbgs() << " with: "; New->dump(&DAG));
189 DAG.ReplaceAllUsesWith(Old, New);
191 UpdatedNodes->insert(New.getNode());
192 ReplacedNode(Old.getNode());
194 void ReplaceNode(SDNode *Old, const SDValue *New) {
195 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG));
197 DAG.ReplaceAllUsesWith(Old, New);
198 for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
199 DEBUG(dbgs() << (i == 0 ? " with: "
203 UpdatedNodes->insert(New[i].getNode());
210 /// Return a vector shuffle operation which
211 /// performs the same shuffe in terms of order or result bytes, but on a type
212 /// whose vector element type is narrower than the original shuffle type.
213 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
214 SDValue SelectionDAGLegalize::ShuffleWithNarrowerEltType(
215 EVT NVT, EVT VT, const SDLoc &dl, SDValue N1, SDValue N2,
216 ArrayRef<int> Mask) const {
217 unsigned NumMaskElts = VT.getVectorNumElements();
218 unsigned NumDestElts = NVT.getVectorNumElements();
219 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
221 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
223 if (NumEltsGrowth == 1)
224 return DAG.getVectorShuffle(NVT, dl, N1, N2, Mask);
226 SmallVector<int, 8> NewMask;
227 for (unsigned i = 0; i != NumMaskElts; ++i) {
229 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
231 NewMask.push_back(-1);
233 NewMask.push_back(Idx * NumEltsGrowth + j);
236 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
237 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
238 return DAG.getVectorShuffle(NVT, dl, N1, N2, NewMask);
241 /// Expands the ConstantFP node to an integer constant or
242 /// a load from the constant pool.
244 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
248 // If a FP immediate is precise when represented as a float and if the
249 // target can do an extending load from float to double, we put it into
250 // the constant pool as a float, even if it's is statically typed as a
251 // double. This shrinks FP constants and canonicalizes them for targets where
252 // an FP extending load is the same cost as a normal load (such as on the x87
253 // fp stack or PPC FP unit).
254 EVT VT = CFP->getValueType(0);
255 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
257 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
258 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), dl,
259 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
262 APFloat APF = CFP->getValueAPF();
266 // We don't want to shrink SNaNs. Converting the SNaN back to its real type
267 // can cause it to be changed into a QNaN on some platforms (e.g. on SystemZ).
268 if (!APF.isSignaling()) {
269 while (SVT != MVT::f32 && SVT != MVT::f16) {
270 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
271 if (ConstantFPSDNode::isValueValidForType(SVT, APF) &&
272 // Only do this if the target has a native EXTLOAD instruction from
274 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
275 TLI.ShouldShrinkFPConstant(OrigVT)) {
276 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
277 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
285 DAG.getConstantPool(LLVMC, TLI.getPointerTy(DAG.getDataLayout()));
286 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
288 SDValue Result = DAG.getExtLoad(
289 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx,
290 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), VT,
294 SDValue Result = DAG.getLoad(
295 OrigVT, dl, DAG.getEntryNode(), CPIdx,
296 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), Alignment);
300 /// Expands the Constant node to a load from the constant pool.
301 SDValue SelectionDAGLegalize::ExpandConstant(ConstantSDNode *CP) {
303 EVT VT = CP->getValueType(0);
304 SDValue CPIdx = DAG.getConstantPool(CP->getConstantIntValue(),
305 TLI.getPointerTy(DAG.getDataLayout()));
306 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
307 SDValue Result = DAG.getLoad(
308 VT, dl, DAG.getEntryNode(), CPIdx,
309 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), Alignment);
313 /// Some target cannot handle a variable insertion index for the
314 /// INSERT_VECTOR_ELT instruction. In this case, it
315 /// is necessary to spill the vector being inserted into to memory, perform
316 /// the insert there, and then read the result back.
317 SDValue SelectionDAGLegalize::PerformInsertVectorEltInMemory(SDValue Vec,
325 // If the target doesn't support this, we have to spill the input vector
326 // to a temporary stack slot, update the element, then reload it. This is
327 // badness. We could also load the value into a vector register (either
328 // with a "move to register" or "extload into register" instruction, then
329 // permute it into place, if the idx is a constant and if the idx is
330 // supported by the target.
331 EVT VT = Tmp1.getValueType();
332 EVT EltVT = VT.getVectorElementType();
333 SDValue StackPtr = DAG.CreateStackTemporary(VT);
335 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
338 SDValue Ch = DAG.getStore(
339 DAG.getEntryNode(), dl, Tmp1, StackPtr,
340 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI));
342 SDValue StackPtr2 = TLI.getVectorElementPointer(DAG, StackPtr, VT, Tmp3);
344 // Store the scalar value.
345 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT);
346 // Load the updated vector.
347 return DAG.getLoad(VT, dl, Ch, StackPtr, MachinePointerInfo::getFixedStack(
348 DAG.getMachineFunction(), SPFI));
351 SDValue SelectionDAGLegalize::ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
354 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
355 // SCALAR_TO_VECTOR requires that the type of the value being inserted
356 // match the element type of the vector being created, except for
357 // integers in which case the inserted value can be over width.
358 EVT EltVT = Vec.getValueType().getVectorElementType();
359 if (Val.getValueType() == EltVT ||
360 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
361 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
362 Vec.getValueType(), Val);
364 unsigned NumElts = Vec.getValueType().getVectorNumElements();
365 // We generate a shuffle of InVec and ScVec, so the shuffle mask
366 // should be 0,1,2,3,4,5... with the appropriate element replaced with
368 SmallVector<int, 8> ShufOps;
369 for (unsigned i = 0; i != NumElts; ++i)
370 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
372 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, ShufOps);
375 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
378 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
379 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
380 // FIXME: We shouldn't do this for TargetConstantFP's.
381 // FIXME: move this to the DAG Combiner! Note that we can't regress due
382 // to phase ordering between legalized code and the dag combiner. This
383 // probably means that we need to integrate dag combiner and legalizer
385 // We generally can't do this one for long doubles.
386 SDValue Chain = ST->getChain();
387 SDValue Ptr = ST->getBasePtr();
388 unsigned Alignment = ST->getAlignment();
389 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
390 AAMDNodes AAInfo = ST->getAAInfo();
392 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
393 if (CFP->getValueType(0) == MVT::f32 &&
394 TLI.isTypeLegal(MVT::i32)) {
395 SDValue Con = DAG.getConstant(CFP->getValueAPF().
396 bitcastToAPInt().zextOrTrunc(32),
397 SDLoc(CFP), MVT::i32);
398 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(), Alignment,
402 if (CFP->getValueType(0) == MVT::f64) {
403 // If this target supports 64-bit registers, do a single 64-bit store.
404 if (TLI.isTypeLegal(MVT::i64)) {
405 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
406 zextOrTrunc(64), SDLoc(CFP), MVT::i64);
407 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
408 Alignment, MMOFlags, AAInfo);
411 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
412 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
413 // stores. If the target supports neither 32- nor 64-bits, this
414 // xform is certainly not worth it.
415 const APInt &IntVal = CFP->getValueAPF().bitcastToAPInt();
416 SDValue Lo = DAG.getConstant(IntVal.trunc(32), dl, MVT::i32);
417 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), dl, MVT::i32);
418 if (DAG.getDataLayout().isBigEndian())
421 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), Alignment,
423 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
424 DAG.getConstant(4, dl, Ptr.getValueType()));
425 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
426 ST->getPointerInfo().getWithOffset(4),
427 MinAlign(Alignment, 4U), MMOFlags, AAInfo);
429 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
433 return SDValue(nullptr, 0);
436 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
437 StoreSDNode *ST = cast<StoreSDNode>(Node);
438 SDValue Chain = ST->getChain();
439 SDValue Ptr = ST->getBasePtr();
442 unsigned Alignment = ST->getAlignment();
443 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
444 AAMDNodes AAInfo = ST->getAAInfo();
446 if (!ST->isTruncatingStore()) {
447 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
448 ReplaceNode(ST, OptStore);
453 SDValue Value = ST->getValue();
454 MVT VT = Value.getSimpleValueType();
455 switch (TLI.getOperationAction(ISD::STORE, VT)) {
456 default: llvm_unreachable("This action is not supported yet!");
457 case TargetLowering::Legal: {
458 // If this is an unaligned store and the target doesn't support it,
460 EVT MemVT = ST->getMemoryVT();
461 unsigned AS = ST->getAddressSpace();
462 unsigned Align = ST->getAlignment();
463 const DataLayout &DL = DAG.getDataLayout();
464 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
465 SDValue Result = TLI.expandUnalignedStore(ST, DAG);
466 ReplaceNode(SDValue(ST, 0), Result);
470 case TargetLowering::Custom: {
471 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
472 if (Res && Res != SDValue(Node, 0))
473 ReplaceNode(SDValue(Node, 0), Res);
476 case TargetLowering::Promote: {
477 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
478 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
479 "Can only promote stores to same size type");
480 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
482 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
483 Alignment, MMOFlags, AAInfo);
484 ReplaceNode(SDValue(Node, 0), Result);
491 SDValue Value = ST->getValue();
493 EVT StVT = ST->getMemoryVT();
494 unsigned StWidth = StVT.getSizeInBits();
495 auto &DL = DAG.getDataLayout();
497 if (StWidth != StVT.getStoreSizeInBits()) {
498 // Promote to a byte-sized store with upper bits zero if not
499 // storing an integral number of bytes. For example, promote
500 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
501 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
502 StVT.getStoreSizeInBits());
503 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
505 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), NVT,
506 Alignment, MMOFlags, AAInfo);
507 ReplaceNode(SDValue(Node, 0), Result);
508 } else if (StWidth & (StWidth - 1)) {
509 // If not storing a power-of-2 number of bits, expand as two stores.
510 assert(!StVT.isVector() && "Unsupported truncstore!");
511 unsigned RoundWidth = 1 << Log2_32(StWidth);
512 assert(RoundWidth < StWidth);
513 unsigned ExtraWidth = StWidth - RoundWidth;
514 assert(ExtraWidth < RoundWidth);
515 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
516 "Store size not an integral number of bytes!");
517 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
518 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
520 unsigned IncrementSize;
522 if (DL.isLittleEndian()) {
523 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
524 // Store the bottom RoundWidth bits.
525 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
526 RoundVT, Alignment, MMOFlags, AAInfo);
528 // Store the remaining ExtraWidth bits.
529 IncrementSize = RoundWidth / 8;
530 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
531 DAG.getConstant(IncrementSize, dl,
532 Ptr.getValueType()));
534 ISD::SRL, dl, Value.getValueType(), Value,
535 DAG.getConstant(RoundWidth, dl,
536 TLI.getShiftAmountTy(Value.getValueType(), DL)));
537 Hi = DAG.getTruncStore(
539 ST->getPointerInfo().getWithOffset(IncrementSize), ExtraVT,
540 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
542 // Big endian - avoid unaligned stores.
543 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
544 // Store the top RoundWidth bits.
546 ISD::SRL, dl, Value.getValueType(), Value,
547 DAG.getConstant(ExtraWidth, dl,
548 TLI.getShiftAmountTy(Value.getValueType(), DL)));
549 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
550 RoundVT, Alignment, MMOFlags, AAInfo);
552 // Store the remaining ExtraWidth bits.
553 IncrementSize = RoundWidth / 8;
554 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
555 DAG.getConstant(IncrementSize, dl,
556 Ptr.getValueType()));
557 Lo = DAG.getTruncStore(
558 Chain, dl, Value, Ptr,
559 ST->getPointerInfo().getWithOffset(IncrementSize), ExtraVT,
560 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
563 // The order of the stores doesn't matter.
564 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
565 ReplaceNode(SDValue(Node, 0), Result);
567 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
568 default: llvm_unreachable("This action is not supported yet!");
569 case TargetLowering::Legal: {
570 EVT MemVT = ST->getMemoryVT();
571 unsigned AS = ST->getAddressSpace();
572 unsigned Align = ST->getAlignment();
573 // If this is an unaligned store and the target doesn't support it,
575 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
576 SDValue Result = TLI.expandUnalignedStore(ST, DAG);
577 ReplaceNode(SDValue(ST, 0), Result);
581 case TargetLowering::Custom: {
582 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
583 if (Res && Res != SDValue(Node, 0))
584 ReplaceNode(SDValue(Node, 0), Res);
587 case TargetLowering::Expand:
588 assert(!StVT.isVector() &&
589 "Vector Stores are handled in LegalizeVectorOps");
591 // TRUNCSTORE:i16 i32 -> STORE i16
592 assert(TLI.isTypeLegal(StVT) &&
593 "Do not know how to expand this store!");
594 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
596 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
597 Alignment, MMOFlags, AAInfo);
598 ReplaceNode(SDValue(Node, 0), Result);
605 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
606 LoadSDNode *LD = cast<LoadSDNode>(Node);
607 SDValue Chain = LD->getChain(); // The chain.
608 SDValue Ptr = LD->getBasePtr(); // The base pointer.
609 SDValue Value; // The value returned by the load op.
612 ISD::LoadExtType ExtType = LD->getExtensionType();
613 if (ExtType == ISD::NON_EXTLOAD) {
614 MVT VT = Node->getSimpleValueType(0);
615 SDValue RVal = SDValue(Node, 0);
616 SDValue RChain = SDValue(Node, 1);
618 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
619 default: llvm_unreachable("This action is not supported yet!");
620 case TargetLowering::Legal: {
621 EVT MemVT = LD->getMemoryVT();
622 unsigned AS = LD->getAddressSpace();
623 unsigned Align = LD->getAlignment();
624 const DataLayout &DL = DAG.getDataLayout();
625 // If this is an unaligned load and the target doesn't support it,
627 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
628 std::tie(RVal, RChain) = TLI.expandUnalignedLoad(LD, DAG);
632 case TargetLowering::Custom: {
633 if (SDValue Res = TLI.LowerOperation(RVal, DAG)) {
635 RChain = Res.getValue(1);
639 case TargetLowering::Promote: {
640 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
641 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
642 "Can only promote loads to same size type");
644 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
645 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
646 RChain = Res.getValue(1);
650 if (RChain.getNode() != Node) {
651 assert(RVal.getNode() != Node && "Load must be completely replaced");
652 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
653 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
655 UpdatedNodes->insert(RVal.getNode());
656 UpdatedNodes->insert(RChain.getNode());
663 EVT SrcVT = LD->getMemoryVT();
664 unsigned SrcWidth = SrcVT.getSizeInBits();
665 unsigned Alignment = LD->getAlignment();
666 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
667 AAMDNodes AAInfo = LD->getAAInfo();
669 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
670 // Some targets pretend to have an i1 loading operation, and actually
671 // load an i8. This trick is correct for ZEXTLOAD because the top 7
672 // bits are guaranteed to be zero; it helps the optimizers understand
673 // that these bits are zero. It is also useful for EXTLOAD, since it
674 // tells the optimizers that those bits are undefined. It would be
675 // nice to have an effective generic way of getting these benefits...
676 // Until such a way is found, don't insist on promoting i1 here.
678 TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) ==
679 TargetLowering::Promote)) {
680 // Promote to a byte-sized load if not loading an integral number of
681 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
682 unsigned NewWidth = SrcVT.getStoreSizeInBits();
683 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
686 // The extra bits are guaranteed to be zero, since we stored them that
687 // way. A zext load from NVT thus automatically gives zext from SrcVT.
689 ISD::LoadExtType NewExtType =
690 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
693 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), Chain, Ptr,
694 LD->getPointerInfo(), NVT, Alignment, MMOFlags, AAInfo);
696 Ch = Result.getValue(1); // The chain.
698 if (ExtType == ISD::SEXTLOAD)
699 // Having the top bits zero doesn't help when sign extending.
700 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
701 Result.getValueType(),
702 Result, DAG.getValueType(SrcVT));
703 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
704 // All the top bits are guaranteed to be zero - inform the optimizers.
705 Result = DAG.getNode(ISD::AssertZext, dl,
706 Result.getValueType(), Result,
707 DAG.getValueType(SrcVT));
711 } else if (SrcWidth & (SrcWidth - 1)) {
712 // If not loading a power-of-2 number of bits, expand as two loads.
713 assert(!SrcVT.isVector() && "Unsupported extload!");
714 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
715 assert(RoundWidth < SrcWidth);
716 unsigned ExtraWidth = SrcWidth - RoundWidth;
717 assert(ExtraWidth < RoundWidth);
718 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
719 "Load size not an integral number of bytes!");
720 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
721 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
723 unsigned IncrementSize;
724 auto &DL = DAG.getDataLayout();
726 if (DL.isLittleEndian()) {
727 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
728 // Load the bottom RoundWidth bits.
729 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
730 LD->getPointerInfo(), RoundVT, Alignment, MMOFlags,
733 // Load the remaining ExtraWidth bits.
734 IncrementSize = RoundWidth / 8;
735 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
736 DAG.getConstant(IncrementSize, dl,
737 Ptr.getValueType()));
738 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
739 LD->getPointerInfo().getWithOffset(IncrementSize),
740 ExtraVT, MinAlign(Alignment, IncrementSize), MMOFlags,
743 // Build a factor node to remember that this load is independent of
745 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
748 // Move the top bits to the right place.
750 ISD::SHL, dl, Hi.getValueType(), Hi,
751 DAG.getConstant(RoundWidth, dl,
752 TLI.getShiftAmountTy(Hi.getValueType(), DL)));
754 // Join the hi and lo parts.
755 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
757 // Big endian - avoid unaligned loads.
758 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
759 // Load the top RoundWidth bits.
760 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
761 LD->getPointerInfo(), RoundVT, Alignment, MMOFlags,
764 // Load the remaining ExtraWidth bits.
765 IncrementSize = RoundWidth / 8;
766 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
767 DAG.getConstant(IncrementSize, dl,
768 Ptr.getValueType()));
769 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
770 LD->getPointerInfo().getWithOffset(IncrementSize),
771 ExtraVT, MinAlign(Alignment, IncrementSize), MMOFlags,
774 // Build a factor node to remember that this load is independent of
776 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
779 // Move the top bits to the right place.
781 ISD::SHL, dl, Hi.getValueType(), Hi,
782 DAG.getConstant(ExtraWidth, dl,
783 TLI.getShiftAmountTy(Hi.getValueType(), DL)));
785 // Join the hi and lo parts.
786 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
791 bool isCustom = false;
792 switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0),
793 SrcVT.getSimpleVT())) {
794 default: llvm_unreachable("This action is not supported yet!");
795 case TargetLowering::Custom:
798 case TargetLowering::Legal: {
799 Value = SDValue(Node, 0);
800 Chain = SDValue(Node, 1);
803 if (SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG)) {
805 Chain = Res.getValue(1);
808 // If this is an unaligned load and the target doesn't support it,
810 EVT MemVT = LD->getMemoryVT();
811 unsigned AS = LD->getAddressSpace();
812 unsigned Align = LD->getAlignment();
813 const DataLayout &DL = DAG.getDataLayout();
814 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
815 std::tie(Value, Chain) = TLI.expandUnalignedLoad(LD, DAG);
820 case TargetLowering::Expand:
821 EVT DestVT = Node->getValueType(0);
822 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) {
823 // If the source type is not legal, see if there is a legal extload to
824 // an intermediate type that we can then extend further.
825 EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT());
826 if (TLI.isTypeLegal(SrcVT) || // Same as SrcVT == LoadVT?
827 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) {
828 // If we are loading a legal type, this is a non-extload followed by a
830 ISD::LoadExtType MidExtType =
831 (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
833 SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr,
834 SrcVT, LD->getMemOperand());
836 ISD::getExtForLoadExtType(SrcVT.isFloatingPoint(), ExtType);
837 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
838 Chain = Load.getValue(1);
842 // Handle the special case of fp16 extloads. EXTLOAD doesn't have the
843 // normal undefined upper bits behavior to allow using an in-reg extend
844 // with the illegal FP type, so load as an integer and do the
845 // from-integer conversion.
846 if (SrcVT.getScalarType() == MVT::f16) {
847 EVT ISrcVT = SrcVT.changeTypeToInteger();
848 EVT IDestVT = DestVT.changeTypeToInteger();
849 EVT LoadVT = TLI.getRegisterType(IDestVT.getSimpleVT());
851 SDValue Result = DAG.getExtLoad(ISD::ZEXTLOAD, dl, LoadVT,
853 LD->getMemOperand());
854 Value = DAG.getNode(ISD::FP16_TO_FP, dl, DestVT, Result);
855 Chain = Result.getValue(1);
860 assert(!SrcVT.isVector() &&
861 "Vector Loads are handled in LegalizeVectorOps");
863 // FIXME: This does not work for vectors on most targets. Sign-
864 // and zero-extend operations are currently folded into extending
865 // loads, whether they are legal or not, and then we end up here
866 // without any support for legalizing them.
867 assert(ExtType != ISD::EXTLOAD &&
868 "EXTLOAD should always be supported!");
869 // Turn the unsupported load into an EXTLOAD followed by an
870 // explicit zero/sign extend inreg.
871 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
872 Node->getValueType(0),
874 LD->getMemOperand());
876 if (ExtType == ISD::SEXTLOAD)
877 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
878 Result.getValueType(),
879 Result, DAG.getValueType(SrcVT));
881 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
883 Chain = Result.getValue(1);
888 // Since loads produce two values, make sure to remember that we legalized
890 if (Chain.getNode() != Node) {
891 assert(Value.getNode() != Node && "Load must be completely replaced");
892 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
893 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
895 UpdatedNodes->insert(Value.getNode());
896 UpdatedNodes->insert(Chain.getNode());
902 static TargetLowering::LegalizeAction
903 getStrictFPOpcodeAction(const TargetLowering &TLI, unsigned Opcode, EVT VT) {
906 default: llvm_unreachable("Unexpected FP pseudo-opcode");
907 case ISD::STRICT_FSQRT: EqOpc = ISD::FSQRT; break;
908 case ISD::STRICT_FPOW: EqOpc = ISD::FPOW; break;
909 case ISD::STRICT_FPOWI: EqOpc = ISD::FPOWI; break;
910 case ISD::STRICT_FSIN: EqOpc = ISD::FSIN; break;
911 case ISD::STRICT_FCOS: EqOpc = ISD::FCOS; break;
912 case ISD::STRICT_FEXP: EqOpc = ISD::FEXP; break;
913 case ISD::STRICT_FEXP2: EqOpc = ISD::FEXP2; break;
914 case ISD::STRICT_FLOG: EqOpc = ISD::FLOG; break;
915 case ISD::STRICT_FLOG10: EqOpc = ISD::FLOG10; break;
916 case ISD::STRICT_FLOG2: EqOpc = ISD::FLOG2; break;
917 case ISD::STRICT_FRINT: EqOpc = ISD::FRINT; break;
918 case ISD::STRICT_FNEARBYINT: EqOpc = ISD::FNEARBYINT; break;
921 auto Action = TLI.getOperationAction(EqOpc, VT);
923 // We don't currently handle Custom or Promote for strict FP pseudo-ops.
924 // For now, we just expand for those cases.
925 if (Action != TargetLowering::Legal)
926 Action = TargetLowering::Expand;
931 /// Return a legal replacement for the given operation, with all legal operands.
932 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
933 DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
935 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
939 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
940 assert((TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
941 TargetLowering::TypeLegal ||
942 TLI.isTypeLegal(Node->getValueType(i))) &&
943 "Unexpected illegal type!");
945 for (const SDValue &Op : Node->op_values())
946 assert((TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) ==
947 TargetLowering::TypeLegal ||
948 TLI.isTypeLegal(Op.getValueType()) ||
949 Op.getOpcode() == ISD::TargetConstant) &&
950 "Unexpected illegal type!");
953 // Figure out the correct action; the way to query this varies by opcode
954 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
955 bool SimpleFinishLegalizing = true;
956 switch (Node->getOpcode()) {
957 case ISD::INTRINSIC_W_CHAIN:
958 case ISD::INTRINSIC_WO_CHAIN:
959 case ISD::INTRINSIC_VOID:
961 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
963 case ISD::GET_DYNAMIC_AREA_OFFSET:
964 Action = TLI.getOperationAction(Node->getOpcode(),
965 Node->getValueType(0));
968 Action = TLI.getOperationAction(Node->getOpcode(),
969 Node->getValueType(0));
970 if (Action != TargetLowering::Promote)
971 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
973 case ISD::FP_TO_FP16:
974 case ISD::SINT_TO_FP:
975 case ISD::UINT_TO_FP:
976 case ISD::EXTRACT_VECTOR_ELT:
977 Action = TLI.getOperationAction(Node->getOpcode(),
978 Node->getOperand(0).getValueType());
980 case ISD::FP_ROUND_INREG:
981 case ISD::SIGN_EXTEND_INREG: {
982 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
983 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
986 case ISD::ATOMIC_STORE: {
987 Action = TLI.getOperationAction(Node->getOpcode(),
988 Node->getOperand(2).getValueType());
994 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
995 Node->getOpcode() == ISD::SETCC ? 2 :
996 Node->getOpcode() == ISD::SETCCE ? 3 : 1;
997 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
998 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
999 ISD::CondCode CCCode =
1000 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1001 Action = TLI.getCondCodeAction(CCCode, OpVT);
1002 if (Action == TargetLowering::Legal) {
1003 if (Node->getOpcode() == ISD::SELECT_CC)
1004 Action = TLI.getOperationAction(Node->getOpcode(),
1005 Node->getValueType(0));
1007 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1013 // FIXME: Model these properly. LOAD and STORE are complicated, and
1014 // STORE expects the unlegalized operand in some cases.
1015 SimpleFinishLegalizing = false;
1017 case ISD::CALLSEQ_START:
1018 case ISD::CALLSEQ_END:
1019 // FIXME: This shouldn't be necessary. These nodes have special properties
1020 // dealing with the recursive nature of legalization. Removing this
1021 // special case should be done as part of making LegalizeDAG non-recursive.
1022 SimpleFinishLegalizing = false;
1024 case ISD::EXTRACT_ELEMENT:
1025 case ISD::FLT_ROUNDS_:
1026 case ISD::MERGE_VALUES:
1027 case ISD::EH_RETURN:
1028 case ISD::FRAME_TO_ARGS_OFFSET:
1029 case ISD::EH_DWARF_CFA:
1030 case ISD::EH_SJLJ_SETJMP:
1031 case ISD::EH_SJLJ_LONGJMP:
1032 case ISD::EH_SJLJ_SETUP_DISPATCH:
1033 // These operations lie about being legal: when they claim to be legal,
1034 // they should actually be expanded.
1035 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1036 if (Action == TargetLowering::Legal)
1037 Action = TargetLowering::Expand;
1039 case ISD::INIT_TRAMPOLINE:
1040 case ISD::ADJUST_TRAMPOLINE:
1041 case ISD::FRAMEADDR:
1042 case ISD::RETURNADDR:
1043 case ISD::ADDROFRETURNADDR:
1044 // These operations lie about being legal: when they claim to be legal,
1045 // they should actually be custom-lowered.
1046 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1047 if (Action == TargetLowering::Legal)
1048 Action = TargetLowering::Custom;
1050 case ISD::READCYCLECOUNTER:
1051 // READCYCLECOUNTER returns an i64, even if type legalization might have
1052 // expanded that to several smaller types.
1053 Action = TLI.getOperationAction(Node->getOpcode(), MVT::i64);
1055 case ISD::READ_REGISTER:
1056 case ISD::WRITE_REGISTER:
1057 // Named register is legal in the DAG, but blocked by register name
1058 // selection if not implemented by target (to chose the correct register)
1059 // They'll be converted to Copy(To/From)Reg.
1060 Action = TargetLowering::Legal;
1062 case ISD::DEBUGTRAP:
1063 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1064 if (Action == TargetLowering::Expand) {
1065 // replace ISD::DEBUGTRAP with ISD::TRAP
1067 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1068 Node->getOperand(0));
1069 ReplaceNode(Node, NewVal.getNode());
1070 LegalizeOp(NewVal.getNode());
1074 case ISD::STRICT_FSQRT:
1075 case ISD::STRICT_FPOW:
1076 case ISD::STRICT_FPOWI:
1077 case ISD::STRICT_FSIN:
1078 case ISD::STRICT_FCOS:
1079 case ISD::STRICT_FEXP:
1080 case ISD::STRICT_FEXP2:
1081 case ISD::STRICT_FLOG:
1082 case ISD::STRICT_FLOG10:
1083 case ISD::STRICT_FLOG2:
1084 case ISD::STRICT_FRINT:
1085 case ISD::STRICT_FNEARBYINT:
1086 // These pseudo-ops get legalized as if they were their non-strict
1087 // equivalent. For instance, if ISD::FSQRT is legal then ISD::STRICT_FSQRT
1088 // is also legal, but if ISD::FSQRT requires expansion then so does
1089 // ISD::STRICT_FSQRT.
1090 Action = getStrictFPOpcodeAction(TLI, Node->getOpcode(),
1091 Node->getValueType(0));
1095 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1096 Action = TargetLowering::Legal;
1098 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1103 if (SimpleFinishLegalizing) {
1104 SDNode *NewNode = Node;
1105 switch (Node->getOpcode()) {
1112 // Legalizing shifts/rotates requires adjusting the shift amount
1113 // to the appropriate width.
1114 SDValue Op0 = Node->getOperand(0);
1115 SDValue Op1 = Node->getOperand(1);
1116 if (!Op1.getValueType().isVector()) {
1117 SDValue SAO = DAG.getShiftAmountOperand(Op0.getValueType(), Op1);
1118 // The getShiftAmountOperand() may create a new operand node or
1119 // return the existing one. If new operand is created we need
1120 // to update the parent node.
1121 // Do not try to legalize SAO here! It will be automatically legalized
1122 // in the next round.
1124 NewNode = DAG.UpdateNodeOperands(Node, Op0, SAO);
1128 case ISD::SRL_PARTS:
1129 case ISD::SRA_PARTS:
1130 case ISD::SHL_PARTS: {
1131 // Legalizing shifts/rotates requires adjusting the shift amount
1132 // to the appropriate width.
1133 SDValue Op0 = Node->getOperand(0);
1134 SDValue Op1 = Node->getOperand(1);
1135 SDValue Op2 = Node->getOperand(2);
1136 if (!Op2.getValueType().isVector()) {
1137 SDValue SAO = DAG.getShiftAmountOperand(Op0.getValueType(), Op2);
1138 // The getShiftAmountOperand() may create a new operand node or
1139 // return the existing one. If new operand is created we need
1140 // to update the parent node.
1142 NewNode = DAG.UpdateNodeOperands(Node, Op0, Op1, SAO);
1148 if (NewNode != Node) {
1149 ReplaceNode(Node, NewNode);
1153 case TargetLowering::Legal:
1155 case TargetLowering::Custom: {
1156 // FIXME: The handling for custom lowering with multiple results is
1158 if (SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG)) {
1159 if (!(Res.getNode() != Node || Res.getResNo() != 0))
1162 if (Node->getNumValues() == 1) {
1163 // We can just directly replace this node with the lowered value.
1164 ReplaceNode(SDValue(Node, 0), Res);
1168 SmallVector<SDValue, 8> ResultVals;
1169 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1170 ResultVals.push_back(Res.getValue(i));
1171 ReplaceNode(Node, ResultVals.data());
1176 case TargetLowering::Expand:
1177 if (ExpandNode(Node))
1180 case TargetLowering::LibCall:
1181 ConvertNodeToLibcall(Node);
1183 case TargetLowering::Promote:
1189 switch (Node->getOpcode()) {
1196 llvm_unreachable("Do not know how to legalize this operator!");
1198 case ISD::CALLSEQ_START:
1199 case ISD::CALLSEQ_END:
1202 return LegalizeLoadOps(Node);
1205 return LegalizeStoreOps(Node);
1210 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1211 SDValue Vec = Op.getOperand(0);
1212 SDValue Idx = Op.getOperand(1);
1215 // Before we generate a new store to a temporary stack slot, see if there is
1216 // already one that we can use. There often is because when we scalarize
1217 // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1218 // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1219 // the vector. If all are expanded here, we don't want one store per vector
1222 // Caches for hasPredecessorHelper
1223 SmallPtrSet<const SDNode *, 32> Visited;
1224 SmallVector<const SDNode *, 16> Worklist;
1225 Worklist.push_back(Idx.getNode());
1226 SDValue StackPtr, Ch;
1227 for (SDNode::use_iterator UI = Vec.getNode()->use_begin(),
1228 UE = Vec.getNode()->use_end(); UI != UE; ++UI) {
1230 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1231 if (ST->isIndexed() || ST->isTruncatingStore() ||
1232 ST->getValue() != Vec)
1235 // Make sure that nothing else could have stored into the destination of
1237 if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1240 // If the index is dependent on the store we will introduce a cycle when
1241 // creating the load (the load uses the index, and by replacing the chain
1242 // we will make the index dependent on the load). Also, the store might be
1243 // dependent on the extractelement and introduce a cycle when creating
1245 if (SDNode::hasPredecessorHelper(ST, Visited, Worklist) ||
1246 ST->hasPredecessor(Op.getNode()))
1249 StackPtr = ST->getBasePtr();
1250 Ch = SDValue(ST, 0);
1255 EVT VecVT = Vec.getValueType();
1257 if (!Ch.getNode()) {
1258 // Store the value to a temporary stack slot, then LOAD the returned part.
1259 StackPtr = DAG.CreateStackTemporary(VecVT);
1260 Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1261 MachinePointerInfo());
1264 StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1268 if (Op.getValueType().isVector())
1270 DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, MachinePointerInfo());
1272 NewLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1273 MachinePointerInfo(),
1274 VecVT.getVectorElementType());
1276 // Replace the chain going out of the store, by the one out of the load.
1277 DAG.ReplaceAllUsesOfValueWith(Ch, SDValue(NewLoad.getNode(), 1));
1279 // We introduced a cycle though, so update the loads operands, making sure
1280 // to use the original store's chain as an incoming chain.
1281 SmallVector<SDValue, 6> NewLoadOperands(NewLoad->op_begin(),
1283 NewLoadOperands[0] = Ch;
1285 SDValue(DAG.UpdateNodeOperands(NewLoad.getNode(), NewLoadOperands), 0);
1289 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1290 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1292 SDValue Vec = Op.getOperand(0);
1293 SDValue Part = Op.getOperand(1);
1294 SDValue Idx = Op.getOperand(2);
1297 // Store the value to a temporary stack slot, then LOAD the returned part.
1298 EVT VecVT = Vec.getValueType();
1299 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1300 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1301 MachinePointerInfo PtrInfo =
1302 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1304 // First store the whole vector.
1305 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo);
1307 // Then store the inserted part.
1308 SDValue SubStackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1310 // Store the subvector.
1311 Ch = DAG.getStore(Ch, dl, Part, SubStackPtr, MachinePointerInfo());
1313 // Finally, load the updated vector.
1314 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo);
1317 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1318 // We can't handle this case efficiently. Allocate a sufficiently
1319 // aligned object on the stack, store each element into it, then load
1320 // the result as a vector.
1321 // Create the stack frame object.
1322 EVT VT = Node->getValueType(0);
1323 EVT EltVT = VT.getVectorElementType();
1325 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1326 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1327 MachinePointerInfo PtrInfo =
1328 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1330 // Emit a store of each element to the stack slot.
1331 SmallVector<SDValue, 8> Stores;
1332 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1333 // Store (in the right endianness) the elements to memory.
1334 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1335 // Ignore undef elements.
1336 if (Node->getOperand(i).isUndef()) continue;
1338 unsigned Offset = TypeByteSize*i;
1340 SDValue Idx = DAG.getConstant(Offset, dl, FIPtr.getValueType());
1341 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1343 // If the destination vector element type is narrower than the source
1344 // element type, only store the bits necessary.
1345 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1346 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1347 Node->getOperand(i), Idx,
1348 PtrInfo.getWithOffset(Offset), EltVT));
1350 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
1351 Idx, PtrInfo.getWithOffset(Offset)));
1355 if (!Stores.empty()) // Not all undef elements?
1356 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1358 StoreChain = DAG.getEntryNode();
1360 // Result is a load from the stack slot.
1361 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo);
1365 /// Keeps track of state when getting the sign of a floating-point value as an
1367 struct FloatSignAsInt {
1372 MachinePointerInfo IntPointerInfo;
1373 MachinePointerInfo FloatPointerInfo;
1380 /// Bitcast a floating-point value to an integer value. Only bitcast the part
1381 /// containing the sign bit if the target has no integer value capable of
1382 /// holding all bits of the floating-point value.
1383 void SelectionDAGLegalize::getSignAsIntValue(FloatSignAsInt &State,
1385 SDValue Value) const {
1386 EVT FloatVT = Value.getValueType();
1387 unsigned NumBits = FloatVT.getSizeInBits();
1388 State.FloatVT = FloatVT;
1389 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), NumBits);
1390 // Convert to an integer of the same size.
1391 if (TLI.isTypeLegal(IVT)) {
1392 State.IntValue = DAG.getNode(ISD::BITCAST, DL, IVT, Value);
1393 State.SignMask = APInt::getSignMask(NumBits);
1394 State.SignBit = NumBits - 1;
1398 auto &DataLayout = DAG.getDataLayout();
1399 // Store the float to memory, then load the sign part out as an integer.
1400 MVT LoadTy = TLI.getRegisterType(*DAG.getContext(), MVT::i8);
1401 // First create a temporary that is aligned for both the load and store.
1402 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1403 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1404 // Then store the float to it.
1405 State.FloatPtr = StackPtr;
1406 MachineFunction &MF = DAG.getMachineFunction();
1407 State.FloatPointerInfo = MachinePointerInfo::getFixedStack(MF, FI);
1408 State.Chain = DAG.getStore(DAG.getEntryNode(), DL, Value, State.FloatPtr,
1409 State.FloatPointerInfo);
1412 if (DataLayout.isBigEndian()) {
1413 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1414 // Load out a legal integer with the same sign bit as the float.
1416 State.IntPointerInfo = State.FloatPointerInfo;
1418 // Advance the pointer so that the loaded byte will contain the sign bit.
1419 unsigned ByteOffset = (FloatVT.getSizeInBits() / 8) - 1;
1420 IntPtr = DAG.getNode(ISD::ADD, DL, StackPtr.getValueType(), StackPtr,
1421 DAG.getConstant(ByteOffset, DL, StackPtr.getValueType()));
1422 State.IntPointerInfo = MachinePointerInfo::getFixedStack(MF, FI,
1426 State.IntPtr = IntPtr;
1427 State.IntValue = DAG.getExtLoad(ISD::EXTLOAD, DL, LoadTy, State.Chain, IntPtr,
1428 State.IntPointerInfo, MVT::i8);
1429 State.SignMask = APInt::getOneBitSet(LoadTy.getSizeInBits(), 7);
1433 /// Replace the integer value produced by getSignAsIntValue() with a new value
1434 /// and cast the result back to a floating-point type.
1435 SDValue SelectionDAGLegalize::modifySignAsInt(const FloatSignAsInt &State,
1437 SDValue NewIntValue) const {
1439 return DAG.getNode(ISD::BITCAST, DL, State.FloatVT, NewIntValue);
1441 // Override the part containing the sign bit in the value stored on the stack.
1442 SDValue Chain = DAG.getTruncStore(State.Chain, DL, NewIntValue, State.IntPtr,
1443 State.IntPointerInfo, MVT::i8);
1444 return DAG.getLoad(State.FloatVT, DL, Chain, State.FloatPtr,
1445 State.FloatPointerInfo);
1448 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode *Node) const {
1450 SDValue Mag = Node->getOperand(0);
1451 SDValue Sign = Node->getOperand(1);
1453 // Get sign bit into an integer value.
1454 FloatSignAsInt SignAsInt;
1455 getSignAsIntValue(SignAsInt, DL, Sign);
1457 EVT IntVT = SignAsInt.IntValue.getValueType();
1458 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT);
1459 SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue,
1462 // If FABS is legal transform FCOPYSIGN(x, y) => sign(x) ? -FABS(x) : FABS(X)
1463 EVT FloatVT = Mag.getValueType();
1464 if (TLI.isOperationLegalOrCustom(ISD::FABS, FloatVT) &&
1465 TLI.isOperationLegalOrCustom(ISD::FNEG, FloatVT)) {
1466 SDValue AbsValue = DAG.getNode(ISD::FABS, DL, FloatVT, Mag);
1467 SDValue NegValue = DAG.getNode(ISD::FNEG, DL, FloatVT, AbsValue);
1468 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit,
1469 DAG.getConstant(0, DL, IntVT), ISD::SETNE);
1470 return DAG.getSelect(DL, FloatVT, Cond, NegValue, AbsValue);
1473 // Transform Mag value to integer, and clear the sign bit.
1474 FloatSignAsInt MagAsInt;
1475 getSignAsIntValue(MagAsInt, DL, Mag);
1476 EVT MagVT = MagAsInt.IntValue.getValueType();
1477 SDValue ClearSignMask = DAG.getConstant(~MagAsInt.SignMask, DL, MagVT);
1478 SDValue ClearedSign = DAG.getNode(ISD::AND, DL, MagVT, MagAsInt.IntValue,
1481 // Get the signbit at the right position for MagAsInt.
1482 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit;
1483 if (SignBit.getValueSizeInBits() > ClearedSign.getValueSizeInBits()) {
1484 if (ShiftAmount > 0) {
1485 SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, IntVT);
1486 SignBit = DAG.getNode(ISD::SRL, DL, IntVT, SignBit, ShiftCnst);
1487 } else if (ShiftAmount < 0) {
1488 SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, IntVT);
1489 SignBit = DAG.getNode(ISD::SHL, DL, IntVT, SignBit, ShiftCnst);
1491 SignBit = DAG.getNode(ISD::TRUNCATE, DL, MagVT, SignBit);
1492 } else if (SignBit.getValueSizeInBits() < ClearedSign.getValueSizeInBits()) {
1493 SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit);
1494 if (ShiftAmount > 0) {
1495 SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, MagVT);
1496 SignBit = DAG.getNode(ISD::SRL, DL, MagVT, SignBit, ShiftCnst);
1497 } else if (ShiftAmount < 0) {
1498 SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, MagVT);
1499 SignBit = DAG.getNode(ISD::SHL, DL, MagVT, SignBit, ShiftCnst);
1503 // Store the part with the modified sign and convert back to float.
1504 SDValue CopiedSign = DAG.getNode(ISD::OR, DL, MagVT, ClearedSign, SignBit);
1505 return modifySignAsInt(MagAsInt, DL, CopiedSign);
1508 SDValue SelectionDAGLegalize::ExpandFABS(SDNode *Node) const {
1510 SDValue Value = Node->getOperand(0);
1512 // Transform FABS(x) => FCOPYSIGN(x, 0.0) if FCOPYSIGN is legal.
1513 EVT FloatVT = Value.getValueType();
1514 if (TLI.isOperationLegalOrCustom(ISD::FCOPYSIGN, FloatVT)) {
1515 SDValue Zero = DAG.getConstantFP(0.0, DL, FloatVT);
1516 return DAG.getNode(ISD::FCOPYSIGN, DL, FloatVT, Value, Zero);
1519 // Transform value to integer, clear the sign bit and transform back.
1520 FloatSignAsInt ValueAsInt;
1521 getSignAsIntValue(ValueAsInt, DL, Value);
1522 EVT IntVT = ValueAsInt.IntValue.getValueType();
1523 SDValue ClearSignMask = DAG.getConstant(~ValueAsInt.SignMask, DL, IntVT);
1524 SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, ValueAsInt.IntValue,
1526 return modifySignAsInt(ValueAsInt, DL, ClearedSign);
1529 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1530 SmallVectorImpl<SDValue> &Results) {
1531 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1532 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1533 " not tell us which reg is the stack pointer!");
1535 EVT VT = Node->getValueType(0);
1536 SDValue Tmp1 = SDValue(Node, 0);
1537 SDValue Tmp2 = SDValue(Node, 1);
1538 SDValue Tmp3 = Node->getOperand(2);
1539 SDValue Chain = Tmp1.getOperand(0);
1541 // Chain the dynamic stack allocation so that it doesn't modify the stack
1542 // pointer when other instructions are using the stack.
1543 Chain = DAG.getCALLSEQ_START(Chain, 0, 0, dl);
1545 SDValue Size = Tmp2.getOperand(1);
1546 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1547 Chain = SP.getValue(1);
1548 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1549 unsigned StackAlign =
1550 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
1551 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1552 if (Align > StackAlign)
1553 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1554 DAG.getConstant(-(uint64_t)Align, dl, VT));
1555 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1557 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
1558 DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
1560 Results.push_back(Tmp1);
1561 Results.push_back(Tmp2);
1564 /// Legalize a SETCC with given LHS and RHS and condition code CC on the current
1567 /// If the SETCC has been legalized using AND / OR, then the legalized node
1568 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1569 /// will be set to false.
1571 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1572 /// then the values of LHS and RHS will be swapped, CC will be set to the
1573 /// new condition, and NeedInvert will be set to false.
1575 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1576 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1577 /// will be set to true. The caller must invert the result of the SETCC with
1578 /// SelectionDAG::getLogicalNOT() or take equivalent action to swap the effect
1579 /// of a true/false result.
1581 /// \returns true if the SetCC has been legalized, false if it hasn't.
1582 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, SDValue &LHS,
1583 SDValue &RHS, SDValue &CC,
1586 MVT OpVT = LHS.getSimpleValueType();
1587 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1589 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1590 default: llvm_unreachable("Unknown condition code action!");
1591 case TargetLowering::Legal:
1594 case TargetLowering::Expand: {
1595 ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1596 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1597 std::swap(LHS, RHS);
1598 CC = DAG.getCondCode(InvCC);
1601 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1604 default: llvm_unreachable("Don't know how to expand this condition!");
1606 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1607 == TargetLowering::Legal
1608 && "If SETO is expanded, SETOEQ must be legal!");
1609 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1611 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1612 == TargetLowering::Legal
1613 && "If SETUO is expanded, SETUNE must be legal!");
1614 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1627 // If we are floating point, assign and break, otherwise fall through.
1628 if (!OpVT.isInteger()) {
1629 // We can use the 4th bit to tell if we are the unordered
1630 // or ordered version of the opcode.
1631 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1632 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1633 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1636 // Fallthrough if we are unsigned integer.
1642 // We only support using the inverted operation, which is computed above
1643 // and not a different manner of supporting expanding these cases.
1644 llvm_unreachable("Don't know how to expand this condition!");
1647 // Try inverting the result of the inverse condition.
1648 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ;
1649 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1650 CC = DAG.getCondCode(InvCC);
1654 // If inverting the condition didn't work then we have no means to expand
1656 llvm_unreachable("Don't know how to expand this condition!");
1659 SDValue SetCC1, SetCC2;
1660 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1661 // If we aren't the ordered or unorder operation,
1662 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1663 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1664 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1666 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1667 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1668 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1670 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1679 /// Emit a store/load combination to the stack. This stores
1680 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1681 /// a load from the stack slot to DestVT, extending it if needed.
1682 /// The resultant code need not be legal.
1683 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
1684 EVT DestVT, const SDLoc &dl) {
1685 // Create the stack frame object.
1686 unsigned SrcAlign = DAG.getDataLayout().getPrefTypeAlignment(
1687 SrcOp.getValueType().getTypeForEVT(*DAG.getContext()));
1688 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1690 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1691 int SPFI = StackPtrFI->getIndex();
1692 MachinePointerInfo PtrInfo =
1693 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI);
1695 unsigned SrcSize = SrcOp.getValueSizeInBits();
1696 unsigned SlotSize = SlotVT.getSizeInBits();
1697 unsigned DestSize = DestVT.getSizeInBits();
1698 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1699 unsigned DestAlign = DAG.getDataLayout().getPrefTypeAlignment(DestType);
1701 // Emit a store to the stack slot. Use a truncstore if the input value is
1702 // later than DestVT.
1705 if (SrcSize > SlotSize)
1706 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, PtrInfo,
1709 assert(SrcSize == SlotSize && "Invalid store");
1711 DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, PtrInfo, SrcAlign);
1714 // Result is a load from the stack slot.
1715 if (SlotSize == DestSize)
1716 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo, DestAlign);
1718 assert(SlotSize < DestSize && "Unknown extension!");
1719 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, PtrInfo, SlotVT,
1723 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1725 // Create a vector sized/aligned stack slot, store the value to element #0,
1726 // then load the whole vector back out.
1727 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1729 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1730 int SPFI = StackPtrFI->getIndex();
1732 SDValue Ch = DAG.getTruncStore(
1733 DAG.getEntryNode(), dl, Node->getOperand(0), StackPtr,
1734 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI),
1735 Node->getValueType(0).getVectorElementType());
1737 Node->getValueType(0), dl, Ch, StackPtr,
1738 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI));
1742 ExpandBVWithShuffles(SDNode *Node, SelectionDAG &DAG,
1743 const TargetLowering &TLI, SDValue &Res) {
1744 unsigned NumElems = Node->getNumOperands();
1746 EVT VT = Node->getValueType(0);
1748 // Try to group the scalars into pairs, shuffle the pairs together, then
1749 // shuffle the pairs of pairs together, etc. until the vector has
1750 // been built. This will work only if all of the necessary shuffle masks
1753 // We do this in two phases; first to check the legality of the shuffles,
1754 // and next, assuming that all shuffles are legal, to create the new nodes.
1755 for (int Phase = 0; Phase < 2; ++Phase) {
1756 SmallVector<std::pair<SDValue, SmallVector<int, 16> >, 16> IntermedVals,
1758 for (unsigned i = 0; i < NumElems; ++i) {
1759 SDValue V = Node->getOperand(i);
1765 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1766 IntermedVals.push_back(std::make_pair(Vec, SmallVector<int, 16>(1, i)));
1769 while (IntermedVals.size() > 2) {
1770 NewIntermedVals.clear();
1771 for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
1772 // This vector and the next vector are shuffled together (simply to
1773 // append the one to the other).
1774 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1776 SmallVector<int, 16> FinalIndices;
1777 FinalIndices.reserve(IntermedVals[i].second.size() +
1778 IntermedVals[i+1].second.size());
1781 for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
1784 FinalIndices.push_back(IntermedVals[i].second[j]);
1786 for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
1788 ShuffleVec[k] = NumElems + j;
1789 FinalIndices.push_back(IntermedVals[i+1].second[j]);
1794 Shuffle = DAG.getVectorShuffle(VT, dl, IntermedVals[i].first,
1795 IntermedVals[i+1].first,
1797 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1799 NewIntermedVals.push_back(
1800 std::make_pair(Shuffle, std::move(FinalIndices)));
1803 // If we had an odd number of defined values, then append the last
1804 // element to the array of new vectors.
1805 if ((IntermedVals.size() & 1) != 0)
1806 NewIntermedVals.push_back(IntermedVals.back());
1808 IntermedVals.swap(NewIntermedVals);
1811 assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
1812 "Invalid number of intermediate vectors");
1813 SDValue Vec1 = IntermedVals[0].first;
1815 if (IntermedVals.size() > 1)
1816 Vec2 = IntermedVals[1].first;
1818 Vec2 = DAG.getUNDEF(VT);
1820 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1821 for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
1822 ShuffleVec[IntermedVals[0].second[i]] = i;
1823 for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
1824 ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
1827 Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec);
1828 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1835 /// Expand a BUILD_VECTOR node on targets that don't
1836 /// support the operation, but do support the resultant vector type.
1837 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1838 unsigned NumElems = Node->getNumOperands();
1839 SDValue Value1, Value2;
1841 EVT VT = Node->getValueType(0);
1842 EVT OpVT = Node->getOperand(0).getValueType();
1843 EVT EltVT = VT.getVectorElementType();
1845 // If the only non-undef value is the low element, turn this into a
1846 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1847 bool isOnlyLowElement = true;
1848 bool MoreThanTwoValues = false;
1849 bool isConstant = true;
1850 for (unsigned i = 0; i < NumElems; ++i) {
1851 SDValue V = Node->getOperand(i);
1855 isOnlyLowElement = false;
1856 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1859 if (!Value1.getNode()) {
1861 } else if (!Value2.getNode()) {
1864 } else if (V != Value1 && V != Value2) {
1865 MoreThanTwoValues = true;
1869 if (!Value1.getNode())
1870 return DAG.getUNDEF(VT);
1872 if (isOnlyLowElement)
1873 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1875 // If all elements are constants, create a load from the constant pool.
1877 SmallVector<Constant*, 16> CV;
1878 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1879 if (ConstantFPSDNode *V =
1880 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1881 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1882 } else if (ConstantSDNode *V =
1883 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1885 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1887 // If OpVT and EltVT don't match, EltVT is not legal and the
1888 // element values have been promoted/truncated earlier. Undo this;
1889 // we don't want a v16i8 to become a v16i32 for example.
1890 const ConstantInt *CI = V->getConstantIntValue();
1891 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1892 CI->getZExtValue()));
1895 assert(Node->getOperand(i).isUndef());
1896 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1897 CV.push_back(UndefValue::get(OpNTy));
1900 Constant *CP = ConstantVector::get(CV);
1902 DAG.getConstantPool(CP, TLI.getPointerTy(DAG.getDataLayout()));
1903 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1905 VT, dl, DAG.getEntryNode(), CPIdx,
1906 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
1910 SmallSet<SDValue, 16> DefinedValues;
1911 for (unsigned i = 0; i < NumElems; ++i) {
1912 if (Node->getOperand(i).isUndef())
1914 DefinedValues.insert(Node->getOperand(i));
1917 if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues.size())) {
1918 if (!MoreThanTwoValues) {
1919 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1920 for (unsigned i = 0; i < NumElems; ++i) {
1921 SDValue V = Node->getOperand(i);
1924 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1926 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1927 // Get the splatted value into the low element of a vector register.
1928 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1930 if (Value2.getNode())
1931 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1933 Vec2 = DAG.getUNDEF(VT);
1935 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1936 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec);
1940 if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
1945 // Otherwise, we can't handle this case efficiently.
1946 return ExpandVectorBuildThroughStack(Node);
1949 // Expand a node into a call to a libcall. If the result value
1950 // does not fit into a register, return the lo part and set the hi part to the
1951 // by-reg argument. If it does fit into a single register, return the result
1952 // and leave the Hi part unset.
1953 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1955 TargetLowering::ArgListTy Args;
1956 TargetLowering::ArgListEntry Entry;
1957 for (const SDValue &Op : Node->op_values()) {
1958 EVT ArgVT = Op.getValueType();
1959 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1962 Entry.IsSExt = isSigned;
1963 Entry.IsZExt = !isSigned;
1964 Args.push_back(Entry);
1966 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1967 TLI.getPointerTy(DAG.getDataLayout()));
1969 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1971 // By default, the input chain to this libcall is the entry node of the
1972 // function. If the libcall is going to be emitted as a tail call then
1973 // TLI.isUsedByReturnOnly will change it to the right chain if the return
1974 // node which is being folded has a non-entry input chain.
1975 SDValue InChain = DAG.getEntryNode();
1977 // isTailCall may be true since the callee does not reference caller stack
1978 // frame. Check if it's in the right position and that the return types match.
1979 SDValue TCChain = InChain;
1980 const Function *F = DAG.getMachineFunction().getFunction();
1982 TLI.isInTailCallPosition(DAG, Node, TCChain) &&
1983 (RetTy == F->getReturnType() || F->getReturnType()->isVoidTy());
1987 TargetLowering::CallLoweringInfo CLI(DAG);
1988 CLI.setDebugLoc(SDLoc(Node))
1990 .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
1992 .setTailCall(isTailCall)
1993 .setSExtResult(isSigned)
1994 .setZExtResult(!isSigned)
1995 .setIsPostTypeLegalization(true);
1997 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1999 if (!CallInfo.second.getNode())
2000 // It's a tailcall, return the chain (which is the DAG root).
2001 return DAG.getRoot();
2003 return CallInfo.first;
2006 /// Generate a libcall taking the given operands as arguments
2007 /// and returning a result of type RetVT.
2008 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2009 const SDValue *Ops, unsigned NumOps,
2010 bool isSigned, const SDLoc &dl) {
2011 TargetLowering::ArgListTy Args;
2012 Args.reserve(NumOps);
2014 TargetLowering::ArgListEntry Entry;
2015 for (unsigned i = 0; i != NumOps; ++i) {
2016 Entry.Node = Ops[i];
2017 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
2018 Entry.IsSExt = isSigned;
2019 Entry.IsZExt = !isSigned;
2020 Args.push_back(Entry);
2022 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2023 TLI.getPointerTy(DAG.getDataLayout()));
2025 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2027 TargetLowering::CallLoweringInfo CLI(DAG);
2029 .setChain(DAG.getEntryNode())
2030 .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2032 .setSExtResult(isSigned)
2033 .setZExtResult(!isSigned)
2034 .setIsPostTypeLegalization(true);
2036 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
2038 return CallInfo.first;
2041 // Expand a node into a call to a libcall. Similar to
2042 // ExpandLibCall except that the first operand is the in-chain.
2043 std::pair<SDValue, SDValue>
2044 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2047 SDValue InChain = Node->getOperand(0);
2049 TargetLowering::ArgListTy Args;
2050 TargetLowering::ArgListEntry Entry;
2051 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2052 EVT ArgVT = Node->getOperand(i).getValueType();
2053 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2054 Entry.Node = Node->getOperand(i);
2056 Entry.IsSExt = isSigned;
2057 Entry.IsZExt = !isSigned;
2058 Args.push_back(Entry);
2060 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2061 TLI.getPointerTy(DAG.getDataLayout()));
2063 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2065 TargetLowering::CallLoweringInfo CLI(DAG);
2066 CLI.setDebugLoc(SDLoc(Node))
2068 .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2070 .setSExtResult(isSigned)
2071 .setZExtResult(!isSigned);
2073 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2078 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2079 RTLIB::Libcall Call_F32,
2080 RTLIB::Libcall Call_F64,
2081 RTLIB::Libcall Call_F80,
2082 RTLIB::Libcall Call_F128,
2083 RTLIB::Libcall Call_PPCF128) {
2084 if (Node->isStrictFPOpcode())
2085 Node = DAG.mutateStrictFPToFP(Node);
2088 switch (Node->getSimpleValueType(0).SimpleTy) {
2089 default: llvm_unreachable("Unexpected request for libcall!");
2090 case MVT::f32: LC = Call_F32; break;
2091 case MVT::f64: LC = Call_F64; break;
2092 case MVT::f80: LC = Call_F80; break;
2093 case MVT::f128: LC = Call_F128; break;
2094 case MVT::ppcf128: LC = Call_PPCF128; break;
2096 return ExpandLibCall(LC, Node, false);
2099 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2100 RTLIB::Libcall Call_I8,
2101 RTLIB::Libcall Call_I16,
2102 RTLIB::Libcall Call_I32,
2103 RTLIB::Libcall Call_I64,
2104 RTLIB::Libcall Call_I128) {
2106 switch (Node->getSimpleValueType(0).SimpleTy) {
2107 default: llvm_unreachable("Unexpected request for libcall!");
2108 case MVT::i8: LC = Call_I8; break;
2109 case MVT::i16: LC = Call_I16; break;
2110 case MVT::i32: LC = Call_I32; break;
2111 case MVT::i64: LC = Call_I64; break;
2112 case MVT::i128: LC = Call_I128; break;
2114 return ExpandLibCall(LC, Node, isSigned);
2117 /// Issue libcalls to __{u}divmod to compute div / rem pairs.
2119 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2120 SmallVectorImpl<SDValue> &Results) {
2121 unsigned Opcode = Node->getOpcode();
2122 bool isSigned = Opcode == ISD::SDIVREM;
2125 switch (Node->getSimpleValueType(0).SimpleTy) {
2126 default: llvm_unreachable("Unexpected request for libcall!");
2127 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2128 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2129 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2130 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2131 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2134 // The input chain to this libcall is the entry node of the function.
2135 // Legalizing the call will automatically add the previous call to the
2137 SDValue InChain = DAG.getEntryNode();
2139 EVT RetVT = Node->getValueType(0);
2140 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2142 TargetLowering::ArgListTy Args;
2143 TargetLowering::ArgListEntry Entry;
2144 for (const SDValue &Op : Node->op_values()) {
2145 EVT ArgVT = Op.getValueType();
2146 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2149 Entry.IsSExt = isSigned;
2150 Entry.IsZExt = !isSigned;
2151 Args.push_back(Entry);
2154 // Also pass the return address of the remainder.
2155 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2157 Entry.Ty = RetTy->getPointerTo();
2158 Entry.IsSExt = isSigned;
2159 Entry.IsZExt = !isSigned;
2160 Args.push_back(Entry);
2162 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2163 TLI.getPointerTy(DAG.getDataLayout()));
2166 TargetLowering::CallLoweringInfo CLI(DAG);
2169 .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2171 .setSExtResult(isSigned)
2172 .setZExtResult(!isSigned);
2174 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2176 // Remainder is loaded back from the stack frame.
2178 DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr, MachinePointerInfo());
2179 Results.push_back(CallInfo.first);
2180 Results.push_back(Rem);
2183 /// Return true if sincos libcall is available.
2184 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2186 switch (Node->getSimpleValueType(0).SimpleTy) {
2187 default: llvm_unreachable("Unexpected request for libcall!");
2188 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2189 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2190 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2191 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2192 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2194 return TLI.getLibcallName(LC) != nullptr;
2197 /// Only issue sincos libcall if both sin and cos are needed.
2198 static bool useSinCos(SDNode *Node) {
2199 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2200 ? ISD::FCOS : ISD::FSIN;
2202 SDValue Op0 = Node->getOperand(0);
2203 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2204 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2208 // The other user might have been turned into sincos already.
2209 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2215 /// Issue libcalls to sincos to compute sin / cos pairs.
2217 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2218 SmallVectorImpl<SDValue> &Results) {
2220 switch (Node->getSimpleValueType(0).SimpleTy) {
2221 default: llvm_unreachable("Unexpected request for libcall!");
2222 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2223 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2224 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2225 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2226 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2229 // The input chain to this libcall is the entry node of the function.
2230 // Legalizing the call will automatically add the previous call to the
2232 SDValue InChain = DAG.getEntryNode();
2234 EVT RetVT = Node->getValueType(0);
2235 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2237 TargetLowering::ArgListTy Args;
2238 TargetLowering::ArgListEntry Entry;
2240 // Pass the argument.
2241 Entry.Node = Node->getOperand(0);
2243 Entry.IsSExt = false;
2244 Entry.IsZExt = false;
2245 Args.push_back(Entry);
2247 // Pass the return address of sin.
2248 SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2249 Entry.Node = SinPtr;
2250 Entry.Ty = RetTy->getPointerTo();
2251 Entry.IsSExt = false;
2252 Entry.IsZExt = false;
2253 Args.push_back(Entry);
2255 // Also pass the return address of the cos.
2256 SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2257 Entry.Node = CosPtr;
2258 Entry.Ty = RetTy->getPointerTo();
2259 Entry.IsSExt = false;
2260 Entry.IsZExt = false;
2261 Args.push_back(Entry);
2263 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2264 TLI.getPointerTy(DAG.getDataLayout()));
2267 TargetLowering::CallLoweringInfo CLI(DAG);
2268 CLI.setDebugLoc(dl).setChain(InChain).setLibCallee(
2269 TLI.getLibcallCallingConv(LC), Type::getVoidTy(*DAG.getContext()), Callee,
2272 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2275 DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr, MachinePointerInfo()));
2277 DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr, MachinePointerInfo()));
2280 /// This function is responsible for legalizing a
2281 /// INT_TO_FP operation of the specified operand when the target requests that
2282 /// we expand it. At this point, we know that the result and operand types are
2283 /// legal for the target.
2284 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0,
2287 // TODO: Should any fast-math-flags be set for the created nodes?
2289 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2290 // simple 32-bit [signed|unsigned] integer to float/double expansion
2292 // Get the stack frame index of a 8 byte buffer.
2293 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2295 // word offset constant for Hi/Lo address computation
2296 SDValue WordOff = DAG.getConstant(sizeof(int), dl,
2297 StackSlot.getValueType());
2298 // set up Hi and Lo (into buffer) address based on endian
2299 SDValue Hi = StackSlot;
2300 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2301 StackSlot, WordOff);
2302 if (DAG.getDataLayout().isLittleEndian())
2305 // if signed map to unsigned space
2308 // constant used to invert sign bit (signed to unsigned mapping)
2309 SDValue SignBit = DAG.getConstant(0x80000000u, dl, MVT::i32);
2310 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2314 // store the lo of the constructed double - based on integer input
2315 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op0Mapped, Lo,
2316 MachinePointerInfo());
2317 // initial hi portion of constructed double
2318 SDValue InitialHi = DAG.getConstant(0x43300000u, dl, MVT::i32);
2319 // store the hi of the constructed double - biased exponent
2321 DAG.getStore(Store1, dl, InitialHi, Hi, MachinePointerInfo());
2322 // load the constructed double
2324 DAG.getLoad(MVT::f64, dl, Store2, StackSlot, MachinePointerInfo());
2325 // FP constant to bias correct the final result
2326 SDValue Bias = DAG.getConstantFP(isSigned ?
2327 BitsToDouble(0x4330000080000000ULL) :
2328 BitsToDouble(0x4330000000000000ULL),
2330 // subtract the bias
2331 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2334 // handle final rounding
2335 if (DestVT == MVT::f64) {
2338 } else if (DestVT.bitsLT(MVT::f64)) {
2339 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2340 DAG.getIntPtrConstant(0, dl));
2341 } else if (DestVT.bitsGT(MVT::f64)) {
2342 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2346 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2347 // Code below here assumes !isSigned without checking again.
2349 // Implementation of unsigned i64 to f64 following the algorithm in
2350 // __floatundidf in compiler_rt. This implementation has the advantage
2351 // of performing rounding correctly, both in the default rounding mode
2352 // and in all alternate rounding modes.
2353 // TODO: Generalize this for use with other types.
2354 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2356 DAG.getConstant(UINT64_C(0x4330000000000000), dl, MVT::i64);
2357 SDValue TwoP84PlusTwoP52 =
2358 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), dl,
2361 DAG.getConstant(UINT64_C(0x4530000000000000), dl, MVT::i64);
2363 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2364 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2365 DAG.getConstant(32, dl, MVT::i64));
2366 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2367 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2368 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2369 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2370 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2372 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2375 // Implementation of unsigned i64 to f32.
2376 // TODO: Generalize this for use with other types.
2377 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2378 // For unsigned conversions, convert them to signed conversions using the
2379 // algorithm from the x86_64 __floatundidf in compiler_rt.
2381 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2383 SDValue ShiftConst = DAG.getConstant(
2384 1, dl, TLI.getShiftAmountTy(Op0.getValueType(), DAG.getDataLayout()));
2385 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2386 SDValue AndConst = DAG.getConstant(1, dl, MVT::i64);
2387 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2388 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2390 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2391 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2393 // TODO: This really should be implemented using a branch rather than a
2394 // select. We happen to get lucky and machinesink does the right
2395 // thing most of the time. This would be a good candidate for a
2396 //pseudo-op, or, even better, for whole-function isel.
2397 SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2398 Op0, DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
2399 return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
2402 // Otherwise, implement the fully general conversion.
2404 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2405 DAG.getConstant(UINT64_C(0xfffffffffffff800), dl, MVT::i64));
2406 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2407 DAG.getConstant(UINT64_C(0x800), dl, MVT::i64));
2408 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2409 DAG.getConstant(UINT64_C(0x7ff), dl, MVT::i64));
2410 SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), And2,
2411 DAG.getConstant(UINT64_C(0), dl, MVT::i64),
2413 SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2414 SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), Op0,
2415 DAG.getConstant(UINT64_C(0x0020000000000000), dl,
2418 SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
2419 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType(), DAG.getDataLayout());
2421 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2422 DAG.getConstant(32, dl, SHVT));
2423 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2424 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2426 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), dl,
2428 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2429 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2430 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2431 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2432 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2433 DAG.getIntPtrConstant(0, dl));
2436 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2438 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2440 DAG.getConstant(0, dl, Op0.getValueType()),
2442 SDValue Zero = DAG.getIntPtrConstant(0, dl),
2443 Four = DAG.getIntPtrConstant(4, dl);
2444 SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2445 SignSet, Four, Zero);
2447 // If the sign bit of the integer is set, the large number will be treated
2448 // as a negative number. To counteract this, the dynamic code adds an
2449 // offset depending on the data type.
2451 switch (Op0.getSimpleValueType().SimpleTy) {
2452 default: llvm_unreachable("Unsupported integer type!");
2453 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2454 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2455 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2456 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2458 if (DAG.getDataLayout().isLittleEndian())
2460 Constant *FudgeFactor = ConstantInt::get(
2461 Type::getInt64Ty(*DAG.getContext()), FF);
2464 DAG.getConstantPool(FudgeFactor, TLI.getPointerTy(DAG.getDataLayout()));
2465 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2466 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2467 Alignment = std::min(Alignment, 4u);
2469 if (DestVT == MVT::f32)
2470 FudgeInReg = DAG.getLoad(
2471 MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2472 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
2475 SDValue Load = DAG.getExtLoad(
2476 ISD::EXTLOAD, dl, DestVT, DAG.getEntryNode(), CPIdx,
2477 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
2479 HandleSDNode Handle(Load);
2480 LegalizeOp(Load.getNode());
2481 FudgeInReg = Handle.getValue();
2484 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2487 /// This function is responsible for legalizing a
2488 /// *INT_TO_FP operation of the specified operand when the target requests that
2489 /// we promote it. At this point, we know that the result and operand types are
2490 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2491 /// operation that takes a larger input.
2492 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT,
2495 // First step, figure out the appropriate *INT_TO_FP operation to use.
2496 EVT NewInTy = LegalOp.getValueType();
2498 unsigned OpToUse = 0;
2500 // Scan for the appropriate larger type to use.
2502 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2503 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2505 // If the target supports SINT_TO_FP of this type, use it.
2506 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2507 OpToUse = ISD::SINT_TO_FP;
2510 if (isSigned) continue;
2512 // If the target supports UINT_TO_FP of this type, use it.
2513 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2514 OpToUse = ISD::UINT_TO_FP;
2518 // Otherwise, try a larger type.
2521 // Okay, we found the operation and type to use. Zero extend our input to the
2522 // desired type then run the operation on it.
2523 return DAG.getNode(OpToUse, dl, DestVT,
2524 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2525 dl, NewInTy, LegalOp));
2528 /// This function is responsible for legalizing a
2529 /// FP_TO_*INT operation of the specified operand when the target requests that
2530 /// we promote it. At this point, we know that the result and operand types are
2531 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2532 /// operation that returns a larger result.
2533 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT,
2536 // First step, figure out the appropriate FP_TO*INT operation to use.
2537 EVT NewOutTy = DestVT;
2539 unsigned OpToUse = 0;
2541 // Scan for the appropriate larger type to use.
2543 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2544 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2546 // A larger signed type can hold all unsigned values of the requested type,
2547 // so using FP_TO_SINT is valid
2548 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2549 OpToUse = ISD::FP_TO_SINT;
2553 // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
2554 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2555 OpToUse = ISD::FP_TO_UINT;
2559 // Otherwise, try a larger type.
2563 // Okay, we found the operation and type to use.
2564 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2566 // Truncate the result of the extended FP_TO_*INT operation to the desired
2568 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2571 /// Legalize a BITREVERSE scalar/vector operation as a series of mask + shifts.
2572 SDValue SelectionDAGLegalize::ExpandBITREVERSE(SDValue Op, const SDLoc &dl) {
2573 EVT VT = Op.getValueType();
2574 EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2575 unsigned Sz = VT.getScalarSizeInBits();
2577 SDValue Tmp, Tmp2, Tmp3;
2579 // If we can, perform BSWAP first and then the mask+swap the i4, then i2
2580 // and finally the i1 pairs.
2581 // TODO: We can easily support i4/i2 legal types if any target ever does.
2582 if (Sz >= 8 && isPowerOf2_32(Sz)) {
2583 // Create the masks - repeating the pattern every byte.
2584 APInt MaskHi4(Sz, 0), MaskHi2(Sz, 0), MaskHi1(Sz, 0);
2585 APInt MaskLo4(Sz, 0), MaskLo2(Sz, 0), MaskLo1(Sz, 0);
2586 for (unsigned J = 0; J != Sz; J += 8) {
2587 MaskHi4 = MaskHi4 | (0xF0ull << J);
2588 MaskLo4 = MaskLo4 | (0x0Full << J);
2589 MaskHi2 = MaskHi2 | (0xCCull << J);
2590 MaskLo2 = MaskLo2 | (0x33ull << J);
2591 MaskHi1 = MaskHi1 | (0xAAull << J);
2592 MaskLo1 = MaskLo1 | (0x55ull << J);
2595 // BSWAP if the type is wider than a single byte.
2596 Tmp = (Sz > 8 ? DAG.getNode(ISD::BSWAP, dl, VT, Op) : Op);
2598 // swap i4: ((V & 0xF0) >> 4) | ((V & 0x0F) << 4)
2599 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi4, dl, VT));
2600 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo4, dl, VT));
2601 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(4, dl, VT));
2602 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(4, dl, VT));
2603 Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2605 // swap i2: ((V & 0xCC) >> 2) | ((V & 0x33) << 2)
2606 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi2, dl, VT));
2607 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo2, dl, VT));
2608 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(2, dl, VT));
2609 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(2, dl, VT));
2610 Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2612 // swap i1: ((V & 0xAA) >> 1) | ((V & 0x55) << 1)
2613 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi1, dl, VT));
2614 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo1, dl, VT));
2615 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(1, dl, VT));
2616 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(1, dl, VT));
2617 Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2621 Tmp = DAG.getConstant(0, dl, VT);
2622 for (unsigned I = 0, J = Sz-1; I < Sz; ++I, --J) {
2625 DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(J - I, dl, SHVT));
2628 DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(I - J, dl, SHVT));
2632 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Shift, dl, VT));
2633 Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp, Tmp2);
2639 /// Open code the operations for BSWAP of the specified operation.
2640 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, const SDLoc &dl) {
2641 EVT VT = Op.getValueType();
2642 EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2643 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2644 switch (VT.getSimpleVT().getScalarType().SimpleTy) {
2645 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2647 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2648 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2649 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2651 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2652 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2653 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2654 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2655 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2656 DAG.getConstant(0xFF0000, dl, VT));
2657 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT));
2658 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2659 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2660 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2662 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2663 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2664 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2665 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2666 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2667 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2668 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2669 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2670 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7,
2671 DAG.getConstant(255ULL<<48, dl, VT));
2672 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6,
2673 DAG.getConstant(255ULL<<40, dl, VT));
2674 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5,
2675 DAG.getConstant(255ULL<<32, dl, VT));
2676 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4,
2677 DAG.getConstant(255ULL<<24, dl, VT));
2678 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2679 DAG.getConstant(255ULL<<16, dl, VT));
2680 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2,
2681 DAG.getConstant(255ULL<<8 , dl, VT));
2682 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2683 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2684 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2685 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2686 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2687 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2688 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2692 /// Expand the specified bitcount instruction into operations.
2693 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2696 default: llvm_unreachable("Cannot expand this yet!");
2698 EVT VT = Op.getValueType();
2699 EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2700 unsigned Len = VT.getSizeInBits();
2702 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2703 "CTPOP not implemented for this type.");
2705 // This is the "best" algorithm from
2706 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2708 SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)),
2710 SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)),
2712 SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)),
2714 SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)),
2717 // v = v - ((v >> 1) & 0x55555555...)
2718 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2719 DAG.getNode(ISD::AND, dl, VT,
2720 DAG.getNode(ISD::SRL, dl, VT, Op,
2721 DAG.getConstant(1, dl, ShVT)),
2723 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2724 Op = DAG.getNode(ISD::ADD, dl, VT,
2725 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2726 DAG.getNode(ISD::AND, dl, VT,
2727 DAG.getNode(ISD::SRL, dl, VT, Op,
2728 DAG.getConstant(2, dl, ShVT)),
2730 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2731 Op = DAG.getNode(ISD::AND, dl, VT,
2732 DAG.getNode(ISD::ADD, dl, VT, Op,
2733 DAG.getNode(ISD::SRL, dl, VT, Op,
2734 DAG.getConstant(4, dl, ShVT))),
2736 // v = (v * 0x01010101...) >> (Len - 8)
2737 Op = DAG.getNode(ISD::SRL, dl, VT,
2738 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2739 DAG.getConstant(Len - 8, dl, ShVT));
2743 case ISD::CTLZ_ZERO_UNDEF:
2744 // This trivially expands to CTLZ.
2745 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2747 EVT VT = Op.getValueType();
2748 unsigned len = VT.getSizeInBits();
2750 if (TLI.isOperationLegalOrCustom(ISD::CTLZ_ZERO_UNDEF, VT)) {
2751 EVT SetCCVT = getSetCCResultType(VT);
2752 SDValue CTLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, VT, Op);
2753 SDValue Zero = DAG.getConstant(0, dl, VT);
2754 SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ);
2755 return DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero,
2756 DAG.getConstant(len, dl, VT), CTLZ);
2759 // for now, we do this:
2760 // x = x | (x >> 1);
2761 // x = x | (x >> 2);
2763 // x = x | (x >>16);
2764 // x = x | (x >>32); // for 64-bit input
2765 // return popcount(~x);
2767 // Ref: "Hacker's Delight" by Henry Warren
2768 EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2769 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2770 SDValue Tmp3 = DAG.getConstant(1ULL << i, dl, ShVT);
2771 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2772 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2774 Op = DAG.getNOT(dl, Op, VT);
2775 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2777 case ISD::CTTZ_ZERO_UNDEF:
2778 // This trivially expands to CTTZ.
2779 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2781 // for now, we use: { return popcount(~x & (x - 1)); }
2782 // unless the target has ctlz but not ctpop, in which case we use:
2783 // { return 32 - nlz(~x & (x-1)); }
2784 // Ref: "Hacker's Delight" by Henry Warren
2785 EVT VT = Op.getValueType();
2786 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2787 DAG.getNOT(dl, Op, VT),
2788 DAG.getNode(ISD::SUB, dl, VT, Op,
2789 DAG.getConstant(1, dl, VT)));
2790 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2791 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2792 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2793 return DAG.getNode(ISD::SUB, dl, VT,
2794 DAG.getConstant(VT.getSizeInBits(), dl, VT),
2795 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2796 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2801 bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2802 SmallVector<SDValue, 8> Results;
2804 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2806 switch (Node->getOpcode()) {
2809 case ISD::CTLZ_ZERO_UNDEF:
2811 case ISD::CTTZ_ZERO_UNDEF:
2812 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2813 Results.push_back(Tmp1);
2815 case ISD::BITREVERSE:
2816 Results.push_back(ExpandBITREVERSE(Node->getOperand(0), dl));
2819 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2821 case ISD::FRAMEADDR:
2822 case ISD::RETURNADDR:
2823 case ISD::FRAME_TO_ARGS_OFFSET:
2824 Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
2826 case ISD::EH_DWARF_CFA: {
2827 SDValue CfaArg = DAG.getSExtOrTrunc(Node->getOperand(0), dl,
2828 TLI.getPointerTy(DAG.getDataLayout()));
2829 SDValue Offset = DAG.getNode(ISD::ADD, dl,
2830 CfaArg.getValueType(),
2831 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
2832 CfaArg.getValueType()),
2834 SDValue FA = DAG.getNode(
2835 ISD::FRAMEADDR, dl, TLI.getPointerTy(DAG.getDataLayout()),
2836 DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout())));
2837 Results.push_back(DAG.getNode(ISD::ADD, dl, FA.getValueType(),
2841 case ISD::FLT_ROUNDS_:
2842 Results.push_back(DAG.getConstant(1, dl, Node->getValueType(0)));
2844 case ISD::EH_RETURN:
2848 case ISD::EH_SJLJ_LONGJMP:
2849 // If the target didn't expand these, there's nothing to do, so just
2850 // preserve the chain and be done.
2851 Results.push_back(Node->getOperand(0));
2853 case ISD::READCYCLECOUNTER:
2854 // If the target didn't expand this, just return 'zero' and preserve the
2856 Results.append(Node->getNumValues() - 1,
2857 DAG.getConstant(0, dl, Node->getValueType(0)));
2858 Results.push_back(Node->getOperand(0));
2860 case ISD::EH_SJLJ_SETJMP:
2861 // If the target didn't expand this, just return 'zero' and preserve the
2863 Results.push_back(DAG.getConstant(0, dl, MVT::i32));
2864 Results.push_back(Node->getOperand(0));
2866 case ISD::ATOMIC_LOAD: {
2867 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2868 SDValue Zero = DAG.getConstant(0, dl, Node->getValueType(0));
2869 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2870 SDValue Swap = DAG.getAtomicCmpSwap(
2871 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2872 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
2873 cast<AtomicSDNode>(Node)->getMemOperand());
2874 Results.push_back(Swap.getValue(0));
2875 Results.push_back(Swap.getValue(1));
2878 case ISD::ATOMIC_STORE: {
2879 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2880 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2881 cast<AtomicSDNode>(Node)->getMemoryVT(),
2882 Node->getOperand(0),
2883 Node->getOperand(1), Node->getOperand(2),
2884 cast<AtomicSDNode>(Node)->getMemOperand());
2885 Results.push_back(Swap.getValue(1));
2888 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
2889 // Expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS produces an ATOMIC_CMP_SWAP and
2890 // splits out the success value as a comparison. Expanding the resulting
2891 // ATOMIC_CMP_SWAP will produce a libcall.
2892 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2893 SDValue Res = DAG.getAtomicCmpSwap(
2894 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2895 Node->getOperand(0), Node->getOperand(1), Node->getOperand(2),
2896 Node->getOperand(3), cast<MemSDNode>(Node)->getMemOperand());
2898 SDValue ExtRes = Res;
2900 SDValue RHS = Node->getOperand(1);
2902 EVT AtomicType = cast<AtomicSDNode>(Node)->getMemoryVT();
2903 EVT OuterType = Node->getValueType(0);
2904 switch (TLI.getExtendForAtomicOps()) {
2905 case ISD::SIGN_EXTEND:
2906 LHS = DAG.getNode(ISD::AssertSext, dl, OuterType, Res,
2907 DAG.getValueType(AtomicType));
2908 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, OuterType,
2909 Node->getOperand(2), DAG.getValueType(AtomicType));
2912 case ISD::ZERO_EXTEND:
2913 LHS = DAG.getNode(ISD::AssertZext, dl, OuterType, Res,
2914 DAG.getValueType(AtomicType));
2915 RHS = DAG.getNode(ISD::ZERO_EXTEND, dl, OuterType, Node->getOperand(2));
2918 case ISD::ANY_EXTEND:
2919 LHS = DAG.getZeroExtendInReg(Res, dl, AtomicType);
2920 RHS = DAG.getNode(ISD::ZERO_EXTEND, dl, OuterType, Node->getOperand(2));
2923 llvm_unreachable("Invalid atomic op extension");
2927 DAG.getSetCC(dl, Node->getValueType(1), LHS, RHS, ISD::SETEQ);
2929 Results.push_back(ExtRes.getValue(0));
2930 Results.push_back(Success);
2931 Results.push_back(Res.getValue(1));
2934 case ISD::DYNAMIC_STACKALLOC:
2935 ExpandDYNAMIC_STACKALLOC(Node, Results);
2937 case ISD::MERGE_VALUES:
2938 for (unsigned i = 0; i < Node->getNumValues(); i++)
2939 Results.push_back(Node->getOperand(i));
2942 EVT VT = Node->getValueType(0);
2944 Results.push_back(DAG.getConstant(0, dl, VT));
2946 assert(VT.isFloatingPoint() && "Unknown value type!");
2947 Results.push_back(DAG.getConstantFP(0, dl, VT));
2953 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2954 Node->getValueType(0), dl);
2955 Results.push_back(Tmp1);
2957 case ISD::FP_EXTEND:
2958 Tmp1 = EmitStackConvert(Node->getOperand(0),
2959 Node->getOperand(0).getValueType(),
2960 Node->getValueType(0), dl);
2961 Results.push_back(Tmp1);
2963 case ISD::SIGN_EXTEND_INREG: {
2964 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2965 EVT VT = Node->getValueType(0);
2967 // An in-register sign-extend of a boolean is a negation:
2968 // 'true' (1) sign-extended is -1.
2969 // 'false' (0) sign-extended is 0.
2970 // However, we must mask the high bits of the source operand because the
2971 // SIGN_EXTEND_INREG does not guarantee that the high bits are already zero.
2973 // TODO: Do this for vectors too?
2974 if (ExtraVT.getSizeInBits() == 1) {
2975 SDValue One = DAG.getConstant(1, dl, VT);
2976 SDValue And = DAG.getNode(ISD::AND, dl, VT, Node->getOperand(0), One);
2977 SDValue Zero = DAG.getConstant(0, dl, VT);
2978 SDValue Neg = DAG.getNode(ISD::SUB, dl, VT, Zero, And);
2979 Results.push_back(Neg);
2983 // NOTE: we could fall back on load/store here too for targets without
2984 // SRA. However, it is doubtful that any exist.
2985 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2988 unsigned BitsDiff = VT.getScalarSizeInBits() -
2989 ExtraVT.getScalarSizeInBits();
2990 SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy);
2991 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2992 Node->getOperand(0), ShiftCst);
2993 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2994 Results.push_back(Tmp1);
2997 case ISD::FP_ROUND_INREG: {
2998 // The only way we can lower this is to turn it into a TRUNCSTORE,
2999 // EXTLOAD pair, targeting a temporary location (a stack slot).
3001 // NOTE: there is a choice here between constantly creating new stack
3002 // slots and always reusing the same one. We currently always create
3003 // new ones, as reuse may inhibit scheduling.
3004 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3005 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
3006 Node->getValueType(0), dl);
3007 Results.push_back(Tmp1);
3010 case ISD::SINT_TO_FP:
3011 case ISD::UINT_TO_FP:
3012 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
3013 Node->getOperand(0), Node->getValueType(0), dl);
3014 Results.push_back(Tmp1);
3016 case ISD::FP_TO_SINT:
3017 if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG))
3018 Results.push_back(Tmp1);
3020 case ISD::FP_TO_UINT: {
3021 SDValue True, False;
3022 EVT VT = Node->getOperand(0).getValueType();
3023 EVT NVT = Node->getValueType(0);
3024 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
3025 APInt::getNullValue(VT.getSizeInBits()));
3026 APInt x = APInt::getSignMask(NVT.getSizeInBits());
3027 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3028 Tmp1 = DAG.getConstantFP(apf, dl, VT);
3029 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
3030 Node->getOperand(0),
3032 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3033 // TODO: Should any fast-math-flags be set for the FSUB?
3034 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3035 DAG.getNode(ISD::FSUB, dl, VT,
3036 Node->getOperand(0), Tmp1));
3037 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3038 DAG.getConstant(x, dl, NVT));
3039 Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
3040 Results.push_back(Tmp1);
3044 Results.push_back(DAG.expandVAArg(Node));
3045 Results.push_back(Results[0].getValue(1));
3048 Results.push_back(DAG.expandVACopy(Node));
3050 case ISD::EXTRACT_VECTOR_ELT:
3051 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3052 // This must be an access of the only element. Return it.
3053 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3054 Node->getOperand(0));
3056 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3057 Results.push_back(Tmp1);
3059 case ISD::EXTRACT_SUBVECTOR:
3060 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3062 case ISD::INSERT_SUBVECTOR:
3063 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3065 case ISD::CONCAT_VECTORS: {
3066 Results.push_back(ExpandVectorBuildThroughStack(Node));
3069 case ISD::SCALAR_TO_VECTOR:
3070 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3072 case ISD::INSERT_VECTOR_ELT:
3073 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3074 Node->getOperand(1),
3075 Node->getOperand(2), dl));
3077 case ISD::VECTOR_SHUFFLE: {
3078 SmallVector<int, 32> NewMask;
3079 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3081 EVT VT = Node->getValueType(0);
3082 EVT EltVT = VT.getVectorElementType();
3083 SDValue Op0 = Node->getOperand(0);
3084 SDValue Op1 = Node->getOperand(1);
3085 if (!TLI.isTypeLegal(EltVT)) {
3087 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3089 // BUILD_VECTOR operands are allowed to be wider than the element type.
3090 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
3092 if (NewEltVT.bitsLT(EltVT)) {
3094 // Convert shuffle node.
3095 // If original node was v4i64 and the new EltVT is i32,
3096 // cast operands to v8i32 and re-build the mask.
3098 // Calculate new VT, the size of the new VT should be equal to original.
3100 EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3101 VT.getSizeInBits() / NewEltVT.getSizeInBits());
3102 assert(NewVT.bitsEq(VT));
3104 // cast operands to new VT
3105 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3106 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3108 // Convert the shuffle mask
3109 unsigned int factor =
3110 NewVT.getVectorNumElements()/VT.getVectorNumElements();
3112 // EltVT gets smaller
3115 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3117 for (unsigned fi = 0; fi < factor; ++fi)
3118 NewMask.push_back(Mask[i]);
3121 for (unsigned fi = 0; fi < factor; ++fi)
3122 NewMask.push_back(Mask[i]*factor+fi);
3130 unsigned NumElems = VT.getVectorNumElements();
3131 SmallVector<SDValue, 16> Ops;
3132 for (unsigned i = 0; i != NumElems; ++i) {
3134 Ops.push_back(DAG.getUNDEF(EltVT));
3137 unsigned Idx = Mask[i];
3139 Ops.push_back(DAG.getNode(
3140 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
3141 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
3143 Ops.push_back(DAG.getNode(
3144 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1,
3145 DAG.getConstant(Idx - NumElems, dl,
3146 TLI.getVectorIdxTy(DAG.getDataLayout()))));
3149 Tmp1 = DAG.getBuildVector(VT, dl, Ops);
3150 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3151 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3152 Results.push_back(Tmp1);
3155 case ISD::EXTRACT_ELEMENT: {
3156 EVT OpTy = Node->getOperand(0).getValueType();
3157 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3159 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3160 DAG.getConstant(OpTy.getSizeInBits() / 2, dl,
3161 TLI.getShiftAmountTy(
3162 Node->getOperand(0).getValueType(),
3163 DAG.getDataLayout())));
3164 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3167 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3168 Node->getOperand(0));
3170 Results.push_back(Tmp1);
3173 case ISD::STACKSAVE:
3174 // Expand to CopyFromReg if the target set
3175 // StackPointerRegisterToSaveRestore.
3176 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3177 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3178 Node->getValueType(0)));
3179 Results.push_back(Results[0].getValue(1));
3181 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3182 Results.push_back(Node->getOperand(0));
3185 case ISD::STACKRESTORE:
3186 // Expand to CopyToReg if the target set
3187 // StackPointerRegisterToSaveRestore.
3188 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3189 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3190 Node->getOperand(1)));
3192 Results.push_back(Node->getOperand(0));
3195 case ISD::GET_DYNAMIC_AREA_OFFSET:
3196 Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
3197 Results.push_back(Results[0].getValue(0));
3199 case ISD::FCOPYSIGN:
3200 Results.push_back(ExpandFCOPYSIGN(Node));
3203 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3204 Tmp1 = DAG.getConstantFP(-0.0, dl, Node->getValueType(0));
3205 // TODO: If FNEG has fast-math-flags, propagate them to the FSUB.
3206 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3207 Node->getOperand(0));
3208 Results.push_back(Tmp1);
3211 Results.push_back(ExpandFABS(Node));
3217 // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B
3219 switch (Node->getOpcode()) {
3220 default: llvm_unreachable("How did we get here?");
3221 case ISD::SMAX: Pred = ISD::SETGT; break;
3222 case ISD::SMIN: Pred = ISD::SETLT; break;
3223 case ISD::UMAX: Pred = ISD::SETUGT; break;
3224 case ISD::UMIN: Pred = ISD::SETULT; break;
3226 Tmp1 = Node->getOperand(0);
3227 Tmp2 = Node->getOperand(1);
3228 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp1, Tmp2, Pred);
3229 Results.push_back(Tmp1);
3235 EVT VT = Node->getValueType(0);
3236 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3237 // fcos which share the same operand and both are used.
3238 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3239 isSinCosLibcallAvailable(Node, TLI))
3240 && useSinCos(Node)) {
3241 SDVTList VTs = DAG.getVTList(VT, VT);
3242 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3243 if (Node->getOpcode() == ISD::FCOS)
3244 Tmp1 = Tmp1.getValue(1);
3245 Results.push_back(Tmp1);
3250 llvm_unreachable("Illegal fmad should never be formed");
3252 case ISD::FP16_TO_FP:
3253 if (Node->getValueType(0) != MVT::f32) {
3254 // We can extend to types bigger than f32 in two steps without changing
3255 // the result. Since "f16 -> f32" is much more commonly available, give
3256 // CodeGen the option of emitting that before resorting to a libcall.
3258 DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0));
3260 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res));
3263 case ISD::FP_TO_FP16:
3264 if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) {
3265 SDValue Op = Node->getOperand(0);
3266 MVT SVT = Op.getSimpleValueType();
3267 if ((SVT == MVT::f64 || SVT == MVT::f80) &&
3268 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) {
3269 // Under fastmath, we can expand this node into a fround followed by
3270 // a float-half conversion.
3271 SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
3272 DAG.getIntPtrConstant(0, dl));
3274 DAG.getNode(ISD::FP_TO_FP16, dl, Node->getValueType(0), FloatVal));
3278 case ISD::ConstantFP: {
3279 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3280 // Check to see if this FP immediate is already legal.
3281 // If this is a legal constant, turn it into a TargetConstantFP node.
3282 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3283 Results.push_back(ExpandConstantFP(CFP, true));
3286 case ISD::Constant: {
3287 ConstantSDNode *CP = cast<ConstantSDNode>(Node);
3288 Results.push_back(ExpandConstant(CP));
3292 EVT VT = Node->getValueType(0);
3293 if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3294 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3295 const SDNodeFlags Flags = Node->getFlags();
3296 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3297 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1, Flags);
3298 Results.push_back(Tmp1);
3303 EVT VT = Node->getValueType(0);
3304 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3305 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3306 "Don't know how to expand this subtraction!");
3307 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3308 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
3310 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT));
3311 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3316 EVT VT = Node->getValueType(0);
3317 bool isSigned = Node->getOpcode() == ISD::SREM;
3318 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3319 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3320 Tmp2 = Node->getOperand(0);
3321 Tmp3 = Node->getOperand(1);
3322 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3323 SDVTList VTs = DAG.getVTList(VT, VT);
3324 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3325 Results.push_back(Tmp1);
3326 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3328 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3329 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3330 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3331 Results.push_back(Tmp1);
3337 bool isSigned = Node->getOpcode() == ISD::SDIV;
3338 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3339 EVT VT = Node->getValueType(0);
3340 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3341 SDVTList VTs = DAG.getVTList(VT, VT);
3342 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3343 Node->getOperand(1));
3344 Results.push_back(Tmp1);
3350 unsigned ExpandOpcode =
3351 Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : ISD::SMUL_LOHI;
3352 EVT VT = Node->getValueType(0);
3353 SDVTList VTs = DAG.getVTList(VT, VT);
3355 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3356 Node->getOperand(1));
3357 Results.push_back(Tmp1.getValue(1));
3360 case ISD::UMUL_LOHI:
3361 case ISD::SMUL_LOHI: {
3362 SDValue LHS = Node->getOperand(0);
3363 SDValue RHS = Node->getOperand(1);
3364 MVT VT = LHS.getSimpleValueType();
3365 unsigned MULHOpcode =
3366 Node->getOpcode() == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS;
3368 if (TLI.isOperationLegalOrCustom(MULHOpcode, VT)) {
3369 Results.push_back(DAG.getNode(ISD::MUL, dl, VT, LHS, RHS));
3370 Results.push_back(DAG.getNode(MULHOpcode, dl, VT, LHS, RHS));
3374 SmallVector<SDValue, 4> Halves;
3375 EVT HalfType = EVT(VT).getHalfSizedIntegerVT(*DAG.getContext());
3376 assert(TLI.isTypeLegal(HalfType));
3377 if (TLI.expandMUL_LOHI(Node->getOpcode(), VT, Node, LHS, RHS, Halves,
3379 TargetLowering::MulExpansionKind::Always)) {
3380 for (unsigned i = 0; i < 2; ++i) {
3381 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Halves[2 * i]);
3382 SDValue Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Halves[2 * i + 1]);
3383 SDValue Shift = DAG.getConstant(
3384 HalfType.getScalarSizeInBits(), dl,
3385 TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3386 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3387 Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3394 EVT VT = Node->getValueType(0);
3395 SDVTList VTs = DAG.getVTList(VT, VT);
3396 // See if multiply or divide can be lowered using two-result operations.
3397 // We just need the low half of the multiply; try both the signed
3398 // and unsigned forms. If the target supports both SMUL_LOHI and
3399 // UMUL_LOHI, form a preference by checking which forms of plain
3400 // MULH it supports.
3401 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3402 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3403 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3404 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3405 unsigned OpToUse = 0;
3406 if (HasSMUL_LOHI && !HasMULHS) {
3407 OpToUse = ISD::SMUL_LOHI;
3408 } else if (HasUMUL_LOHI && !HasMULHU) {
3409 OpToUse = ISD::UMUL_LOHI;
3410 } else if (HasSMUL_LOHI) {
3411 OpToUse = ISD::SMUL_LOHI;
3412 } else if (HasUMUL_LOHI) {
3413 OpToUse = ISD::UMUL_LOHI;
3416 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3417 Node->getOperand(1)));
3422 EVT HalfType = VT.getHalfSizedIntegerVT(*DAG.getContext());
3423 if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3424 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3425 TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3426 TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3427 TLI.expandMUL(Node, Lo, Hi, HalfType, DAG,
3428 TargetLowering::MulExpansionKind::OnlyLegalOrCustom)) {
3429 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3430 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3432 DAG.getConstant(HalfType.getSizeInBits(), dl,
3433 TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3434 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3435 Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3441 SDValue LHS = Node->getOperand(0);
3442 SDValue RHS = Node->getOperand(1);
3443 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3444 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3446 Results.push_back(Sum);
3447 EVT ResultType = Node->getValueType(1);
3448 EVT OType = getSetCCResultType(Node->getValueType(0));
3450 SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
3452 // LHSSign -> LHS >= 0
3453 // RHSSign -> RHS >= 0
3454 // SumSign -> Sum >= 0
3457 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3459 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3461 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3462 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3463 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3464 Node->getOpcode() == ISD::SADDO ?
3465 ISD::SETEQ : ISD::SETNE);
3467 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3468 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3470 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3471 Results.push_back(DAG.getBoolExtOrTrunc(Cmp, dl, ResultType, ResultType));
3476 SDValue LHS = Node->getOperand(0);
3477 SDValue RHS = Node->getOperand(1);
3478 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3479 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3481 Results.push_back(Sum);
3483 EVT ResultType = Node->getValueType(1);
3484 EVT SetCCType = getSetCCResultType(Node->getValueType(0));
3486 = Node->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT;
3487 SDValue SetCC = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC);
3489 Results.push_back(DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType));
3494 EVT VT = Node->getValueType(0);
3495 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3496 SDValue LHS = Node->getOperand(0);
3497 SDValue RHS = Node->getOperand(1);
3500 static const unsigned Ops[2][3] =
3501 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3502 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3503 bool isSigned = Node->getOpcode() == ISD::SMULO;
3504 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3505 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3506 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3507 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3508 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3510 TopHalf = BottomHalf.getValue(1);
3511 } else if (TLI.isTypeLegal(WideVT)) {
3512 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3513 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3514 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3515 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3516 DAG.getIntPtrConstant(0, dl));
3517 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3518 DAG.getIntPtrConstant(1, dl));
3520 // We can fall back to a libcall with an illegal type for the MUL if we
3521 // have a libcall big enough.
3522 // Also, we can fall back to a division in some cases, but that's a big
3523 // performance hit in the general case.
3524 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3525 if (WideVT == MVT::i16)
3526 LC = RTLIB::MUL_I16;
3527 else if (WideVT == MVT::i32)
3528 LC = RTLIB::MUL_I32;
3529 else if (WideVT == MVT::i64)
3530 LC = RTLIB::MUL_I64;
3531 else if (WideVT == MVT::i128)
3532 LC = RTLIB::MUL_I128;
3533 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3538 // The high part is obtained by SRA'ing all but one of the bits of low
3540 unsigned LoSize = VT.getSizeInBits();
3542 DAG.getNode(ISD::SRA, dl, VT, LHS,
3543 DAG.getConstant(LoSize - 1, dl,
3544 TLI.getPointerTy(DAG.getDataLayout())));
3546 DAG.getNode(ISD::SRA, dl, VT, RHS,
3547 DAG.getConstant(LoSize - 1, dl,
3548 TLI.getPointerTy(DAG.getDataLayout())));
3550 HiLHS = DAG.getConstant(0, dl, VT);
3551 HiRHS = DAG.getConstant(0, dl, VT);
3554 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3555 // pre-lowered to the correct types. This all depends upon WideVT not
3556 // being a legal type for the architecture and thus has to be split to
3559 if(DAG.getDataLayout().isLittleEndian()) {
3560 // Halves of WideVT are packed into registers in different order
3561 // depending on platform endianness. This is usually handled by
3562 // the C calling convention, but we can't defer to it in
3564 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3565 Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3567 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
3568 Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3570 assert(Ret.getOpcode() == ISD::MERGE_VALUES &&
3571 "Ret value is a collection of constituent nodes holding result.");
3572 BottomHalf = Ret.getOperand(0);
3573 TopHalf = Ret.getOperand(1);
3577 Tmp1 = DAG.getConstant(
3578 VT.getSizeInBits() - 1, dl,
3579 TLI.getShiftAmountTy(BottomHalf.getValueType(), DAG.getDataLayout()));
3580 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3581 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3584 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3585 DAG.getConstant(0, dl, VT), ISD::SETNE);
3588 // Truncate the result if SetCC returns a larger type than needed.
3589 EVT RType = Node->getValueType(1);
3590 if (RType.getSizeInBits() < TopHalf.getValueSizeInBits())
3591 TopHalf = DAG.getNode(ISD::TRUNCATE, dl, RType, TopHalf);
3593 assert(RType.getSizeInBits() == TopHalf.getValueSizeInBits() &&
3594 "Unexpected result type for S/UMULO legalization");
3596 Results.push_back(BottomHalf);
3597 Results.push_back(TopHalf);
3600 case ISD::BUILD_PAIR: {
3601 EVT PairTy = Node->getValueType(0);
3602 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3603 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3605 ISD::SHL, dl, PairTy, Tmp2,
3606 DAG.getConstant(PairTy.getSizeInBits() / 2, dl,
3607 TLI.getShiftAmountTy(PairTy, DAG.getDataLayout())));
3608 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3612 Tmp1 = Node->getOperand(0);
3613 Tmp2 = Node->getOperand(1);
3614 Tmp3 = Node->getOperand(2);
3615 if (Tmp1.getOpcode() == ISD::SETCC) {
3616 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3618 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3620 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3621 DAG.getConstant(0, dl, Tmp1.getValueType()),
3622 Tmp2, Tmp3, ISD::SETNE);
3624 Results.push_back(Tmp1);
3627 SDValue Chain = Node->getOperand(0);
3628 SDValue Table = Node->getOperand(1);
3629 SDValue Index = Node->getOperand(2);
3631 const DataLayout &TD = DAG.getDataLayout();
3632 EVT PTy = TLI.getPointerTy(TD);
3634 unsigned EntrySize =
3635 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3637 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
3638 DAG.getConstant(EntrySize, dl, Index.getValueType()));
3639 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3642 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3643 SDValue LD = DAG.getExtLoad(
3644 ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3645 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()), MemVT);
3647 if (TLI.isJumpTableRelative()) {
3648 // For PIC, the sequence is:
3649 // BRIND(load(Jumptable + index) + RelocBase)
3650 // RelocBase can be JumpTable, GOT or some sort of global base.
3651 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3652 TLI.getPICJumpTableRelocBase(Table, DAG));
3654 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3655 Results.push_back(Tmp1);
3659 // Expand brcond's setcc into its constituent parts and create a BR_CC
3661 Tmp1 = Node->getOperand(0);
3662 Tmp2 = Node->getOperand(1);
3663 if (Tmp2.getOpcode() == ISD::SETCC) {
3664 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3665 Tmp1, Tmp2.getOperand(2),
3666 Tmp2.getOperand(0), Tmp2.getOperand(1),
3667 Node->getOperand(2));
3669 // We test only the i1 bit. Skip the AND if UNDEF.
3670 Tmp3 = (Tmp2.isUndef()) ? Tmp2 :
3671 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3672 DAG.getConstant(1, dl, Tmp2.getValueType()));
3673 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3674 DAG.getCondCode(ISD::SETNE), Tmp3,
3675 DAG.getConstant(0, dl, Tmp3.getValueType()),
3676 Node->getOperand(2));
3678 Results.push_back(Tmp1);
3681 Tmp1 = Node->getOperand(0);
3682 Tmp2 = Node->getOperand(1);
3683 Tmp3 = Node->getOperand(2);
3684 bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3685 Tmp3, NeedInvert, dl);
3688 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3689 // condition code, create a new SETCC node.
3691 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3694 // If we expanded the SETCC by inverting the condition code, then wrap
3695 // the existing SETCC in a NOT to restore the intended condition.
3697 Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
3699 Results.push_back(Tmp1);
3703 // Otherwise, SETCC for the given comparison type must be completely
3704 // illegal; expand it into a SELECT_CC.
3705 EVT VT = Node->getValueType(0);
3707 switch (TLI.getBooleanContents(Tmp1->getValueType(0))) {
3708 case TargetLowering::ZeroOrOneBooleanContent:
3709 case TargetLowering::UndefinedBooleanContent:
3712 case TargetLowering::ZeroOrNegativeOneBooleanContent:
3716 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3717 DAG.getConstant(TrueValue, dl, VT),
3718 DAG.getConstant(0, dl, VT),
3720 Results.push_back(Tmp1);
3723 case ISD::SELECT_CC: {
3724 Tmp1 = Node->getOperand(0); // LHS
3725 Tmp2 = Node->getOperand(1); // RHS
3726 Tmp3 = Node->getOperand(2); // True
3727 Tmp4 = Node->getOperand(3); // False
3728 EVT VT = Node->getValueType(0);
3729 SDValue CC = Node->getOperand(4);
3730 ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
3732 if (TLI.isCondCodeLegal(CCOp, Tmp1.getSimpleValueType())) {
3733 // If the condition code is legal, then we need to expand this
3734 // node using SETCC and SELECT.
3735 EVT CmpVT = Tmp1.getValueType();
3736 assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
3737 "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
3740 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), CmpVT);
3741 SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC);
3742 Results.push_back(DAG.getSelect(dl, VT, Cond, Tmp3, Tmp4));
3746 // SELECT_CC is legal, so the condition code must not be.
3747 bool Legalized = false;
3748 // Try to legalize by inverting the condition. This is for targets that
3749 // might support an ordered version of a condition, but not the unordered
3750 // version (or vice versa).
3751 ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
3752 Tmp1.getValueType().isInteger());
3753 if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) {
3754 // Use the new condition code and swap true and false
3756 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3758 // If The inverse is not legal, then try to swap the arguments using
3759 // the inverse condition code.
3760 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3761 if (TLI.isCondCodeLegal(SwapInvCC, Tmp1.getSimpleValueType())) {
3762 // The swapped inverse condition is legal, so swap true and false,
3765 Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3770 Legalized = LegalizeSetCCCondCode(
3771 getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3774 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3776 // If we expanded the SETCC by inverting the condition code, then swap
3777 // the True/False operands to match.
3779 std::swap(Tmp3, Tmp4);
3781 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3782 // condition code, create a new SELECT_CC node.
3784 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3785 Tmp1, Tmp2, Tmp3, Tmp4, CC);
3787 Tmp2 = DAG.getConstant(0, dl, Tmp1.getValueType());
3788 CC = DAG.getCondCode(ISD::SETNE);
3789 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
3790 Tmp2, Tmp3, Tmp4, CC);
3793 Results.push_back(Tmp1);
3797 Tmp1 = Node->getOperand(0); // Chain
3798 Tmp2 = Node->getOperand(2); // LHS
3799 Tmp3 = Node->getOperand(3); // RHS
3800 Tmp4 = Node->getOperand(1); // CC
3802 bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
3803 Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
3805 assert(Legalized && "Can't legalize BR_CC with legal condition!");
3807 // If we expanded the SETCC by inverting the condition code, then wrap
3808 // the existing SETCC in a NOT to restore the intended condition.
3810 Tmp4 = DAG.getNOT(dl, Tmp4, Tmp4->getValueType(0));
3812 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
3814 if (Tmp4.getNode()) {
3815 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
3816 Tmp4, Tmp2, Tmp3, Node->getOperand(4));
3818 Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType());
3819 Tmp4 = DAG.getCondCode(ISD::SETNE);
3820 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
3821 Tmp2, Tmp3, Node->getOperand(4));
3823 Results.push_back(Tmp1);
3826 case ISD::BUILD_VECTOR:
3827 Results.push_back(ExpandBUILD_VECTOR(Node));
3832 // Scalarize vector SRA/SRL/SHL.
3833 EVT VT = Node->getValueType(0);
3834 assert(VT.isVector() && "Unable to legalize non-vector shift");
3835 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3836 unsigned NumElem = VT.getVectorNumElements();
3838 SmallVector<SDValue, 8> Scalars;
3839 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3840 SDValue Ex = DAG.getNode(
3841 ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(0),
3842 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3843 SDValue Sh = DAG.getNode(
3844 ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(1),
3845 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3846 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3847 VT.getScalarType(), Ex, Sh));
3850 SDValue Result = DAG.getBuildVector(Node->getValueType(0), dl, Scalars);
3851 ReplaceNode(SDValue(Node, 0), Result);
3854 case ISD::GLOBAL_OFFSET_TABLE:
3855 case ISD::GlobalAddress:
3856 case ISD::GlobalTLSAddress:
3857 case ISD::ExternalSymbol:
3858 case ISD::ConstantPool:
3859 case ISD::JumpTable:
3860 case ISD::INTRINSIC_W_CHAIN:
3861 case ISD::INTRINSIC_WO_CHAIN:
3862 case ISD::INTRINSIC_VOID:
3863 // FIXME: Custom lowering for these operations shouldn't return null!
3867 // Replace the original node with the legalized result.
3868 if (Results.empty())
3871 ReplaceNode(Node, Results.data());
3875 void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
3876 SmallVector<SDValue, 8> Results;
3878 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
3879 unsigned Opc = Node->getOpcode();
3881 case ISD::ATOMIC_FENCE: {
3882 // If the target didn't lower this, lower it to '__sync_synchronize()' call
3883 // FIXME: handle "fence singlethread" more efficiently.
3884 TargetLowering::ArgListTy Args;
3886 TargetLowering::CallLoweringInfo CLI(DAG);
3888 .setChain(Node->getOperand(0))
3890 CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3891 DAG.getExternalSymbol("__sync_synchronize",
3892 TLI.getPointerTy(DAG.getDataLayout())),
3895 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3897 Results.push_back(CallResult.second);
3900 // By default, atomic intrinsics are marked Legal and lowered. Targets
3901 // which don't support them directly, however, may want libcalls, in which
3902 // case they mark them Expand, and we get here.
3903 case ISD::ATOMIC_SWAP:
3904 case ISD::ATOMIC_LOAD_ADD:
3905 case ISD::ATOMIC_LOAD_SUB:
3906 case ISD::ATOMIC_LOAD_AND:
3907 case ISD::ATOMIC_LOAD_OR:
3908 case ISD::ATOMIC_LOAD_XOR:
3909 case ISD::ATOMIC_LOAD_NAND:
3910 case ISD::ATOMIC_LOAD_MIN:
3911 case ISD::ATOMIC_LOAD_MAX:
3912 case ISD::ATOMIC_LOAD_UMIN:
3913 case ISD::ATOMIC_LOAD_UMAX:
3914 case ISD::ATOMIC_CMP_SWAP: {
3915 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
3916 RTLIB::Libcall LC = RTLIB::getSYNC(Opc, VT);
3917 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
3919 std::pair<SDValue, SDValue> Tmp = ExpandChainLibCall(LC, Node, false);
3920 Results.push_back(Tmp.first);
3921 Results.push_back(Tmp.second);
3925 // If this operation is not supported, lower it to 'abort()' call
3926 TargetLowering::ArgListTy Args;
3927 TargetLowering::CallLoweringInfo CLI(DAG);
3929 .setChain(Node->getOperand(0))
3930 .setLibCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3931 DAG.getExternalSymbol(
3932 "abort", TLI.getPointerTy(DAG.getDataLayout())),
3934 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3936 Results.push_back(CallResult.second);
3940 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
3941 RTLIB::FMIN_F80, RTLIB::FMIN_F128,
3942 RTLIB::FMIN_PPCF128));
3945 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
3946 RTLIB::FMAX_F80, RTLIB::FMAX_F128,
3947 RTLIB::FMAX_PPCF128));
3950 case ISD::STRICT_FSQRT:
3951 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3952 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3953 RTLIB::SQRT_PPCF128));
3956 case ISD::STRICT_FSIN:
3957 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3958 RTLIB::SIN_F80, RTLIB::SIN_F128,
3959 RTLIB::SIN_PPCF128));
3962 case ISD::STRICT_FCOS:
3963 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3964 RTLIB::COS_F80, RTLIB::COS_F128,
3965 RTLIB::COS_PPCF128));
3968 // Expand into sincos libcall.
3969 ExpandSinCosLibCall(Node, Results);
3972 case ISD::STRICT_FLOG:
3973 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3974 RTLIB::LOG_F80, RTLIB::LOG_F128,
3975 RTLIB::LOG_PPCF128));
3978 case ISD::STRICT_FLOG2:
3979 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3980 RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3981 RTLIB::LOG2_PPCF128));
3984 case ISD::STRICT_FLOG10:
3985 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3986 RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3987 RTLIB::LOG10_PPCF128));
3990 case ISD::STRICT_FEXP:
3991 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3992 RTLIB::EXP_F80, RTLIB::EXP_F128,
3993 RTLIB::EXP_PPCF128));
3996 case ISD::STRICT_FEXP2:
3997 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3998 RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3999 RTLIB::EXP2_PPCF128));
4002 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
4003 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
4004 RTLIB::TRUNC_PPCF128));
4007 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
4008 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
4009 RTLIB::FLOOR_PPCF128));
4012 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
4013 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
4014 RTLIB::CEIL_PPCF128));
4017 case ISD::STRICT_FRINT:
4018 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
4019 RTLIB::RINT_F80, RTLIB::RINT_F128,
4020 RTLIB::RINT_PPCF128));
4022 case ISD::FNEARBYINT:
4023 case ISD::STRICT_FNEARBYINT:
4024 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
4025 RTLIB::NEARBYINT_F64,
4026 RTLIB::NEARBYINT_F80,
4027 RTLIB::NEARBYINT_F128,
4028 RTLIB::NEARBYINT_PPCF128));
4031 Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
4035 RTLIB::ROUND_PPCF128));
4038 case ISD::STRICT_FPOWI:
4039 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
4040 RTLIB::POWI_F80, RTLIB::POWI_F128,
4041 RTLIB::POWI_PPCF128));
4044 case ISD::STRICT_FPOW:
4045 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
4046 RTLIB::POW_F80, RTLIB::POW_F128,
4047 RTLIB::POW_PPCF128));
4050 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
4051 RTLIB::DIV_F80, RTLIB::DIV_F128,
4052 RTLIB::DIV_PPCF128));
4055 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
4056 RTLIB::REM_F80, RTLIB::REM_F128,
4057 RTLIB::REM_PPCF128));
4060 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
4061 RTLIB::FMA_F80, RTLIB::FMA_F128,
4062 RTLIB::FMA_PPCF128));
4065 Results.push_back(ExpandFPLibCall(Node, RTLIB::ADD_F32, RTLIB::ADD_F64,
4066 RTLIB::ADD_F80, RTLIB::ADD_F128,
4067 RTLIB::ADD_PPCF128));
4070 Results.push_back(ExpandFPLibCall(Node, RTLIB::MUL_F32, RTLIB::MUL_F64,
4071 RTLIB::MUL_F80, RTLIB::MUL_F128,
4072 RTLIB::MUL_PPCF128));
4074 case ISD::FP16_TO_FP:
4075 if (Node->getValueType(0) == MVT::f32) {
4076 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
4079 case ISD::FP_TO_FP16: {
4081 RTLIB::getFPROUND(Node->getOperand(0).getValueType(), MVT::f16);
4082 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_fp16");
4083 Results.push_back(ExpandLibCall(LC, Node, false));
4087 Results.push_back(ExpandFPLibCall(Node, RTLIB::SUB_F32, RTLIB::SUB_F64,
4088 RTLIB::SUB_F80, RTLIB::SUB_F128,
4089 RTLIB::SUB_PPCF128));
4092 Results.push_back(ExpandIntLibCall(Node, true,
4094 RTLIB::SREM_I16, RTLIB::SREM_I32,
4095 RTLIB::SREM_I64, RTLIB::SREM_I128));
4098 Results.push_back(ExpandIntLibCall(Node, false,
4100 RTLIB::UREM_I16, RTLIB::UREM_I32,
4101 RTLIB::UREM_I64, RTLIB::UREM_I128));
4104 Results.push_back(ExpandIntLibCall(Node, true,
4106 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
4107 RTLIB::SDIV_I64, RTLIB::SDIV_I128));
4110 Results.push_back(ExpandIntLibCall(Node, false,
4112 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
4113 RTLIB::UDIV_I64, RTLIB::UDIV_I128));
4117 // Expand into divrem libcall
4118 ExpandDivRemLibCall(Node, Results);
4121 Results.push_back(ExpandIntLibCall(Node, false,
4123 RTLIB::MUL_I16, RTLIB::MUL_I32,
4124 RTLIB::MUL_I64, RTLIB::MUL_I128));
4128 // Replace the original node with the legalized result.
4129 if (!Results.empty())
4130 ReplaceNode(Node, Results.data());
4133 // Determine the vector type to use in place of an original scalar element when
4134 // promoting equally sized vectors.
4135 static MVT getPromotedVectorElementType(const TargetLowering &TLI,
4136 MVT EltVT, MVT NewEltVT) {
4137 unsigned OldEltsPerNewElt = EltVT.getSizeInBits() / NewEltVT.getSizeInBits();
4138 MVT MidVT = MVT::getVectorVT(NewEltVT, OldEltsPerNewElt);
4139 assert(TLI.isTypeLegal(MidVT) && "unexpected");
4143 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
4144 SmallVector<SDValue, 8> Results;
4145 MVT OVT = Node->getSimpleValueType(0);
4146 if (Node->getOpcode() == ISD::UINT_TO_FP ||
4147 Node->getOpcode() == ISD::SINT_TO_FP ||
4148 Node->getOpcode() == ISD::SETCC ||
4149 Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
4150 Node->getOpcode() == ISD::INSERT_VECTOR_ELT) {
4151 OVT = Node->getOperand(0).getSimpleValueType();
4153 if (Node->getOpcode() == ISD::BR_CC)
4154 OVT = Node->getOperand(2).getSimpleValueType();
4155 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
4157 SDValue Tmp1, Tmp2, Tmp3;
4158 switch (Node->getOpcode()) {
4160 case ISD::CTTZ_ZERO_UNDEF:
4162 case ISD::CTLZ_ZERO_UNDEF:
4164 // Zero extend the argument.
4165 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4166 if (Node->getOpcode() == ISD::CTTZ) {
4167 // The count is the same in the promoted type except if the original
4168 // value was zero. This can be handled by setting the bit just off
4169 // the top of the original type.
4170 auto TopBit = APInt::getOneBitSet(NVT.getSizeInBits(),
4171 OVT.getSizeInBits());
4172 Tmp1 = DAG.getNode(ISD::OR, dl, NVT, Tmp1,
4173 DAG.getConstant(TopBit, dl, NVT));
4175 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
4176 // already the correct result.
4177 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4178 if (Node->getOpcode() == ISD::CTLZ ||
4179 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4180 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4181 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4182 DAG.getConstant(NVT.getSizeInBits() -
4183 OVT.getSizeInBits(), dl, NVT));
4185 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4187 case ISD::BITREVERSE:
4189 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
4190 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4191 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4193 ISD::SRL, dl, NVT, Tmp1,
4194 DAG.getConstant(DiffBits, dl,
4195 TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
4196 Results.push_back(Tmp1);
4199 case ISD::FP_TO_UINT:
4200 case ISD::FP_TO_SINT:
4201 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
4202 Node->getOpcode() == ISD::FP_TO_SINT, dl);
4203 Results.push_back(Tmp1);
4205 case ISD::UINT_TO_FP:
4206 case ISD::SINT_TO_FP:
4207 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
4208 Node->getOpcode() == ISD::SINT_TO_FP, dl);
4209 Results.push_back(Tmp1);
4212 SDValue Chain = Node->getOperand(0); // Get the chain.
4213 SDValue Ptr = Node->getOperand(1); // Get the pointer.
4216 if (OVT.isVector()) {
4217 TruncOp = ISD::BITCAST;
4219 assert(OVT.isInteger()
4220 && "VAARG promotion is supported only for vectors or integer types");
4221 TruncOp = ISD::TRUNCATE;
4224 // Perform the larger operation, then convert back
4225 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
4226 Node->getConstantOperandVal(3));
4227 Chain = Tmp1.getValue(1);
4229 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
4231 // Modified the chain result - switch anything that used the old chain to
4233 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
4234 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4236 UpdatedNodes->insert(Tmp2.getNode());
4237 UpdatedNodes->insert(Chain.getNode());
4250 unsigned ExtOp, TruncOp;
4251 if (OVT.isVector()) {
4252 ExtOp = ISD::BITCAST;
4253 TruncOp = ISD::BITCAST;
4255 assert(OVT.isInteger() && "Cannot promote logic operation");
4257 switch (Node->getOpcode()) {
4259 ExtOp = ISD::ANY_EXTEND;
4263 ExtOp = ISD::SIGN_EXTEND;
4267 ExtOp = ISD::ZERO_EXTEND;
4270 TruncOp = ISD::TRUNCATE;
4272 // Promote each of the values to the new type.
4273 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4274 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4275 // Perform the larger operation, then convert back
4276 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4277 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4280 case ISD::UMUL_LOHI:
4281 case ISD::SMUL_LOHI: {
4282 // Promote to a multiply in a wider integer type.
4283 unsigned ExtOp = Node->getOpcode() == ISD::UMUL_LOHI ? ISD::ZERO_EXTEND
4285 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4286 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4287 Tmp1 = DAG.getNode(ISD::MUL, dl, NVT, Tmp1, Tmp2);
4289 auto &DL = DAG.getDataLayout();
4290 unsigned OriginalSize = OVT.getScalarSizeInBits();
4292 ISD::SRL, dl, NVT, Tmp1,
4293 DAG.getConstant(OriginalSize, dl, TLI.getScalarShiftAmountTy(DL, NVT)));
4294 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4295 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp2));
4299 unsigned ExtOp, TruncOp;
4300 if (Node->getValueType(0).isVector() ||
4301 Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4302 ExtOp = ISD::BITCAST;
4303 TruncOp = ISD::BITCAST;
4304 } else if (Node->getValueType(0).isInteger()) {
4305 ExtOp = ISD::ANY_EXTEND;
4306 TruncOp = ISD::TRUNCATE;
4308 ExtOp = ISD::FP_EXTEND;
4309 TruncOp = ISD::FP_ROUND;
4311 Tmp1 = Node->getOperand(0);
4312 // Promote each of the values to the new type.
4313 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4314 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4315 // Perform the larger operation, then round down.
4316 Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4317 if (TruncOp != ISD::FP_ROUND)
4318 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4320 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4321 DAG.getIntPtrConstant(0, dl));
4322 Results.push_back(Tmp1);
4325 case ISD::VECTOR_SHUFFLE: {
4326 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4328 // Cast the two input vectors.
4329 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4330 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4332 // Convert the shuffle mask to the right # elements.
4333 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4334 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4335 Results.push_back(Tmp1);
4339 unsigned ExtOp = ISD::FP_EXTEND;
4340 if (NVT.isInteger()) {
4341 ISD::CondCode CCCode =
4342 cast<CondCodeSDNode>(Node->getOperand(2))->get();
4343 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4345 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4346 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4347 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4348 Tmp1, Tmp2, Node->getOperand(2)));
4352 unsigned ExtOp = ISD::FP_EXTEND;
4353 if (NVT.isInteger()) {
4354 ISD::CondCode CCCode =
4355 cast<CondCodeSDNode>(Node->getOperand(1))->get();
4356 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4358 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4359 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(3));
4360 Results.push_back(DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0),
4361 Node->getOperand(0), Node->getOperand(1),
4362 Tmp1, Tmp2, Node->getOperand(4)));
4373 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4374 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4375 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2,
4377 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4378 Tmp3, DAG.getIntPtrConstant(0, dl)));
4382 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4383 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4384 Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2));
4386 DAG.getNode(ISD::FP_ROUND, dl, OVT,
4387 DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3),
4388 DAG.getIntPtrConstant(0, dl)));
4391 case ISD::FCOPYSIGN:
4393 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4394 Tmp2 = Node->getOperand(1);
4395 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4397 // fcopysign doesn't change anything but the sign bit, so
4398 // (fp_round (fcopysign (fpext a), b))
4400 // (fp_round (fpext a))
4401 // which is a no-op. Mark it as a TRUNCating FP_ROUND.
4402 const bool isTrunc = (Node->getOpcode() == ISD::FCOPYSIGN);
4403 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4404 Tmp3, DAG.getIntPtrConstant(isTrunc, dl)));
4410 case ISD::FNEARBYINT:
4423 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4424 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4425 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4426 Tmp2, DAG.getIntPtrConstant(0, dl)));
4429 case ISD::BUILD_VECTOR: {
4430 MVT EltVT = OVT.getVectorElementType();
4431 MVT NewEltVT = NVT.getVectorElementType();
4433 // Handle bitcasts to a different vector type with the same total bit size
4435 // e.g. v2i64 = build_vector i64:x, i64:y => v4i32
4437 // v4i32 = concat_vectors (v2i32 (bitcast i64:x)), (v2i32 (bitcast i64:y))
4439 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4440 "Invalid promote type for build_vector");
4441 assert(NewEltVT.bitsLT(EltVT) && "not handled");
4443 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4445 SmallVector<SDValue, 8> NewOps;
4446 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) {
4447 SDValue Op = Node->getOperand(I);
4448 NewOps.push_back(DAG.getNode(ISD::BITCAST, SDLoc(Op), MidVT, Op));
4452 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps);
4453 SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4454 Results.push_back(CvtVec);
4457 case ISD::EXTRACT_VECTOR_ELT: {
4458 MVT EltVT = OVT.getVectorElementType();
4459 MVT NewEltVT = NVT.getVectorElementType();
4461 // Handle bitcasts to a different vector type with the same total bit size.
4463 // e.g. v2i64 = extract_vector_elt x:v2i64, y:i32
4465 // v4i32:castx = bitcast x:v2i64
4468 // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))),
4469 // (i32 (extract_vector_elt castx, (2 * y + 1)))
4472 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4473 "Invalid promote type for extract_vector_elt");
4474 assert(NewEltVT.bitsLT(EltVT) && "not handled");
4476 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4477 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4479 SDValue Idx = Node->getOperand(1);
4480 EVT IdxVT = Idx.getValueType();
4482 SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SL, IdxVT);
4483 SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4485 SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4487 SmallVector<SDValue, 8> NewOps;
4488 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4489 SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4490 SDValue TmpIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4492 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4494 NewOps.push_back(Elt);
4497 SDValue NewVec = DAG.getBuildVector(MidVT, SL, NewOps);
4498 Results.push_back(DAG.getNode(ISD::BITCAST, SL, EltVT, NewVec));
4501 case ISD::INSERT_VECTOR_ELT: {
4502 MVT EltVT = OVT.getVectorElementType();
4503 MVT NewEltVT = NVT.getVectorElementType();
4505 // Handle bitcasts to a different vector type with the same total bit size
4507 // e.g. v2i64 = insert_vector_elt x:v2i64, y:i64, z:i32
4509 // v4i32:castx = bitcast x:v2i64
4510 // v2i32:casty = bitcast y:i64
4513 // (v4i32 insert_vector_elt
4514 // (v4i32 insert_vector_elt v4i32:castx,
4515 // (extract_vector_elt casty, 0), 2 * z),
4516 // (extract_vector_elt casty, 1), (2 * z + 1))
4518 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4519 "Invalid promote type for insert_vector_elt");
4520 assert(NewEltVT.bitsLT(EltVT) && "not handled");
4522 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4523 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4525 SDValue Val = Node->getOperand(1);
4526 SDValue Idx = Node->getOperand(2);
4527 EVT IdxVT = Idx.getValueType();
4530 SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SDLoc(), IdxVT);
4531 SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4533 SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4534 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4536 SDValue NewVec = CastVec;
4537 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4538 SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4539 SDValue InEltIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4541 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4542 CastVal, IdxOffset);
4544 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT,
4545 NewVec, Elt, InEltIdx);
4548 Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewVec));
4551 case ISD::SCALAR_TO_VECTOR: {
4552 MVT EltVT = OVT.getVectorElementType();
4553 MVT NewEltVT = NVT.getVectorElementType();
4555 // Handle bitcasts to different vector type with the same total bit size.
4557 // e.g. v2i64 = scalar_to_vector x:i64
4559 // concat_vectors (v2i32 bitcast x:i64), (v2i32 undef)
4562 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4563 SDValue Val = Node->getOperand(0);
4566 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4567 SDValue Undef = DAG.getUNDEF(MidVT);
4569 SmallVector<SDValue, 8> NewElts;
4570 NewElts.push_back(CastVal);
4571 for (unsigned I = 1, NElts = OVT.getVectorNumElements(); I != NElts; ++I)
4572 NewElts.push_back(Undef);
4574 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts);
4575 SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4576 Results.push_back(CvtVec);
4581 // Replace the original node with the legalized result.
4582 if (!Results.empty())
4583 ReplaceNode(Node, Results.data());
4586 /// This is the entry point for the file.
4587 void SelectionDAG::Legalize() {
4588 AssignTopologicalOrder();
4590 SmallPtrSet<SDNode *, 16> LegalizedNodes;
4591 // Use a delete listener to remove nodes which were deleted during
4592 // legalization from LegalizeNodes. This is needed to handle the situation
4593 // where a new node is allocated by the object pool to the same address of a
4594 // previously deleted node.
4595 DAGNodeDeletedListener DeleteListener(
4597 [&LegalizedNodes](SDNode *N, SDNode *E) { LegalizedNodes.erase(N); });
4599 SelectionDAGLegalize Legalizer(*this, LegalizedNodes);
4601 // Visit all the nodes. We start in topological order, so that we see
4602 // nodes with their original operands intact. Legalization can produce
4603 // new nodes which may themselves need to be legalized. Iterate until all
4604 // nodes have been legalized.
4606 bool AnyLegalized = false;
4607 for (auto NI = allnodes_end(); NI != allnodes_begin();) {
4611 if (N->use_empty() && N != getRoot().getNode()) {
4617 if (LegalizedNodes.insert(N).second) {
4618 AnyLegalized = true;
4619 Legalizer.LegalizeOp(N);
4621 if (N->use_empty() && N != getRoot().getNode()) {
4632 // Remove dead nodes now.
4636 bool SelectionDAG::LegalizeOp(SDNode *N,
4637 SmallSetVector<SDNode *, 16> &UpdatedNodes) {
4638 SmallPtrSet<SDNode *, 16> LegalizedNodes;
4639 SelectionDAGLegalize Legalizer(*this, LegalizedNodes, &UpdatedNodes);
4641 // Directly insert the node in question, and legalize it. This will recurse
4642 // as needed through operands.
4643 LegalizedNodes.insert(N);
4644 Legalizer.LegalizeOp(N);
4646 return LegalizedNodes.count(N);