1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/ADT/SetVector.h"
15 #include "llvm/ADT/SmallPtrSet.h"
16 #include "llvm/ADT/SmallSet.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGNodes.h"
23 #include "llvm/IR/CallingConv.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/DebugInfo.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetSubtargetInfo.h"
40 #define DEBUG_TYPE "legalizedag"
44 struct FloatSignAsInt;
46 //===----------------------------------------------------------------------===//
47 /// This takes an arbitrary SelectionDAG as input and
48 /// hacks on it until the target machine can handle it. This involves
49 /// eliminating value sizes the machine cannot handle (promoting small sizes to
50 /// large sizes or splitting up large values into small values) as well as
51 /// eliminating operations the machine cannot handle.
53 /// This code also does a small amount of optimization and recognition of idioms
54 /// as part of its processing. For example, if a target does not support a
55 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
56 /// will attempt merge setcc and brc instructions into brcc's.
58 class SelectionDAGLegalize {
59 const TargetMachine &TM;
60 const TargetLowering &TLI;
63 /// \brief The set of nodes which have already been legalized. We hold a
64 /// reference to it in order to update as necessary on node deletion.
65 SmallPtrSetImpl<SDNode *> &LegalizedNodes;
67 /// \brief A set of all the nodes updated during legalization.
68 SmallSetVector<SDNode *, 16> *UpdatedNodes;
70 EVT getSetCCResultType(EVT VT) const {
71 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
74 // Libcall insertion helpers.
77 SelectionDAGLegalize(SelectionDAG &DAG,
78 SmallPtrSetImpl<SDNode *> &LegalizedNodes,
79 SmallSetVector<SDNode *, 16> *UpdatedNodes = nullptr)
80 : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
81 LegalizedNodes(LegalizedNodes), UpdatedNodes(UpdatedNodes) {}
83 /// \brief Legalizes the given operation.
84 void LegalizeOp(SDNode *Node);
87 SDValue OptimizeFloatStore(StoreSDNode *ST);
89 void LegalizeLoadOps(SDNode *Node);
90 void LegalizeStoreOps(SDNode *Node);
92 /// Some targets cannot handle a variable
93 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
94 /// is necessary to spill the vector being inserted into to memory, perform
95 /// the insert there, and then read the result back.
96 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
98 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx,
101 /// Return a vector shuffle operation which
102 /// performs the same shuffe in terms of order or result bytes, but on a type
103 /// whose vector element type is narrower than the original shuffle type.
104 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
105 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, const SDLoc &dl,
106 SDValue N1, SDValue N2,
107 ArrayRef<int> Mask) const;
109 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
110 bool &NeedInvert, const SDLoc &dl);
112 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
113 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
114 unsigned NumOps, bool isSigned, const SDLoc &dl);
116 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
117 SDNode *Node, bool isSigned);
118 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
119 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
120 RTLIB::Libcall Call_F128,
121 RTLIB::Libcall Call_PPCF128);
122 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
123 RTLIB::Libcall Call_I8,
124 RTLIB::Libcall Call_I16,
125 RTLIB::Libcall Call_I32,
126 RTLIB::Libcall Call_I64,
127 RTLIB::Libcall Call_I128);
128 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
129 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
131 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
133 SDValue ExpandBUILD_VECTOR(SDNode *Node);
134 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
135 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
136 SmallVectorImpl<SDValue> &Results);
137 void getSignAsIntValue(FloatSignAsInt &State, const SDLoc &DL,
138 SDValue Value) const;
139 SDValue modifySignAsInt(const FloatSignAsInt &State, const SDLoc &DL,
140 SDValue NewIntValue) const;
141 SDValue ExpandFCOPYSIGN(SDNode *Node) const;
142 SDValue ExpandFABS(SDNode *Node) const;
143 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
145 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
147 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
150 SDValue ExpandBITREVERSE(SDValue Op, const SDLoc &dl);
151 SDValue ExpandBSWAP(SDValue Op, const SDLoc &dl);
152 SDValue ExpandBitCount(unsigned Opc, SDValue Op, const SDLoc &dl);
154 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
155 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
156 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
158 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
159 SDValue ExpandConstant(ConstantSDNode *CP);
161 // if ExpandNode returns false, LegalizeOp falls back to ConvertNodeToLibcall
162 bool ExpandNode(SDNode *Node);
163 void ConvertNodeToLibcall(SDNode *Node);
164 void PromoteNode(SDNode *Node);
167 // Node replacement helpers
168 void ReplacedNode(SDNode *N) {
169 LegalizedNodes.erase(N);
171 UpdatedNodes->insert(N);
173 void ReplaceNode(SDNode *Old, SDNode *New) {
174 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
175 dbgs() << " with: "; New->dump(&DAG));
177 assert(Old->getNumValues() == New->getNumValues() &&
178 "Replacing one node with another that produces a different number "
180 DAG.ReplaceAllUsesWith(Old, New);
182 UpdatedNodes->insert(New);
185 void ReplaceNode(SDValue Old, SDValue New) {
186 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
187 dbgs() << " with: "; New->dump(&DAG));
189 DAG.ReplaceAllUsesWith(Old, New);
191 UpdatedNodes->insert(New.getNode());
192 ReplacedNode(Old.getNode());
194 void ReplaceNode(SDNode *Old, const SDValue *New) {
195 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG));
197 DAG.ReplaceAllUsesWith(Old, New);
198 for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
199 DEBUG(dbgs() << (i == 0 ? " with: "
203 UpdatedNodes->insert(New[i].getNode());
210 /// Return a vector shuffle operation which
211 /// performs the same shuffe in terms of order or result bytes, but on a type
212 /// whose vector element type is narrower than the original shuffle type.
213 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
214 SDValue SelectionDAGLegalize::ShuffleWithNarrowerEltType(
215 EVT NVT, EVT VT, const SDLoc &dl, SDValue N1, SDValue N2,
216 ArrayRef<int> Mask) const {
217 unsigned NumMaskElts = VT.getVectorNumElements();
218 unsigned NumDestElts = NVT.getVectorNumElements();
219 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
221 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
223 if (NumEltsGrowth == 1)
224 return DAG.getVectorShuffle(NVT, dl, N1, N2, Mask);
226 SmallVector<int, 8> NewMask;
227 for (unsigned i = 0; i != NumMaskElts; ++i) {
229 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
231 NewMask.push_back(-1);
233 NewMask.push_back(Idx * NumEltsGrowth + j);
236 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
237 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
238 return DAG.getVectorShuffle(NVT, dl, N1, N2, NewMask);
241 /// Expands the ConstantFP node to an integer constant or
242 /// a load from the constant pool.
244 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
248 // If a FP immediate is precise when represented as a float and if the
249 // target can do an extending load from float to double, we put it into
250 // the constant pool as a float, even if it's is statically typed as a
251 // double. This shrinks FP constants and canonicalizes them for targets where
252 // an FP extending load is the same cost as a normal load (such as on the x87
253 // fp stack or PPC FP unit).
254 EVT VT = CFP->getValueType(0);
255 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
257 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
258 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), dl,
259 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
262 APFloat APF = CFP->getValueAPF();
266 // We don't want to shrink SNaNs. Converting the SNaN back to its real type
267 // can cause it to be changed into a QNaN on some platforms (e.g. on SystemZ).
268 if (!APF.isSignaling()) {
269 while (SVT != MVT::f32 && SVT != MVT::f16) {
270 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
271 if (ConstantFPSDNode::isValueValidForType(SVT, APF) &&
272 // Only do this if the target has a native EXTLOAD instruction from
274 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
275 TLI.ShouldShrinkFPConstant(OrigVT)) {
276 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
277 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
285 DAG.getConstantPool(LLVMC, TLI.getPointerTy(DAG.getDataLayout()));
286 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
288 SDValue Result = DAG.getExtLoad(
289 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx,
290 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), VT,
294 SDValue Result = DAG.getLoad(
295 OrigVT, dl, DAG.getEntryNode(), CPIdx,
296 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), Alignment);
300 /// Expands the Constant node to a load from the constant pool.
301 SDValue SelectionDAGLegalize::ExpandConstant(ConstantSDNode *CP) {
303 EVT VT = CP->getValueType(0);
304 SDValue CPIdx = DAG.getConstantPool(CP->getConstantIntValue(),
305 TLI.getPointerTy(DAG.getDataLayout()));
306 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
307 SDValue Result = DAG.getLoad(
308 VT, dl, DAG.getEntryNode(), CPIdx,
309 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), Alignment);
313 /// Some target cannot handle a variable insertion index for the
314 /// INSERT_VECTOR_ELT instruction. In this case, it
315 /// is necessary to spill the vector being inserted into to memory, perform
316 /// the insert there, and then read the result back.
317 SDValue SelectionDAGLegalize::PerformInsertVectorEltInMemory(SDValue Vec,
325 // If the target doesn't support this, we have to spill the input vector
326 // to a temporary stack slot, update the element, then reload it. This is
327 // badness. We could also load the value into a vector register (either
328 // with a "move to register" or "extload into register" instruction, then
329 // permute it into place, if the idx is a constant and if the idx is
330 // supported by the target.
331 EVT VT = Tmp1.getValueType();
332 EVT EltVT = VT.getVectorElementType();
333 EVT IdxVT = Tmp3.getValueType();
334 EVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
335 SDValue StackPtr = DAG.CreateStackTemporary(VT);
337 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
340 SDValue Ch = DAG.getStore(
341 DAG.getEntryNode(), dl, Tmp1, StackPtr,
342 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI));
344 // Truncate or zero extend offset to target pointer type.
345 Tmp3 = DAG.getZExtOrTrunc(Tmp3, dl, PtrVT);
346 // Add the offset to the index.
347 unsigned EltSize = EltVT.getSizeInBits()/8;
348 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,
349 DAG.getConstant(EltSize, dl, IdxVT));
350 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
351 // Store the scalar value.
352 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT);
353 // Load the updated vector.
354 return DAG.getLoad(VT, dl, Ch, StackPtr, MachinePointerInfo::getFixedStack(
355 DAG.getMachineFunction(), SPFI));
358 SDValue SelectionDAGLegalize::ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
361 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
362 // SCALAR_TO_VECTOR requires that the type of the value being inserted
363 // match the element type of the vector being created, except for
364 // integers in which case the inserted value can be over width.
365 EVT EltVT = Vec.getValueType().getVectorElementType();
366 if (Val.getValueType() == EltVT ||
367 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
368 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
369 Vec.getValueType(), Val);
371 unsigned NumElts = Vec.getValueType().getVectorNumElements();
372 // We generate a shuffle of InVec and ScVec, so the shuffle mask
373 // should be 0,1,2,3,4,5... with the appropriate element replaced with
375 SmallVector<int, 8> ShufOps;
376 for (unsigned i = 0; i != NumElts; ++i)
377 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
379 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, ShufOps);
382 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
385 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
386 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
387 // FIXME: We shouldn't do this for TargetConstantFP's.
388 // FIXME: move this to the DAG Combiner! Note that we can't regress due
389 // to phase ordering between legalized code and the dag combiner. This
390 // probably means that we need to integrate dag combiner and legalizer
392 // We generally can't do this one for long doubles.
393 SDValue Chain = ST->getChain();
394 SDValue Ptr = ST->getBasePtr();
395 unsigned Alignment = ST->getAlignment();
396 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
397 AAMDNodes AAInfo = ST->getAAInfo();
399 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
400 if (CFP->getValueType(0) == MVT::f32 &&
401 TLI.isTypeLegal(MVT::i32)) {
402 SDValue Con = DAG.getConstant(CFP->getValueAPF().
403 bitcastToAPInt().zextOrTrunc(32),
404 SDLoc(CFP), MVT::i32);
405 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(), Alignment,
409 if (CFP->getValueType(0) == MVT::f64) {
410 // If this target supports 64-bit registers, do a single 64-bit store.
411 if (TLI.isTypeLegal(MVT::i64)) {
412 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
413 zextOrTrunc(64), SDLoc(CFP), MVT::i64);
414 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
415 Alignment, MMOFlags, AAInfo);
418 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
419 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
420 // stores. If the target supports neither 32- nor 64-bits, this
421 // xform is certainly not worth it.
422 const APInt &IntVal = CFP->getValueAPF().bitcastToAPInt();
423 SDValue Lo = DAG.getConstant(IntVal.trunc(32), dl, MVT::i32);
424 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), dl, MVT::i32);
425 if (DAG.getDataLayout().isBigEndian())
428 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), Alignment,
430 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
431 DAG.getConstant(4, dl, Ptr.getValueType()));
432 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
433 ST->getPointerInfo().getWithOffset(4),
434 MinAlign(Alignment, 4U), MMOFlags, AAInfo);
436 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
440 return SDValue(nullptr, 0);
443 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
444 StoreSDNode *ST = cast<StoreSDNode>(Node);
445 SDValue Chain = ST->getChain();
446 SDValue Ptr = ST->getBasePtr();
449 unsigned Alignment = ST->getAlignment();
450 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
451 AAMDNodes AAInfo = ST->getAAInfo();
453 if (!ST->isTruncatingStore()) {
454 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
455 ReplaceNode(ST, OptStore);
460 SDValue Value = ST->getValue();
461 MVT VT = Value.getSimpleValueType();
462 switch (TLI.getOperationAction(ISD::STORE, VT)) {
463 default: llvm_unreachable("This action is not supported yet!");
464 case TargetLowering::Legal: {
465 // If this is an unaligned store and the target doesn't support it,
467 EVT MemVT = ST->getMemoryVT();
468 unsigned AS = ST->getAddressSpace();
469 unsigned Align = ST->getAlignment();
470 const DataLayout &DL = DAG.getDataLayout();
471 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
472 SDValue Result = TLI.expandUnalignedStore(ST, DAG);
473 ReplaceNode(SDValue(ST, 0), Result);
477 case TargetLowering::Custom: {
478 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
479 if (Res && Res != SDValue(Node, 0))
480 ReplaceNode(SDValue(Node, 0), Res);
483 case TargetLowering::Promote: {
484 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
485 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
486 "Can only promote stores to same size type");
487 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
489 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
490 Alignment, MMOFlags, AAInfo);
491 ReplaceNode(SDValue(Node, 0), Result);
498 SDValue Value = ST->getValue();
500 EVT StVT = ST->getMemoryVT();
501 unsigned StWidth = StVT.getSizeInBits();
502 auto &DL = DAG.getDataLayout();
504 if (StWidth != StVT.getStoreSizeInBits()) {
505 // Promote to a byte-sized store with upper bits zero if not
506 // storing an integral number of bytes. For example, promote
507 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
508 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
509 StVT.getStoreSizeInBits());
510 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
512 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), NVT,
513 Alignment, MMOFlags, AAInfo);
514 ReplaceNode(SDValue(Node, 0), Result);
515 } else if (StWidth & (StWidth - 1)) {
516 // If not storing a power-of-2 number of bits, expand as two stores.
517 assert(!StVT.isVector() && "Unsupported truncstore!");
518 unsigned RoundWidth = 1 << Log2_32(StWidth);
519 assert(RoundWidth < StWidth);
520 unsigned ExtraWidth = StWidth - RoundWidth;
521 assert(ExtraWidth < RoundWidth);
522 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
523 "Store size not an integral number of bytes!");
524 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
525 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
527 unsigned IncrementSize;
529 if (DL.isLittleEndian()) {
530 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
531 // Store the bottom RoundWidth bits.
532 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
533 RoundVT, Alignment, MMOFlags, AAInfo);
535 // Store the remaining ExtraWidth bits.
536 IncrementSize = RoundWidth / 8;
537 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
538 DAG.getConstant(IncrementSize, dl,
539 Ptr.getValueType()));
541 ISD::SRL, dl, Value.getValueType(), Value,
542 DAG.getConstant(RoundWidth, dl,
543 TLI.getShiftAmountTy(Value.getValueType(), DL)));
544 Hi = DAG.getTruncStore(
546 ST->getPointerInfo().getWithOffset(IncrementSize), ExtraVT,
547 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
549 // Big endian - avoid unaligned stores.
550 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
551 // Store the top RoundWidth bits.
553 ISD::SRL, dl, Value.getValueType(), Value,
554 DAG.getConstant(ExtraWidth, dl,
555 TLI.getShiftAmountTy(Value.getValueType(), DL)));
556 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
557 RoundVT, Alignment, MMOFlags, AAInfo);
559 // Store the remaining ExtraWidth bits.
560 IncrementSize = RoundWidth / 8;
561 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
562 DAG.getConstant(IncrementSize, dl,
563 Ptr.getValueType()));
564 Lo = DAG.getTruncStore(
565 Chain, dl, Value, Ptr,
566 ST->getPointerInfo().getWithOffset(IncrementSize), ExtraVT,
567 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
570 // The order of the stores doesn't matter.
571 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
572 ReplaceNode(SDValue(Node, 0), Result);
574 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
575 default: llvm_unreachable("This action is not supported yet!");
576 case TargetLowering::Legal: {
577 EVT MemVT = ST->getMemoryVT();
578 unsigned AS = ST->getAddressSpace();
579 unsigned Align = ST->getAlignment();
580 // If this is an unaligned store and the target doesn't support it,
582 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
583 SDValue Result = TLI.expandUnalignedStore(ST, DAG);
584 ReplaceNode(SDValue(ST, 0), Result);
588 case TargetLowering::Custom: {
589 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
590 if (Res && Res != SDValue(Node, 0))
591 ReplaceNode(SDValue(Node, 0), Res);
594 case TargetLowering::Expand:
595 assert(!StVT.isVector() &&
596 "Vector Stores are handled in LegalizeVectorOps");
598 // TRUNCSTORE:i16 i32 -> STORE i16
599 assert(TLI.isTypeLegal(StVT) &&
600 "Do not know how to expand this store!");
601 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
603 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
604 Alignment, MMOFlags, AAInfo);
605 ReplaceNode(SDValue(Node, 0), Result);
612 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
613 LoadSDNode *LD = cast<LoadSDNode>(Node);
614 SDValue Chain = LD->getChain(); // The chain.
615 SDValue Ptr = LD->getBasePtr(); // The base pointer.
616 SDValue Value; // The value returned by the load op.
619 ISD::LoadExtType ExtType = LD->getExtensionType();
620 if (ExtType == ISD::NON_EXTLOAD) {
621 MVT VT = Node->getSimpleValueType(0);
622 SDValue RVal = SDValue(Node, 0);
623 SDValue RChain = SDValue(Node, 1);
625 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
626 default: llvm_unreachable("This action is not supported yet!");
627 case TargetLowering::Legal: {
628 EVT MemVT = LD->getMemoryVT();
629 unsigned AS = LD->getAddressSpace();
630 unsigned Align = LD->getAlignment();
631 const DataLayout &DL = DAG.getDataLayout();
632 // If this is an unaligned load and the target doesn't support it,
634 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
635 std::tie(RVal, RChain) = TLI.expandUnalignedLoad(LD, DAG);
639 case TargetLowering::Custom: {
640 if (SDValue Res = TLI.LowerOperation(RVal, DAG)) {
642 RChain = Res.getValue(1);
646 case TargetLowering::Promote: {
647 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
648 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
649 "Can only promote loads to same size type");
651 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
652 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
653 RChain = Res.getValue(1);
657 if (RChain.getNode() != Node) {
658 assert(RVal.getNode() != Node && "Load must be completely replaced");
659 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
660 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
662 UpdatedNodes->insert(RVal.getNode());
663 UpdatedNodes->insert(RChain.getNode());
670 EVT SrcVT = LD->getMemoryVT();
671 unsigned SrcWidth = SrcVT.getSizeInBits();
672 unsigned Alignment = LD->getAlignment();
673 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
674 AAMDNodes AAInfo = LD->getAAInfo();
676 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
677 // Some targets pretend to have an i1 loading operation, and actually
678 // load an i8. This trick is correct for ZEXTLOAD because the top 7
679 // bits are guaranteed to be zero; it helps the optimizers understand
680 // that these bits are zero. It is also useful for EXTLOAD, since it
681 // tells the optimizers that those bits are undefined. It would be
682 // nice to have an effective generic way of getting these benefits...
683 // Until such a way is found, don't insist on promoting i1 here.
685 TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) ==
686 TargetLowering::Promote)) {
687 // Promote to a byte-sized load if not loading an integral number of
688 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
689 unsigned NewWidth = SrcVT.getStoreSizeInBits();
690 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
693 // The extra bits are guaranteed to be zero, since we stored them that
694 // way. A zext load from NVT thus automatically gives zext from SrcVT.
696 ISD::LoadExtType NewExtType =
697 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
700 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), Chain, Ptr,
701 LD->getPointerInfo(), NVT, Alignment, MMOFlags, AAInfo);
703 Ch = Result.getValue(1); // The chain.
705 if (ExtType == ISD::SEXTLOAD)
706 // Having the top bits zero doesn't help when sign extending.
707 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
708 Result.getValueType(),
709 Result, DAG.getValueType(SrcVT));
710 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
711 // All the top bits are guaranteed to be zero - inform the optimizers.
712 Result = DAG.getNode(ISD::AssertZext, dl,
713 Result.getValueType(), Result,
714 DAG.getValueType(SrcVT));
718 } else if (SrcWidth & (SrcWidth - 1)) {
719 // If not loading a power-of-2 number of bits, expand as two loads.
720 assert(!SrcVT.isVector() && "Unsupported extload!");
721 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
722 assert(RoundWidth < SrcWidth);
723 unsigned ExtraWidth = SrcWidth - RoundWidth;
724 assert(ExtraWidth < RoundWidth);
725 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
726 "Load size not an integral number of bytes!");
727 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
728 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
730 unsigned IncrementSize;
731 auto &DL = DAG.getDataLayout();
733 if (DL.isLittleEndian()) {
734 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
735 // Load the bottom RoundWidth bits.
736 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
737 LD->getPointerInfo(), RoundVT, Alignment, MMOFlags,
740 // Load the remaining ExtraWidth bits.
741 IncrementSize = RoundWidth / 8;
742 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
743 DAG.getConstant(IncrementSize, dl,
744 Ptr.getValueType()));
745 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
746 LD->getPointerInfo().getWithOffset(IncrementSize),
747 ExtraVT, MinAlign(Alignment, IncrementSize), MMOFlags,
750 // Build a factor node to remember that this load is independent of
752 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
755 // Move the top bits to the right place.
757 ISD::SHL, dl, Hi.getValueType(), Hi,
758 DAG.getConstant(RoundWidth, dl,
759 TLI.getShiftAmountTy(Hi.getValueType(), DL)));
761 // Join the hi and lo parts.
762 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
764 // Big endian - avoid unaligned loads.
765 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
766 // Load the top RoundWidth bits.
767 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
768 LD->getPointerInfo(), RoundVT, Alignment, MMOFlags,
771 // Load the remaining ExtraWidth bits.
772 IncrementSize = RoundWidth / 8;
773 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
774 DAG.getConstant(IncrementSize, dl,
775 Ptr.getValueType()));
776 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
777 LD->getPointerInfo().getWithOffset(IncrementSize),
778 ExtraVT, MinAlign(Alignment, IncrementSize), MMOFlags,
781 // Build a factor node to remember that this load is independent of
783 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
786 // Move the top bits to the right place.
788 ISD::SHL, dl, Hi.getValueType(), Hi,
789 DAG.getConstant(ExtraWidth, dl,
790 TLI.getShiftAmountTy(Hi.getValueType(), DL)));
792 // Join the hi and lo parts.
793 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
798 bool isCustom = false;
799 switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0),
800 SrcVT.getSimpleVT())) {
801 default: llvm_unreachable("This action is not supported yet!");
802 case TargetLowering::Custom:
805 case TargetLowering::Legal: {
806 Value = SDValue(Node, 0);
807 Chain = SDValue(Node, 1);
810 if (SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG)) {
812 Chain = Res.getValue(1);
815 // If this is an unaligned load and the target doesn't support it,
817 EVT MemVT = LD->getMemoryVT();
818 unsigned AS = LD->getAddressSpace();
819 unsigned Align = LD->getAlignment();
820 const DataLayout &DL = DAG.getDataLayout();
821 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
822 std::tie(Value, Chain) = TLI.expandUnalignedLoad(LD, DAG);
827 case TargetLowering::Expand:
828 EVT DestVT = Node->getValueType(0);
829 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) {
830 // If the source type is not legal, see if there is a legal extload to
831 // an intermediate type that we can then extend further.
832 EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT());
833 if (TLI.isTypeLegal(SrcVT) || // Same as SrcVT == LoadVT?
834 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) {
835 // If we are loading a legal type, this is a non-extload followed by a
837 ISD::LoadExtType MidExtType =
838 (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
840 SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr,
841 SrcVT, LD->getMemOperand());
843 ISD::getExtForLoadExtType(SrcVT.isFloatingPoint(), ExtType);
844 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
845 Chain = Load.getValue(1);
849 // Handle the special case of fp16 extloads. EXTLOAD doesn't have the
850 // normal undefined upper bits behavior to allow using an in-reg extend
851 // with the illegal FP type, so load as an integer and do the
852 // from-integer conversion.
853 if (SrcVT.getScalarType() == MVT::f16) {
854 EVT ISrcVT = SrcVT.changeTypeToInteger();
855 EVT IDestVT = DestVT.changeTypeToInteger();
856 EVT LoadVT = TLI.getRegisterType(IDestVT.getSimpleVT());
858 SDValue Result = DAG.getExtLoad(ISD::ZEXTLOAD, dl, LoadVT,
860 LD->getMemOperand());
861 Value = DAG.getNode(ISD::FP16_TO_FP, dl, DestVT, Result);
862 Chain = Result.getValue(1);
867 assert(!SrcVT.isVector() &&
868 "Vector Loads are handled in LegalizeVectorOps");
870 // FIXME: This does not work for vectors on most targets. Sign-
871 // and zero-extend operations are currently folded into extending
872 // loads, whether they are legal or not, and then we end up here
873 // without any support for legalizing them.
874 assert(ExtType != ISD::EXTLOAD &&
875 "EXTLOAD should always be supported!");
876 // Turn the unsupported load into an EXTLOAD followed by an
877 // explicit zero/sign extend inreg.
878 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
879 Node->getValueType(0),
881 LD->getMemOperand());
883 if (ExtType == ISD::SEXTLOAD)
884 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
885 Result.getValueType(),
886 Result, DAG.getValueType(SrcVT));
888 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
890 Chain = Result.getValue(1);
895 // Since loads produce two values, make sure to remember that we legalized
897 if (Chain.getNode() != Node) {
898 assert(Value.getNode() != Node && "Load must be completely replaced");
899 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
900 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
902 UpdatedNodes->insert(Value.getNode());
903 UpdatedNodes->insert(Chain.getNode());
909 /// Return a legal replacement for the given operation, with all legal operands.
910 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
911 DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
913 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
917 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
918 assert((TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
919 TargetLowering::TypeLegal ||
920 TLI.isTypeLegal(Node->getValueType(i))) &&
921 "Unexpected illegal type!");
923 for (const SDValue &Op : Node->op_values())
924 assert((TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) ==
925 TargetLowering::TypeLegal ||
926 TLI.isTypeLegal(Op.getValueType()) ||
927 Op.getOpcode() == ISD::TargetConstant) &&
928 "Unexpected illegal type!");
931 // Figure out the correct action; the way to query this varies by opcode
932 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
933 bool SimpleFinishLegalizing = true;
934 switch (Node->getOpcode()) {
935 case ISD::INTRINSIC_W_CHAIN:
936 case ISD::INTRINSIC_WO_CHAIN:
937 case ISD::INTRINSIC_VOID:
939 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
941 case ISD::GET_DYNAMIC_AREA_OFFSET:
942 Action = TLI.getOperationAction(Node->getOpcode(),
943 Node->getValueType(0));
946 Action = TLI.getOperationAction(Node->getOpcode(),
947 Node->getValueType(0));
948 if (Action != TargetLowering::Promote)
949 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
951 case ISD::FP_TO_FP16:
952 case ISD::SINT_TO_FP:
953 case ISD::UINT_TO_FP:
954 case ISD::EXTRACT_VECTOR_ELT:
955 Action = TLI.getOperationAction(Node->getOpcode(),
956 Node->getOperand(0).getValueType());
958 case ISD::FP_ROUND_INREG:
959 case ISD::SIGN_EXTEND_INREG: {
960 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
961 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
964 case ISD::ATOMIC_STORE: {
965 Action = TLI.getOperationAction(Node->getOpcode(),
966 Node->getOperand(2).getValueType());
972 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
973 Node->getOpcode() == ISD::SETCC ? 2 :
974 Node->getOpcode() == ISD::SETCCE ? 3 : 1;
975 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
976 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
977 ISD::CondCode CCCode =
978 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
979 Action = TLI.getCondCodeAction(CCCode, OpVT);
980 if (Action == TargetLowering::Legal) {
981 if (Node->getOpcode() == ISD::SELECT_CC)
982 Action = TLI.getOperationAction(Node->getOpcode(),
983 Node->getValueType(0));
985 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
991 // FIXME: Model these properly. LOAD and STORE are complicated, and
992 // STORE expects the unlegalized operand in some cases.
993 SimpleFinishLegalizing = false;
995 case ISD::CALLSEQ_START:
996 case ISD::CALLSEQ_END:
997 // FIXME: This shouldn't be necessary. These nodes have special properties
998 // dealing with the recursive nature of legalization. Removing this
999 // special case should be done as part of making LegalizeDAG non-recursive.
1000 SimpleFinishLegalizing = false;
1002 case ISD::EXTRACT_ELEMENT:
1003 case ISD::FLT_ROUNDS_:
1005 case ISD::MERGE_VALUES:
1006 case ISD::EH_RETURN:
1007 case ISD::FRAME_TO_ARGS_OFFSET:
1008 case ISD::EH_DWARF_CFA:
1009 case ISD::EH_SJLJ_SETJMP:
1010 case ISD::EH_SJLJ_LONGJMP:
1011 case ISD::EH_SJLJ_SETUP_DISPATCH:
1012 // These operations lie about being legal: when they claim to be legal,
1013 // they should actually be expanded.
1014 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1015 if (Action == TargetLowering::Legal)
1016 Action = TargetLowering::Expand;
1018 case ISD::INIT_TRAMPOLINE:
1019 case ISD::ADJUST_TRAMPOLINE:
1020 case ISD::FRAMEADDR:
1021 case ISD::RETURNADDR:
1022 case ISD::ADDROFRETURNADDR:
1023 // These operations lie about being legal: when they claim to be legal,
1024 // they should actually be custom-lowered.
1025 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1026 if (Action == TargetLowering::Legal)
1027 Action = TargetLowering::Custom;
1029 case ISD::READCYCLECOUNTER:
1030 // READCYCLECOUNTER returns an i64, even if type legalization might have
1031 // expanded that to several smaller types.
1032 Action = TLI.getOperationAction(Node->getOpcode(), MVT::i64);
1034 case ISD::READ_REGISTER:
1035 case ISD::WRITE_REGISTER:
1036 // Named register is legal in the DAG, but blocked by register name
1037 // selection if not implemented by target (to chose the correct register)
1038 // They'll be converted to Copy(To/From)Reg.
1039 Action = TargetLowering::Legal;
1041 case ISD::DEBUGTRAP:
1042 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1043 if (Action == TargetLowering::Expand) {
1044 // replace ISD::DEBUGTRAP with ISD::TRAP
1046 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1047 Node->getOperand(0));
1048 ReplaceNode(Node, NewVal.getNode());
1049 LegalizeOp(NewVal.getNode());
1055 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1056 Action = TargetLowering::Legal;
1058 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1063 if (SimpleFinishLegalizing) {
1064 SDNode *NewNode = Node;
1065 switch (Node->getOpcode()) {
1072 // Legalizing shifts/rotates requires adjusting the shift amount
1073 // to the appropriate width.
1074 SDValue Op0 = Node->getOperand(0);
1075 SDValue Op1 = Node->getOperand(1);
1076 if (!Op1.getValueType().isVector()) {
1077 SDValue SAO = DAG.getShiftAmountOperand(Op0.getValueType(), Op1);
1078 // The getShiftAmountOperand() may create a new operand node or
1079 // return the existing one. If new operand is created we need
1080 // to update the parent node.
1081 // Do not try to legalize SAO here! It will be automatically legalized
1082 // in the next round.
1084 NewNode = DAG.UpdateNodeOperands(Node, Op0, SAO);
1088 case ISD::SRL_PARTS:
1089 case ISD::SRA_PARTS:
1090 case ISD::SHL_PARTS: {
1091 // Legalizing shifts/rotates requires adjusting the shift amount
1092 // to the appropriate width.
1093 SDValue Op0 = Node->getOperand(0);
1094 SDValue Op1 = Node->getOperand(1);
1095 SDValue Op2 = Node->getOperand(2);
1096 if (!Op2.getValueType().isVector()) {
1097 SDValue SAO = DAG.getShiftAmountOperand(Op0.getValueType(), Op2);
1098 // The getShiftAmountOperand() may create a new operand node or
1099 // return the existing one. If new operand is created we need
1100 // to update the parent node.
1102 NewNode = DAG.UpdateNodeOperands(Node, Op0, Op1, SAO);
1108 if (NewNode != Node) {
1109 ReplaceNode(Node, NewNode);
1113 case TargetLowering::Legal:
1115 case TargetLowering::Custom: {
1116 // FIXME: The handling for custom lowering with multiple results is
1118 if (SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG)) {
1119 if (!(Res.getNode() != Node || Res.getResNo() != 0))
1122 if (Node->getNumValues() == 1) {
1123 // We can just directly replace this node with the lowered value.
1124 ReplaceNode(SDValue(Node, 0), Res);
1128 SmallVector<SDValue, 8> ResultVals;
1129 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1130 ResultVals.push_back(Res.getValue(i));
1131 ReplaceNode(Node, ResultVals.data());
1136 case TargetLowering::Expand:
1137 if (ExpandNode(Node))
1140 case TargetLowering::LibCall:
1141 ConvertNodeToLibcall(Node);
1143 case TargetLowering::Promote:
1149 switch (Node->getOpcode()) {
1156 llvm_unreachable("Do not know how to legalize this operator!");
1158 case ISD::CALLSEQ_START:
1159 case ISD::CALLSEQ_END:
1162 return LegalizeLoadOps(Node);
1165 return LegalizeStoreOps(Node);
1170 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1171 SDValue Vec = Op.getOperand(0);
1172 SDValue Idx = Op.getOperand(1);
1175 // Before we generate a new store to a temporary stack slot, see if there is
1176 // already one that we can use. There often is because when we scalarize
1177 // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1178 // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1179 // the vector. If all are expanded here, we don't want one store per vector
1182 // Caches for hasPredecessorHelper
1183 SmallPtrSet<const SDNode *, 32> Visited;
1184 SmallVector<const SDNode *, 16> Worklist;
1185 Worklist.push_back(Idx.getNode());
1186 SDValue StackPtr, Ch;
1187 for (SDNode::use_iterator UI = Vec.getNode()->use_begin(),
1188 UE = Vec.getNode()->use_end(); UI != UE; ++UI) {
1190 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1191 if (ST->isIndexed() || ST->isTruncatingStore() ||
1192 ST->getValue() != Vec)
1195 // Make sure that nothing else could have stored into the destination of
1197 if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1200 // If the index is dependent on the store we will introduce a cycle when
1201 // creating the load (the load uses the index, and by replacing the chain
1202 // we will make the index dependent on the load).
1203 if (SDNode::hasPredecessorHelper(ST, Visited, Worklist))
1206 StackPtr = ST->getBasePtr();
1207 Ch = SDValue(ST, 0);
1212 if (!Ch.getNode()) {
1213 // Store the value to a temporary stack slot, then LOAD the returned part.
1214 StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1215 Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1216 MachinePointerInfo());
1219 // Add the offset to the index.
1220 unsigned EltSize = Vec.getScalarValueSizeInBits() / 8;
1221 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1222 DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType()));
1224 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy(DAG.getDataLayout()));
1225 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1229 if (Op.getValueType().isVector())
1231 DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, MachinePointerInfo());
1233 NewLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1234 MachinePointerInfo(),
1235 Vec.getValueType().getVectorElementType());
1237 // Replace the chain going out of the store, by the one out of the load.
1238 DAG.ReplaceAllUsesOfValueWith(Ch, SDValue(NewLoad.getNode(), 1));
1240 // We introduced a cycle though, so update the loads operands, making sure
1241 // to use the original store's chain as an incoming chain.
1242 SmallVector<SDValue, 6> NewLoadOperands(NewLoad->op_begin(),
1244 NewLoadOperands[0] = Ch;
1246 SDValue(DAG.UpdateNodeOperands(NewLoad.getNode(), NewLoadOperands), 0);
1250 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1251 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1253 SDValue Vec = Op.getOperand(0);
1254 SDValue Part = Op.getOperand(1);
1255 SDValue Idx = Op.getOperand(2);
1258 // Store the value to a temporary stack slot, then LOAD the returned part.
1260 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1261 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1262 MachinePointerInfo PtrInfo =
1263 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1265 // First store the whole vector.
1266 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo);
1268 // Then store the inserted part.
1270 // Add the offset to the index.
1271 unsigned EltSize = Vec.getScalarValueSizeInBits() / 8;
1273 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1274 DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType()));
1275 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy(DAG.getDataLayout()));
1277 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1280 // Store the subvector.
1281 Ch = DAG.getStore(Ch, dl, Part, SubStackPtr, MachinePointerInfo());
1283 // Finally, load the updated vector.
1284 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo);
1287 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1288 // We can't handle this case efficiently. Allocate a sufficiently
1289 // aligned object on the stack, store each element into it, then load
1290 // the result as a vector.
1291 // Create the stack frame object.
1292 EVT VT = Node->getValueType(0);
1293 EVT EltVT = VT.getVectorElementType();
1295 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1296 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1297 MachinePointerInfo PtrInfo =
1298 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1300 // Emit a store of each element to the stack slot.
1301 SmallVector<SDValue, 8> Stores;
1302 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1303 // Store (in the right endianness) the elements to memory.
1304 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1305 // Ignore undef elements.
1306 if (Node->getOperand(i).isUndef()) continue;
1308 unsigned Offset = TypeByteSize*i;
1310 SDValue Idx = DAG.getConstant(Offset, dl, FIPtr.getValueType());
1311 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1313 // If the destination vector element type is narrower than the source
1314 // element type, only store the bits necessary.
1315 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1316 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1317 Node->getOperand(i), Idx,
1318 PtrInfo.getWithOffset(Offset), EltVT));
1320 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
1321 Idx, PtrInfo.getWithOffset(Offset)));
1325 if (!Stores.empty()) // Not all undef elements?
1326 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1328 StoreChain = DAG.getEntryNode();
1330 // Result is a load from the stack slot.
1331 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo);
1335 /// Keeps track of state when getting the sign of a floating-point value as an
1337 struct FloatSignAsInt {
1342 MachinePointerInfo IntPointerInfo;
1343 MachinePointerInfo FloatPointerInfo;
1350 /// Bitcast a floating-point value to an integer value. Only bitcast the part
1351 /// containing the sign bit if the target has no integer value capable of
1352 /// holding all bits of the floating-point value.
1353 void SelectionDAGLegalize::getSignAsIntValue(FloatSignAsInt &State,
1355 SDValue Value) const {
1356 EVT FloatVT = Value.getValueType();
1357 unsigned NumBits = FloatVT.getSizeInBits();
1358 State.FloatVT = FloatVT;
1359 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), NumBits);
1360 // Convert to an integer of the same size.
1361 if (TLI.isTypeLegal(IVT)) {
1362 State.IntValue = DAG.getNode(ISD::BITCAST, DL, IVT, Value);
1363 State.SignMask = APInt::getSignBit(NumBits);
1364 State.SignBit = NumBits - 1;
1368 auto &DataLayout = DAG.getDataLayout();
1369 // Store the float to memory, then load the sign part out as an integer.
1370 MVT LoadTy = TLI.getRegisterType(*DAG.getContext(), MVT::i8);
1371 // First create a temporary that is aligned for both the load and store.
1372 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1373 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1374 // Then store the float to it.
1375 State.FloatPtr = StackPtr;
1376 MachineFunction &MF = DAG.getMachineFunction();
1377 State.FloatPointerInfo = MachinePointerInfo::getFixedStack(MF, FI);
1378 State.Chain = DAG.getStore(DAG.getEntryNode(), DL, Value, State.FloatPtr,
1379 State.FloatPointerInfo);
1382 if (DataLayout.isBigEndian()) {
1383 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1384 // Load out a legal integer with the same sign bit as the float.
1386 State.IntPointerInfo = State.FloatPointerInfo;
1388 // Advance the pointer so that the loaded byte will contain the sign bit.
1389 unsigned ByteOffset = (FloatVT.getSizeInBits() / 8) - 1;
1390 IntPtr = DAG.getNode(ISD::ADD, DL, StackPtr.getValueType(), StackPtr,
1391 DAG.getConstant(ByteOffset, DL, StackPtr.getValueType()));
1392 State.IntPointerInfo = MachinePointerInfo::getFixedStack(MF, FI,
1396 State.IntPtr = IntPtr;
1397 State.IntValue = DAG.getExtLoad(ISD::EXTLOAD, DL, LoadTy, State.Chain, IntPtr,
1398 State.IntPointerInfo, MVT::i8);
1399 State.SignMask = APInt::getOneBitSet(LoadTy.getSizeInBits(), 7);
1403 /// Replace the integer value produced by getSignAsIntValue() with a new value
1404 /// and cast the result back to a floating-point type.
1405 SDValue SelectionDAGLegalize::modifySignAsInt(const FloatSignAsInt &State,
1407 SDValue NewIntValue) const {
1409 return DAG.getNode(ISD::BITCAST, DL, State.FloatVT, NewIntValue);
1411 // Override the part containing the sign bit in the value stored on the stack.
1412 SDValue Chain = DAG.getTruncStore(State.Chain, DL, NewIntValue, State.IntPtr,
1413 State.IntPointerInfo, MVT::i8);
1414 return DAG.getLoad(State.FloatVT, DL, Chain, State.FloatPtr,
1415 State.FloatPointerInfo);
1418 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode *Node) const {
1420 SDValue Mag = Node->getOperand(0);
1421 SDValue Sign = Node->getOperand(1);
1423 // Get sign bit into an integer value.
1424 FloatSignAsInt SignAsInt;
1425 getSignAsIntValue(SignAsInt, DL, Sign);
1427 EVT IntVT = SignAsInt.IntValue.getValueType();
1428 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT);
1429 SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue,
1432 // If FABS is legal transform FCOPYSIGN(x, y) => sign(x) ? -FABS(x) : FABS(X)
1433 EVT FloatVT = Mag.getValueType();
1434 if (TLI.isOperationLegalOrCustom(ISD::FABS, FloatVT) &&
1435 TLI.isOperationLegalOrCustom(ISD::FNEG, FloatVT)) {
1436 SDValue AbsValue = DAG.getNode(ISD::FABS, DL, FloatVT, Mag);
1437 SDValue NegValue = DAG.getNode(ISD::FNEG, DL, FloatVT, AbsValue);
1438 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit,
1439 DAG.getConstant(0, DL, IntVT), ISD::SETNE);
1440 return DAG.getSelect(DL, FloatVT, Cond, NegValue, AbsValue);
1443 // Transform Mag value to integer, and clear the sign bit.
1444 FloatSignAsInt MagAsInt;
1445 getSignAsIntValue(MagAsInt, DL, Mag);
1446 EVT MagVT = MagAsInt.IntValue.getValueType();
1447 SDValue ClearSignMask = DAG.getConstant(~MagAsInt.SignMask, DL, MagVT);
1448 SDValue ClearedSign = DAG.getNode(ISD::AND, DL, MagVT, MagAsInt.IntValue,
1451 // Get the signbit at the right position for MagAsInt.
1452 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit;
1453 if (SignBit.getValueSizeInBits() > ClearedSign.getValueSizeInBits()) {
1454 if (ShiftAmount > 0) {
1455 SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, IntVT);
1456 SignBit = DAG.getNode(ISD::SRL, DL, IntVT, SignBit, ShiftCnst);
1457 } else if (ShiftAmount < 0) {
1458 SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, IntVT);
1459 SignBit = DAG.getNode(ISD::SHL, DL, IntVT, SignBit, ShiftCnst);
1461 SignBit = DAG.getNode(ISD::TRUNCATE, DL, MagVT, SignBit);
1462 } else if (SignBit.getValueSizeInBits() < ClearedSign.getValueSizeInBits()) {
1463 SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit);
1464 if (ShiftAmount > 0) {
1465 SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, MagVT);
1466 SignBit = DAG.getNode(ISD::SRL, DL, MagVT, SignBit, ShiftCnst);
1467 } else if (ShiftAmount < 0) {
1468 SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, MagVT);
1469 SignBit = DAG.getNode(ISD::SHL, DL, MagVT, SignBit, ShiftCnst);
1473 // Store the part with the modified sign and convert back to float.
1474 SDValue CopiedSign = DAG.getNode(ISD::OR, DL, MagVT, ClearedSign, SignBit);
1475 return modifySignAsInt(MagAsInt, DL, CopiedSign);
1478 SDValue SelectionDAGLegalize::ExpandFABS(SDNode *Node) const {
1480 SDValue Value = Node->getOperand(0);
1482 // Transform FABS(x) => FCOPYSIGN(x, 0.0) if FCOPYSIGN is legal.
1483 EVT FloatVT = Value.getValueType();
1484 if (TLI.isOperationLegalOrCustom(ISD::FCOPYSIGN, FloatVT)) {
1485 SDValue Zero = DAG.getConstantFP(0.0, DL, FloatVT);
1486 return DAG.getNode(ISD::FCOPYSIGN, DL, FloatVT, Value, Zero);
1489 // Transform value to integer, clear the sign bit and transform back.
1490 FloatSignAsInt ValueAsInt;
1491 getSignAsIntValue(ValueAsInt, DL, Value);
1492 EVT IntVT = ValueAsInt.IntValue.getValueType();
1493 SDValue ClearSignMask = DAG.getConstant(~ValueAsInt.SignMask, DL, IntVT);
1494 SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, ValueAsInt.IntValue,
1496 return modifySignAsInt(ValueAsInt, DL, ClearedSign);
1499 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1500 SmallVectorImpl<SDValue> &Results) {
1501 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1502 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1503 " not tell us which reg is the stack pointer!");
1505 EVT VT = Node->getValueType(0);
1506 SDValue Tmp1 = SDValue(Node, 0);
1507 SDValue Tmp2 = SDValue(Node, 1);
1508 SDValue Tmp3 = Node->getOperand(2);
1509 SDValue Chain = Tmp1.getOperand(0);
1511 // Chain the dynamic stack allocation so that it doesn't modify the stack
1512 // pointer when other instructions are using the stack.
1513 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true), dl);
1515 SDValue Size = Tmp2.getOperand(1);
1516 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1517 Chain = SP.getValue(1);
1518 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1519 unsigned StackAlign =
1520 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
1521 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1522 if (Align > StackAlign)
1523 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1524 DAG.getConstant(-(uint64_t)Align, dl, VT));
1525 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1527 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
1528 DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
1530 Results.push_back(Tmp1);
1531 Results.push_back(Tmp2);
1534 /// Legalize a SETCC with given LHS and RHS and condition code CC on the current
1537 /// If the SETCC has been legalized using AND / OR, then the legalized node
1538 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1539 /// will be set to false.
1541 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1542 /// then the values of LHS and RHS will be swapped, CC will be set to the
1543 /// new condition, and NeedInvert will be set to false.
1545 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1546 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1547 /// will be set to true. The caller must invert the result of the SETCC with
1548 /// SelectionDAG::getLogicalNOT() or take equivalent action to swap the effect
1549 /// of a true/false result.
1551 /// \returns true if the SetCC has been legalized, false if it hasn't.
1552 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, SDValue &LHS,
1553 SDValue &RHS, SDValue &CC,
1556 MVT OpVT = LHS.getSimpleValueType();
1557 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1559 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1560 default: llvm_unreachable("Unknown condition code action!");
1561 case TargetLowering::Legal:
1564 case TargetLowering::Expand: {
1565 ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1566 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1567 std::swap(LHS, RHS);
1568 CC = DAG.getCondCode(InvCC);
1571 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1574 default: llvm_unreachable("Don't know how to expand this condition!");
1576 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1577 == TargetLowering::Legal
1578 && "If SETO is expanded, SETOEQ must be legal!");
1579 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1581 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1582 == TargetLowering::Legal
1583 && "If SETUO is expanded, SETUNE must be legal!");
1584 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1597 // If we are floating point, assign and break, otherwise fall through.
1598 if (!OpVT.isInteger()) {
1599 // We can use the 4th bit to tell if we are the unordered
1600 // or ordered version of the opcode.
1601 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1602 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1603 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1606 // Fallthrough if we are unsigned integer.
1612 // We only support using the inverted operation, which is computed above
1613 // and not a different manner of supporting expanding these cases.
1614 llvm_unreachable("Don't know how to expand this condition!");
1617 // Try inverting the result of the inverse condition.
1618 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ;
1619 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1620 CC = DAG.getCondCode(InvCC);
1624 // If inverting the condition didn't work then we have no means to expand
1626 llvm_unreachable("Don't know how to expand this condition!");
1629 SDValue SetCC1, SetCC2;
1630 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1631 // If we aren't the ordered or unorder operation,
1632 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1633 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1634 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1636 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1637 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1638 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1640 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1649 /// Emit a store/load combination to the stack. This stores
1650 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1651 /// a load from the stack slot to DestVT, extending it if needed.
1652 /// The resultant code need not be legal.
1653 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
1654 EVT DestVT, const SDLoc &dl) {
1655 // Create the stack frame object.
1656 unsigned SrcAlign = DAG.getDataLayout().getPrefTypeAlignment(
1657 SrcOp.getValueType().getTypeForEVT(*DAG.getContext()));
1658 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1660 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1661 int SPFI = StackPtrFI->getIndex();
1662 MachinePointerInfo PtrInfo =
1663 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI);
1665 unsigned SrcSize = SrcOp.getValueSizeInBits();
1666 unsigned SlotSize = SlotVT.getSizeInBits();
1667 unsigned DestSize = DestVT.getSizeInBits();
1668 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1669 unsigned DestAlign = DAG.getDataLayout().getPrefTypeAlignment(DestType);
1671 // Emit a store to the stack slot. Use a truncstore if the input value is
1672 // later than DestVT.
1675 if (SrcSize > SlotSize)
1676 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, PtrInfo,
1679 assert(SrcSize == SlotSize && "Invalid store");
1681 DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, PtrInfo, SrcAlign);
1684 // Result is a load from the stack slot.
1685 if (SlotSize == DestSize)
1686 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo, DestAlign);
1688 assert(SlotSize < DestSize && "Unknown extension!");
1689 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, PtrInfo, SlotVT,
1693 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1695 // Create a vector sized/aligned stack slot, store the value to element #0,
1696 // then load the whole vector back out.
1697 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1699 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1700 int SPFI = StackPtrFI->getIndex();
1702 SDValue Ch = DAG.getTruncStore(
1703 DAG.getEntryNode(), dl, Node->getOperand(0), StackPtr,
1704 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI),
1705 Node->getValueType(0).getVectorElementType());
1707 Node->getValueType(0), dl, Ch, StackPtr,
1708 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI));
1712 ExpandBVWithShuffles(SDNode *Node, SelectionDAG &DAG,
1713 const TargetLowering &TLI, SDValue &Res) {
1714 unsigned NumElems = Node->getNumOperands();
1716 EVT VT = Node->getValueType(0);
1718 // Try to group the scalars into pairs, shuffle the pairs together, then
1719 // shuffle the pairs of pairs together, etc. until the vector has
1720 // been built. This will work only if all of the necessary shuffle masks
1723 // We do this in two phases; first to check the legality of the shuffles,
1724 // and next, assuming that all shuffles are legal, to create the new nodes.
1725 for (int Phase = 0; Phase < 2; ++Phase) {
1726 SmallVector<std::pair<SDValue, SmallVector<int, 16> >, 16> IntermedVals,
1728 for (unsigned i = 0; i < NumElems; ++i) {
1729 SDValue V = Node->getOperand(i);
1735 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1736 IntermedVals.push_back(std::make_pair(Vec, SmallVector<int, 16>(1, i)));
1739 while (IntermedVals.size() > 2) {
1740 NewIntermedVals.clear();
1741 for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
1742 // This vector and the next vector are shuffled together (simply to
1743 // append the one to the other).
1744 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1746 SmallVector<int, 16> FinalIndices;
1747 FinalIndices.reserve(IntermedVals[i].second.size() +
1748 IntermedVals[i+1].second.size());
1751 for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
1754 FinalIndices.push_back(IntermedVals[i].second[j]);
1756 for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
1758 ShuffleVec[k] = NumElems + j;
1759 FinalIndices.push_back(IntermedVals[i+1].second[j]);
1764 Shuffle = DAG.getVectorShuffle(VT, dl, IntermedVals[i].first,
1765 IntermedVals[i+1].first,
1767 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1769 NewIntermedVals.push_back(
1770 std::make_pair(Shuffle, std::move(FinalIndices)));
1773 // If we had an odd number of defined values, then append the last
1774 // element to the array of new vectors.
1775 if ((IntermedVals.size() & 1) != 0)
1776 NewIntermedVals.push_back(IntermedVals.back());
1778 IntermedVals.swap(NewIntermedVals);
1781 assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
1782 "Invalid number of intermediate vectors");
1783 SDValue Vec1 = IntermedVals[0].first;
1785 if (IntermedVals.size() > 1)
1786 Vec2 = IntermedVals[1].first;
1788 Vec2 = DAG.getUNDEF(VT);
1790 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1791 for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
1792 ShuffleVec[IntermedVals[0].second[i]] = i;
1793 for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
1794 ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
1797 Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec);
1798 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1805 /// Expand a BUILD_VECTOR node on targets that don't
1806 /// support the operation, but do support the resultant vector type.
1807 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1808 unsigned NumElems = Node->getNumOperands();
1809 SDValue Value1, Value2;
1811 EVT VT = Node->getValueType(0);
1812 EVT OpVT = Node->getOperand(0).getValueType();
1813 EVT EltVT = VT.getVectorElementType();
1815 // If the only non-undef value is the low element, turn this into a
1816 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1817 bool isOnlyLowElement = true;
1818 bool MoreThanTwoValues = false;
1819 bool isConstant = true;
1820 for (unsigned i = 0; i < NumElems; ++i) {
1821 SDValue V = Node->getOperand(i);
1825 isOnlyLowElement = false;
1826 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1829 if (!Value1.getNode()) {
1831 } else if (!Value2.getNode()) {
1834 } else if (V != Value1 && V != Value2) {
1835 MoreThanTwoValues = true;
1839 if (!Value1.getNode())
1840 return DAG.getUNDEF(VT);
1842 if (isOnlyLowElement)
1843 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1845 // If all elements are constants, create a load from the constant pool.
1847 SmallVector<Constant*, 16> CV;
1848 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1849 if (ConstantFPSDNode *V =
1850 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1851 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1852 } else if (ConstantSDNode *V =
1853 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1855 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1857 // If OpVT and EltVT don't match, EltVT is not legal and the
1858 // element values have been promoted/truncated earlier. Undo this;
1859 // we don't want a v16i8 to become a v16i32 for example.
1860 const ConstantInt *CI = V->getConstantIntValue();
1861 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1862 CI->getZExtValue()));
1865 assert(Node->getOperand(i).isUndef());
1866 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1867 CV.push_back(UndefValue::get(OpNTy));
1870 Constant *CP = ConstantVector::get(CV);
1872 DAG.getConstantPool(CP, TLI.getPointerTy(DAG.getDataLayout()));
1873 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1875 VT, dl, DAG.getEntryNode(), CPIdx,
1876 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
1880 SmallSet<SDValue, 16> DefinedValues;
1881 for (unsigned i = 0; i < NumElems; ++i) {
1882 if (Node->getOperand(i).isUndef())
1884 DefinedValues.insert(Node->getOperand(i));
1887 if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues.size())) {
1888 if (!MoreThanTwoValues) {
1889 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1890 for (unsigned i = 0; i < NumElems; ++i) {
1891 SDValue V = Node->getOperand(i);
1894 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1896 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1897 // Get the splatted value into the low element of a vector register.
1898 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1900 if (Value2.getNode())
1901 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1903 Vec2 = DAG.getUNDEF(VT);
1905 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1906 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec);
1910 if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
1915 // Otherwise, we can't handle this case efficiently.
1916 return ExpandVectorBuildThroughStack(Node);
1919 // Expand a node into a call to a libcall. If the result value
1920 // does not fit into a register, return the lo part and set the hi part to the
1921 // by-reg argument. If it does fit into a single register, return the result
1922 // and leave the Hi part unset.
1923 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1925 TargetLowering::ArgListTy Args;
1926 TargetLowering::ArgListEntry Entry;
1927 for (const SDValue &Op : Node->op_values()) {
1928 EVT ArgVT = Op.getValueType();
1929 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1932 Entry.isSExt = isSigned;
1933 Entry.isZExt = !isSigned;
1934 Args.push_back(Entry);
1936 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1937 TLI.getPointerTy(DAG.getDataLayout()));
1939 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1941 // By default, the input chain to this libcall is the entry node of the
1942 // function. If the libcall is going to be emitted as a tail call then
1943 // TLI.isUsedByReturnOnly will change it to the right chain if the return
1944 // node which is being folded has a non-entry input chain.
1945 SDValue InChain = DAG.getEntryNode();
1947 // isTailCall may be true since the callee does not reference caller stack
1948 // frame. Check if it's in the right position and that the return types match.
1949 SDValue TCChain = InChain;
1950 const Function *F = DAG.getMachineFunction().getFunction();
1952 TLI.isInTailCallPosition(DAG, Node, TCChain) &&
1953 (RetTy == F->getReturnType() || F->getReturnType()->isVoidTy());
1957 TargetLowering::CallLoweringInfo CLI(DAG);
1958 CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
1959 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
1960 .setTailCall(isTailCall).setSExtResult(isSigned).setZExtResult(!isSigned);
1962 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1964 if (!CallInfo.second.getNode())
1965 // It's a tailcall, return the chain (which is the DAG root).
1966 return DAG.getRoot();
1968 return CallInfo.first;
1971 /// Generate a libcall taking the given operands as arguments
1972 /// and returning a result of type RetVT.
1973 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
1974 const SDValue *Ops, unsigned NumOps,
1975 bool isSigned, const SDLoc &dl) {
1976 TargetLowering::ArgListTy Args;
1977 Args.reserve(NumOps);
1979 TargetLowering::ArgListEntry Entry;
1980 for (unsigned i = 0; i != NumOps; ++i) {
1981 Entry.Node = Ops[i];
1982 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
1983 Entry.isSExt = isSigned;
1984 Entry.isZExt = !isSigned;
1985 Args.push_back(Entry);
1987 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1988 TLI.getPointerTy(DAG.getDataLayout()));
1990 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
1992 TargetLowering::CallLoweringInfo CLI(DAG);
1993 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1994 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
1995 .setSExtResult(isSigned).setZExtResult(!isSigned);
1997 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
1999 return CallInfo.first;
2002 // Expand a node into a call to a libcall. Similar to
2003 // ExpandLibCall except that the first operand is the in-chain.
2004 std::pair<SDValue, SDValue>
2005 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2008 SDValue InChain = Node->getOperand(0);
2010 TargetLowering::ArgListTy Args;
2011 TargetLowering::ArgListEntry Entry;
2012 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2013 EVT ArgVT = Node->getOperand(i).getValueType();
2014 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2015 Entry.Node = Node->getOperand(i);
2017 Entry.isSExt = isSigned;
2018 Entry.isZExt = !isSigned;
2019 Args.push_back(Entry);
2021 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2022 TLI.getPointerTy(DAG.getDataLayout()));
2024 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2026 TargetLowering::CallLoweringInfo CLI(DAG);
2027 CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2028 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
2029 .setSExtResult(isSigned).setZExtResult(!isSigned);
2031 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2036 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2037 RTLIB::Libcall Call_F32,
2038 RTLIB::Libcall Call_F64,
2039 RTLIB::Libcall Call_F80,
2040 RTLIB::Libcall Call_F128,
2041 RTLIB::Libcall Call_PPCF128) {
2043 switch (Node->getSimpleValueType(0).SimpleTy) {
2044 default: llvm_unreachable("Unexpected request for libcall!");
2045 case MVT::f32: LC = Call_F32; break;
2046 case MVT::f64: LC = Call_F64; break;
2047 case MVT::f80: LC = Call_F80; break;
2048 case MVT::f128: LC = Call_F128; break;
2049 case MVT::ppcf128: LC = Call_PPCF128; break;
2051 return ExpandLibCall(LC, Node, false);
2054 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2055 RTLIB::Libcall Call_I8,
2056 RTLIB::Libcall Call_I16,
2057 RTLIB::Libcall Call_I32,
2058 RTLIB::Libcall Call_I64,
2059 RTLIB::Libcall Call_I128) {
2061 switch (Node->getSimpleValueType(0).SimpleTy) {
2062 default: llvm_unreachable("Unexpected request for libcall!");
2063 case MVT::i8: LC = Call_I8; break;
2064 case MVT::i16: LC = Call_I16; break;
2065 case MVT::i32: LC = Call_I32; break;
2066 case MVT::i64: LC = Call_I64; break;
2067 case MVT::i128: LC = Call_I128; break;
2069 return ExpandLibCall(LC, Node, isSigned);
2072 /// Issue libcalls to __{u}divmod to compute div / rem pairs.
2074 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2075 SmallVectorImpl<SDValue> &Results) {
2076 unsigned Opcode = Node->getOpcode();
2077 bool isSigned = Opcode == ISD::SDIVREM;
2080 switch (Node->getSimpleValueType(0).SimpleTy) {
2081 default: llvm_unreachable("Unexpected request for libcall!");
2082 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2083 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2084 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2085 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2086 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2089 // The input chain to this libcall is the entry node of the function.
2090 // Legalizing the call will automatically add the previous call to the
2092 SDValue InChain = DAG.getEntryNode();
2094 EVT RetVT = Node->getValueType(0);
2095 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2097 TargetLowering::ArgListTy Args;
2098 TargetLowering::ArgListEntry Entry;
2099 for (const SDValue &Op : Node->op_values()) {
2100 EVT ArgVT = Op.getValueType();
2101 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2104 Entry.isSExt = isSigned;
2105 Entry.isZExt = !isSigned;
2106 Args.push_back(Entry);
2109 // Also pass the return address of the remainder.
2110 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2112 Entry.Ty = RetTy->getPointerTo();
2113 Entry.isSExt = isSigned;
2114 Entry.isZExt = !isSigned;
2115 Args.push_back(Entry);
2117 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2118 TLI.getPointerTy(DAG.getDataLayout()));
2121 TargetLowering::CallLoweringInfo CLI(DAG);
2122 CLI.setDebugLoc(dl).setChain(InChain)
2123 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
2124 .setSExtResult(isSigned).setZExtResult(!isSigned);
2126 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2128 // Remainder is loaded back from the stack frame.
2130 DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr, MachinePointerInfo());
2131 Results.push_back(CallInfo.first);
2132 Results.push_back(Rem);
2135 /// Return true if sincos libcall is available.
2136 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2138 switch (Node->getSimpleValueType(0).SimpleTy) {
2139 default: llvm_unreachable("Unexpected request for libcall!");
2140 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2141 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2142 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2143 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2144 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2146 return TLI.getLibcallName(LC) != nullptr;
2149 /// Return true if sincos libcall is available and can be used to combine sin
2151 static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
2152 const TargetMachine &TM) {
2153 if (!isSinCosLibcallAvailable(Node, TLI))
2155 // GNU sin/cos functions set errno while sincos does not. Therefore
2156 // combining sin and cos is only safe if unsafe-fpmath is enabled.
2157 if (TM.getTargetTriple().isGNUEnvironment() && !TM.Options.UnsafeFPMath)
2162 /// Only issue sincos libcall if both sin and cos are needed.
2163 static bool useSinCos(SDNode *Node) {
2164 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2165 ? ISD::FCOS : ISD::FSIN;
2167 SDValue Op0 = Node->getOperand(0);
2168 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2169 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2173 // The other user might have been turned into sincos already.
2174 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2180 /// Issue libcalls to sincos to compute sin / cos pairs.
2182 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2183 SmallVectorImpl<SDValue> &Results) {
2185 switch (Node->getSimpleValueType(0).SimpleTy) {
2186 default: llvm_unreachable("Unexpected request for libcall!");
2187 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2188 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2189 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2190 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2191 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2194 // The input chain to this libcall is the entry node of the function.
2195 // Legalizing the call will automatically add the previous call to the
2197 SDValue InChain = DAG.getEntryNode();
2199 EVT RetVT = Node->getValueType(0);
2200 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2202 TargetLowering::ArgListTy Args;
2203 TargetLowering::ArgListEntry Entry;
2205 // Pass the argument.
2206 Entry.Node = Node->getOperand(0);
2208 Entry.isSExt = false;
2209 Entry.isZExt = false;
2210 Args.push_back(Entry);
2212 // Pass the return address of sin.
2213 SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2214 Entry.Node = SinPtr;
2215 Entry.Ty = RetTy->getPointerTo();
2216 Entry.isSExt = false;
2217 Entry.isZExt = false;
2218 Args.push_back(Entry);
2220 // Also pass the return address of the cos.
2221 SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2222 Entry.Node = CosPtr;
2223 Entry.Ty = RetTy->getPointerTo();
2224 Entry.isSExt = false;
2225 Entry.isZExt = false;
2226 Args.push_back(Entry);
2228 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2229 TLI.getPointerTy(DAG.getDataLayout()));
2232 TargetLowering::CallLoweringInfo CLI(DAG);
2233 CLI.setDebugLoc(dl).setChain(InChain)
2234 .setCallee(TLI.getLibcallCallingConv(LC),
2235 Type::getVoidTy(*DAG.getContext()), Callee, std::move(Args));
2237 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2240 DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr, MachinePointerInfo()));
2242 DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr, MachinePointerInfo()));
2245 /// This function is responsible for legalizing a
2246 /// INT_TO_FP operation of the specified operand when the target requests that
2247 /// we expand it. At this point, we know that the result and operand types are
2248 /// legal for the target.
2249 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0,
2252 // TODO: Should any fast-math-flags be set for the created nodes?
2254 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2255 // simple 32-bit [signed|unsigned] integer to float/double expansion
2257 // Get the stack frame index of a 8 byte buffer.
2258 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2260 // word offset constant for Hi/Lo address computation
2261 SDValue WordOff = DAG.getConstant(sizeof(int), dl,
2262 StackSlot.getValueType());
2263 // set up Hi and Lo (into buffer) address based on endian
2264 SDValue Hi = StackSlot;
2265 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2266 StackSlot, WordOff);
2267 if (DAG.getDataLayout().isLittleEndian())
2270 // if signed map to unsigned space
2273 // constant used to invert sign bit (signed to unsigned mapping)
2274 SDValue SignBit = DAG.getConstant(0x80000000u, dl, MVT::i32);
2275 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2279 // store the lo of the constructed double - based on integer input
2280 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op0Mapped, Lo,
2281 MachinePointerInfo());
2282 // initial hi portion of constructed double
2283 SDValue InitialHi = DAG.getConstant(0x43300000u, dl, MVT::i32);
2284 // store the hi of the constructed double - biased exponent
2286 DAG.getStore(Store1, dl, InitialHi, Hi, MachinePointerInfo());
2287 // load the constructed double
2289 DAG.getLoad(MVT::f64, dl, Store2, StackSlot, MachinePointerInfo());
2290 // FP constant to bias correct the final result
2291 SDValue Bias = DAG.getConstantFP(isSigned ?
2292 BitsToDouble(0x4330000080000000ULL) :
2293 BitsToDouble(0x4330000000000000ULL),
2295 // subtract the bias
2296 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2299 // handle final rounding
2300 if (DestVT == MVT::f64) {
2303 } else if (DestVT.bitsLT(MVT::f64)) {
2304 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2305 DAG.getIntPtrConstant(0, dl));
2306 } else if (DestVT.bitsGT(MVT::f64)) {
2307 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2311 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2312 // Code below here assumes !isSigned without checking again.
2314 // Implementation of unsigned i64 to f64 following the algorithm in
2315 // __floatundidf in compiler_rt. This implementation has the advantage
2316 // of performing rounding correctly, both in the default rounding mode
2317 // and in all alternate rounding modes.
2318 // TODO: Generalize this for use with other types.
2319 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2321 DAG.getConstant(UINT64_C(0x4330000000000000), dl, MVT::i64);
2322 SDValue TwoP84PlusTwoP52 =
2323 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), dl,
2326 DAG.getConstant(UINT64_C(0x4530000000000000), dl, MVT::i64);
2328 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2329 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2330 DAG.getConstant(32, dl, MVT::i64));
2331 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2332 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2333 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2334 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2335 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2337 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2340 // Implementation of unsigned i64 to f32.
2341 // TODO: Generalize this for use with other types.
2342 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2343 // For unsigned conversions, convert them to signed conversions using the
2344 // algorithm from the x86_64 __floatundidf in compiler_rt.
2346 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2348 SDValue ShiftConst = DAG.getConstant(
2349 1, dl, TLI.getShiftAmountTy(Op0.getValueType(), DAG.getDataLayout()));
2350 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2351 SDValue AndConst = DAG.getConstant(1, dl, MVT::i64);
2352 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2353 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2355 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2356 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2358 // TODO: This really should be implemented using a branch rather than a
2359 // select. We happen to get lucky and machinesink does the right
2360 // thing most of the time. This would be a good candidate for a
2361 //pseudo-op, or, even better, for whole-function isel.
2362 SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2363 Op0, DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
2364 return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
2367 // Otherwise, implement the fully general conversion.
2369 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2370 DAG.getConstant(UINT64_C(0xfffffffffffff800), dl, MVT::i64));
2371 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2372 DAG.getConstant(UINT64_C(0x800), dl, MVT::i64));
2373 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2374 DAG.getConstant(UINT64_C(0x7ff), dl, MVT::i64));
2375 SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), And2,
2376 DAG.getConstant(UINT64_C(0), dl, MVT::i64),
2378 SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2379 SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), Op0,
2380 DAG.getConstant(UINT64_C(0x0020000000000000), dl,
2383 SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
2384 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType(), DAG.getDataLayout());
2386 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2387 DAG.getConstant(32, dl, SHVT));
2388 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2389 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2391 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), dl,
2393 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2394 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2395 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2396 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2397 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2398 DAG.getIntPtrConstant(0, dl));
2401 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2403 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2405 DAG.getConstant(0, dl, Op0.getValueType()),
2407 SDValue Zero = DAG.getIntPtrConstant(0, dl),
2408 Four = DAG.getIntPtrConstant(4, dl);
2409 SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2410 SignSet, Four, Zero);
2412 // If the sign bit of the integer is set, the large number will be treated
2413 // as a negative number. To counteract this, the dynamic code adds an
2414 // offset depending on the data type.
2416 switch (Op0.getSimpleValueType().SimpleTy) {
2417 default: llvm_unreachable("Unsupported integer type!");
2418 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2419 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2420 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2421 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2423 if (DAG.getDataLayout().isLittleEndian())
2425 Constant *FudgeFactor = ConstantInt::get(
2426 Type::getInt64Ty(*DAG.getContext()), FF);
2429 DAG.getConstantPool(FudgeFactor, TLI.getPointerTy(DAG.getDataLayout()));
2430 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2431 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2432 Alignment = std::min(Alignment, 4u);
2434 if (DestVT == MVT::f32)
2435 FudgeInReg = DAG.getLoad(
2436 MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2437 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
2440 SDValue Load = DAG.getExtLoad(
2441 ISD::EXTLOAD, dl, DestVT, DAG.getEntryNode(), CPIdx,
2442 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
2444 HandleSDNode Handle(Load);
2445 LegalizeOp(Load.getNode());
2446 FudgeInReg = Handle.getValue();
2449 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2452 /// This function is responsible for legalizing a
2453 /// *INT_TO_FP operation of the specified operand when the target requests that
2454 /// we promote it. At this point, we know that the result and operand types are
2455 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2456 /// operation that takes a larger input.
2457 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT,
2460 // First step, figure out the appropriate *INT_TO_FP operation to use.
2461 EVT NewInTy = LegalOp.getValueType();
2463 unsigned OpToUse = 0;
2465 // Scan for the appropriate larger type to use.
2467 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2468 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2470 // If the target supports SINT_TO_FP of this type, use it.
2471 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2472 OpToUse = ISD::SINT_TO_FP;
2475 if (isSigned) continue;
2477 // If the target supports UINT_TO_FP of this type, use it.
2478 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2479 OpToUse = ISD::UINT_TO_FP;
2483 // Otherwise, try a larger type.
2486 // Okay, we found the operation and type to use. Zero extend our input to the
2487 // desired type then run the operation on it.
2488 return DAG.getNode(OpToUse, dl, DestVT,
2489 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2490 dl, NewInTy, LegalOp));
2493 /// This function is responsible for legalizing a
2494 /// FP_TO_*INT operation of the specified operand when the target requests that
2495 /// we promote it. At this point, we know that the result and operand types are
2496 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2497 /// operation that returns a larger result.
2498 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT,
2501 // First step, figure out the appropriate FP_TO*INT operation to use.
2502 EVT NewOutTy = DestVT;
2504 unsigned OpToUse = 0;
2506 // Scan for the appropriate larger type to use.
2508 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2509 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2511 // A larger signed type can hold all unsigned values of the requested type,
2512 // so using FP_TO_SINT is valid
2513 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2514 OpToUse = ISD::FP_TO_SINT;
2518 // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
2519 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2520 OpToUse = ISD::FP_TO_UINT;
2524 // Otherwise, try a larger type.
2528 // Okay, we found the operation and type to use.
2529 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2531 // Truncate the result of the extended FP_TO_*INT operation to the desired
2533 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2536 /// Legalize a BITREVERSE scalar/vector operation as a series of mask + shifts.
2537 SDValue SelectionDAGLegalize::ExpandBITREVERSE(SDValue Op, const SDLoc &dl) {
2538 EVT VT = Op.getValueType();
2539 EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2540 unsigned Sz = VT.getScalarSizeInBits();
2542 SDValue Tmp, Tmp2, Tmp3;
2544 // If we can, perform BSWAP first and then the mask+swap the i4, then i2
2545 // and finally the i1 pairs.
2546 // TODO: We can easily support i4/i2 legal types if any target ever does.
2547 if (Sz >= 8 && isPowerOf2_32(Sz)) {
2548 // Create the masks - repeating the pattern every byte.
2549 APInt MaskHi4(Sz, 0), MaskHi2(Sz, 0), MaskHi1(Sz, 0);
2550 APInt MaskLo4(Sz, 0), MaskLo2(Sz, 0), MaskLo1(Sz, 0);
2551 for (unsigned J = 0; J != Sz; J += 8) {
2552 MaskHi4 = MaskHi4.Or(APInt(Sz, 0xF0ull << J));
2553 MaskLo4 = MaskLo4.Or(APInt(Sz, 0x0Full << J));
2554 MaskHi2 = MaskHi2.Or(APInt(Sz, 0xCCull << J));
2555 MaskLo2 = MaskLo2.Or(APInt(Sz, 0x33ull << J));
2556 MaskHi1 = MaskHi1.Or(APInt(Sz, 0xAAull << J));
2557 MaskLo1 = MaskLo1.Or(APInt(Sz, 0x55ull << J));
2560 // BSWAP if the type is wider than a single byte.
2561 Tmp = (Sz > 8 ? DAG.getNode(ISD::BSWAP, dl, VT, Op) : Op);
2563 // swap i4: ((V & 0xF0) >> 4) | ((V & 0x0F) << 4)
2564 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi4, dl, VT));
2565 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo4, dl, VT));
2566 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(4, dl, VT));
2567 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(4, dl, VT));
2568 Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2570 // swap i2: ((V & 0xCC) >> 2) | ((V & 0x33) << 2)
2571 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi2, dl, VT));
2572 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo2, dl, VT));
2573 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(2, dl, VT));
2574 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(2, dl, VT));
2575 Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2577 // swap i1: ((V & 0xAA) >> 1) | ((V & 0x55) << 1)
2578 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi1, dl, VT));
2579 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo1, dl, VT));
2580 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(1, dl, VT));
2581 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(1, dl, VT));
2582 Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2586 Tmp = DAG.getConstant(0, dl, VT);
2587 for (unsigned I = 0, J = Sz-1; I < Sz; ++I, --J) {
2590 DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(J - I, dl, SHVT));
2593 DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(I - J, dl, SHVT));
2596 Shift = Shift.shl(J);
2597 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Shift, dl, VT));
2598 Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp, Tmp2);
2604 /// Open code the operations for BSWAP of the specified operation.
2605 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, const SDLoc &dl) {
2606 EVT VT = Op.getValueType();
2607 EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2608 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2609 switch (VT.getSimpleVT().getScalarType().SimpleTy) {
2610 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2612 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2613 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2614 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2616 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2617 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2618 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2619 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2620 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2621 DAG.getConstant(0xFF0000, dl, VT));
2622 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT));
2623 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2624 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2625 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2627 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2628 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2629 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2630 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2631 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2632 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2633 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2634 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2635 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7,
2636 DAG.getConstant(255ULL<<48, dl, VT));
2637 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6,
2638 DAG.getConstant(255ULL<<40, dl, VT));
2639 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5,
2640 DAG.getConstant(255ULL<<32, dl, VT));
2641 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4,
2642 DAG.getConstant(255ULL<<24, dl, VT));
2643 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2644 DAG.getConstant(255ULL<<16, dl, VT));
2645 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2,
2646 DAG.getConstant(255ULL<<8 , dl, VT));
2647 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2648 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2649 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2650 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2651 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2652 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2653 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2657 /// Expand the specified bitcount instruction into operations.
2658 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2661 default: llvm_unreachable("Cannot expand this yet!");
2663 EVT VT = Op.getValueType();
2664 EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2665 unsigned Len = VT.getSizeInBits();
2667 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2668 "CTPOP not implemented for this type.");
2670 // This is the "best" algorithm from
2671 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2673 SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)),
2675 SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)),
2677 SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)),
2679 SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)),
2682 // v = v - ((v >> 1) & 0x55555555...)
2683 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2684 DAG.getNode(ISD::AND, dl, VT,
2685 DAG.getNode(ISD::SRL, dl, VT, Op,
2686 DAG.getConstant(1, dl, ShVT)),
2688 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2689 Op = DAG.getNode(ISD::ADD, dl, VT,
2690 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2691 DAG.getNode(ISD::AND, dl, VT,
2692 DAG.getNode(ISD::SRL, dl, VT, Op,
2693 DAG.getConstant(2, dl, ShVT)),
2695 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2696 Op = DAG.getNode(ISD::AND, dl, VT,
2697 DAG.getNode(ISD::ADD, dl, VT, Op,
2698 DAG.getNode(ISD::SRL, dl, VT, Op,
2699 DAG.getConstant(4, dl, ShVT))),
2701 // v = (v * 0x01010101...) >> (Len - 8)
2702 Op = DAG.getNode(ISD::SRL, dl, VT,
2703 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2704 DAG.getConstant(Len - 8, dl, ShVT));
2708 case ISD::CTLZ_ZERO_UNDEF:
2709 // This trivially expands to CTLZ.
2710 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2712 EVT VT = Op.getValueType();
2713 unsigned len = VT.getSizeInBits();
2715 if (TLI.isOperationLegalOrCustom(ISD::CTLZ_ZERO_UNDEF, VT)) {
2716 EVT SetCCVT = getSetCCResultType(VT);
2717 SDValue CTLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, VT, Op);
2718 SDValue Zero = DAG.getConstant(0, dl, VT);
2719 SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ);
2720 return DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero,
2721 DAG.getConstant(len, dl, VT), CTLZ);
2724 // for now, we do this:
2725 // x = x | (x >> 1);
2726 // x = x | (x >> 2);
2728 // x = x | (x >>16);
2729 // x = x | (x >>32); // for 64-bit input
2730 // return popcount(~x);
2732 // Ref: "Hacker's Delight" by Henry Warren
2733 EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2734 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2735 SDValue Tmp3 = DAG.getConstant(1ULL << i, dl, ShVT);
2736 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2737 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2739 Op = DAG.getNOT(dl, Op, VT);
2740 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2742 case ISD::CTTZ_ZERO_UNDEF:
2743 // This trivially expands to CTTZ.
2744 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2746 // for now, we use: { return popcount(~x & (x - 1)); }
2747 // unless the target has ctlz but not ctpop, in which case we use:
2748 // { return 32 - nlz(~x & (x-1)); }
2749 // Ref: "Hacker's Delight" by Henry Warren
2750 EVT VT = Op.getValueType();
2751 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2752 DAG.getNOT(dl, Op, VT),
2753 DAG.getNode(ISD::SUB, dl, VT, Op,
2754 DAG.getConstant(1, dl, VT)));
2755 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2756 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2757 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2758 return DAG.getNode(ISD::SUB, dl, VT,
2759 DAG.getConstant(VT.getSizeInBits(), dl, VT),
2760 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2761 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2766 bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2767 SmallVector<SDValue, 8> Results;
2769 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2771 switch (Node->getOpcode()) {
2774 case ISD::CTLZ_ZERO_UNDEF:
2776 case ISD::CTTZ_ZERO_UNDEF:
2777 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2778 Results.push_back(Tmp1);
2780 case ISD::BITREVERSE:
2781 Results.push_back(ExpandBITREVERSE(Node->getOperand(0), dl));
2784 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2786 case ISD::FRAMEADDR:
2787 case ISD::RETURNADDR:
2788 case ISD::FRAME_TO_ARGS_OFFSET:
2789 Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
2791 case ISD::EH_DWARF_CFA: {
2792 SDValue CfaArg = DAG.getSExtOrTrunc(Node->getOperand(0), dl,
2793 TLI.getPointerTy(DAG.getDataLayout()));
2794 SDValue Offset = DAG.getNode(ISD::ADD, dl,
2795 CfaArg.getValueType(),
2796 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
2797 CfaArg.getValueType()),
2799 SDValue FA = DAG.getNode(
2800 ISD::FRAMEADDR, dl, TLI.getPointerTy(DAG.getDataLayout()),
2801 DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout())));
2802 Results.push_back(DAG.getNode(ISD::ADD, dl, FA.getValueType(),
2806 case ISD::FLT_ROUNDS_:
2807 Results.push_back(DAG.getConstant(1, dl, Node->getValueType(0)));
2809 case ISD::EH_RETURN:
2813 case ISD::EH_SJLJ_LONGJMP:
2814 // If the target didn't expand these, there's nothing to do, so just
2815 // preserve the chain and be done.
2816 Results.push_back(Node->getOperand(0));
2818 case ISD::READCYCLECOUNTER:
2819 // If the target didn't expand this, just return 'zero' and preserve the
2821 Results.append(Node->getNumValues() - 1,
2822 DAG.getConstant(0, dl, Node->getValueType(0)));
2823 Results.push_back(Node->getOperand(0));
2825 case ISD::EH_SJLJ_SETJMP:
2826 // If the target didn't expand this, just return 'zero' and preserve the
2828 Results.push_back(DAG.getConstant(0, dl, MVT::i32));
2829 Results.push_back(Node->getOperand(0));
2831 case ISD::ATOMIC_LOAD: {
2832 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2833 SDValue Zero = DAG.getConstant(0, dl, Node->getValueType(0));
2834 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2835 SDValue Swap = DAG.getAtomicCmpSwap(
2836 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2837 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
2838 cast<AtomicSDNode>(Node)->getMemOperand());
2839 Results.push_back(Swap.getValue(0));
2840 Results.push_back(Swap.getValue(1));
2843 case ISD::ATOMIC_STORE: {
2844 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2845 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2846 cast<AtomicSDNode>(Node)->getMemoryVT(),
2847 Node->getOperand(0),
2848 Node->getOperand(1), Node->getOperand(2),
2849 cast<AtomicSDNode>(Node)->getMemOperand());
2850 Results.push_back(Swap.getValue(1));
2853 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
2854 // Expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS produces an ATOMIC_CMP_SWAP and
2855 // splits out the success value as a comparison. Expanding the resulting
2856 // ATOMIC_CMP_SWAP will produce a libcall.
2857 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2858 SDValue Res = DAG.getAtomicCmpSwap(
2859 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2860 Node->getOperand(0), Node->getOperand(1), Node->getOperand(2),
2861 Node->getOperand(3), cast<MemSDNode>(Node)->getMemOperand());
2863 SDValue ExtRes = Res;
2865 SDValue RHS = Node->getOperand(1);
2867 EVT AtomicType = cast<AtomicSDNode>(Node)->getMemoryVT();
2868 EVT OuterType = Node->getValueType(0);
2869 switch (TLI.getExtendForAtomicOps()) {
2870 case ISD::SIGN_EXTEND:
2871 LHS = DAG.getNode(ISD::AssertSext, dl, OuterType, Res,
2872 DAG.getValueType(AtomicType));
2873 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, OuterType,
2874 Node->getOperand(2), DAG.getValueType(AtomicType));
2877 case ISD::ZERO_EXTEND:
2878 LHS = DAG.getNode(ISD::AssertZext, dl, OuterType, Res,
2879 DAG.getValueType(AtomicType));
2880 RHS = DAG.getNode(ISD::ZERO_EXTEND, dl, OuterType, Node->getOperand(2));
2883 case ISD::ANY_EXTEND:
2884 LHS = DAG.getZeroExtendInReg(Res, dl, AtomicType);
2885 RHS = DAG.getNode(ISD::ZERO_EXTEND, dl, OuterType, Node->getOperand(2));
2888 llvm_unreachable("Invalid atomic op extension");
2892 DAG.getSetCC(dl, Node->getValueType(1), LHS, RHS, ISD::SETEQ);
2894 Results.push_back(ExtRes.getValue(0));
2895 Results.push_back(Success);
2896 Results.push_back(Res.getValue(1));
2899 case ISD::DYNAMIC_STACKALLOC:
2900 ExpandDYNAMIC_STACKALLOC(Node, Results);
2902 case ISD::MERGE_VALUES:
2903 for (unsigned i = 0; i < Node->getNumValues(); i++)
2904 Results.push_back(Node->getOperand(i));
2907 EVT VT = Node->getValueType(0);
2909 Results.push_back(DAG.getConstant(0, dl, VT));
2911 assert(VT.isFloatingPoint() && "Unknown value type!");
2912 Results.push_back(DAG.getConstantFP(0, dl, VT));
2918 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2919 Node->getValueType(0), dl);
2920 Results.push_back(Tmp1);
2922 case ISD::FP_EXTEND:
2923 Tmp1 = EmitStackConvert(Node->getOperand(0),
2924 Node->getOperand(0).getValueType(),
2925 Node->getValueType(0), dl);
2926 Results.push_back(Tmp1);
2928 case ISD::SIGN_EXTEND_INREG: {
2929 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2930 EVT VT = Node->getValueType(0);
2932 // An in-register sign-extend of a boolean is a negation:
2933 // 'true' (1) sign-extended is -1.
2934 // 'false' (0) sign-extended is 0.
2935 // However, we must mask the high bits of the source operand because the
2936 // SIGN_EXTEND_INREG does not guarantee that the high bits are already zero.
2938 // TODO: Do this for vectors too?
2939 if (ExtraVT.getSizeInBits() == 1) {
2940 SDValue One = DAG.getConstant(1, dl, VT);
2941 SDValue And = DAG.getNode(ISD::AND, dl, VT, Node->getOperand(0), One);
2942 SDValue Zero = DAG.getConstant(0, dl, VT);
2943 SDValue Neg = DAG.getNode(ISD::SUB, dl, VT, Zero, And);
2944 Results.push_back(Neg);
2948 // NOTE: we could fall back on load/store here too for targets without
2949 // SRA. However, it is doubtful that any exist.
2950 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2953 unsigned BitsDiff = VT.getScalarSizeInBits() -
2954 ExtraVT.getScalarSizeInBits();
2955 SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy);
2956 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2957 Node->getOperand(0), ShiftCst);
2958 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2959 Results.push_back(Tmp1);
2962 case ISD::FP_ROUND_INREG: {
2963 // The only way we can lower this is to turn it into a TRUNCSTORE,
2964 // EXTLOAD pair, targeting a temporary location (a stack slot).
2966 // NOTE: there is a choice here between constantly creating new stack
2967 // slots and always reusing the same one. We currently always create
2968 // new ones, as reuse may inhibit scheduling.
2969 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2970 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2971 Node->getValueType(0), dl);
2972 Results.push_back(Tmp1);
2975 case ISD::SINT_TO_FP:
2976 case ISD::UINT_TO_FP:
2977 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2978 Node->getOperand(0), Node->getValueType(0), dl);
2979 Results.push_back(Tmp1);
2981 case ISD::FP_TO_SINT:
2982 if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG))
2983 Results.push_back(Tmp1);
2985 case ISD::FP_TO_UINT: {
2986 SDValue True, False;
2987 EVT VT = Node->getOperand(0).getValueType();
2988 EVT NVT = Node->getValueType(0);
2989 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
2990 APInt::getNullValue(VT.getSizeInBits()));
2991 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2992 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2993 Tmp1 = DAG.getConstantFP(apf, dl, VT);
2994 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
2995 Node->getOperand(0),
2997 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2998 // TODO: Should any fast-math-flags be set for the FSUB?
2999 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3000 DAG.getNode(ISD::FSUB, dl, VT,
3001 Node->getOperand(0), Tmp1));
3002 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3003 DAG.getConstant(x, dl, NVT));
3004 Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
3005 Results.push_back(Tmp1);
3009 Results.push_back(DAG.expandVAArg(Node));
3010 Results.push_back(Results[0].getValue(1));
3013 Results.push_back(DAG.expandVACopy(Node));
3015 case ISD::EXTRACT_VECTOR_ELT:
3016 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3017 // This must be an access of the only element. Return it.
3018 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3019 Node->getOperand(0));
3021 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3022 Results.push_back(Tmp1);
3024 case ISD::EXTRACT_SUBVECTOR:
3025 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3027 case ISD::INSERT_SUBVECTOR:
3028 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3030 case ISD::CONCAT_VECTORS: {
3031 Results.push_back(ExpandVectorBuildThroughStack(Node));
3034 case ISD::SCALAR_TO_VECTOR:
3035 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3037 case ISD::INSERT_VECTOR_ELT:
3038 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3039 Node->getOperand(1),
3040 Node->getOperand(2), dl));
3042 case ISD::VECTOR_SHUFFLE: {
3043 SmallVector<int, 32> NewMask;
3044 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3046 EVT VT = Node->getValueType(0);
3047 EVT EltVT = VT.getVectorElementType();
3048 SDValue Op0 = Node->getOperand(0);
3049 SDValue Op1 = Node->getOperand(1);
3050 if (!TLI.isTypeLegal(EltVT)) {
3052 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3054 // BUILD_VECTOR operands are allowed to be wider than the element type.
3055 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
3057 if (NewEltVT.bitsLT(EltVT)) {
3059 // Convert shuffle node.
3060 // If original node was v4i64 and the new EltVT is i32,
3061 // cast operands to v8i32 and re-build the mask.
3063 // Calculate new VT, the size of the new VT should be equal to original.
3065 EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3066 VT.getSizeInBits() / NewEltVT.getSizeInBits());
3067 assert(NewVT.bitsEq(VT));
3069 // cast operands to new VT
3070 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3071 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3073 // Convert the shuffle mask
3074 unsigned int factor =
3075 NewVT.getVectorNumElements()/VT.getVectorNumElements();
3077 // EltVT gets smaller
3080 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3082 for (unsigned fi = 0; fi < factor; ++fi)
3083 NewMask.push_back(Mask[i]);
3086 for (unsigned fi = 0; fi < factor; ++fi)
3087 NewMask.push_back(Mask[i]*factor+fi);
3095 unsigned NumElems = VT.getVectorNumElements();
3096 SmallVector<SDValue, 16> Ops;
3097 for (unsigned i = 0; i != NumElems; ++i) {
3099 Ops.push_back(DAG.getUNDEF(EltVT));
3102 unsigned Idx = Mask[i];
3104 Ops.push_back(DAG.getNode(
3105 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
3106 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
3108 Ops.push_back(DAG.getNode(
3109 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1,
3110 DAG.getConstant(Idx - NumElems, dl,
3111 TLI.getVectorIdxTy(DAG.getDataLayout()))));
3114 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3115 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3116 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3117 Results.push_back(Tmp1);
3120 case ISD::EXTRACT_ELEMENT: {
3121 EVT OpTy = Node->getOperand(0).getValueType();
3122 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3124 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3125 DAG.getConstant(OpTy.getSizeInBits() / 2, dl,
3126 TLI.getShiftAmountTy(
3127 Node->getOperand(0).getValueType(),
3128 DAG.getDataLayout())));
3129 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3132 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3133 Node->getOperand(0));
3135 Results.push_back(Tmp1);
3138 case ISD::STACKSAVE:
3139 // Expand to CopyFromReg if the target set
3140 // StackPointerRegisterToSaveRestore.
3141 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3142 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3143 Node->getValueType(0)));
3144 Results.push_back(Results[0].getValue(1));
3146 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3147 Results.push_back(Node->getOperand(0));
3150 case ISD::STACKRESTORE:
3151 // Expand to CopyToReg if the target set
3152 // StackPointerRegisterToSaveRestore.
3153 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3154 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3155 Node->getOperand(1)));
3157 Results.push_back(Node->getOperand(0));
3160 case ISD::GET_DYNAMIC_AREA_OFFSET:
3161 Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
3162 Results.push_back(Results[0].getValue(0));
3164 case ISD::FCOPYSIGN:
3165 Results.push_back(ExpandFCOPYSIGN(Node));
3168 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3169 Tmp1 = DAG.getConstantFP(-0.0, dl, Node->getValueType(0));
3170 // TODO: If FNEG has fast-math-flags, propagate them to the FSUB.
3171 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3172 Node->getOperand(0));
3173 Results.push_back(Tmp1);
3176 Results.push_back(ExpandFABS(Node));
3182 // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B
3184 switch (Node->getOpcode()) {
3185 default: llvm_unreachable("How did we get here?");
3186 case ISD::SMAX: Pred = ISD::SETGT; break;
3187 case ISD::SMIN: Pred = ISD::SETLT; break;
3188 case ISD::UMAX: Pred = ISD::SETUGT; break;
3189 case ISD::UMIN: Pred = ISD::SETULT; break;
3191 Tmp1 = Node->getOperand(0);
3192 Tmp2 = Node->getOperand(1);
3193 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp1, Tmp2, Pred);
3194 Results.push_back(Tmp1);
3200 EVT VT = Node->getValueType(0);
3201 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3202 // fcos which share the same operand and both are used.
3203 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3204 canCombineSinCosLibcall(Node, TLI, TM))
3205 && useSinCos(Node)) {
3206 SDVTList VTs = DAG.getVTList(VT, VT);
3207 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3208 if (Node->getOpcode() == ISD::FCOS)
3209 Tmp1 = Tmp1.getValue(1);
3210 Results.push_back(Tmp1);
3215 llvm_unreachable("Illegal fmad should never be formed");
3217 case ISD::FP16_TO_FP:
3218 if (Node->getValueType(0) != MVT::f32) {
3219 // We can extend to types bigger than f32 in two steps without changing
3220 // the result. Since "f16 -> f32" is much more commonly available, give
3221 // CodeGen the option of emitting that before resorting to a libcall.
3223 DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0));
3225 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res));
3228 case ISD::FP_TO_FP16:
3229 if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) {
3230 SDValue Op = Node->getOperand(0);
3231 MVT SVT = Op.getSimpleValueType();
3232 if ((SVT == MVT::f64 || SVT == MVT::f80) &&
3233 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) {
3234 // Under fastmath, we can expand this node into a fround followed by
3235 // a float-half conversion.
3236 SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
3237 DAG.getIntPtrConstant(0, dl));
3239 DAG.getNode(ISD::FP_TO_FP16, dl, Node->getValueType(0), FloatVal));
3243 case ISD::ConstantFP: {
3244 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3245 // Check to see if this FP immediate is already legal.
3246 // If this is a legal constant, turn it into a TargetConstantFP node.
3247 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3248 Results.push_back(ExpandConstantFP(CFP, true));
3251 case ISD::Constant: {
3252 ConstantSDNode *CP = cast<ConstantSDNode>(Node);
3253 Results.push_back(ExpandConstant(CP));
3257 EVT VT = Node->getValueType(0);
3258 if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3259 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3260 const SDNodeFlags *Flags = &cast<BinaryWithFlagsSDNode>(Node)->Flags;
3261 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3262 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1, Flags);
3263 Results.push_back(Tmp1);
3268 EVT VT = Node->getValueType(0);
3269 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3270 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3271 "Don't know how to expand this subtraction!");
3272 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3273 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
3275 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT));
3276 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3281 EVT VT = Node->getValueType(0);
3282 bool isSigned = Node->getOpcode() == ISD::SREM;
3283 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3284 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3285 Tmp2 = Node->getOperand(0);
3286 Tmp3 = Node->getOperand(1);
3287 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3288 SDVTList VTs = DAG.getVTList(VT, VT);
3289 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3290 Results.push_back(Tmp1);
3291 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3293 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3294 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3295 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3296 Results.push_back(Tmp1);
3302 bool isSigned = Node->getOpcode() == ISD::SDIV;
3303 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3304 EVT VT = Node->getValueType(0);
3305 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3306 SDVTList VTs = DAG.getVTList(VT, VT);
3307 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3308 Node->getOperand(1));
3309 Results.push_back(Tmp1);
3315 unsigned ExpandOpcode =
3316 Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : ISD::SMUL_LOHI;
3317 EVT VT = Node->getValueType(0);
3318 SDVTList VTs = DAG.getVTList(VT, VT);
3320 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3321 Node->getOperand(1));
3322 Results.push_back(Tmp1.getValue(1));
3325 case ISD::UMUL_LOHI:
3326 case ISD::SMUL_LOHI: {
3327 SDValue LHS = Node->getOperand(0);
3328 SDValue RHS = Node->getOperand(1);
3329 MVT VT = LHS.getSimpleValueType();
3330 unsigned MULHOpcode =
3331 Node->getOpcode() == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS;
3333 if (TLI.isOperationLegalOrCustom(MULHOpcode, VT)) {
3334 Results.push_back(DAG.getNode(ISD::MUL, dl, VT, LHS, RHS));
3335 Results.push_back(DAG.getNode(MULHOpcode, dl, VT, LHS, RHS));
3339 SmallVector<SDValue, 4> Halves;
3340 EVT HalfType = EVT(VT).getHalfSizedIntegerVT(*DAG.getContext());
3341 assert(TLI.isTypeLegal(HalfType));
3342 if (TLI.expandMUL_LOHI(Node->getOpcode(), VT, Node, LHS, RHS, Halves,
3344 TargetLowering::MulExpansionKind::Always)) {
3345 for (unsigned i = 0; i < 2; ++i) {
3346 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Halves[2 * i]);
3347 SDValue Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Halves[2 * i + 1]);
3348 SDValue Shift = DAG.getConstant(
3349 HalfType.getScalarSizeInBits(), dl,
3350 TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3351 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3352 Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3359 EVT VT = Node->getValueType(0);
3360 SDVTList VTs = DAG.getVTList(VT, VT);
3361 // See if multiply or divide can be lowered using two-result operations.
3362 // We just need the low half of the multiply; try both the signed
3363 // and unsigned forms. If the target supports both SMUL_LOHI and
3364 // UMUL_LOHI, form a preference by checking which forms of plain
3365 // MULH it supports.
3366 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3367 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3368 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3369 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3370 unsigned OpToUse = 0;
3371 if (HasSMUL_LOHI && !HasMULHS) {
3372 OpToUse = ISD::SMUL_LOHI;
3373 } else if (HasUMUL_LOHI && !HasMULHU) {
3374 OpToUse = ISD::UMUL_LOHI;
3375 } else if (HasSMUL_LOHI) {
3376 OpToUse = ISD::SMUL_LOHI;
3377 } else if (HasUMUL_LOHI) {
3378 OpToUse = ISD::UMUL_LOHI;
3381 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3382 Node->getOperand(1)));
3387 EVT HalfType = VT.getHalfSizedIntegerVT(*DAG.getContext());
3388 if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3389 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3390 TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3391 TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3392 TLI.expandMUL(Node, Lo, Hi, HalfType, DAG,
3393 TargetLowering::MulExpansionKind::OnlyLegalOrCustom)) {
3394 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3395 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3397 DAG.getConstant(HalfType.getSizeInBits(), dl,
3398 TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3399 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3400 Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3406 SDValue LHS = Node->getOperand(0);
3407 SDValue RHS = Node->getOperand(1);
3408 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3409 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3411 Results.push_back(Sum);
3412 EVT ResultType = Node->getValueType(1);
3413 EVT OType = getSetCCResultType(Node->getValueType(0));
3415 SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
3417 // LHSSign -> LHS >= 0
3418 // RHSSign -> RHS >= 0
3419 // SumSign -> Sum >= 0
3422 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3424 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3426 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3427 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3428 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3429 Node->getOpcode() == ISD::SADDO ?
3430 ISD::SETEQ : ISD::SETNE);
3432 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3433 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3435 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3436 Results.push_back(DAG.getBoolExtOrTrunc(Cmp, dl, ResultType, ResultType));
3441 SDValue LHS = Node->getOperand(0);
3442 SDValue RHS = Node->getOperand(1);
3443 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3444 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3446 Results.push_back(Sum);
3448 EVT ResultType = Node->getValueType(1);
3449 EVT SetCCType = getSetCCResultType(Node->getValueType(0));
3451 = Node->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT;
3452 SDValue SetCC = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC);
3454 Results.push_back(DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType));
3459 EVT VT = Node->getValueType(0);
3460 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3461 SDValue LHS = Node->getOperand(0);
3462 SDValue RHS = Node->getOperand(1);
3465 static const unsigned Ops[2][3] =
3466 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3467 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3468 bool isSigned = Node->getOpcode() == ISD::SMULO;
3469 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3470 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3471 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3472 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3473 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3475 TopHalf = BottomHalf.getValue(1);
3476 } else if (TLI.isTypeLegal(WideVT)) {
3477 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3478 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3479 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3480 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3481 DAG.getIntPtrConstant(0, dl));
3482 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3483 DAG.getIntPtrConstant(1, dl));
3485 // We can fall back to a libcall with an illegal type for the MUL if we
3486 // have a libcall big enough.
3487 // Also, we can fall back to a division in some cases, but that's a big
3488 // performance hit in the general case.
3489 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3490 if (WideVT == MVT::i16)
3491 LC = RTLIB::MUL_I16;
3492 else if (WideVT == MVT::i32)
3493 LC = RTLIB::MUL_I32;
3494 else if (WideVT == MVT::i64)
3495 LC = RTLIB::MUL_I64;
3496 else if (WideVT == MVT::i128)
3497 LC = RTLIB::MUL_I128;
3498 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3500 // The high part is obtained by SRA'ing all but one of the bits of low
3502 unsigned LoSize = VT.getSizeInBits();
3504 DAG.getNode(ISD::SRA, dl, VT, RHS,
3505 DAG.getConstant(LoSize - 1, dl,
3506 TLI.getPointerTy(DAG.getDataLayout())));
3508 DAG.getNode(ISD::SRA, dl, VT, LHS,
3509 DAG.getConstant(LoSize - 1, dl,
3510 TLI.getPointerTy(DAG.getDataLayout())));
3512 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3513 // pre-lowered to the correct types. This all depends upon WideVT not
3514 // being a legal type for the architecture and thus has to be split to
3517 if(DAG.getDataLayout().isLittleEndian()) {
3518 // Halves of WideVT are packed into registers in different order
3519 // depending on platform endianness. This is usually handled by
3520 // the C calling convention, but we can't defer to it in
3522 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3523 Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3525 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
3526 Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3528 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3529 DAG.getIntPtrConstant(0, dl));
3530 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3531 DAG.getIntPtrConstant(1, dl));
3532 // Ret is a node with an illegal type. Because such things are not
3533 // generally permitted during this phase of legalization, make sure the
3534 // node has no more uses. The above EXTRACT_ELEMENT nodes should have been
3536 assert(Ret->use_empty() &&
3537 "Unexpected uses of illegally type from expanded lib call.");
3541 Tmp1 = DAG.getConstant(
3542 VT.getSizeInBits() - 1, dl,
3543 TLI.getShiftAmountTy(BottomHalf.getValueType(), DAG.getDataLayout()));
3544 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3545 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3548 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3549 DAG.getConstant(0, dl, VT), ISD::SETNE);
3552 // Truncate the result if SetCC returns a larger type than needed.
3553 EVT RType = Node->getValueType(1);
3554 if (RType.getSizeInBits() < TopHalf.getValueSizeInBits())
3555 TopHalf = DAG.getNode(ISD::TRUNCATE, dl, RType, TopHalf);
3557 assert(RType.getSizeInBits() == TopHalf.getValueSizeInBits() &&
3558 "Unexpected result type for S/UMULO legalization");
3560 Results.push_back(BottomHalf);
3561 Results.push_back(TopHalf);
3564 case ISD::BUILD_PAIR: {
3565 EVT PairTy = Node->getValueType(0);
3566 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3567 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3569 ISD::SHL, dl, PairTy, Tmp2,
3570 DAG.getConstant(PairTy.getSizeInBits() / 2, dl,
3571 TLI.getShiftAmountTy(PairTy, DAG.getDataLayout())));
3572 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3576 Tmp1 = Node->getOperand(0);
3577 Tmp2 = Node->getOperand(1);
3578 Tmp3 = Node->getOperand(2);
3579 if (Tmp1.getOpcode() == ISD::SETCC) {
3580 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3582 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3584 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3585 DAG.getConstant(0, dl, Tmp1.getValueType()),
3586 Tmp2, Tmp3, ISD::SETNE);
3588 Results.push_back(Tmp1);
3591 SDValue Chain = Node->getOperand(0);
3592 SDValue Table = Node->getOperand(1);
3593 SDValue Index = Node->getOperand(2);
3595 const DataLayout &TD = DAG.getDataLayout();
3596 EVT PTy = TLI.getPointerTy(TD);
3598 unsigned EntrySize =
3599 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3601 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
3602 DAG.getConstant(EntrySize, dl, Index.getValueType()));
3603 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3606 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3607 SDValue LD = DAG.getExtLoad(
3608 ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3609 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()), MemVT);
3611 if (TLI.isJumpTableRelative()) {
3612 // For PIC, the sequence is:
3613 // BRIND(load(Jumptable + index) + RelocBase)
3614 // RelocBase can be JumpTable, GOT or some sort of global base.
3615 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3616 TLI.getPICJumpTableRelocBase(Table, DAG));
3618 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3619 Results.push_back(Tmp1);
3623 // Expand brcond's setcc into its constituent parts and create a BR_CC
3625 Tmp1 = Node->getOperand(0);
3626 Tmp2 = Node->getOperand(1);
3627 if (Tmp2.getOpcode() == ISD::SETCC) {
3628 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3629 Tmp1, Tmp2.getOperand(2),
3630 Tmp2.getOperand(0), Tmp2.getOperand(1),
3631 Node->getOperand(2));
3633 // We test only the i1 bit. Skip the AND if UNDEF.
3634 Tmp3 = (Tmp2.isUndef()) ? Tmp2 :
3635 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3636 DAG.getConstant(1, dl, Tmp2.getValueType()));
3637 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3638 DAG.getCondCode(ISD::SETNE), Tmp3,
3639 DAG.getConstant(0, dl, Tmp3.getValueType()),
3640 Node->getOperand(2));
3642 Results.push_back(Tmp1);
3645 Tmp1 = Node->getOperand(0);
3646 Tmp2 = Node->getOperand(1);
3647 Tmp3 = Node->getOperand(2);
3648 bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3649 Tmp3, NeedInvert, dl);
3652 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3653 // condition code, create a new SETCC node.
3655 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3658 // If we expanded the SETCC by inverting the condition code, then wrap
3659 // the existing SETCC in a NOT to restore the intended condition.
3661 Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
3663 Results.push_back(Tmp1);
3667 // Otherwise, SETCC for the given comparison type must be completely
3668 // illegal; expand it into a SELECT_CC.
3669 EVT VT = Node->getValueType(0);
3671 switch (TLI.getBooleanContents(Tmp1->getValueType(0))) {
3672 case TargetLowering::ZeroOrOneBooleanContent:
3673 case TargetLowering::UndefinedBooleanContent:
3676 case TargetLowering::ZeroOrNegativeOneBooleanContent:
3680 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3681 DAG.getConstant(TrueValue, dl, VT),
3682 DAG.getConstant(0, dl, VT),
3684 Results.push_back(Tmp1);
3687 case ISD::SELECT_CC: {
3688 Tmp1 = Node->getOperand(0); // LHS
3689 Tmp2 = Node->getOperand(1); // RHS
3690 Tmp3 = Node->getOperand(2); // True
3691 Tmp4 = Node->getOperand(3); // False
3692 EVT VT = Node->getValueType(0);
3693 SDValue CC = Node->getOperand(4);
3694 ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
3696 if (TLI.isCondCodeLegal(CCOp, Tmp1.getSimpleValueType())) {
3697 // If the condition code is legal, then we need to expand this
3698 // node using SETCC and SELECT.
3699 EVT CmpVT = Tmp1.getValueType();
3700 assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
3701 "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
3704 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), CmpVT);
3705 SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC);
3706 Results.push_back(DAG.getSelect(dl, VT, Cond, Tmp3, Tmp4));
3710 // SELECT_CC is legal, so the condition code must not be.
3711 bool Legalized = false;
3712 // Try to legalize by inverting the condition. This is for targets that
3713 // might support an ordered version of a condition, but not the unordered
3714 // version (or vice versa).
3715 ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
3716 Tmp1.getValueType().isInteger());
3717 if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) {
3718 // Use the new condition code and swap true and false
3720 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3722 // If The inverse is not legal, then try to swap the arguments using
3723 // the inverse condition code.
3724 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3725 if (TLI.isCondCodeLegal(SwapInvCC, Tmp1.getSimpleValueType())) {
3726 // The swapped inverse condition is legal, so swap true and false,
3729 Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3734 Legalized = LegalizeSetCCCondCode(
3735 getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3738 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3740 // If we expanded the SETCC by inverting the condition code, then swap
3741 // the True/False operands to match.
3743 std::swap(Tmp3, Tmp4);
3745 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3746 // condition code, create a new SELECT_CC node.
3748 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3749 Tmp1, Tmp2, Tmp3, Tmp4, CC);
3751 Tmp2 = DAG.getConstant(0, dl, Tmp1.getValueType());
3752 CC = DAG.getCondCode(ISD::SETNE);
3753 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
3754 Tmp2, Tmp3, Tmp4, CC);
3757 Results.push_back(Tmp1);
3761 Tmp1 = Node->getOperand(0); // Chain
3762 Tmp2 = Node->getOperand(2); // LHS
3763 Tmp3 = Node->getOperand(3); // RHS
3764 Tmp4 = Node->getOperand(1); // CC
3766 bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
3767 Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
3769 assert(Legalized && "Can't legalize BR_CC with legal condition!");
3771 // If we expanded the SETCC by inverting the condition code, then wrap
3772 // the existing SETCC in a NOT to restore the intended condition.
3774 Tmp4 = DAG.getNOT(dl, Tmp4, Tmp4->getValueType(0));
3776 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
3778 if (Tmp4.getNode()) {
3779 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
3780 Tmp4, Tmp2, Tmp3, Node->getOperand(4));
3782 Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType());
3783 Tmp4 = DAG.getCondCode(ISD::SETNE);
3784 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
3785 Tmp2, Tmp3, Node->getOperand(4));
3787 Results.push_back(Tmp1);
3790 case ISD::BUILD_VECTOR:
3791 Results.push_back(ExpandBUILD_VECTOR(Node));
3796 // Scalarize vector SRA/SRL/SHL.
3797 EVT VT = Node->getValueType(0);
3798 assert(VT.isVector() && "Unable to legalize non-vector shift");
3799 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3800 unsigned NumElem = VT.getVectorNumElements();
3802 SmallVector<SDValue, 8> Scalars;
3803 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3804 SDValue Ex = DAG.getNode(
3805 ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(0),
3806 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3807 SDValue Sh = DAG.getNode(
3808 ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(1),
3809 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3810 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3811 VT.getScalarType(), Ex, Sh));
3814 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Scalars);
3815 ReplaceNode(SDValue(Node, 0), Result);
3818 case ISD::GLOBAL_OFFSET_TABLE:
3819 case ISD::GlobalAddress:
3820 case ISD::GlobalTLSAddress:
3821 case ISD::ExternalSymbol:
3822 case ISD::ConstantPool:
3823 case ISD::JumpTable:
3824 case ISD::INTRINSIC_W_CHAIN:
3825 case ISD::INTRINSIC_WO_CHAIN:
3826 case ISD::INTRINSIC_VOID:
3827 // FIXME: Custom lowering for these operations shouldn't return null!
3831 // Replace the original node with the legalized result.
3832 if (Results.empty())
3835 ReplaceNode(Node, Results.data());
3839 void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
3840 SmallVector<SDValue, 8> Results;
3842 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
3843 unsigned Opc = Node->getOpcode();
3845 case ISD::ATOMIC_FENCE: {
3846 // If the target didn't lower this, lower it to '__sync_synchronize()' call
3847 // FIXME: handle "fence singlethread" more efficiently.
3848 TargetLowering::ArgListTy Args;
3850 TargetLowering::CallLoweringInfo CLI(DAG);
3852 .setChain(Node->getOperand(0))
3853 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3854 DAG.getExternalSymbol("__sync_synchronize",
3855 TLI.getPointerTy(DAG.getDataLayout())),
3858 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3860 Results.push_back(CallResult.second);
3863 // By default, atomic intrinsics are marked Legal and lowered. Targets
3864 // which don't support them directly, however, may want libcalls, in which
3865 // case they mark them Expand, and we get here.
3866 case ISD::ATOMIC_SWAP:
3867 case ISD::ATOMIC_LOAD_ADD:
3868 case ISD::ATOMIC_LOAD_SUB:
3869 case ISD::ATOMIC_LOAD_AND:
3870 case ISD::ATOMIC_LOAD_OR:
3871 case ISD::ATOMIC_LOAD_XOR:
3872 case ISD::ATOMIC_LOAD_NAND:
3873 case ISD::ATOMIC_LOAD_MIN:
3874 case ISD::ATOMIC_LOAD_MAX:
3875 case ISD::ATOMIC_LOAD_UMIN:
3876 case ISD::ATOMIC_LOAD_UMAX:
3877 case ISD::ATOMIC_CMP_SWAP: {
3878 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
3879 RTLIB::Libcall LC = RTLIB::getSYNC(Opc, VT);
3880 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
3882 std::pair<SDValue, SDValue> Tmp = ExpandChainLibCall(LC, Node, false);
3883 Results.push_back(Tmp.first);
3884 Results.push_back(Tmp.second);
3888 // If this operation is not supported, lower it to 'abort()' call
3889 TargetLowering::ArgListTy Args;
3890 TargetLowering::CallLoweringInfo CLI(DAG);
3892 .setChain(Node->getOperand(0))
3893 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3894 DAG.getExternalSymbol("abort",
3895 TLI.getPointerTy(DAG.getDataLayout())),
3897 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3899 Results.push_back(CallResult.second);
3903 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
3904 RTLIB::FMIN_F80, RTLIB::FMIN_F128,
3905 RTLIB::FMIN_PPCF128));
3908 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
3909 RTLIB::FMAX_F80, RTLIB::FMAX_F128,
3910 RTLIB::FMAX_PPCF128));
3913 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3914 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3915 RTLIB::SQRT_PPCF128));
3918 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3919 RTLIB::SIN_F80, RTLIB::SIN_F128,
3920 RTLIB::SIN_PPCF128));
3923 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3924 RTLIB::COS_F80, RTLIB::COS_F128,
3925 RTLIB::COS_PPCF128));
3928 // Expand into sincos libcall.
3929 ExpandSinCosLibCall(Node, Results);
3932 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3933 RTLIB::LOG_F80, RTLIB::LOG_F128,
3934 RTLIB::LOG_PPCF128));
3937 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3938 RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3939 RTLIB::LOG2_PPCF128));
3942 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3943 RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3944 RTLIB::LOG10_PPCF128));
3947 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3948 RTLIB::EXP_F80, RTLIB::EXP_F128,
3949 RTLIB::EXP_PPCF128));
3952 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3953 RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3954 RTLIB::EXP2_PPCF128));
3957 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3958 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3959 RTLIB::TRUNC_PPCF128));
3962 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3963 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3964 RTLIB::FLOOR_PPCF128));
3967 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3968 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3969 RTLIB::CEIL_PPCF128));
3972 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3973 RTLIB::RINT_F80, RTLIB::RINT_F128,
3974 RTLIB::RINT_PPCF128));
3976 case ISD::FNEARBYINT:
3977 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3978 RTLIB::NEARBYINT_F64,
3979 RTLIB::NEARBYINT_F80,
3980 RTLIB::NEARBYINT_F128,
3981 RTLIB::NEARBYINT_PPCF128));
3984 Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3988 RTLIB::ROUND_PPCF128));
3991 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3992 RTLIB::POWI_F80, RTLIB::POWI_F128,
3993 RTLIB::POWI_PPCF128));
3996 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3997 RTLIB::POW_F80, RTLIB::POW_F128,
3998 RTLIB::POW_PPCF128));
4001 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
4002 RTLIB::DIV_F80, RTLIB::DIV_F128,
4003 RTLIB::DIV_PPCF128));
4006 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
4007 RTLIB::REM_F80, RTLIB::REM_F128,
4008 RTLIB::REM_PPCF128));
4011 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
4012 RTLIB::FMA_F80, RTLIB::FMA_F128,
4013 RTLIB::FMA_PPCF128));
4016 Results.push_back(ExpandFPLibCall(Node, RTLIB::ADD_F32, RTLIB::ADD_F64,
4017 RTLIB::ADD_F80, RTLIB::ADD_F128,
4018 RTLIB::ADD_PPCF128));
4021 Results.push_back(ExpandFPLibCall(Node, RTLIB::MUL_F32, RTLIB::MUL_F64,
4022 RTLIB::MUL_F80, RTLIB::MUL_F128,
4023 RTLIB::MUL_PPCF128));
4025 case ISD::FP16_TO_FP:
4026 if (Node->getValueType(0) == MVT::f32) {
4027 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
4030 case ISD::FP_TO_FP16: {
4032 RTLIB::getFPROUND(Node->getOperand(0).getValueType(), MVT::f16);
4033 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_fp16");
4034 Results.push_back(ExpandLibCall(LC, Node, false));
4038 Results.push_back(ExpandFPLibCall(Node, RTLIB::SUB_F32, RTLIB::SUB_F64,
4039 RTLIB::SUB_F80, RTLIB::SUB_F128,
4040 RTLIB::SUB_PPCF128));
4043 Results.push_back(ExpandIntLibCall(Node, true,
4045 RTLIB::SREM_I16, RTLIB::SREM_I32,
4046 RTLIB::SREM_I64, RTLIB::SREM_I128));
4049 Results.push_back(ExpandIntLibCall(Node, false,
4051 RTLIB::UREM_I16, RTLIB::UREM_I32,
4052 RTLIB::UREM_I64, RTLIB::UREM_I128));
4055 Results.push_back(ExpandIntLibCall(Node, true,
4057 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
4058 RTLIB::SDIV_I64, RTLIB::SDIV_I128));
4061 Results.push_back(ExpandIntLibCall(Node, false,
4063 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
4064 RTLIB::UDIV_I64, RTLIB::UDIV_I128));
4068 // Expand into divrem libcall
4069 ExpandDivRemLibCall(Node, Results);
4072 Results.push_back(ExpandIntLibCall(Node, false,
4074 RTLIB::MUL_I16, RTLIB::MUL_I32,
4075 RTLIB::MUL_I64, RTLIB::MUL_I128));
4079 // Replace the original node with the legalized result.
4080 if (!Results.empty())
4081 ReplaceNode(Node, Results.data());
4084 // Determine the vector type to use in place of an original scalar element when
4085 // promoting equally sized vectors.
4086 static MVT getPromotedVectorElementType(const TargetLowering &TLI,
4087 MVT EltVT, MVT NewEltVT) {
4088 unsigned OldEltsPerNewElt = EltVT.getSizeInBits() / NewEltVT.getSizeInBits();
4089 MVT MidVT = MVT::getVectorVT(NewEltVT, OldEltsPerNewElt);
4090 assert(TLI.isTypeLegal(MidVT) && "unexpected");
4094 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
4095 SmallVector<SDValue, 8> Results;
4096 MVT OVT = Node->getSimpleValueType(0);
4097 if (Node->getOpcode() == ISD::UINT_TO_FP ||
4098 Node->getOpcode() == ISD::SINT_TO_FP ||
4099 Node->getOpcode() == ISD::SETCC ||
4100 Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
4101 Node->getOpcode() == ISD::INSERT_VECTOR_ELT) {
4102 OVT = Node->getOperand(0).getSimpleValueType();
4104 if (Node->getOpcode() == ISD::BR_CC)
4105 OVT = Node->getOperand(2).getSimpleValueType();
4106 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
4108 SDValue Tmp1, Tmp2, Tmp3;
4109 switch (Node->getOpcode()) {
4111 case ISD::CTTZ_ZERO_UNDEF:
4113 case ISD::CTLZ_ZERO_UNDEF:
4115 // Zero extend the argument.
4116 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4117 if (Node->getOpcode() == ISD::CTTZ) {
4118 // The count is the same in the promoted type except if the original
4119 // value was zero. This can be handled by setting the bit just off
4120 // the top of the original type.
4121 auto TopBit = APInt::getOneBitSet(NVT.getSizeInBits(),
4122 OVT.getSizeInBits());
4123 Tmp1 = DAG.getNode(ISD::OR, dl, NVT, Tmp1,
4124 DAG.getConstant(TopBit, dl, NVT));
4126 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
4127 // already the correct result.
4128 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4129 if (Node->getOpcode() == ISD::CTLZ ||
4130 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4131 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4132 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4133 DAG.getConstant(NVT.getSizeInBits() -
4134 OVT.getSizeInBits(), dl, NVT));
4136 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4138 case ISD::BITREVERSE:
4140 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
4141 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4142 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4144 ISD::SRL, dl, NVT, Tmp1,
4145 DAG.getConstant(DiffBits, dl,
4146 TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
4147 Results.push_back(Tmp1);
4150 case ISD::FP_TO_UINT:
4151 case ISD::FP_TO_SINT:
4152 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
4153 Node->getOpcode() == ISD::FP_TO_SINT, dl);
4154 Results.push_back(Tmp1);
4156 case ISD::UINT_TO_FP:
4157 case ISD::SINT_TO_FP:
4158 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
4159 Node->getOpcode() == ISD::SINT_TO_FP, dl);
4160 Results.push_back(Tmp1);
4163 SDValue Chain = Node->getOperand(0); // Get the chain.
4164 SDValue Ptr = Node->getOperand(1); // Get the pointer.
4167 if (OVT.isVector()) {
4168 TruncOp = ISD::BITCAST;
4170 assert(OVT.isInteger()
4171 && "VAARG promotion is supported only for vectors or integer types");
4172 TruncOp = ISD::TRUNCATE;
4175 // Perform the larger operation, then convert back
4176 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
4177 Node->getConstantOperandVal(3));
4178 Chain = Tmp1.getValue(1);
4180 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
4182 // Modified the chain result - switch anything that used the old chain to
4184 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
4185 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4187 UpdatedNodes->insert(Tmp2.getNode());
4188 UpdatedNodes->insert(Chain.getNode());
4200 unsigned ExtOp, TruncOp;
4201 if (OVT.isVector()) {
4202 ExtOp = ISD::BITCAST;
4203 TruncOp = ISD::BITCAST;
4205 assert(OVT.isInteger() && "Cannot promote logic operation");
4207 switch (Node->getOpcode()) {
4209 ExtOp = ISD::ANY_EXTEND;
4213 ExtOp = ISD::SIGN_EXTEND;
4217 ExtOp = ISD::ZERO_EXTEND;
4220 TruncOp = ISD::TRUNCATE;
4222 // Promote each of the values to the new type.
4223 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4224 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4225 // Perform the larger operation, then convert back
4226 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4227 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4230 case ISD::UMUL_LOHI:
4231 case ISD::SMUL_LOHI: {
4232 // Promote to a multiply in a wider integer type.
4233 unsigned ExtOp = Node->getOpcode() == ISD::UMUL_LOHI ? ISD::ZERO_EXTEND
4235 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4236 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4237 Tmp1 = DAG.getNode(ISD::MUL, dl, NVT, Tmp1, Tmp2);
4239 auto &DL = DAG.getDataLayout();
4240 unsigned OriginalSize = OVT.getScalarSizeInBits();
4242 ISD::SRL, dl, NVT, Tmp1,
4243 DAG.getConstant(OriginalSize, dl, TLI.getScalarShiftAmountTy(DL, NVT)));
4244 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4245 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp2));
4249 unsigned ExtOp, TruncOp;
4250 if (Node->getValueType(0).isVector() ||
4251 Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4252 ExtOp = ISD::BITCAST;
4253 TruncOp = ISD::BITCAST;
4254 } else if (Node->getValueType(0).isInteger()) {
4255 ExtOp = ISD::ANY_EXTEND;
4256 TruncOp = ISD::TRUNCATE;
4258 ExtOp = ISD::FP_EXTEND;
4259 TruncOp = ISD::FP_ROUND;
4261 Tmp1 = Node->getOperand(0);
4262 // Promote each of the values to the new type.
4263 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4264 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4265 // Perform the larger operation, then round down.
4266 Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4267 if (TruncOp != ISD::FP_ROUND)
4268 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4270 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4271 DAG.getIntPtrConstant(0, dl));
4272 Results.push_back(Tmp1);
4275 case ISD::VECTOR_SHUFFLE: {
4276 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4278 // Cast the two input vectors.
4279 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4280 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4282 // Convert the shuffle mask to the right # elements.
4283 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4284 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4285 Results.push_back(Tmp1);
4289 unsigned ExtOp = ISD::FP_EXTEND;
4290 if (NVT.isInteger()) {
4291 ISD::CondCode CCCode =
4292 cast<CondCodeSDNode>(Node->getOperand(2))->get();
4293 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4295 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4296 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4297 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4298 Tmp1, Tmp2, Node->getOperand(2)));
4302 unsigned ExtOp = ISD::FP_EXTEND;
4303 if (NVT.isInteger()) {
4304 ISD::CondCode CCCode =
4305 cast<CondCodeSDNode>(Node->getOperand(1))->get();
4306 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4308 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4309 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(3));
4310 Results.push_back(DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0),
4311 Node->getOperand(0), Node->getOperand(1),
4312 Tmp1, Tmp2, Node->getOperand(4)));
4323 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4324 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4325 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2,
4327 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4328 Tmp3, DAG.getIntPtrConstant(0, dl)));
4332 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4333 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4334 Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2));
4336 DAG.getNode(ISD::FP_ROUND, dl, OVT,
4337 DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3),
4338 DAG.getIntPtrConstant(0, dl)));
4341 case ISD::FCOPYSIGN:
4343 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4344 Tmp2 = Node->getOperand(1);
4345 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4347 // fcopysign doesn't change anything but the sign bit, so
4348 // (fp_round (fcopysign (fpext a), b))
4350 // (fp_round (fpext a))
4351 // which is a no-op. Mark it as a TRUNCating FP_ROUND.
4352 const bool isTrunc = (Node->getOpcode() == ISD::FCOPYSIGN);
4353 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4354 Tmp3, DAG.getIntPtrConstant(isTrunc, dl)));
4360 case ISD::FNEARBYINT:
4373 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4374 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4375 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4376 Tmp2, DAG.getIntPtrConstant(0, dl)));
4379 case ISD::BUILD_VECTOR: {
4380 MVT EltVT = OVT.getVectorElementType();
4381 MVT NewEltVT = NVT.getVectorElementType();
4383 // Handle bitcasts to a different vector type with the same total bit size
4385 // e.g. v2i64 = build_vector i64:x, i64:y => v4i32
4387 // v4i32 = concat_vectors (v2i32 (bitcast i64:x)), (v2i32 (bitcast i64:y))
4389 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4390 "Invalid promote type for build_vector");
4391 assert(NewEltVT.bitsLT(EltVT) && "not handled");
4393 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4395 SmallVector<SDValue, 8> NewOps;
4396 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) {
4397 SDValue Op = Node->getOperand(I);
4398 NewOps.push_back(DAG.getNode(ISD::BITCAST, SDLoc(Op), MidVT, Op));
4402 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps);
4403 SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4404 Results.push_back(CvtVec);
4407 case ISD::EXTRACT_VECTOR_ELT: {
4408 MVT EltVT = OVT.getVectorElementType();
4409 MVT NewEltVT = NVT.getVectorElementType();
4411 // Handle bitcasts to a different vector type with the same total bit size.
4413 // e.g. v2i64 = extract_vector_elt x:v2i64, y:i32
4415 // v4i32:castx = bitcast x:v2i64
4418 // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))),
4419 // (i32 (extract_vector_elt castx, (2 * y + 1)))
4422 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4423 "Invalid promote type for extract_vector_elt");
4424 assert(NewEltVT.bitsLT(EltVT) && "not handled");
4426 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4427 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4429 SDValue Idx = Node->getOperand(1);
4430 EVT IdxVT = Idx.getValueType();
4432 SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SL, IdxVT);
4433 SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4435 SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4437 SmallVector<SDValue, 8> NewOps;
4438 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4439 SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4440 SDValue TmpIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4442 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4444 NewOps.push_back(Elt);
4447 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, SL, MidVT, NewOps);
4449 Results.push_back(DAG.getNode(ISD::BITCAST, SL, EltVT, NewVec));
4452 case ISD::INSERT_VECTOR_ELT: {
4453 MVT EltVT = OVT.getVectorElementType();
4454 MVT NewEltVT = NVT.getVectorElementType();
4456 // Handle bitcasts to a different vector type with the same total bit size
4458 // e.g. v2i64 = insert_vector_elt x:v2i64, y:i64, z:i32
4460 // v4i32:castx = bitcast x:v2i64
4461 // v2i32:casty = bitcast y:i64
4464 // (v4i32 insert_vector_elt
4465 // (v4i32 insert_vector_elt v4i32:castx,
4466 // (extract_vector_elt casty, 0), 2 * z),
4467 // (extract_vector_elt casty, 1), (2 * z + 1))
4469 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4470 "Invalid promote type for insert_vector_elt");
4471 assert(NewEltVT.bitsLT(EltVT) && "not handled");
4473 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4474 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4476 SDValue Val = Node->getOperand(1);
4477 SDValue Idx = Node->getOperand(2);
4478 EVT IdxVT = Idx.getValueType();
4481 SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SDLoc(), IdxVT);
4482 SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4484 SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4485 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4487 SDValue NewVec = CastVec;
4488 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4489 SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4490 SDValue InEltIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4492 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4493 CastVal, IdxOffset);
4495 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT,
4496 NewVec, Elt, InEltIdx);
4499 Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewVec));
4502 case ISD::SCALAR_TO_VECTOR: {
4503 MVT EltVT = OVT.getVectorElementType();
4504 MVT NewEltVT = NVT.getVectorElementType();
4506 // Handle bitcasts to different vector type with the same total bit size.
4508 // e.g. v2i64 = scalar_to_vector x:i64
4510 // concat_vectors (v2i32 bitcast x:i64), (v2i32 undef)
4513 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4514 SDValue Val = Node->getOperand(0);
4517 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4518 SDValue Undef = DAG.getUNDEF(MidVT);
4520 SmallVector<SDValue, 8> NewElts;
4521 NewElts.push_back(CastVal);
4522 for (unsigned I = 1, NElts = OVT.getVectorNumElements(); I != NElts; ++I)
4523 NewElts.push_back(Undef);
4525 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts);
4526 SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4527 Results.push_back(CvtVec);
4532 // Replace the original node with the legalized result.
4533 if (!Results.empty())
4534 ReplaceNode(Node, Results.data());
4537 /// This is the entry point for the file.
4538 void SelectionDAG::Legalize() {
4539 AssignTopologicalOrder();
4541 SmallPtrSet<SDNode *, 16> LegalizedNodes;
4542 SelectionDAGLegalize Legalizer(*this, LegalizedNodes);
4544 // Visit all the nodes. We start in topological order, so that we see
4545 // nodes with their original operands intact. Legalization can produce
4546 // new nodes which may themselves need to be legalized. Iterate until all
4547 // nodes have been legalized.
4549 bool AnyLegalized = false;
4550 for (auto NI = allnodes_end(); NI != allnodes_begin();) {
4554 if (N->use_empty() && N != getRoot().getNode()) {
4560 if (LegalizedNodes.insert(N).second) {
4561 AnyLegalized = true;
4562 Legalizer.LegalizeOp(N);
4564 if (N->use_empty() && N != getRoot().getNode()) {
4575 // Remove dead nodes now.
4579 bool SelectionDAG::LegalizeOp(SDNode *N,
4580 SmallSetVector<SDNode *, 16> &UpdatedNodes) {
4581 SmallPtrSet<SDNode *, 16> LegalizedNodes;
4582 SelectionDAGLegalize Legalizer(*this, LegalizedNodes, &UpdatedNodes);
4584 // Directly insert the node in question, and legalize it. This will recurse
4585 // as needed through operands.
4586 LegalizedNodes.insert(N);
4587 Legalizer.LegalizeOp(N);
4589 return LegalizedNodes.count(N);