1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/IR/DerivedTypes.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 #define DEBUG_TYPE "legalize-types"
29 //===----------------------------------------------------------------------===//
30 // Integer Result Promotion
31 //===----------------------------------------------------------------------===//
33 /// PromoteIntegerResult - This method is called when a result of a node is
34 /// found to be in need of promotion to a larger type. At this point, the node
35 /// may also have invalid operands or may have other results that need
36 /// expansion, we just know that (at least) one result needs promotion.
37 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
38 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
39 SDValue Res = SDValue();
41 // See if the target wants to custom expand this node.
42 if (CustomLowerNode(N, N->getValueType(ResNo), true))
45 switch (N->getOpcode()) {
48 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
49 N->dump(&DAG); dbgs() << "\n";
51 llvm_unreachable("Do not know how to promote this operator!");
52 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
56 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
57 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
58 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
59 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
60 case ISD::CONVERT_RNDSAT:
61 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
62 case ISD::CTLZ_ZERO_UNDEF:
63 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
64 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
65 case ISD::CTTZ_ZERO_UNDEF:
66 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
67 case ISD::EXTRACT_VECTOR_ELT:
68 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
69 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N)); break;
70 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));
72 case ISD::MGATHER: Res = PromoteIntRes_MGATHER(cast<MaskedGatherSDNode>(N));
74 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
75 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
76 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
77 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
79 case ISD::SMAX: Res = PromoteIntRes_SExtIntBinOp(N); break;
81 case ISD::UMAX: Res = PromoteIntRes_ZExtIntBinOp(N); break;
83 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
84 case ISD::SIGN_EXTEND_INREG:
85 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
86 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
87 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
88 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
89 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
90 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
92 case ISD::EXTRACT_SUBVECTOR:
93 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
94 case ISD::VECTOR_SHUFFLE:
95 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
96 case ISD::INSERT_VECTOR_ELT:
97 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
98 case ISD::BUILD_VECTOR:
99 Res = PromoteIntRes_BUILD_VECTOR(N); break;
100 case ISD::SCALAR_TO_VECTOR:
101 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
102 case ISD::CONCAT_VECTORS:
103 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
105 case ISD::SIGN_EXTEND:
106 case ISD::ZERO_EXTEND:
107 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
109 case ISD::FP_TO_SINT:
110 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
112 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
119 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
122 case ISD::SREM: Res = PromoteIntRes_SExtIntBinOp(N); break;
125 case ISD::UREM: Res = PromoteIntRes_ZExtIntBinOp(N); break;
128 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
130 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
132 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
134 case ISD::ATOMIC_LOAD:
135 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
137 case ISD::ATOMIC_LOAD_ADD:
138 case ISD::ATOMIC_LOAD_SUB:
139 case ISD::ATOMIC_LOAD_AND:
140 case ISD::ATOMIC_LOAD_OR:
141 case ISD::ATOMIC_LOAD_XOR:
142 case ISD::ATOMIC_LOAD_NAND:
143 case ISD::ATOMIC_LOAD_MIN:
144 case ISD::ATOMIC_LOAD_MAX:
145 case ISD::ATOMIC_LOAD_UMIN:
146 case ISD::ATOMIC_LOAD_UMAX:
147 case ISD::ATOMIC_SWAP:
148 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
150 case ISD::ATOMIC_CMP_SWAP:
151 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
152 Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
156 // If the result is null then the sub-method took care of registering it.
158 SetPromotedInteger(SDValue(N, ResNo), Res);
161 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
163 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
164 return GetPromotedInteger(Op);
167 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
168 // Sign-extend the new bits, and continue the assertion.
169 SDValue Op = SExtPromotedInteger(N->getOperand(0));
170 return DAG.getNode(ISD::AssertSext, SDLoc(N),
171 Op.getValueType(), Op, N->getOperand(1));
174 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
175 // Zero the new bits, and continue the assertion.
176 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
177 return DAG.getNode(ISD::AssertZext, SDLoc(N),
178 Op.getValueType(), Op, N->getOperand(1));
181 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
182 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
183 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
184 N->getMemoryVT(), ResVT,
185 N->getChain(), N->getBasePtr(),
186 N->getMemOperand(), N->getOrdering(),
188 // Legalize the chain result - switch anything that used the old chain to
190 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
194 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
195 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
196 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
198 N->getChain(), N->getBasePtr(),
199 Op2, N->getMemOperand(), N->getOrdering(),
201 // Legalize the chain result - switch anything that used the old chain to
203 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
207 SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
210 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
211 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
212 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
214 // Only use the result of getSetCCResultType if it is legal,
215 // otherwise just use the promoted result type (NVT).
216 if (!TLI.isTypeLegal(SVT))
219 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
220 SDValue Res = DAG.getAtomicCmpSwap(
221 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
222 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
223 N->getMemOperand(), N->getSuccessOrdering(), N->getFailureOrdering(),
225 ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
226 ReplaceValueWith(SDValue(N, 2), Res.getValue(2));
227 return Res.getValue(1);
230 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
231 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
233 DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
234 SDValue Res = DAG.getAtomicCmpSwap(
235 N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
236 N->getBasePtr(), Op2, Op3, N->getMemOperand(), N->getSuccessOrdering(),
237 N->getFailureOrdering(), N->getSynchScope());
238 // Update the use to N with the newly created Res.
239 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
240 ReplaceValueWith(SDValue(N, i), Res.getValue(i));
244 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
245 SDValue InOp = N->getOperand(0);
246 EVT InVT = InOp.getValueType();
247 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
248 EVT OutVT = N->getValueType(0);
249 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
252 switch (getTypeAction(InVT)) {
253 case TargetLowering::TypeLegal:
255 case TargetLowering::TypePromoteInteger:
256 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
257 // The input promotes to the same size. Convert the promoted value.
258 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
260 case TargetLowering::TypeSoftenFloat:
261 // Promote the integer operand by hand.
262 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
263 case TargetLowering::TypePromoteFloat: {
264 // Convert the promoted float by hand.
265 SDValue PromotedOp = GetPromotedFloat(InOp);
266 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp);
269 case TargetLowering::TypeExpandInteger:
270 case TargetLowering::TypeExpandFloat:
272 case TargetLowering::TypeScalarizeVector:
273 // Convert the element to an integer and promote it by hand.
274 if (!NOutVT.isVector())
275 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
276 BitConvertToInteger(GetScalarizedVector(InOp)));
278 case TargetLowering::TypeSplitVector: {
279 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
280 // pieces of the input into integers and reassemble in the final type.
282 GetSplitVector(N->getOperand(0), Lo, Hi);
283 Lo = BitConvertToInteger(Lo);
284 Hi = BitConvertToInteger(Hi);
286 if (DAG.getDataLayout().isBigEndian())
289 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
290 EVT::getIntegerVT(*DAG.getContext(),
291 NOutVT.getSizeInBits()),
292 JoinIntegers(Lo, Hi));
293 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
295 case TargetLowering::TypeWidenVector:
296 // The input is widened to the same size. Convert to the widened value.
297 // Make sure that the outgoing value is not a vector, because this would
298 // make us bitcast between two vectors which are legalized in different ways.
299 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector())
300 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
303 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
304 CreateStackStoreLoad(InOp, OutVT));
307 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
308 SDValue Op = GetPromotedInteger(N->getOperand(0));
309 EVT OVT = N->getValueType(0);
310 EVT NVT = Op.getValueType();
313 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
315 ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
316 DAG.getConstant(DiffBits, dl,
317 TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
320 SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
321 SDValue Op = GetPromotedInteger(N->getOperand(0));
322 EVT OVT = N->getValueType(0);
323 EVT NVT = Op.getValueType();
326 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
328 ISD::SRL, dl, NVT, DAG.getNode(ISD::BITREVERSE, dl, NVT, Op),
329 DAG.getConstant(DiffBits, dl,
330 TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
333 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
334 // The pair element type may be legal, or may not promote to the same type as
335 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
336 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
337 TLI.getTypeToTransformTo(*DAG.getContext(),
338 N->getValueType(0)), JoinIntegers(N->getOperand(0),
342 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
343 EVT VT = N->getValueType(0);
344 // FIXME there is no actual debug info here
346 // Zero extend things like i1, sign extend everything else. It shouldn't
347 // matter in theory which one we pick, but this tends to give better code?
348 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
349 SDValue Result = DAG.getNode(Opc, dl,
350 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
352 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
356 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
357 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
358 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
359 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
360 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
361 "can only promote integers");
362 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
363 return DAG.getConvertRndSat(OutVT, SDLoc(N), N->getOperand(0),
364 N->getOperand(1), N->getOperand(2),
365 N->getOperand(3), N->getOperand(4), CvtCode);
368 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
369 // Zero extend to the promoted type and do the count there.
370 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
372 EVT OVT = N->getValueType(0);
373 EVT NVT = Op.getValueType();
374 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
375 // Subtract off the extra leading bits in the bigger type.
377 ISD::SUB, dl, NVT, Op,
378 DAG.getConstant(NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), dl,
382 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
383 // Zero extend to the promoted type and do the count there.
384 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
385 return DAG.getNode(ISD::CTPOP, SDLoc(N), Op.getValueType(), Op);
388 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
389 SDValue Op = GetPromotedInteger(N->getOperand(0));
390 EVT OVT = N->getValueType(0);
391 EVT NVT = Op.getValueType();
393 if (N->getOpcode() == ISD::CTTZ) {
394 // The count is the same in the promoted type except if the original
395 // value was zero. This can be handled by setting the bit just off
396 // the top of the original type.
397 auto TopBit = APInt::getOneBitSet(NVT.getScalarSizeInBits(),
398 OVT.getScalarSizeInBits());
399 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, dl, NVT));
401 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
404 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
406 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
407 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
411 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
412 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
413 unsigned NewOpc = N->getOpcode();
416 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
417 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
418 // and SINT conversions are Custom, there is no way to tell which is
419 // preferable. We choose SINT because that's the right thing on PPC.)
420 if (N->getOpcode() == ISD::FP_TO_UINT &&
421 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
422 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
423 NewOpc = ISD::FP_TO_SINT;
425 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
427 // Assert that the converted value fits in the original type. If it doesn't
428 // (eg: because the value being converted is too big), then the result of the
429 // original operation was undefined anyway, so the assert is still correct.
430 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
431 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
432 DAG.getValueType(N->getValueType(0).getScalarType()));
435 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) {
436 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
439 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
441 return DAG.getNode(ISD::AssertZext, dl,
442 NVT, Res, DAG.getValueType(N->getValueType(0)));
445 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
446 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
449 if (getTypeAction(N->getOperand(0).getValueType())
450 == TargetLowering::TypePromoteInteger) {
451 SDValue Res = GetPromotedInteger(N->getOperand(0));
452 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
454 // If the result and operand types are the same after promotion, simplify
455 // to an in-register extension.
456 if (NVT == Res.getValueType()) {
457 // The high bits are not guaranteed to be anything. Insert an extend.
458 if (N->getOpcode() == ISD::SIGN_EXTEND)
459 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
460 DAG.getValueType(N->getOperand(0).getValueType()));
461 if (N->getOpcode() == ISD::ZERO_EXTEND)
462 return DAG.getZeroExtendInReg(Res, dl,
463 N->getOperand(0).getValueType().getScalarType());
464 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
469 // Otherwise, just extend the original operand all the way to the larger type.
470 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
473 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
474 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
475 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
476 ISD::LoadExtType ExtType =
477 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
479 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
480 N->getMemoryVT(), N->getMemOperand());
482 // Legalize the chain result - switch anything that used the old chain to
484 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
488 SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
489 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
490 SDValue ExtSrc0 = GetPromotedInteger(N->getSrc0());
493 SDValue Res = DAG.getMaskedLoad(NVT, dl, N->getChain(), N->getBasePtr(),
494 N->getMask(), ExtSrc0, N->getMemoryVT(),
495 N->getMemOperand(), ISD::SEXTLOAD);
496 // Legalize the chain result - switch anything that used the old chain to
498 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
502 SDValue DAGTypeLegalizer::PromoteIntRes_MGATHER(MaskedGatherSDNode *N) {
503 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
504 SDValue ExtSrc0 = GetPromotedInteger(N->getValue());
505 assert(NVT == ExtSrc0.getValueType() &&
506 "Gather result type and the passThru agrument type should be the same");
509 SDValue Ops[] = {N->getChain(), ExtSrc0, N->getMask(), N->getBasePtr(),
511 SDValue Res = DAG.getMaskedGather(DAG.getVTList(NVT, MVT::Other),
512 N->getMemoryVT(), dl, Ops,
514 // Legalize the chain result - switch anything that used the old chain to
516 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
520 /// Promote the overflow flag of an overflowing arithmetic node.
521 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
522 // Simply change the return type of the boolean result.
523 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
524 EVT ValueVTs[] = { N->getValueType(0), NVT };
525 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
526 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),
527 DAG.getVTList(ValueVTs), Ops);
529 // Modified the sum result - switch anything that used the old sum to use
531 ReplaceValueWith(SDValue(N, 0), Res);
533 return SDValue(Res.getNode(), 1);
536 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
538 return PromoteIntRes_Overflow(N);
540 // The operation overflowed iff the result in the larger type is not the
541 // sign extension of its truncation to the original type.
542 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
543 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
544 EVT OVT = N->getOperand(0).getValueType();
545 EVT NVT = LHS.getValueType();
548 // Do the arithmetic in the larger type.
549 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
550 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
552 // Calculate the overflow flag: sign extend the arithmetic result from
553 // the original type.
554 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
555 DAG.getValueType(OVT));
556 // Overflowed if and only if this is not equal to Res.
557 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
559 // Use the calculated overflow everywhere.
560 ReplaceValueWith(SDValue(N, 1), Ofl);
565 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
566 SDValue LHS = GetPromotedInteger(N->getOperand(1));
567 SDValue RHS = GetPromotedInteger(N->getOperand(2));
568 return DAG.getSelect(SDLoc(N),
569 LHS.getValueType(), N->getOperand(0), LHS, RHS);
572 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
573 SDValue Mask = N->getOperand(0);
574 EVT OpTy = N->getOperand(1).getValueType();
576 // Promote all the way up to the canonical SetCC type.
577 Mask = PromoteTargetBoolean(Mask, OpTy);
578 SDValue LHS = GetPromotedInteger(N->getOperand(1));
579 SDValue RHS = GetPromotedInteger(N->getOperand(2));
580 return DAG.getNode(ISD::VSELECT, SDLoc(N),
581 LHS.getValueType(), Mask, LHS, RHS);
584 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
585 SDValue LHS = GetPromotedInteger(N->getOperand(2));
586 SDValue RHS = GetPromotedInteger(N->getOperand(3));
587 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
588 LHS.getValueType(), N->getOperand(0),
589 N->getOperand(1), LHS, RHS, N->getOperand(4));
592 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
593 EVT SVT = getSetCCResultType(N->getOperand(0).getValueType());
595 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
597 // Only use the result of getSetCCResultType if it is legal,
598 // otherwise just use the promoted result type (NVT).
599 if (!TLI.isTypeLegal(SVT))
603 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
604 "Vector compare must return a vector result!");
606 SDValue LHS = N->getOperand(0);
607 SDValue RHS = N->getOperand(1);
608 if (LHS.getValueType() != RHS.getValueType()) {
609 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger &&
610 !LHS.getValueType().isVector())
611 LHS = GetPromotedInteger(LHS);
612 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger &&
613 !RHS.getValueType().isVector())
614 RHS = GetPromotedInteger(RHS);
617 // Get the SETCC result using the canonical SETCC type.
618 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
621 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
622 // Convert to the expected type.
623 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
626 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
627 SDValue LHS = N->getOperand(0);
628 SDValue RHS = N->getOperand(1);
629 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
630 LHS = GetPromotedInteger(LHS);
631 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
632 RHS = ZExtPromotedInteger(RHS);
633 return DAG.getNode(ISD::SHL, SDLoc(N), LHS.getValueType(), LHS, RHS);
636 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
637 SDValue Op = GetPromotedInteger(N->getOperand(0));
638 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
639 Op.getValueType(), Op, N->getOperand(1));
642 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
643 // The input may have strange things in the top bits of the registers, but
644 // these operations don't care. They may have weird bits going out, but
645 // that too is okay if they are integer operations.
646 SDValue LHS = GetPromotedInteger(N->getOperand(0));
647 SDValue RHS = GetPromotedInteger(N->getOperand(1));
648 return DAG.getNode(N->getOpcode(), SDLoc(N),
649 LHS.getValueType(), LHS, RHS);
652 SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(SDNode *N) {
653 // Sign extend the input.
654 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
655 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
656 return DAG.getNode(N->getOpcode(), SDLoc(N),
657 LHS.getValueType(), LHS, RHS);
660 SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
661 // Zero extend the input.
662 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
663 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
664 return DAG.getNode(N->getOpcode(), SDLoc(N),
665 LHS.getValueType(), LHS, RHS);
668 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
669 SDValue LHS = N->getOperand(0);
670 SDValue RHS = N->getOperand(1);
671 // The input value must be properly sign extended.
672 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
673 LHS = SExtPromotedInteger(LHS);
674 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
675 RHS = ZExtPromotedInteger(RHS);
676 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS);
679 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
680 SDValue LHS = N->getOperand(0);
681 SDValue RHS = N->getOperand(1);
682 // The input value must be properly zero extended.
683 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
684 LHS = ZExtPromotedInteger(LHS);
685 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
686 RHS = ZExtPromotedInteger(RHS);
687 return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS);
690 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
691 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
693 SDValue InOp = N->getOperand(0);
696 switch (getTypeAction(InOp.getValueType())) {
697 default: llvm_unreachable("Unknown type action!");
698 case TargetLowering::TypeLegal:
699 case TargetLowering::TypeExpandInteger:
702 case TargetLowering::TypePromoteInteger:
703 Res = GetPromotedInteger(InOp);
705 case TargetLowering::TypeSplitVector:
706 EVT InVT = InOp.getValueType();
707 assert(InVT.isVector() && "Cannot split scalar types");
708 unsigned NumElts = InVT.getVectorNumElements();
709 assert(NumElts == NVT.getVectorNumElements() &&
710 "Dst and Src must have the same number of elements");
711 assert(isPowerOf2_32(NumElts) &&
712 "Promoted vector type must be a power of two");
715 GetSplitVector(InOp, EOp1, EOp2);
717 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
719 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
720 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
722 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
725 // Truncate to NVT instead of VT
726 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
729 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
731 return PromoteIntRes_Overflow(N);
733 // The operation overflowed iff the result in the larger type is not the
734 // zero extension of its truncation to the original type.
735 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
736 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
737 EVT OVT = N->getOperand(0).getValueType();
738 EVT NVT = LHS.getValueType();
741 // Do the arithmetic in the larger type.
742 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
743 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
745 // Calculate the overflow flag: zero extend the arithmetic result from
746 // the original type.
747 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
748 // Overflowed if and only if this is not equal to Res.
749 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
751 // Use the calculated overflow everywhere.
752 ReplaceValueWith(SDValue(N, 1), Ofl);
757 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
758 // Promote the overflow bit trivially.
760 return PromoteIntRes_Overflow(N);
762 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
764 EVT SmallVT = LHS.getValueType();
766 // To determine if the result overflowed in a larger type, we extend the
767 // input to the larger type, do the multiply (checking if it overflows),
768 // then also check the high bits of the result to see if overflow happened
770 if (N->getOpcode() == ISD::SMULO) {
771 LHS = SExtPromotedInteger(LHS);
772 RHS = SExtPromotedInteger(RHS);
774 LHS = ZExtPromotedInteger(LHS);
775 RHS = ZExtPromotedInteger(RHS);
777 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
778 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
780 // Overflow occurred if it occurred in the larger type, or if the high part
781 // of the result does not zero/sign-extend the low part. Check this second
782 // possibility first.
784 if (N->getOpcode() == ISD::UMULO) {
785 // Unsigned overflow occurred if the high part is non-zero.
786 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
787 DAG.getIntPtrConstant(SmallVT.getSizeInBits(),
789 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
790 DAG.getConstant(0, DL, Hi.getValueType()),
793 // Signed overflow occurred if the high part does not sign extend the low.
794 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
795 Mul, DAG.getValueType(SmallVT));
796 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
799 // The only other way for overflow to occur is if the multiplication in the
800 // larger type itself overflowed.
801 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
802 SDValue(Mul.getNode(), 1));
804 // Use the calculated overflow everywhere.
805 ReplaceValueWith(SDValue(N, 1), Overflow);
809 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
810 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
811 N->getValueType(0)));
814 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
815 SDValue Chain = N->getOperand(0); // Get the chain.
816 SDValue Ptr = N->getOperand(1); // Get the pointer.
817 EVT VT = N->getValueType(0);
820 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
821 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
822 // The argument is passed as NumRegs registers of type RegVT.
824 SmallVector<SDValue, 8> Parts(NumRegs);
825 for (unsigned i = 0; i < NumRegs; ++i) {
826 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
827 N->getConstantOperandVal(3));
828 Chain = Parts[i].getValue(1);
831 // Handle endianness of the load.
832 if (DAG.getDataLayout().isBigEndian())
833 std::reverse(Parts.begin(), Parts.end());
835 // Assemble the parts in the promoted type.
836 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
837 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
838 for (unsigned i = 1; i < NumRegs; ++i) {
839 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
840 // Shift it to the right position and "or" it in.
841 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
842 DAG.getConstant(i * RegVT.getSizeInBits(), dl,
843 TLI.getPointerTy(DAG.getDataLayout())));
844 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
847 // Modified the chain result - switch anything that used the old chain to
849 ReplaceValueWith(SDValue(N, 1), Chain);
854 //===----------------------------------------------------------------------===//
855 // Integer Operand Promotion
856 //===----------------------------------------------------------------------===//
858 /// PromoteIntegerOperand - This method is called when the specified operand of
859 /// the specified node is found to need promotion. At this point, all of the
860 /// result types of the node are known to be legal, but other operands of the
861 /// node may need promotion or expansion as well as the specified one.
862 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
863 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
864 SDValue Res = SDValue();
866 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
869 switch (N->getOpcode()) {
872 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
873 N->dump(&DAG); dbgs() << "\n";
875 llvm_unreachable("Do not know how to promote this operator's operand!");
877 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
878 case ISD::ATOMIC_STORE:
879 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
881 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
882 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
883 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
884 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
885 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
886 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
887 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
888 case ISD::CONVERT_RNDSAT:
889 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
890 case ISD::INSERT_VECTOR_ELT:
891 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
892 case ISD::SCALAR_TO_VECTOR:
893 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
895 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
896 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
897 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
898 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
899 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
900 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
902 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
904 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
906 case ISD::MGATHER: Res = PromoteIntOp_MGATHER(cast<MaskedGatherSDNode>(N),
908 case ISD::MSCATTER: Res = PromoteIntOp_MSCATTER(cast<MaskedScatterSDNode>(N),
910 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
911 case ISD::FP16_TO_FP:
912 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
913 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
914 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
920 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
923 // If the result is null, the sub-method took care of registering results etc.
924 if (!Res.getNode()) return false;
926 // If the result is N, the sub-method updated N in place. Tell the legalizer
928 if (Res.getNode() == N)
931 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
932 "Invalid operand expansion");
934 ReplaceValueWith(SDValue(N, 0), Res);
938 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
939 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
940 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
941 ISD::CondCode CCCode) {
942 // We have to insert explicit sign or zero extends. Note that we could
943 // insert sign extends for ALL conditions, but zero extend is cheaper on
944 // many machines (an AND instead of two shifts), so prefer it.
946 default: llvm_unreachable("Unknown integer comparison!");
949 SDValue OpL = GetPromotedInteger(NewLHS);
950 SDValue OpR = GetPromotedInteger(NewRHS);
952 // We would prefer to promote the comparison operand with sign extension,
953 // if we find the operand is actually to truncate an AssertSext. With this
954 // optimization, we can avoid inserting real truncate instruction, which
955 // is redudant eventually.
956 if (OpL->getOpcode() == ISD::AssertSext &&
957 cast<VTSDNode>(OpL->getOperand(1))->getVT() == NewLHS.getValueType() &&
958 OpR->getOpcode() == ISD::AssertSext &&
959 cast<VTSDNode>(OpR->getOperand(1))->getVT() == NewRHS.getValueType()) {
963 NewLHS = ZExtPromotedInteger(NewLHS);
964 NewRHS = ZExtPromotedInteger(NewRHS);
972 // ALL of these operations will work if we either sign or zero extend
973 // the operands (including the unsigned comparisons!). Zero extend is
974 // usually a simpler/cheaper operation, so prefer it.
975 NewLHS = ZExtPromotedInteger(NewLHS);
976 NewRHS = ZExtPromotedInteger(NewRHS);
982 NewLHS = SExtPromotedInteger(NewLHS);
983 NewRHS = SExtPromotedInteger(NewRHS);
988 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
989 SDValue Op = GetPromotedInteger(N->getOperand(0));
990 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
993 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
994 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
995 return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
996 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(),
997 N->getOrdering(), N->getSynchScope());
1000 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
1001 // This should only occur in unusual situations like bitcasting to an
1002 // x86_fp80, so just turn it into a store+load
1003 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
1006 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
1007 assert(OpNo == 2 && "Don't know how to promote this operand!");
1009 SDValue LHS = N->getOperand(2);
1010 SDValue RHS = N->getOperand(3);
1011 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
1013 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
1015 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1016 N->getOperand(1), LHS, RHS, N->getOperand(4)),
1020 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
1021 assert(OpNo == 1 && "only know how to promote condition");
1023 // Promote all the way up to the canonical SetCC type.
1024 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), MVT::Other);
1026 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
1027 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
1028 N->getOperand(2)), 0);
1031 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
1032 // Since the result type is legal, the operands must promote to it.
1033 EVT OVT = N->getOperand(0).getValueType();
1034 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
1035 SDValue Hi = GetPromotedInteger(N->getOperand(1));
1036 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
1039 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
1040 DAG.getConstant(OVT.getSizeInBits(), dl,
1041 TLI.getPointerTy(DAG.getDataLayout())));
1042 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
1045 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
1046 // The vector type is legal but the element type is not. This implies
1047 // that the vector is a power-of-two in length and that the element
1048 // type does not have a strange size (eg: it is not i1).
1049 EVT VecVT = N->getValueType(0);
1050 unsigned NumElts = VecVT.getVectorNumElements();
1051 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
1052 "Legal vector of one illegal element?");
1054 // Promote the inserted value. The type does not need to match the
1055 // vector element type. Check that any extra bits introduced will be
1057 assert(N->getOperand(0).getValueType().getSizeInBits() >=
1058 N->getValueType(0).getVectorElementType().getSizeInBits() &&
1059 "Type of inserted value narrower than vector element type!");
1061 SmallVector<SDValue, 16> NewOps;
1062 for (unsigned i = 0; i < NumElts; ++i)
1063 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
1065 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1068 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
1069 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1070 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
1071 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
1072 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
1073 "can only promote integer arguments");
1074 SDValue InOp = GetPromotedInteger(N->getOperand(0));
1075 return DAG.getConvertRndSat(N->getValueType(0), SDLoc(N), InOp,
1076 N->getOperand(1), N->getOperand(2),
1077 N->getOperand(3), N->getOperand(4), CvtCode);
1080 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
1083 // Promote the inserted value. This is valid because the type does not
1084 // have to match the vector element type.
1086 // Check that any extra bits introduced will be truncated away.
1087 assert(N->getOperand(1).getValueType().getSizeInBits() >=
1088 N->getValueType(0).getVectorElementType().getSizeInBits() &&
1089 "Type of inserted value narrower than vector element type!");
1090 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1091 GetPromotedInteger(N->getOperand(1)),
1096 assert(OpNo == 2 && "Different operand and result vector types?");
1098 // Promote the index.
1099 SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
1100 TLI.getVectorIdxTy(DAG.getDataLayout()));
1101 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1102 N->getOperand(1), Idx), 0);
1105 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
1106 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
1107 // the operand in place.
1108 return SDValue(DAG.UpdateNodeOperands(N,
1109 GetPromotedInteger(N->getOperand(0))), 0);
1112 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
1113 assert(OpNo == 0 && "Only know how to promote the condition!");
1114 SDValue Cond = N->getOperand(0);
1115 EVT OpTy = N->getOperand(1).getValueType();
1117 // Promote all the way up to the canonical SetCC type.
1118 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1119 Cond = PromoteTargetBoolean(Cond, OpVT);
1121 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
1122 N->getOperand(2)), 0);
1125 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1126 assert(OpNo == 0 && "Don't know how to promote this operand!");
1128 SDValue LHS = N->getOperand(0);
1129 SDValue RHS = N->getOperand(1);
1130 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1132 // The CC (#4) and the possible return values (#2 and #3) have legal types.
1133 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1134 N->getOperand(3), N->getOperand(4)), 0);
1137 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1138 assert(OpNo == 0 && "Don't know how to promote this operand!");
1140 SDValue LHS = N->getOperand(0);
1141 SDValue RHS = N->getOperand(1);
1142 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1144 // The CC (#2) is always legal.
1145 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1148 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1149 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1150 ZExtPromotedInteger(N->getOperand(1))), 0);
1153 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1154 SDValue Op = GetPromotedInteger(N->getOperand(0));
1156 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1157 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1158 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1161 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1162 return SDValue(DAG.UpdateNodeOperands(N,
1163 SExtPromotedInteger(N->getOperand(0))), 0);
1166 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1167 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1168 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1171 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1173 // Truncate the value and store the result.
1174 return DAG.getTruncStore(Ch, dl, Val, Ptr,
1175 N->getMemoryVT(), N->getMemOperand());
1178 SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N,
1181 SDValue DataOp = N->getValue();
1182 EVT DataVT = DataOp.getValueType();
1183 SDValue Mask = N->getMask();
1186 bool TruncateStore = false;
1188 // Mask comes before the data operand. If the data operand is legal, we just
1189 // promote the mask.
1190 // When the data operand has illegal type, we should legalize the data
1191 // operand first. The mask will be promoted/splitted/widened according to
1192 // the data operand type.
1193 if (TLI.isTypeLegal(DataVT))
1194 Mask = PromoteTargetBoolean(Mask, DataVT);
1196 if (getTypeAction(DataVT) == TargetLowering::TypePromoteInteger)
1197 return PromoteIntOp_MSTORE(N, 3);
1199 else if (getTypeAction(DataVT) == TargetLowering::TypeWidenVector)
1200 return WidenVecOp_MSTORE(N, 3);
1203 assert (getTypeAction(DataVT) == TargetLowering::TypeSplitVector);
1204 return SplitVecOp_MSTORE(N, 3);
1207 } else { // Data operand
1208 assert(OpNo == 3 && "Unexpected operand for promotion");
1209 DataOp = GetPromotedInteger(DataOp);
1210 Mask = PromoteTargetBoolean(Mask, DataOp.getValueType());
1211 TruncateStore = true;
1214 return DAG.getMaskedStore(N->getChain(), dl, DataOp, N->getBasePtr(), Mask,
1215 N->getMemoryVT(), N->getMemOperand(),
1219 SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N,
1221 assert(OpNo == 2 && "Only know how to promote the mask!");
1222 EVT DataVT = N->getValueType(0);
1223 SDValue Mask = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1224 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1225 NewOps[OpNo] = Mask;
1226 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1229 SDValue DAGTypeLegalizer::PromoteIntOp_MGATHER(MaskedGatherSDNode *N,
1232 SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
1235 EVT DataVT = N->getValueType(0);
1236 NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1238 NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
1239 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1242 SDValue DAGTypeLegalizer::PromoteIntOp_MSCATTER(MaskedScatterSDNode *N,
1244 SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
1247 EVT DataVT = N->getValue().getValueType();
1248 NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1250 NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
1251 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1254 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1255 SDValue Op = GetPromotedInteger(N->getOperand(0));
1256 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
1259 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1260 return SDValue(DAG.UpdateNodeOperands(N,
1261 ZExtPromotedInteger(N->getOperand(0))), 0);
1264 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1266 SDValue Op = GetPromotedInteger(N->getOperand(0));
1267 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1268 return DAG.getZeroExtendInReg(Op, dl,
1269 N->getOperand(0).getValueType().getScalarType());
1273 //===----------------------------------------------------------------------===//
1274 // Integer Result Expansion
1275 //===----------------------------------------------------------------------===//
1277 /// ExpandIntegerResult - This method is called when the specified result of the
1278 /// specified node is found to need expansion. At this point, the node may also
1279 /// have invalid operands or may have other results that need promotion, we just
1280 /// know that (at least) one result needs expansion.
1281 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1282 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
1284 Lo = Hi = SDValue();
1286 // See if the target wants to custom expand this node.
1287 if (CustomLowerNode(N, N->getValueType(ResNo), true))
1290 switch (N->getOpcode()) {
1293 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1294 N->dump(&DAG); dbgs() << "\n";
1296 llvm_unreachable("Do not know how to expand the result of this operator!");
1298 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1299 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1300 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1301 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1303 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1304 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1305 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1306 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1307 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1309 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1310 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1311 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1312 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break;
1313 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1314 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1315 case ISD::CTLZ_ZERO_UNDEF:
1316 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1317 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1318 case ISD::CTTZ_ZERO_UNDEF:
1319 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1320 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1321 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1322 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1323 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1324 case ISD::READCYCLECOUNTER: ExpandIntRes_READCYCLECOUNTER(N, Lo, Hi); break;
1325 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1326 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1327 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1328 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1329 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1330 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1331 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1332 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1333 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1335 case ISD::ATOMIC_LOAD_ADD:
1336 case ISD::ATOMIC_LOAD_SUB:
1337 case ISD::ATOMIC_LOAD_AND:
1338 case ISD::ATOMIC_LOAD_OR:
1339 case ISD::ATOMIC_LOAD_XOR:
1340 case ISD::ATOMIC_LOAD_NAND:
1341 case ISD::ATOMIC_LOAD_MIN:
1342 case ISD::ATOMIC_LOAD_MAX:
1343 case ISD::ATOMIC_LOAD_UMIN:
1344 case ISD::ATOMIC_LOAD_UMAX:
1345 case ISD::ATOMIC_SWAP:
1346 case ISD::ATOMIC_CMP_SWAP: {
1347 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1348 SplitInteger(Tmp.first, Lo, Hi);
1349 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1352 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
1353 AtomicSDNode *AN = cast<AtomicSDNode>(N);
1354 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::Other);
1355 SDValue Tmp = DAG.getAtomicCmpSwap(
1356 ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
1357 N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3),
1358 AN->getMemOperand(), AN->getSuccessOrdering(), AN->getFailureOrdering(),
1359 AN->getSynchScope());
1361 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
1362 // success simply by comparing the loaded value against the ingoing
1364 SDValue Success = DAG.getSetCC(SDLoc(N), N->getValueType(1), Tmp,
1365 N->getOperand(2), ISD::SETEQ);
1367 SplitInteger(Tmp, Lo, Hi);
1368 ReplaceValueWith(SDValue(N, 1), Success);
1369 ReplaceValueWith(SDValue(N, 2), Tmp.getValue(1));
1375 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1378 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1381 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1384 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1388 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1391 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1393 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1395 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1398 // If Lo/Hi is null, the sub-method took care of registering results etc.
1400 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1403 /// Lower an atomic node to the appropriate builtin call.
1404 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1405 unsigned Opc = Node->getOpcode();
1406 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1407 RTLIB::Libcall LC = RTLIB::getATOMIC(Opc, VT);
1408 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
1410 return ExpandChainLibCall(LC, Node, false);
1413 /// N is a shift by a value that needs to be expanded,
1414 /// and the shift amount is a constant 'Amt'. Expand the operation.
1415 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
1416 SDValue &Lo, SDValue &Hi) {
1418 // Expand the incoming operand to be shifted, so that we have its parts
1420 GetExpandedInteger(N->getOperand(0), InL, InH);
1422 // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
1423 // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
1430 EVT NVT = InL.getValueType();
1431 unsigned VTBits = N->getValueType(0).getSizeInBits();
1432 unsigned NVTBits = NVT.getSizeInBits();
1433 EVT ShTy = N->getOperand(1).getValueType();
1435 if (N->getOpcode() == ISD::SHL) {
1436 if (Amt.ugt(VTBits)) {
1437 Lo = Hi = DAG.getConstant(0, DL, NVT);
1438 } else if (Amt.ugt(NVTBits)) {
1439 Lo = DAG.getConstant(0, DL, NVT);
1440 Hi = DAG.getNode(ISD::SHL, DL,
1441 NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy));
1442 } else if (Amt == NVTBits) {
1443 Lo = DAG.getConstant(0, DL, NVT);
1445 } else if (Amt == 1 &&
1446 TLI.isOperationLegalOrCustom(ISD::ADDC,
1447 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1448 // Emit this X << 1 as X+X.
1449 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1450 SDValue LoOps[2] = { InL, InL };
1451 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps);
1452 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1453 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps);
1455 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy));
1456 Hi = DAG.getNode(ISD::OR, DL, NVT,
1457 DAG.getNode(ISD::SHL, DL, NVT, InH,
1458 DAG.getConstant(Amt, DL, ShTy)),
1459 DAG.getNode(ISD::SRL, DL, NVT, InL,
1460 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1465 if (N->getOpcode() == ISD::SRL) {
1466 if (Amt.ugt(VTBits)) {
1467 Lo = Hi = DAG.getConstant(0, DL, NVT);
1468 } else if (Amt.ugt(NVTBits)) {
1469 Lo = DAG.getNode(ISD::SRL, DL,
1470 NVT, InH, DAG.getConstant(Amt - NVTBits, DL, ShTy));
1471 Hi = DAG.getConstant(0, DL, NVT);
1472 } else if (Amt == NVTBits) {
1474 Hi = DAG.getConstant(0, DL, NVT);
1476 Lo = DAG.getNode(ISD::OR, DL, NVT,
1477 DAG.getNode(ISD::SRL, DL, NVT, InL,
1478 DAG.getConstant(Amt, DL, ShTy)),
1479 DAG.getNode(ISD::SHL, DL, NVT, InH,
1480 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1481 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
1486 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1487 if (Amt.ugt(VTBits)) {
1488 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1489 DAG.getConstant(NVTBits - 1, DL, ShTy));
1490 } else if (Amt.ugt(NVTBits)) {
1491 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1492 DAG.getConstant(Amt - NVTBits, DL, ShTy));
1493 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1494 DAG.getConstant(NVTBits - 1, DL, ShTy));
1495 } else if (Amt == NVTBits) {
1497 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1498 DAG.getConstant(NVTBits - 1, DL, ShTy));
1500 Lo = DAG.getNode(ISD::OR, DL, NVT,
1501 DAG.getNode(ISD::SRL, DL, NVT, InL,
1502 DAG.getConstant(Amt, DL, ShTy)),
1503 DAG.getNode(ISD::SHL, DL, NVT, InH,
1504 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1505 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
1509 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1510 /// this shift based on knowledge of the high bit of the shift amount. If we
1511 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1513 bool DAGTypeLegalizer::
1514 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1515 SDValue Amt = N->getOperand(1);
1516 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1517 EVT ShTy = Amt.getValueType();
1518 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1519 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1520 assert(isPowerOf2_32(NVTBits) &&
1521 "Expanded integer type size not a power of two!");
1524 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1525 APInt KnownZero, KnownOne;
1526 DAG.computeKnownBits(N->getOperand(1), KnownZero, KnownOne);
1528 // If we don't know anything about the high bits, exit.
1529 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1532 // Get the incoming operand to be shifted.
1534 GetExpandedInteger(N->getOperand(0), InL, InH);
1536 // If we know that any of the high bits of the shift amount are one, then we
1537 // can do this as a couple of simple shifts.
1538 if (KnownOne.intersects(HighBitMask)) {
1539 // Mask out the high bit, which we know is set.
1540 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1541 DAG.getConstant(~HighBitMask, dl, ShTy));
1543 switch (N->getOpcode()) {
1544 default: llvm_unreachable("Unknown shift");
1546 Lo = DAG.getConstant(0, dl, NVT); // Low part is zero.
1547 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1550 Hi = DAG.getConstant(0, dl, NVT); // Hi part is zero.
1551 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1554 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1555 DAG.getConstant(NVTBits - 1, dl, ShTy));
1556 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1561 // If we know that all of the high bits of the shift amount are zero, then we
1562 // can do this as a couple of simple shifts.
1563 if ((KnownZero & HighBitMask) == HighBitMask) {
1564 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
1565 // shift if x is zero. We can use XOR here because x is known to be smaller
1567 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
1568 DAG.getConstant(NVTBits - 1, dl, ShTy));
1571 switch (N->getOpcode()) {
1572 default: llvm_unreachable("Unknown shift");
1573 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1575 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1578 // When shifting right the arithmetic for Lo and Hi is swapped.
1579 if (N->getOpcode() != ISD::SHL)
1580 std::swap(InL, InH);
1582 // Use a little trick to get the bits that move from Lo to Hi. First
1583 // shift by one bit.
1584 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, dl, ShTy));
1585 // Then compute the remaining shift with amount-1.
1586 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
1588 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
1589 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
1591 if (N->getOpcode() != ISD::SHL)
1599 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1601 bool DAGTypeLegalizer::
1602 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1603 SDValue Amt = N->getOperand(1);
1604 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1605 EVT ShTy = Amt.getValueType();
1606 unsigned NVTBits = NVT.getSizeInBits();
1607 assert(isPowerOf2_32(NVTBits) &&
1608 "Expanded integer type size not a power of two!");
1611 // Get the incoming operand to be shifted.
1613 GetExpandedInteger(N->getOperand(0), InL, InH);
1615 SDValue NVBitsNode = DAG.getConstant(NVTBits, dl, ShTy);
1616 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1617 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1618 SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1619 Amt, NVBitsNode, ISD::SETULT);
1620 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1621 Amt, DAG.getConstant(0, dl, ShTy),
1624 SDValue LoS, HiS, LoL, HiL;
1625 switch (N->getOpcode()) {
1626 default: llvm_unreachable("Unknown shift");
1628 // Short: ShAmt < NVTBits
1629 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1630 HiS = DAG.getNode(ISD::OR, dl, NVT,
1631 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1632 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1634 // Long: ShAmt >= NVTBits
1635 LoL = DAG.getConstant(0, dl, NVT); // Lo part is zero.
1636 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1638 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1639 Hi = DAG.getSelect(dl, NVT, isZero, InH,
1640 DAG.getSelect(dl, NVT, isShort, HiS, HiL));
1643 // Short: ShAmt < NVTBits
1644 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1645 LoS = DAG.getNode(ISD::OR, dl, NVT,
1646 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1647 // FIXME: If Amt is zero, the following shift generates an undefined result
1648 // on some architectures.
1649 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1651 // Long: ShAmt >= NVTBits
1652 HiL = DAG.getConstant(0, dl, NVT); // Hi part is zero.
1653 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1655 Lo = DAG.getSelect(dl, NVT, isZero, InL,
1656 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
1657 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1660 // Short: ShAmt < NVTBits
1661 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1662 LoS = DAG.getNode(ISD::OR, dl, NVT,
1663 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1664 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1666 // Long: ShAmt >= NVTBits
1667 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1668 DAG.getConstant(NVTBits - 1, dl, ShTy));
1669 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1671 Lo = DAG.getSelect(dl, NVT, isZero, InL,
1672 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
1673 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1678 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1679 SDValue &Lo, SDValue &Hi) {
1681 // Expand the subcomponents.
1682 SDValue LHSL, LHSH, RHSL, RHSH;
1683 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1684 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1686 EVT NVT = LHSL.getValueType();
1687 SDValue LoOps[2] = { LHSL, RHSL };
1688 SDValue HiOps[3] = { LHSH, RHSH };
1690 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1691 // them. TODO: Teach operation legalization how to expand unsupported
1692 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1693 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1694 // generate a value of this type in the expanded code sequence.
1696 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1697 ISD::ADDC : ISD::SUBC,
1698 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1701 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1702 if (N->getOpcode() == ISD::ADD) {
1703 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1704 HiOps[2] = Lo.getValue(1);
1705 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1707 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1708 HiOps[2] = Lo.getValue(1);
1709 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1715 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1716 ISD::UADDO : ISD::USUBO,
1717 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1719 SDVTList VTList = DAG.getVTList(NVT, NVT);
1720 TargetLoweringBase::BooleanContent BoolType = TLI.getBooleanContents(NVT);
1722 if (N->getOpcode() == ISD::ADD) {
1724 Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
1725 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
1728 Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
1729 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
1731 SDValue OVF = Lo.getValue(1);
1734 case TargetLoweringBase::UndefinedBooleanContent:
1735 OVF = DAG.getNode(ISD::AND, dl, NVT, DAG.getConstant(1, dl, NVT), OVF);
1737 case TargetLoweringBase::ZeroOrOneBooleanContent:
1738 Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF);
1740 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
1741 Hi = DAG.getNode(RevOpc, dl, NVT, Hi, OVF);
1746 if (N->getOpcode() == ISD::ADD) {
1747 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
1748 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
1749 SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
1751 SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
1752 DAG.getConstant(1, dl, NVT),
1753 DAG.getConstant(0, dl, NVT));
1754 SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
1756 SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
1757 DAG.getConstant(1, dl, NVT), Carry1);
1758 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1760 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
1761 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
1763 DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
1764 LoOps[0], LoOps[1], ISD::SETULT);
1765 SDValue Borrow = DAG.getSelect(dl, NVT, Cmp,
1766 DAG.getConstant(1, dl, NVT),
1767 DAG.getConstant(0, dl, NVT));
1768 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1772 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1773 SDValue &Lo, SDValue &Hi) {
1774 // Expand the subcomponents.
1775 SDValue LHSL, LHSH, RHSL, RHSH;
1777 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1778 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1779 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1780 SDValue LoOps[2] = { LHSL, RHSL };
1781 SDValue HiOps[3] = { LHSH, RHSH };
1783 if (N->getOpcode() == ISD::ADDC) {
1784 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1785 HiOps[2] = Lo.getValue(1);
1786 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1788 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1789 HiOps[2] = Lo.getValue(1);
1790 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1793 // Legalized the flag result - switch anything that used the old flag to
1795 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1798 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1799 SDValue &Lo, SDValue &Hi) {
1800 // Expand the subcomponents.
1801 SDValue LHSL, LHSH, RHSL, RHSH;
1803 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1804 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1805 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1806 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1807 SDValue HiOps[3] = { LHSH, RHSH };
1809 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
1810 HiOps[2] = Lo.getValue(1);
1811 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
1813 // Legalized the flag result - switch anything that used the old flag to
1815 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1818 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1819 SDValue &Lo, SDValue &Hi) {
1820 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1822 SDValue Op = N->getOperand(0);
1823 if (Op.getValueType().bitsLE(NVT)) {
1824 // The low part is any extension of the input (which degenerates to a copy).
1825 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1826 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1828 // For example, extension of an i48 to an i64. The operand type necessarily
1829 // promotes to the result type, so will end up being expanded too.
1830 assert(getTypeAction(Op.getValueType()) ==
1831 TargetLowering::TypePromoteInteger &&
1832 "Only know how to promote this result!");
1833 SDValue Res = GetPromotedInteger(Op);
1834 assert(Res.getValueType() == N->getValueType(0) &&
1835 "Operand over promoted?");
1836 // Split the promoted operand. This will simplify when it is expanded.
1837 SplitInteger(Res, Lo, Hi);
1841 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1842 SDValue &Lo, SDValue &Hi) {
1844 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1845 EVT NVT = Lo.getValueType();
1846 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1847 unsigned NVTBits = NVT.getSizeInBits();
1848 unsigned EVTBits = EVT.getSizeInBits();
1850 if (NVTBits < EVTBits) {
1851 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1852 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1853 EVTBits - NVTBits)));
1855 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1856 // The high part replicates the sign bit of Lo, make it explicit.
1857 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1858 DAG.getConstant(NVTBits - 1, dl,
1859 TLI.getPointerTy(DAG.getDataLayout())));
1863 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1864 SDValue &Lo, SDValue &Hi) {
1866 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1867 EVT NVT = Lo.getValueType();
1868 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1869 unsigned NVTBits = NVT.getSizeInBits();
1870 unsigned EVTBits = EVT.getSizeInBits();
1872 if (NVTBits < EVTBits) {
1873 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1874 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1875 EVTBits - NVTBits)));
1877 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1878 // The high part must be zero, make it explicit.
1879 Hi = DAG.getConstant(0, dl, NVT);
1883 void DAGTypeLegalizer::ExpandIntRes_BITREVERSE(SDNode *N,
1884 SDValue &Lo, SDValue &Hi) {
1886 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1887 Lo = DAG.getNode(ISD::BITREVERSE, dl, Lo.getValueType(), Lo);
1888 Hi = DAG.getNode(ISD::BITREVERSE, dl, Hi.getValueType(), Hi);
1891 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1892 SDValue &Lo, SDValue &Hi) {
1894 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1895 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1896 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1899 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1900 SDValue &Lo, SDValue &Hi) {
1901 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1902 unsigned NBitWidth = NVT.getSizeInBits();
1903 auto Constant = cast<ConstantSDNode>(N);
1904 const APInt &Cst = Constant->getAPIntValue();
1905 bool IsTarget = Constant->isTargetOpcode();
1906 bool IsOpaque = Constant->isOpaque();
1908 Lo = DAG.getConstant(Cst.trunc(NBitWidth), dl, NVT, IsTarget, IsOpaque);
1909 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), dl, NVT, IsTarget,
1913 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1914 SDValue &Lo, SDValue &Hi) {
1916 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1917 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1918 EVT NVT = Lo.getValueType();
1920 SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
1921 DAG.getConstant(0, dl, NVT), ISD::SETNE);
1923 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
1924 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
1926 Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
1927 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1928 DAG.getConstant(NVT.getSizeInBits(), dl,
1930 Hi = DAG.getConstant(0, dl, NVT);
1933 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1934 SDValue &Lo, SDValue &Hi) {
1936 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1937 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1938 EVT NVT = Lo.getValueType();
1939 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1940 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1941 Hi = DAG.getConstant(0, dl, NVT);
1944 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1945 SDValue &Lo, SDValue &Hi) {
1947 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1948 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1949 EVT NVT = Lo.getValueType();
1951 SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
1952 DAG.getConstant(0, dl, NVT), ISD::SETNE);
1954 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
1955 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
1957 Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
1958 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1959 DAG.getConstant(NVT.getSizeInBits(), dl,
1961 Hi = DAG.getConstant(0, dl, NVT);
1964 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1967 EVT VT = N->getValueType(0);
1969 SDValue Op = N->getOperand(0);
1970 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
1971 Op = GetPromotedFloat(Op);
1973 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1974 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1975 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Op, true/*irrelevant*/, dl).first,
1979 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1982 EVT VT = N->getValueType(0);
1984 SDValue Op = N->getOperand(0);
1985 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
1986 Op = GetPromotedFloat(Op);
1988 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1989 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1990 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Op, false/*irrelevant*/, dl).first,
1994 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1995 SDValue &Lo, SDValue &Hi) {
1996 if (ISD::isNormalLoad(N)) {
1997 ExpandRes_NormalLoad(N, Lo, Hi);
2001 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
2003 EVT VT = N->getValueType(0);
2004 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2005 SDValue Ch = N->getChain();
2006 SDValue Ptr = N->getBasePtr();
2007 ISD::LoadExtType ExtType = N->getExtensionType();
2008 unsigned Alignment = N->getAlignment();
2009 bool isVolatile = N->isVolatile();
2010 bool isNonTemporal = N->isNonTemporal();
2011 bool isInvariant = N->isInvariant();
2012 AAMDNodes AAInfo = N->getAAInfo();
2015 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2017 if (N->getMemoryVT().bitsLE(NVT)) {
2018 EVT MemVT = N->getMemoryVT();
2020 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
2021 MemVT, isVolatile, isNonTemporal, isInvariant,
2024 // Remember the chain.
2025 Ch = Lo.getValue(1);
2027 if (ExtType == ISD::SEXTLOAD) {
2028 // The high part is obtained by SRA'ing all but one of the bits of the
2030 unsigned LoSize = Lo.getValueType().getSizeInBits();
2031 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2032 DAG.getConstant(LoSize - 1, dl,
2033 TLI.getPointerTy(DAG.getDataLayout())));
2034 } else if (ExtType == ISD::ZEXTLOAD) {
2035 // The high part is just a zero.
2036 Hi = DAG.getConstant(0, dl, NVT);
2038 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
2039 // The high part is undefined.
2040 Hi = DAG.getUNDEF(NVT);
2042 } else if (DAG.getDataLayout().isLittleEndian()) {
2043 // Little-endian - low bits are at low addresses.
2044 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
2045 isVolatile, isNonTemporal, isInvariant, Alignment,
2048 unsigned ExcessBits =
2049 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2050 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2052 // Increment the pointer to the other half.
2053 unsigned IncrementSize = NVT.getSizeInBits()/8;
2054 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2055 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2056 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
2057 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
2058 isVolatile, isNonTemporal, isInvariant,
2059 MinAlign(Alignment, IncrementSize), AAInfo);
2061 // Build a factor node to remember that this load is independent of the
2063 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2066 // Big-endian - high bits are at low addresses. Favor aligned loads at
2067 // the cost of some bit-fiddling.
2068 EVT MemVT = N->getMemoryVT();
2069 unsigned EBytes = MemVT.getStoreSize();
2070 unsigned IncrementSize = NVT.getSizeInBits()/8;
2071 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2073 // Load both the high bits and maybe some of the low bits.
2074 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
2075 EVT::getIntegerVT(*DAG.getContext(),
2076 MemVT.getSizeInBits() - ExcessBits),
2077 isVolatile, isNonTemporal, isInvariant, Alignment,
2080 // Increment the pointer to the other half.
2081 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2082 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2083 // Load the rest of the low bits.
2084 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
2085 N->getPointerInfo().getWithOffset(IncrementSize),
2086 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2087 isVolatile, isNonTemporal, isInvariant,
2088 MinAlign(Alignment, IncrementSize), AAInfo);
2090 // Build a factor node to remember that this load is independent of the
2092 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2095 if (ExcessBits < NVT.getSizeInBits()) {
2096 // Transfer low bits from the bottom of Hi to the top of Lo.
2098 ISD::OR, dl, NVT, Lo,
2099 DAG.getNode(ISD::SHL, dl, NVT, Hi,
2100 DAG.getConstant(ExcessBits, dl,
2101 TLI.getPointerTy(DAG.getDataLayout()))));
2102 // Move high bits to the right position in Hi.
2103 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT,
2105 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
2106 TLI.getPointerTy(DAG.getDataLayout())));
2110 // Legalize the chain result - switch anything that used the old chain to
2112 ReplaceValueWith(SDValue(N, 1), Ch);
2115 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
2116 SDValue &Lo, SDValue &Hi) {
2118 SDValue LL, LH, RL, RH;
2119 GetExpandedInteger(N->getOperand(0), LL, LH);
2120 GetExpandedInteger(N->getOperand(1), RL, RH);
2121 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
2122 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
2125 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
2126 SDValue &Lo, SDValue &Hi) {
2127 EVT VT = N->getValueType(0);
2128 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2131 SDValue LL, LH, RL, RH;
2132 GetExpandedInteger(N->getOperand(0), LL, LH);
2133 GetExpandedInteger(N->getOperand(1), RL, RH);
2135 if (TLI.expandMUL(N, Lo, Hi, NVT, DAG, LL, LH, RL, RH))
2138 // If nothing else, we can make a libcall.
2139 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2141 LC = RTLIB::MUL_I16;
2142 else if (VT == MVT::i32)
2143 LC = RTLIB::MUL_I32;
2144 else if (VT == MVT::i64)
2145 LC = RTLIB::MUL_I64;
2146 else if (VT == MVT::i128)
2147 LC = RTLIB::MUL_I128;
2148 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
2150 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2151 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, true/*irrelevant*/, dl).first,
2155 void DAGTypeLegalizer::ExpandIntRes_READCYCLECOUNTER(SDNode *N, SDValue &Lo,
2158 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2159 SDVTList VTs = DAG.getVTList(NVT, NVT, MVT::Other);
2160 SDValue R = DAG.getNode(N->getOpcode(), DL, VTs, N->getOperand(0));
2163 ReplaceValueWith(SDValue(N, 1), R.getValue(2));
2166 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
2167 SDValue &Lo, SDValue &Hi) {
2168 SDValue LHS = Node->getOperand(0);
2169 SDValue RHS = Node->getOperand(1);
2172 // Expand the result by simply replacing it with the equivalent
2173 // non-overflow-checking operation.
2174 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2175 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2177 SplitInteger(Sum, Lo, Hi);
2179 // Compute the overflow.
2181 // LHSSign -> LHS >= 0
2182 // RHSSign -> RHS >= 0
2183 // SumSign -> Sum >= 0
2186 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2188 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2190 EVT OType = Node->getValueType(1);
2191 SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
2193 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2194 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2195 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2196 Node->getOpcode() == ISD::SADDO ?
2197 ISD::SETEQ : ISD::SETNE);
2199 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2200 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2202 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2204 // Use the calculated overflow everywhere.
2205 ReplaceValueWith(SDValue(Node, 1), Cmp);
2208 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
2209 SDValue &Lo, SDValue &Hi) {
2210 EVT VT = N->getValueType(0);
2212 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2214 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
2215 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2216 SplitInteger(Res.getValue(0), Lo, Hi);
2220 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2222 LC = RTLIB::SDIV_I16;
2223 else if (VT == MVT::i32)
2224 LC = RTLIB::SDIV_I32;
2225 else if (VT == MVT::i64)
2226 LC = RTLIB::SDIV_I64;
2227 else if (VT == MVT::i128)
2228 LC = RTLIB::SDIV_I128;
2229 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
2231 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, true, dl).first, Lo, Hi);
2234 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
2235 SDValue &Lo, SDValue &Hi) {
2236 EVT VT = N->getValueType(0);
2239 // If we can emit an efficient shift operation, do so now. Check to see if
2240 // the RHS is a constant.
2241 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2242 return ExpandShiftByConstant(N, CN->getAPIntValue(), Lo, Hi);
2244 // If we can determine that the high bit of the shift is zero or one, even if
2245 // the low bits are variable, emit this shift in an optimized form.
2246 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
2249 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
2251 if (N->getOpcode() == ISD::SHL) {
2252 PartsOpc = ISD::SHL_PARTS;
2253 } else if (N->getOpcode() == ISD::SRL) {
2254 PartsOpc = ISD::SRL_PARTS;
2256 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2257 PartsOpc = ISD::SRA_PARTS;
2260 // Next check to see if the target supports this SHL_PARTS operation or if it
2261 // will custom expand it.
2262 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2263 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
2264 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
2265 Action == TargetLowering::Custom) {
2266 // Expand the subcomponents.
2268 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2269 EVT VT = LHSL.getValueType();
2271 // If the shift amount operand is coming from a vector legalization it may
2272 // have an illegal type. Fix that first by casting the operand, otherwise
2273 // the new SHL_PARTS operation would need further legalization.
2274 SDValue ShiftOp = N->getOperand(1);
2275 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2276 assert(ShiftTy.getScalarType().getSizeInBits() >=
2277 Log2_32_Ceil(VT.getScalarType().getSizeInBits()) &&
2278 "ShiftAmountTy is too small to cover the range of this type!");
2279 if (ShiftOp.getValueType() != ShiftTy)
2280 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
2282 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
2283 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops);
2284 Hi = Lo.getValue(1);
2288 // Otherwise, emit a libcall.
2289 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2291 if (N->getOpcode() == ISD::SHL) {
2292 isSigned = false; /*sign irrelevant*/
2294 LC = RTLIB::SHL_I16;
2295 else if (VT == MVT::i32)
2296 LC = RTLIB::SHL_I32;
2297 else if (VT == MVT::i64)
2298 LC = RTLIB::SHL_I64;
2299 else if (VT == MVT::i128)
2300 LC = RTLIB::SHL_I128;
2301 } else if (N->getOpcode() == ISD::SRL) {
2304 LC = RTLIB::SRL_I16;
2305 else if (VT == MVT::i32)
2306 LC = RTLIB::SRL_I32;
2307 else if (VT == MVT::i64)
2308 LC = RTLIB::SRL_I64;
2309 else if (VT == MVT::i128)
2310 LC = RTLIB::SRL_I128;
2312 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2315 LC = RTLIB::SRA_I16;
2316 else if (VT == MVT::i32)
2317 LC = RTLIB::SRA_I32;
2318 else if (VT == MVT::i64)
2319 LC = RTLIB::SRA_I64;
2320 else if (VT == MVT::i128)
2321 LC = RTLIB::SRA_I128;
2324 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2325 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2326 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, isSigned, dl).first, Lo, Hi);
2330 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2331 llvm_unreachable("Unsupported shift!");
2334 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2335 SDValue &Lo, SDValue &Hi) {
2336 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2338 SDValue Op = N->getOperand(0);
2339 if (Op.getValueType().bitsLE(NVT)) {
2340 // The low part is sign extension of the input (degenerates to a copy).
2341 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2342 // The high part is obtained by SRA'ing all but one of the bits of low part.
2343 unsigned LoSize = NVT.getSizeInBits();
2345 ISD::SRA, dl, NVT, Lo,
2346 DAG.getConstant(LoSize - 1, dl, TLI.getPointerTy(DAG.getDataLayout())));
2348 // For example, extension of an i48 to an i64. The operand type necessarily
2349 // promotes to the result type, so will end up being expanded too.
2350 assert(getTypeAction(Op.getValueType()) ==
2351 TargetLowering::TypePromoteInteger &&
2352 "Only know how to promote this result!");
2353 SDValue Res = GetPromotedInteger(Op);
2354 assert(Res.getValueType() == N->getValueType(0) &&
2355 "Operand over promoted?");
2356 // Split the promoted operand. This will simplify when it is expanded.
2357 SplitInteger(Res, Lo, Hi);
2358 unsigned ExcessBits =
2359 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2360 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2361 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2366 void DAGTypeLegalizer::
2367 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2369 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2370 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2372 if (EVT.bitsLE(Lo.getValueType())) {
2373 // sext_inreg the low part if needed.
2374 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2377 // The high part gets the sign extension from the lo-part. This handles
2378 // things like sextinreg V:i64 from i8.
2379 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2380 DAG.getConstant(Hi.getValueType().getSizeInBits() - 1, dl,
2381 TLI.getPointerTy(DAG.getDataLayout())));
2383 // For example, extension of an i48 to an i64. Leave the low part alone,
2384 // sext_inreg the high part.
2385 unsigned ExcessBits =
2386 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2387 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2388 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2393 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2394 SDValue &Lo, SDValue &Hi) {
2395 EVT VT = N->getValueType(0);
2397 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2399 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
2400 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2401 SplitInteger(Res.getValue(1), Lo, Hi);
2405 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2407 LC = RTLIB::SREM_I16;
2408 else if (VT == MVT::i32)
2409 LC = RTLIB::SREM_I32;
2410 else if (VT == MVT::i64)
2411 LC = RTLIB::SREM_I64;
2412 else if (VT == MVT::i128)
2413 LC = RTLIB::SREM_I128;
2414 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2416 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, true, dl).first, Lo, Hi);
2419 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2420 SDValue &Lo, SDValue &Hi) {
2421 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2423 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2424 Hi = DAG.getNode(ISD::SRL, dl, N->getOperand(0).getValueType(),
2426 DAG.getConstant(NVT.getSizeInBits(), dl,
2427 TLI.getPointerTy(DAG.getDataLayout())));
2428 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2431 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2432 SDValue &Lo, SDValue &Hi) {
2433 SDValue LHS = N->getOperand(0);
2434 SDValue RHS = N->getOperand(1);
2437 // Expand the result by simply replacing it with the equivalent
2438 // non-overflow-checking operation.
2439 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2440 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2442 SplitInteger(Sum, Lo, Hi);
2444 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2445 // overflows iff a - b > a.
2446 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2447 N->getOpcode () == ISD::UADDO ?
2448 ISD::SETULT : ISD::SETUGT);
2450 // Use the calculated overflow everywhere.
2451 ReplaceValueWith(SDValue(N, 1), Ofl);
2454 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
2455 SDValue &Lo, SDValue &Hi) {
2456 EVT VT = N->getValueType(0);
2459 // A divide for UMULO should be faster than a function call.
2460 if (N->getOpcode() == ISD::UMULO) {
2461 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
2463 SDValue MUL = DAG.getNode(ISD::MUL, dl, LHS.getValueType(), LHS, RHS);
2464 SplitInteger(MUL, Lo, Hi);
2466 // A divide for UMULO will be faster than a function call. Select to
2467 // make sure we aren't using 0.
2468 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(VT),
2469 RHS, DAG.getConstant(0, dl, VT), ISD::SETEQ);
2470 SDValue NotZero = DAG.getSelect(dl, VT, isZero,
2471 DAG.getConstant(1, dl, VT), RHS);
2472 SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero);
2473 SDValue Overflow = DAG.getSetCC(dl, N->getValueType(1), DIV, LHS,
2475 Overflow = DAG.getSelect(dl, N->getValueType(1), isZero,
2476 DAG.getConstant(0, dl, N->getValueType(1)),
2478 ReplaceValueWith(SDValue(N, 1), Overflow);
2482 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
2483 EVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2484 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
2486 // Replace this with a libcall that will check overflow.
2487 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2489 LC = RTLIB::MULO_I32;
2490 else if (VT == MVT::i64)
2491 LC = RTLIB::MULO_I64;
2492 else if (VT == MVT::i128)
2493 LC = RTLIB::MULO_I128;
2494 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!");
2496 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
2497 // Temporary for the overflow value, default it to zero.
2498 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
2499 DAG.getConstant(0, dl, PtrVT), Temp,
2500 MachinePointerInfo(), false, false, 0);
2502 TargetLowering::ArgListTy Args;
2503 TargetLowering::ArgListEntry Entry;
2504 for (const SDValue &Op : N->op_values()) {
2505 EVT ArgVT = Op.getValueType();
2506 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2509 Entry.isSExt = true;
2510 Entry.isZExt = false;
2511 Args.push_back(Entry);
2514 // Also pass the address of the overflow check.
2516 Entry.Ty = PtrTy->getPointerTo();
2517 Entry.isSExt = true;
2518 Entry.isZExt = false;
2519 Args.push_back(Entry);
2521 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
2523 TargetLowering::CallLoweringInfo CLI(DAG);
2524 CLI.setDebugLoc(dl).setChain(Chain)
2525 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Func, std::move(Args), 0)
2528 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2530 SplitInteger(CallInfo.first, Lo, Hi);
2531 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
2532 MachinePointerInfo(), false, false, false, 0);
2533 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
2534 DAG.getConstant(0, dl, PtrVT),
2536 // Use the overflow from the libcall everywhere.
2537 ReplaceValueWith(SDValue(N, 1), Ofl);
2540 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2541 SDValue &Lo, SDValue &Hi) {
2542 EVT VT = N->getValueType(0);
2544 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2546 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
2547 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2548 SplitInteger(Res.getValue(0), Lo, Hi);
2552 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2554 LC = RTLIB::UDIV_I16;
2555 else if (VT == MVT::i32)
2556 LC = RTLIB::UDIV_I32;
2557 else if (VT == MVT::i64)
2558 LC = RTLIB::UDIV_I64;
2559 else if (VT == MVT::i128)
2560 LC = RTLIB::UDIV_I128;
2561 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2563 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, false, dl).first, Lo, Hi);
2566 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2567 SDValue &Lo, SDValue &Hi) {
2568 EVT VT = N->getValueType(0);
2570 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2572 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
2573 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2574 SplitInteger(Res.getValue(1), Lo, Hi);
2578 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2580 LC = RTLIB::UREM_I16;
2581 else if (VT == MVT::i32)
2582 LC = RTLIB::UREM_I32;
2583 else if (VT == MVT::i64)
2584 LC = RTLIB::UREM_I64;
2585 else if (VT == MVT::i128)
2586 LC = RTLIB::UREM_I128;
2587 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2589 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, false, dl).first, Lo, Hi);
2592 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2593 SDValue &Lo, SDValue &Hi) {
2594 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2596 SDValue Op = N->getOperand(0);
2597 if (Op.getValueType().bitsLE(NVT)) {
2598 // The low part is zero extension of the input (degenerates to a copy).
2599 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2600 Hi = DAG.getConstant(0, dl, NVT); // The high part is just a zero.
2602 // For example, extension of an i48 to an i64. The operand type necessarily
2603 // promotes to the result type, so will end up being expanded too.
2604 assert(getTypeAction(Op.getValueType()) ==
2605 TargetLowering::TypePromoteInteger &&
2606 "Only know how to promote this result!");
2607 SDValue Res = GetPromotedInteger(Op);
2608 assert(Res.getValueType() == N->getValueType(0) &&
2609 "Operand over promoted?");
2610 // Split the promoted operand. This will simplify when it is expanded.
2611 SplitInteger(Res, Lo, Hi);
2612 unsigned ExcessBits =
2613 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2614 Hi = DAG.getZeroExtendInReg(Hi, dl,
2615 EVT::getIntegerVT(*DAG.getContext(),
2620 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
2621 SDValue &Lo, SDValue &Hi) {
2623 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
2624 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
2625 SDValue Zero = DAG.getConstant(0, dl, VT);
2626 SDValue Swap = DAG.getAtomicCmpSwap(
2627 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
2628 cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->getOperand(0),
2629 N->getOperand(1), Zero, Zero, cast<AtomicSDNode>(N)->getMemOperand(),
2630 cast<AtomicSDNode>(N)->getOrdering(),
2631 cast<AtomicSDNode>(N)->getOrdering(),
2632 cast<AtomicSDNode>(N)->getSynchScope());
2634 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
2635 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
2638 //===----------------------------------------------------------------------===//
2639 // Integer Operand Expansion
2640 //===----------------------------------------------------------------------===//
2642 /// ExpandIntegerOperand - This method is called when the specified operand of
2643 /// the specified node is found to need expansion. At this point, all of the
2644 /// result types of the node are known to be legal, but other operands of the
2645 /// node may need promotion or expansion as well as the specified one.
2646 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2647 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2648 SDValue Res = SDValue();
2650 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2653 switch (N->getOpcode()) {
2656 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2657 N->dump(&DAG); dbgs() << "\n";
2659 llvm_unreachable("Do not know how to expand this operator's operand!");
2661 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2662 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2663 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2664 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2665 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2666 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2667 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2668 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2669 case ISD::SETCCE: Res = ExpandIntOp_SETCCE(N); break;
2670 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2671 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2672 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2673 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2679 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2680 case ISD::RETURNADDR:
2681 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2683 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
2686 // If the result is null, the sub-method took care of registering results etc.
2687 if (!Res.getNode()) return false;
2689 // If the result is N, the sub-method updated N in place. Tell the legalizer
2691 if (Res.getNode() == N)
2694 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2695 "Invalid operand expansion");
2697 ReplaceValueWith(SDValue(N, 0), Res);
2701 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2702 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2703 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2705 ISD::CondCode &CCCode,
2707 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2708 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2709 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2711 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2712 if (RHSLo == RHSHi) {
2713 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2714 if (RHSCST->isAllOnesValue()) {
2715 // Equality comparison to -1.
2716 NewLHS = DAG.getNode(ISD::AND, dl,
2717 LHSLo.getValueType(), LHSLo, LHSHi);
2724 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2725 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2726 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2727 NewRHS = DAG.getConstant(0, dl, NewLHS.getValueType());
2731 // If this is a comparison of the sign bit, just look at the top part.
2733 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2734 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2735 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2741 // FIXME: This generated code sucks.
2742 ISD::CondCode LowCC;
2744 default: llvm_unreachable("Unknown integer setcc!");
2746 case ISD::SETULT: LowCC = ISD::SETULT; break;
2748 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2750 case ISD::SETULE: LowCC = ISD::SETULE; break;
2752 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2755 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2756 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2757 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2759 // NOTE: on targets without efficient SELECT of bools, we can always use
2760 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2761 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
2764 if (TLI.isTypeLegal(LHSLo.getValueType()) &&
2765 TLI.isTypeLegal(RHSLo.getValueType()))
2766 Tmp1 = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()),
2767 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2768 if (!Tmp1.getNode())
2769 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()),
2770 LHSLo, RHSLo, LowCC);
2771 if (TLI.isTypeLegal(LHSHi.getValueType()) &&
2772 TLI.isTypeLegal(RHSHi.getValueType()))
2773 Tmp2 = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2774 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2775 if (!Tmp2.getNode())
2776 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2777 getSetCCResultType(LHSHi.getValueType()),
2778 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2780 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2781 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2782 if ((Tmp1C && Tmp1C->isNullValue()) ||
2783 (Tmp2C && Tmp2C->isNullValue() &&
2784 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2785 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2786 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2787 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2788 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2789 // low part is known false, returns high part.
2790 // For LE / GE, if high part is known false, ignore the low part.
2791 // For LT / GT, if high part is known true, ignore the low part.
2797 if (LHSHi == RHSHi) {
2798 // Comparing the low bits is enough.
2804 // Lower with SETCCE if the target supports it.
2805 // FIXME: Make all targets support this, then remove the other lowering.
2806 if (TLI.getOperationAction(
2808 TLI.getTypeToExpandTo(*DAG.getContext(), LHSLo.getValueType())) ==
2809 TargetLowering::Custom) {
2810 // SETCCE can detect < and >= directly. For > and <=, flip operands and
2812 bool FlipOperands = false;
2814 case ISD::SETGT: CCCode = ISD::SETLT; FlipOperands = true; break;
2815 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break;
2816 case ISD::SETLE: CCCode = ISD::SETGE; FlipOperands = true; break;
2817 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break;
2821 std::swap(LHSLo, RHSLo);
2822 std::swap(LHSHi, RHSHi);
2824 // Perform a wide subtraction, feeding the carry from the low part into
2825 // SETCCE. The SETCCE operation is essentially looking at the high part of
2826 // the result of LHS - RHS. It is negative iff LHS < RHS. It is zero or
2827 // positive iff LHS >= RHS.
2828 SDVTList VTList = DAG.getVTList(LHSLo.getValueType(), MVT::Glue);
2829 SDValue LowCmp = DAG.getNode(ISD::SUBC, dl, VTList, LHSLo, RHSLo);
2831 DAG.getNode(ISD::SETCCE, dl, getSetCCResultType(LHSLo.getValueType()),
2832 LHSHi, RHSHi, LowCmp.getValue(1), DAG.getCondCode(CCCode));
2838 NewLHS = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2839 LHSHi, RHSHi, ISD::SETEQ, false,
2840 DagCombineInfo, dl);
2841 if (!NewLHS.getNode())
2842 NewLHS = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
2843 LHSHi, RHSHi, ISD::SETEQ);
2844 NewLHS = DAG.getSelect(dl, Tmp1.getValueType(),
2845 NewLHS, Tmp1, Tmp2);
2849 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2850 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2851 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2852 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2854 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2855 // against zero to select between true and false values.
2856 if (!NewRHS.getNode()) {
2857 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
2858 CCCode = ISD::SETNE;
2861 // Update N to have the operands specified.
2862 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2863 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2864 N->getOperand(4)), 0);
2867 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2868 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2869 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2870 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2872 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2873 // against zero to select between true and false values.
2874 if (!NewRHS.getNode()) {
2875 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
2876 CCCode = ISD::SETNE;
2879 // Update N to have the operands specified.
2880 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2881 N->getOperand(2), N->getOperand(3),
2882 DAG.getCondCode(CCCode)), 0);
2885 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2886 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2887 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2888 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2890 // If ExpandSetCCOperands returned a scalar, use it.
2891 if (!NewRHS.getNode()) {
2892 assert(NewLHS.getValueType() == N->getValueType(0) &&
2893 "Unexpected setcc expansion!");
2897 // Otherwise, update N to have the operands specified.
2898 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2899 DAG.getCondCode(CCCode)), 0);
2902 SDValue DAGTypeLegalizer::ExpandIntOp_SETCCE(SDNode *N) {
2903 SDValue LHS = N->getOperand(0);
2904 SDValue RHS = N->getOperand(1);
2905 SDValue Carry = N->getOperand(2);
2906 SDValue Cond = N->getOperand(3);
2907 SDLoc dl = SDLoc(N);
2909 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2910 GetExpandedInteger(LHS, LHSLo, LHSHi);
2911 GetExpandedInteger(RHS, RHSLo, RHSHi);
2913 // Expand to a SUBE for the low part and a smaller SETCCE for the high.
2914 SDVTList VTList = DAG.getVTList(LHSLo.getValueType(), MVT::Glue);
2915 SDValue LowCmp = DAG.getNode(ISD::SUBE, dl, VTList, LHSLo, RHSLo, Carry);
2916 return DAG.getNode(ISD::SETCCE, dl, N->getValueType(0), LHSHi, RHSHi,
2917 LowCmp.getValue(1), Cond);
2920 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2921 // The value being shifted is legal, but the shift amount is too big.
2922 // It follows that either the result of the shift is undefined, or the
2923 // upper half of the shift amount is zero. Just use the lower half.
2925 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2926 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2929 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2930 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2931 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2932 // constant to valid type.
2934 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2935 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2938 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2939 SDValue Op = N->getOperand(0);
2940 EVT DstVT = N->getValueType(0);
2941 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2942 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2943 "Don't know how to expand this SINT_TO_FP!");
2944 return TLI.makeLibCall(DAG, LC, DstVT, Op, true, SDLoc(N)).first;
2947 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2948 if (ISD::isNormalStore(N))
2949 return ExpandOp_NormalStore(N, OpNo);
2951 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2952 assert(OpNo == 1 && "Can only expand the stored value so far");
2954 EVT VT = N->getOperand(1).getValueType();
2955 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2956 SDValue Ch = N->getChain();
2957 SDValue Ptr = N->getBasePtr();
2958 unsigned Alignment = N->getAlignment();
2959 bool isVolatile = N->isVolatile();
2960 bool isNonTemporal = N->isNonTemporal();
2961 AAMDNodes AAInfo = N->getAAInfo();
2965 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2967 if (N->getMemoryVT().bitsLE(NVT)) {
2968 GetExpandedInteger(N->getValue(), Lo, Hi);
2969 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2970 N->getMemoryVT(), isVolatile, isNonTemporal,
2974 if (DAG.getDataLayout().isLittleEndian()) {
2975 // Little-endian - low bits are at low addresses.
2976 GetExpandedInteger(N->getValue(), Lo, Hi);
2978 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2979 isVolatile, isNonTemporal, Alignment, AAInfo);
2981 unsigned ExcessBits =
2982 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2983 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2985 // Increment the pointer to the other half.
2986 unsigned IncrementSize = NVT.getSizeInBits()/8;
2987 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2988 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2989 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2990 N->getPointerInfo().getWithOffset(IncrementSize),
2991 NEVT, isVolatile, isNonTemporal,
2992 MinAlign(Alignment, IncrementSize), AAInfo);
2993 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2996 // Big-endian - high bits are at low addresses. Favor aligned stores at
2997 // the cost of some bit-fiddling.
2998 GetExpandedInteger(N->getValue(), Lo, Hi);
3000 EVT ExtVT = N->getMemoryVT();
3001 unsigned EBytes = ExtVT.getStoreSize();
3002 unsigned IncrementSize = NVT.getSizeInBits()/8;
3003 unsigned ExcessBits = (EBytes - IncrementSize)*8;
3004 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
3005 ExtVT.getSizeInBits() - ExcessBits);
3007 if (ExcessBits < NVT.getSizeInBits()) {
3008 // Transfer high bits from the top of Lo to the bottom of Hi.
3009 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
3010 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
3011 TLI.getPointerTy(DAG.getDataLayout())));
3013 ISD::OR, dl, NVT, Hi,
3014 DAG.getNode(ISD::SRL, dl, NVT, Lo,
3015 DAG.getConstant(ExcessBits, dl,
3016 TLI.getPointerTy(DAG.getDataLayout()))));
3019 // Store both the high bits and maybe some of the low bits.
3020 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
3021 HiVT, isVolatile, isNonTemporal, Alignment, AAInfo);
3023 // Increment the pointer to the other half.
3024 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
3025 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
3026 // Store the lowest ExcessBits bits in the second half.
3027 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
3028 N->getPointerInfo().getWithOffset(IncrementSize),
3029 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
3030 isVolatile, isNonTemporal,
3031 MinAlign(Alignment, IncrementSize), AAInfo);
3032 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
3035 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
3037 GetExpandedInteger(N->getOperand(0), InL, InH);
3038 // Just truncate the low part of the source.
3039 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL);
3042 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
3043 SDValue Op = N->getOperand(0);
3044 EVT SrcVT = Op.getValueType();
3045 EVT DstVT = N->getValueType(0);
3048 // The following optimization is valid only if every value in SrcVT (when
3049 // treated as signed) is representable in DstVT. Check that the mantissa
3050 // size of DstVT is >= than the number of bits in SrcVT -1.
3051 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT);
3052 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 &&
3053 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
3054 // Do a signed conversion then adjust the result.
3055 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
3056 SignedConv = TLI.LowerOperation(SignedConv, DAG);
3058 // The result of the signed conversion needs adjusting if the 'sign bit' of
3059 // the incoming integer was set. To handle this, we dynamically test to see
3060 // if it is set, and, if so, add a fudge factor.
3062 const uint64_t F32TwoE32 = 0x4F800000ULL;
3063 const uint64_t F32TwoE64 = 0x5F800000ULL;
3064 const uint64_t F32TwoE128 = 0x7F800000ULL;
3067 if (SrcVT == MVT::i32)
3068 FF = APInt(32, F32TwoE32);
3069 else if (SrcVT == MVT::i64)
3070 FF = APInt(32, F32TwoE64);
3071 else if (SrcVT == MVT::i128)
3072 FF = APInt(32, F32TwoE128);
3074 llvm_unreachable("Unsupported UINT_TO_FP!");
3076 // Check whether the sign bit is set.
3078 GetExpandedInteger(Op, Lo, Hi);
3079 SDValue SignSet = DAG.getSetCC(dl,
3080 getSetCCResultType(Hi.getValueType()),
3082 DAG.getConstant(0, dl, Hi.getValueType()),
3085 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
3087 DAG.getConstantPool(ConstantInt::get(*DAG.getContext(), FF.zext(64)),
3088 TLI.getPointerTy(DAG.getDataLayout()));
3090 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
3091 SDValue Zero = DAG.getIntPtrConstant(0, dl);
3092 SDValue Four = DAG.getIntPtrConstant(4, dl);
3093 if (DAG.getDataLayout().isBigEndian())
3094 std::swap(Zero, Four);
3095 SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet,
3097 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
3098 FudgePtr = DAG.getNode(ISD::ADD, dl, FudgePtr.getValueType(),
3100 Alignment = std::min(Alignment, 4u);
3102 // Load the value out, extending it from f32 to the destination float type.
3103 // FIXME: Avoid the extend by constructing the right constant pool?
3104 SDValue Fudge = DAG.getExtLoad(
3105 ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), FudgePtr,
3106 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
3107 false, false, false, Alignment);
3108 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
3111 // Otherwise, use a libcall.
3112 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
3113 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
3114 "Don't know how to expand this UINT_TO_FP!");
3115 return TLI.makeLibCall(DAG, LC, DstVT, Op, true, dl).first;
3118 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
3120 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
3121 cast<AtomicSDNode>(N)->getMemoryVT(),
3123 N->getOperand(1), N->getOperand(2),
3124 cast<AtomicSDNode>(N)->getMemOperand(),
3125 cast<AtomicSDNode>(N)->getOrdering(),
3126 cast<AtomicSDNode>(N)->getSynchScope());
3127 return Swap.getValue(1);
3131 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
3132 SDValue InOp0 = N->getOperand(0);
3133 EVT InVT = InOp0.getValueType();
3135 EVT OutVT = N->getValueType(0);
3136 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3137 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3138 unsigned OutNumElems = OutVT.getVectorNumElements();
3139 EVT NOutVTElem = NOutVT.getVectorElementType();
3142 SDValue BaseIdx = N->getOperand(1);
3144 SmallVector<SDValue, 8> Ops;
3145 Ops.reserve(OutNumElems);
3146 for (unsigned i = 0; i != OutNumElems; ++i) {
3148 // Extract the element from the original vector.
3149 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
3150 BaseIdx, DAG.getConstant(i, dl, BaseIdx.getValueType()));
3151 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3152 InVT.getVectorElementType(), N->getOperand(0), Index);
3154 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
3155 // Insert the converted element to the new vector.
3159 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3163 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
3164 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
3165 EVT VT = N->getValueType(0);
3168 ArrayRef<int> NewMask = SV->getMask().slice(0, VT.getVectorNumElements());
3170 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3171 SDValue V1 = GetPromotedInteger(N->getOperand(1));
3172 EVT OutVT = V0.getValueType();
3174 return DAG.getVectorShuffle(OutVT, dl, V0, V1, NewMask);
3178 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
3179 EVT OutVT = N->getValueType(0);
3180 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3181 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3182 unsigned NumElems = N->getNumOperands();
3183 EVT NOutVTElem = NOutVT.getVectorElementType();
3187 SmallVector<SDValue, 8> Ops;
3188 Ops.reserve(NumElems);
3189 for (unsigned i = 0; i != NumElems; ++i) {
3191 // BUILD_VECTOR integer operand types are allowed to be larger than the
3192 // result's element type. This may still be true after the promotion. For
3193 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
3194 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
3195 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
3196 Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
3198 Op = N->getOperand(i);
3202 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3205 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
3209 assert(!N->getOperand(0).getValueType().isVector() &&
3210 "Input must be a scalar");
3212 EVT OutVT = N->getValueType(0);
3213 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3214 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3215 EVT NOutVTElem = NOutVT.getVectorElementType();
3217 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
3219 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
3222 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
3225 EVT OutVT = N->getValueType(0);
3226 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3227 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3229 EVT InElemTy = OutVT.getVectorElementType();
3230 EVT OutElemTy = NOutVT.getVectorElementType();
3232 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
3233 unsigned NumOutElem = NOutVT.getVectorNumElements();
3234 unsigned NumOperands = N->getNumOperands();
3235 assert(NumElem * NumOperands == NumOutElem &&
3236 "Unexpected number of elements");
3238 // Take the elements from the first vector.
3239 SmallVector<SDValue, 8> Ops(NumOutElem);
3240 for (unsigned i = 0; i < NumOperands; ++i) {
3241 SDValue Op = N->getOperand(i);
3242 for (unsigned j = 0; j < NumElem; ++j) {
3243 SDValue Ext = DAG.getNode(
3244 ISD::EXTRACT_VECTOR_ELT, dl, InElemTy, Op,
3245 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3246 Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
3250 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3253 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
3254 EVT OutVT = N->getValueType(0);
3255 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3256 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3258 EVT NOutVTElem = NOutVT.getVectorElementType();
3261 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3263 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
3264 NOutVTElem, N->getOperand(1));
3265 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
3266 V0, ConvElem, N->getOperand(2));
3269 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3271 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3272 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl,
3273 TLI.getVectorIdxTy(DAG.getDataLayout()));
3274 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3275 V0->getValueType(0).getScalarType(), V0, V1);
3277 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
3278 // element types. If this is the case then we need to expand the outgoing
3279 // value and not truncate it.
3280 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
3283 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N) {
3285 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3286 MVT InVT = V0.getValueType().getSimpleVT();
3287 MVT OutVT = MVT::getVectorVT(InVT.getVectorElementType(),
3288 N->getValueType(0).getVectorNumElements());
3289 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1));
3290 return DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), Ext);
3293 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
3295 unsigned NumElems = N->getNumOperands();
3297 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
3299 SmallVector<SDValue, 8> NewOps;
3300 NewOps.reserve(NumElems);
3302 // For each incoming vector
3303 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
3304 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
3305 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
3306 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
3308 for (unsigned i=0; i<NumElem; ++i) {
3309 // Extract element from incoming vector
3310 SDValue Ex = DAG.getNode(
3311 ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Incoming,
3312 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3313 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
3314 NewOps.push_back(Tr);
3318 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0), NewOps);