1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/IR/DerivedTypes.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 #define DEBUG_TYPE "legalize-types"
29 //===----------------------------------------------------------------------===//
30 // Integer Result Promotion
31 //===----------------------------------------------------------------------===//
33 /// PromoteIntegerResult - This method is called when a result of a node is
34 /// found to be in need of promotion to a larger type. At this point, the node
35 /// may also have invalid operands or may have other results that need
36 /// expansion, we just know that (at least) one result needs promotion.
37 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
38 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
39 SDValue Res = SDValue();
41 // See if the target wants to custom expand this node.
42 if (CustomLowerNode(N, N->getValueType(ResNo), true))
45 switch (N->getOpcode()) {
48 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
49 N->dump(&DAG); dbgs() << "\n";
51 llvm_unreachable("Do not know how to promote this operator!");
52 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
56 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
57 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
58 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
59 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
60 case ISD::CONVERT_RNDSAT:
61 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
62 case ISD::CTLZ_ZERO_UNDEF:
63 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
64 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
65 case ISD::CTTZ_ZERO_UNDEF:
66 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
67 case ISD::EXTRACT_VECTOR_ELT:
68 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
69 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N)); break;
70 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));
72 case ISD::MGATHER: Res = PromoteIntRes_MGATHER(cast<MaskedGatherSDNode>(N));
74 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
75 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
76 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
77 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
79 case ISD::SMAX: Res = PromoteIntRes_SExtIntBinOp(N); break;
81 case ISD::UMAX: Res = PromoteIntRes_ZExtIntBinOp(N); break;
83 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
84 case ISD::SIGN_EXTEND_INREG:
85 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
86 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
87 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
88 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
89 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
90 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
92 case ISD::EXTRACT_SUBVECTOR:
93 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
94 case ISD::VECTOR_SHUFFLE:
95 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
96 case ISD::INSERT_VECTOR_ELT:
97 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
98 case ISD::BUILD_VECTOR:
99 Res = PromoteIntRes_BUILD_VECTOR(N); break;
100 case ISD::SCALAR_TO_VECTOR:
101 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
102 case ISD::CONCAT_VECTORS:
103 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
105 case ISD::SIGN_EXTEND:
106 case ISD::ZERO_EXTEND:
107 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
109 case ISD::FP_TO_SINT:
110 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
112 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
119 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
122 case ISD::SREM: Res = PromoteIntRes_SExtIntBinOp(N); break;
125 case ISD::UREM: Res = PromoteIntRes_ZExtIntBinOp(N); break;
128 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
130 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
132 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
134 case ISD::ATOMIC_LOAD:
135 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
137 case ISD::ATOMIC_LOAD_ADD:
138 case ISD::ATOMIC_LOAD_SUB:
139 case ISD::ATOMIC_LOAD_AND:
140 case ISD::ATOMIC_LOAD_OR:
141 case ISD::ATOMIC_LOAD_XOR:
142 case ISD::ATOMIC_LOAD_NAND:
143 case ISD::ATOMIC_LOAD_MIN:
144 case ISD::ATOMIC_LOAD_MAX:
145 case ISD::ATOMIC_LOAD_UMIN:
146 case ISD::ATOMIC_LOAD_UMAX:
147 case ISD::ATOMIC_SWAP:
148 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
150 case ISD::ATOMIC_CMP_SWAP:
151 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
152 Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
156 // If the result is null then the sub-method took care of registering it.
158 SetPromotedInteger(SDValue(N, ResNo), Res);
161 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
163 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
164 return GetPromotedInteger(Op);
167 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
168 // Sign-extend the new bits, and continue the assertion.
169 SDValue Op = SExtPromotedInteger(N->getOperand(0));
170 return DAG.getNode(ISD::AssertSext, SDLoc(N),
171 Op.getValueType(), Op, N->getOperand(1));
174 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
175 // Zero the new bits, and continue the assertion.
176 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
177 return DAG.getNode(ISD::AssertZext, SDLoc(N),
178 Op.getValueType(), Op, N->getOperand(1));
181 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
182 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
183 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
184 N->getMemoryVT(), ResVT,
185 N->getChain(), N->getBasePtr(),
186 N->getMemOperand(), N->getOrdering(),
188 // Legalize the chain result - switch anything that used the old chain to
190 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
194 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
195 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
196 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
198 N->getChain(), N->getBasePtr(),
199 Op2, N->getMemOperand(), N->getOrdering(),
201 // Legalize the chain result - switch anything that used the old chain to
203 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
207 SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
210 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
211 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
212 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
214 // Only use the result of getSetCCResultType if it is legal,
215 // otherwise just use the promoted result type (NVT).
216 if (!TLI.isTypeLegal(SVT))
219 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
220 SDValue Res = DAG.getAtomicCmpSwap(
221 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
222 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
223 N->getMemOperand(), N->getSuccessOrdering(), N->getFailureOrdering(),
225 ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
226 ReplaceValueWith(SDValue(N, 2), Res.getValue(2));
227 return Res.getValue(1);
230 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
231 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
233 DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
234 SDValue Res = DAG.getAtomicCmpSwap(
235 N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
236 N->getBasePtr(), Op2, Op3, N->getMemOperand(), N->getSuccessOrdering(),
237 N->getFailureOrdering(), N->getSynchScope());
238 // Update the use to N with the newly created Res.
239 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
240 ReplaceValueWith(SDValue(N, i), Res.getValue(i));
244 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
245 SDValue InOp = N->getOperand(0);
246 EVT InVT = InOp.getValueType();
247 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
248 EVT OutVT = N->getValueType(0);
249 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
252 switch (getTypeAction(InVT)) {
253 case TargetLowering::TypeLegal:
255 case TargetLowering::TypePromoteInteger:
256 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
257 // The input promotes to the same size. Convert the promoted value.
258 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
260 case TargetLowering::TypeSoftenFloat:
261 // Promote the integer operand by hand.
262 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
263 case TargetLowering::TypePromoteFloat: {
264 // Convert the promoted float by hand.
265 if (NOutVT.bitsEq(NInVT)) {
266 SDValue PromotedOp = GetPromotedFloat(InOp);
267 SDValue Trunc = DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp);
268 return DAG.getNode(ISD::AssertZext, dl, NOutVT, Trunc,
269 DAG.getValueType(OutVT));
273 case TargetLowering::TypeExpandInteger:
274 case TargetLowering::TypeExpandFloat:
276 case TargetLowering::TypeScalarizeVector:
277 // Convert the element to an integer and promote it by hand.
278 if (!NOutVT.isVector())
279 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
280 BitConvertToInteger(GetScalarizedVector(InOp)));
282 case TargetLowering::TypeSplitVector: {
283 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
284 // pieces of the input into integers and reassemble in the final type.
286 GetSplitVector(N->getOperand(0), Lo, Hi);
287 Lo = BitConvertToInteger(Lo);
288 Hi = BitConvertToInteger(Hi);
290 if (DAG.getDataLayout().isBigEndian())
293 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
294 EVT::getIntegerVT(*DAG.getContext(),
295 NOutVT.getSizeInBits()),
296 JoinIntegers(Lo, Hi));
297 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
299 case TargetLowering::TypeWidenVector:
300 // The input is widened to the same size. Convert to the widened value.
301 // Make sure that the outgoing value is not a vector, because this would
302 // make us bitcast between two vectors which are legalized in different ways.
303 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector())
304 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
307 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
308 CreateStackStoreLoad(InOp, OutVT));
311 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
312 SDValue Op = GetPromotedInteger(N->getOperand(0));
313 EVT OVT = N->getValueType(0);
314 EVT NVT = Op.getValueType();
317 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
319 ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
320 DAG.getConstant(DiffBits, dl,
321 TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
324 SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
325 SDValue Op = GetPromotedInteger(N->getOperand(0));
326 EVT OVT = N->getValueType(0);
327 EVT NVT = Op.getValueType();
330 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
332 ISD::SRL, dl, NVT, DAG.getNode(ISD::BITREVERSE, dl, NVT, Op),
333 DAG.getConstant(DiffBits, dl,
334 TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
337 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
338 // The pair element type may be legal, or may not promote to the same type as
339 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
340 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
341 TLI.getTypeToTransformTo(*DAG.getContext(),
342 N->getValueType(0)), JoinIntegers(N->getOperand(0),
346 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
347 EVT VT = N->getValueType(0);
348 // FIXME there is no actual debug info here
350 // Zero extend things like i1, sign extend everything else. It shouldn't
351 // matter in theory which one we pick, but this tends to give better code?
352 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
353 SDValue Result = DAG.getNode(Opc, dl,
354 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
356 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
360 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
361 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
362 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
363 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
364 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
365 "can only promote integers");
366 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
367 return DAG.getConvertRndSat(OutVT, SDLoc(N), N->getOperand(0),
368 N->getOperand(1), N->getOperand(2),
369 N->getOperand(3), N->getOperand(4), CvtCode);
372 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
373 // Zero extend to the promoted type and do the count there.
374 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
376 EVT OVT = N->getValueType(0);
377 EVT NVT = Op.getValueType();
378 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
379 // Subtract off the extra leading bits in the bigger type.
381 ISD::SUB, dl, NVT, Op,
382 DAG.getConstant(NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), dl,
386 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
387 // Zero extend to the promoted type and do the count there.
388 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
389 return DAG.getNode(ISD::CTPOP, SDLoc(N), Op.getValueType(), Op);
392 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
393 SDValue Op = GetPromotedInteger(N->getOperand(0));
394 EVT OVT = N->getValueType(0);
395 EVT NVT = Op.getValueType();
397 if (N->getOpcode() == ISD::CTTZ) {
398 // The count is the same in the promoted type except if the original
399 // value was zero. This can be handled by setting the bit just off
400 // the top of the original type.
401 auto TopBit = APInt::getOneBitSet(NVT.getScalarSizeInBits(),
402 OVT.getScalarSizeInBits());
403 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, dl, NVT));
405 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
408 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
410 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
411 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
415 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
416 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
417 unsigned NewOpc = N->getOpcode();
420 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
421 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
422 // and SINT conversions are Custom, there is no way to tell which is
423 // preferable. We choose SINT because that's the right thing on PPC.)
424 if (N->getOpcode() == ISD::FP_TO_UINT &&
425 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
426 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
427 NewOpc = ISD::FP_TO_SINT;
429 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
431 // Assert that the converted value fits in the original type. If it doesn't
432 // (eg: because the value being converted is too big), then the result of the
433 // original operation was undefined anyway, so the assert is still correct.
434 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
435 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
436 DAG.getValueType(N->getValueType(0).getScalarType()));
439 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) {
440 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
443 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
445 return DAG.getNode(ISD::AssertZext, dl,
446 NVT, Res, DAG.getValueType(N->getValueType(0)));
449 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
450 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
453 if (getTypeAction(N->getOperand(0).getValueType())
454 == TargetLowering::TypePromoteInteger) {
455 SDValue Res = GetPromotedInteger(N->getOperand(0));
456 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
458 // If the result and operand types are the same after promotion, simplify
459 // to an in-register extension.
460 if (NVT == Res.getValueType()) {
461 // The high bits are not guaranteed to be anything. Insert an extend.
462 if (N->getOpcode() == ISD::SIGN_EXTEND)
463 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
464 DAG.getValueType(N->getOperand(0).getValueType()));
465 if (N->getOpcode() == ISD::ZERO_EXTEND)
466 return DAG.getZeroExtendInReg(Res, dl,
467 N->getOperand(0).getValueType().getScalarType());
468 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
473 // Otherwise, just extend the original operand all the way to the larger type.
474 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
477 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
478 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
479 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
480 ISD::LoadExtType ExtType =
481 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
483 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
484 N->getMemoryVT(), N->getMemOperand());
486 // Legalize the chain result - switch anything that used the old chain to
488 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
492 SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
493 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
494 SDValue ExtSrc0 = GetPromotedInteger(N->getSrc0());
497 SDValue Res = DAG.getMaskedLoad(NVT, dl, N->getChain(), N->getBasePtr(),
498 N->getMask(), ExtSrc0, N->getMemoryVT(),
499 N->getMemOperand(), ISD::SEXTLOAD);
500 // Legalize the chain result - switch anything that used the old chain to
502 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
506 SDValue DAGTypeLegalizer::PromoteIntRes_MGATHER(MaskedGatherSDNode *N) {
507 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
508 SDValue ExtSrc0 = GetPromotedInteger(N->getValue());
509 assert(NVT == ExtSrc0.getValueType() &&
510 "Gather result type and the passThru agrument type should be the same");
513 SDValue Ops[] = {N->getChain(), ExtSrc0, N->getMask(), N->getBasePtr(),
515 SDValue Res = DAG.getMaskedGather(DAG.getVTList(NVT, MVT::Other),
516 N->getMemoryVT(), dl, Ops,
518 // Legalize the chain result - switch anything that used the old chain to
520 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
524 /// Promote the overflow flag of an overflowing arithmetic node.
525 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
526 // Simply change the return type of the boolean result.
527 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
528 EVT ValueVTs[] = { N->getValueType(0), NVT };
529 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
530 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),
531 DAG.getVTList(ValueVTs), Ops);
533 // Modified the sum result - switch anything that used the old sum to use
535 ReplaceValueWith(SDValue(N, 0), Res);
537 return SDValue(Res.getNode(), 1);
540 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
542 return PromoteIntRes_Overflow(N);
544 // The operation overflowed iff the result in the larger type is not the
545 // sign extension of its truncation to the original type.
546 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
547 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
548 EVT OVT = N->getOperand(0).getValueType();
549 EVT NVT = LHS.getValueType();
552 // Do the arithmetic in the larger type.
553 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
554 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
556 // Calculate the overflow flag: sign extend the arithmetic result from
557 // the original type.
558 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
559 DAG.getValueType(OVT));
560 // Overflowed if and only if this is not equal to Res.
561 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
563 // Use the calculated overflow everywhere.
564 ReplaceValueWith(SDValue(N, 1), Ofl);
569 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
570 SDValue LHS = GetPromotedInteger(N->getOperand(1));
571 SDValue RHS = GetPromotedInteger(N->getOperand(2));
572 return DAG.getSelect(SDLoc(N),
573 LHS.getValueType(), N->getOperand(0), LHS, RHS);
576 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
577 SDValue Mask = N->getOperand(0);
578 EVT OpTy = N->getOperand(1).getValueType();
580 // Promote all the way up to the canonical SetCC type.
581 Mask = PromoteTargetBoolean(Mask, OpTy);
582 SDValue LHS = GetPromotedInteger(N->getOperand(1));
583 SDValue RHS = GetPromotedInteger(N->getOperand(2));
584 return DAG.getNode(ISD::VSELECT, SDLoc(N),
585 LHS.getValueType(), Mask, LHS, RHS);
588 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
589 SDValue LHS = GetPromotedInteger(N->getOperand(2));
590 SDValue RHS = GetPromotedInteger(N->getOperand(3));
591 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
592 LHS.getValueType(), N->getOperand(0),
593 N->getOperand(1), LHS, RHS, N->getOperand(4));
596 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
597 EVT SVT = getSetCCResultType(N->getOperand(0).getValueType());
599 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
601 // Only use the result of getSetCCResultType if it is legal,
602 // otherwise just use the promoted result type (NVT).
603 if (!TLI.isTypeLegal(SVT))
607 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
608 "Vector compare must return a vector result!");
610 SDValue LHS = N->getOperand(0);
611 SDValue RHS = N->getOperand(1);
612 if (LHS.getValueType() != RHS.getValueType()) {
613 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger &&
614 !LHS.getValueType().isVector())
615 LHS = GetPromotedInteger(LHS);
616 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger &&
617 !RHS.getValueType().isVector())
618 RHS = GetPromotedInteger(RHS);
621 // Get the SETCC result using the canonical SETCC type.
622 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
625 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
626 // Convert to the expected type.
627 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
630 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
631 SDValue LHS = N->getOperand(0);
632 SDValue RHS = N->getOperand(1);
633 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
634 LHS = GetPromotedInteger(LHS);
635 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
636 RHS = ZExtPromotedInteger(RHS);
637 return DAG.getNode(ISD::SHL, SDLoc(N), LHS.getValueType(), LHS, RHS);
640 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
641 SDValue Op = GetPromotedInteger(N->getOperand(0));
642 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
643 Op.getValueType(), Op, N->getOperand(1));
646 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
647 // The input may have strange things in the top bits of the registers, but
648 // these operations don't care. They may have weird bits going out, but
649 // that too is okay if they are integer operations.
650 SDValue LHS = GetPromotedInteger(N->getOperand(0));
651 SDValue RHS = GetPromotedInteger(N->getOperand(1));
652 return DAG.getNode(N->getOpcode(), SDLoc(N),
653 LHS.getValueType(), LHS, RHS);
656 SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(SDNode *N) {
657 // Sign extend the input.
658 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
659 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
660 return DAG.getNode(N->getOpcode(), SDLoc(N),
661 LHS.getValueType(), LHS, RHS);
664 SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
665 // Zero extend the input.
666 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
667 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
668 return DAG.getNode(N->getOpcode(), SDLoc(N),
669 LHS.getValueType(), LHS, RHS);
672 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
673 SDValue LHS = N->getOperand(0);
674 SDValue RHS = N->getOperand(1);
675 // The input value must be properly sign extended.
676 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
677 LHS = SExtPromotedInteger(LHS);
678 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
679 RHS = ZExtPromotedInteger(RHS);
680 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS);
683 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
684 SDValue LHS = N->getOperand(0);
685 SDValue RHS = N->getOperand(1);
686 // The input value must be properly zero extended.
687 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
688 LHS = ZExtPromotedInteger(LHS);
689 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
690 RHS = ZExtPromotedInteger(RHS);
691 return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS);
694 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
695 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
697 SDValue InOp = N->getOperand(0);
700 switch (getTypeAction(InOp.getValueType())) {
701 default: llvm_unreachable("Unknown type action!");
702 case TargetLowering::TypeLegal:
703 case TargetLowering::TypeExpandInteger:
706 case TargetLowering::TypePromoteInteger:
707 Res = GetPromotedInteger(InOp);
709 case TargetLowering::TypeSplitVector:
710 EVT InVT = InOp.getValueType();
711 assert(InVT.isVector() && "Cannot split scalar types");
712 unsigned NumElts = InVT.getVectorNumElements();
713 assert(NumElts == NVT.getVectorNumElements() &&
714 "Dst and Src must have the same number of elements");
715 assert(isPowerOf2_32(NumElts) &&
716 "Promoted vector type must be a power of two");
719 GetSplitVector(InOp, EOp1, EOp2);
721 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
723 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
724 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
726 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
729 // Truncate to NVT instead of VT
730 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
733 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
735 return PromoteIntRes_Overflow(N);
737 // The operation overflowed iff the result in the larger type is not the
738 // zero extension of its truncation to the original type.
739 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
740 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
741 EVT OVT = N->getOperand(0).getValueType();
742 EVT NVT = LHS.getValueType();
745 // Do the arithmetic in the larger type.
746 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
747 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
749 // Calculate the overflow flag: zero extend the arithmetic result from
750 // the original type.
751 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
752 // Overflowed if and only if this is not equal to Res.
753 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
755 // Use the calculated overflow everywhere.
756 ReplaceValueWith(SDValue(N, 1), Ofl);
761 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
762 // Promote the overflow bit trivially.
764 return PromoteIntRes_Overflow(N);
766 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
768 EVT SmallVT = LHS.getValueType();
770 // To determine if the result overflowed in a larger type, we extend the
771 // input to the larger type, do the multiply (checking if it overflows),
772 // then also check the high bits of the result to see if overflow happened
774 if (N->getOpcode() == ISD::SMULO) {
775 LHS = SExtPromotedInteger(LHS);
776 RHS = SExtPromotedInteger(RHS);
778 LHS = ZExtPromotedInteger(LHS);
779 RHS = ZExtPromotedInteger(RHS);
781 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
782 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
784 // Overflow occurred if it occurred in the larger type, or if the high part
785 // of the result does not zero/sign-extend the low part. Check this second
786 // possibility first.
788 if (N->getOpcode() == ISD::UMULO) {
789 // Unsigned overflow occurred if the high part is non-zero.
790 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
791 DAG.getIntPtrConstant(SmallVT.getSizeInBits(),
793 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
794 DAG.getConstant(0, DL, Hi.getValueType()),
797 // Signed overflow occurred if the high part does not sign extend the low.
798 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
799 Mul, DAG.getValueType(SmallVT));
800 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
803 // The only other way for overflow to occur is if the multiplication in the
804 // larger type itself overflowed.
805 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
806 SDValue(Mul.getNode(), 1));
808 // Use the calculated overflow everywhere.
809 ReplaceValueWith(SDValue(N, 1), Overflow);
813 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
814 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
815 N->getValueType(0)));
818 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
819 SDValue Chain = N->getOperand(0); // Get the chain.
820 SDValue Ptr = N->getOperand(1); // Get the pointer.
821 EVT VT = N->getValueType(0);
824 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
825 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
826 // The argument is passed as NumRegs registers of type RegVT.
828 SmallVector<SDValue, 8> Parts(NumRegs);
829 for (unsigned i = 0; i < NumRegs; ++i) {
830 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
831 N->getConstantOperandVal(3));
832 Chain = Parts[i].getValue(1);
835 // Handle endianness of the load.
836 if (DAG.getDataLayout().isBigEndian())
837 std::reverse(Parts.begin(), Parts.end());
839 // Assemble the parts in the promoted type.
840 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
841 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
842 for (unsigned i = 1; i < NumRegs; ++i) {
843 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
844 // Shift it to the right position and "or" it in.
845 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
846 DAG.getConstant(i * RegVT.getSizeInBits(), dl,
847 TLI.getPointerTy(DAG.getDataLayout())));
848 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
851 // Modified the chain result - switch anything that used the old chain to
853 ReplaceValueWith(SDValue(N, 1), Chain);
858 //===----------------------------------------------------------------------===//
859 // Integer Operand Promotion
860 //===----------------------------------------------------------------------===//
862 /// PromoteIntegerOperand - This method is called when the specified operand of
863 /// the specified node is found to need promotion. At this point, all of the
864 /// result types of the node are known to be legal, but other operands of the
865 /// node may need promotion or expansion as well as the specified one.
866 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
867 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
868 SDValue Res = SDValue();
870 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
873 switch (N->getOpcode()) {
876 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
877 N->dump(&DAG); dbgs() << "\n";
879 llvm_unreachable("Do not know how to promote this operator's operand!");
881 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
882 case ISD::ATOMIC_STORE:
883 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
885 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
886 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
887 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
888 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
889 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
890 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
891 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
892 case ISD::CONVERT_RNDSAT:
893 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
894 case ISD::INSERT_VECTOR_ELT:
895 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
896 case ISD::SCALAR_TO_VECTOR:
897 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
899 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
900 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
901 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
902 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
903 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
904 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
906 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
908 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
910 case ISD::MGATHER: Res = PromoteIntOp_MGATHER(cast<MaskedGatherSDNode>(N),
912 case ISD::MSCATTER: Res = PromoteIntOp_MSCATTER(cast<MaskedScatterSDNode>(N),
914 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
915 case ISD::FP16_TO_FP:
916 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
917 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
918 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
924 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
927 // If the result is null, the sub-method took care of registering results etc.
928 if (!Res.getNode()) return false;
930 // If the result is N, the sub-method updated N in place. Tell the legalizer
932 if (Res.getNode() == N)
935 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
936 "Invalid operand expansion");
938 ReplaceValueWith(SDValue(N, 0), Res);
942 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
943 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
944 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
945 ISD::CondCode CCCode) {
946 // We have to insert explicit sign or zero extends. Note that we could
947 // insert sign extends for ALL conditions, but zero extend is cheaper on
948 // many machines (an AND instead of two shifts), so prefer it.
950 default: llvm_unreachable("Unknown integer comparison!");
953 SDValue OpL = GetPromotedInteger(NewLHS);
954 SDValue OpR = GetPromotedInteger(NewRHS);
956 // We would prefer to promote the comparison operand with sign extension,
957 // if we find the operand is actually to truncate an AssertSext. With this
958 // optimization, we can avoid inserting real truncate instruction, which
959 // is redudant eventually.
960 if (OpL->getOpcode() == ISD::AssertSext &&
961 cast<VTSDNode>(OpL->getOperand(1))->getVT() == NewLHS.getValueType() &&
962 OpR->getOpcode() == ISD::AssertSext &&
963 cast<VTSDNode>(OpR->getOperand(1))->getVT() == NewRHS.getValueType()) {
967 NewLHS = ZExtPromotedInteger(NewLHS);
968 NewRHS = ZExtPromotedInteger(NewRHS);
976 // ALL of these operations will work if we either sign or zero extend
977 // the operands (including the unsigned comparisons!). Zero extend is
978 // usually a simpler/cheaper operation, so prefer it.
979 NewLHS = ZExtPromotedInteger(NewLHS);
980 NewRHS = ZExtPromotedInteger(NewRHS);
986 NewLHS = SExtPromotedInteger(NewLHS);
987 NewRHS = SExtPromotedInteger(NewRHS);
992 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
993 SDValue Op = GetPromotedInteger(N->getOperand(0));
994 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
997 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
998 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
999 return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
1000 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(),
1001 N->getOrdering(), N->getSynchScope());
1004 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
1005 // This should only occur in unusual situations like bitcasting to an
1006 // x86_fp80, so just turn it into a store+load
1007 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
1010 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
1011 assert(OpNo == 2 && "Don't know how to promote this operand!");
1013 SDValue LHS = N->getOperand(2);
1014 SDValue RHS = N->getOperand(3);
1015 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
1017 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
1019 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1020 N->getOperand(1), LHS, RHS, N->getOperand(4)),
1024 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
1025 assert(OpNo == 1 && "only know how to promote condition");
1027 // Promote all the way up to the canonical SetCC type.
1028 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), MVT::Other);
1030 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
1031 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
1032 N->getOperand(2)), 0);
1035 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
1036 // Since the result type is legal, the operands must promote to it.
1037 EVT OVT = N->getOperand(0).getValueType();
1038 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
1039 SDValue Hi = GetPromotedInteger(N->getOperand(1));
1040 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
1043 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
1044 DAG.getConstant(OVT.getSizeInBits(), dl,
1045 TLI.getPointerTy(DAG.getDataLayout())));
1046 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
1049 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
1050 // The vector type is legal but the element type is not. This implies
1051 // that the vector is a power-of-two in length and that the element
1052 // type does not have a strange size (eg: it is not i1).
1053 EVT VecVT = N->getValueType(0);
1054 unsigned NumElts = VecVT.getVectorNumElements();
1055 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
1056 "Legal vector of one illegal element?");
1058 // Promote the inserted value. The type does not need to match the
1059 // vector element type. Check that any extra bits introduced will be
1061 assert(N->getOperand(0).getValueType().getSizeInBits() >=
1062 N->getValueType(0).getVectorElementType().getSizeInBits() &&
1063 "Type of inserted value narrower than vector element type!");
1065 SmallVector<SDValue, 16> NewOps;
1066 for (unsigned i = 0; i < NumElts; ++i)
1067 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
1069 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1072 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
1073 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1074 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
1075 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
1076 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
1077 "can only promote integer arguments");
1078 SDValue InOp = GetPromotedInteger(N->getOperand(0));
1079 return DAG.getConvertRndSat(N->getValueType(0), SDLoc(N), InOp,
1080 N->getOperand(1), N->getOperand(2),
1081 N->getOperand(3), N->getOperand(4), CvtCode);
1084 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
1087 // Promote the inserted value. This is valid because the type does not
1088 // have to match the vector element type.
1090 // Check that any extra bits introduced will be truncated away.
1091 assert(N->getOperand(1).getValueType().getSizeInBits() >=
1092 N->getValueType(0).getVectorElementType().getSizeInBits() &&
1093 "Type of inserted value narrower than vector element type!");
1094 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1095 GetPromotedInteger(N->getOperand(1)),
1100 assert(OpNo == 2 && "Different operand and result vector types?");
1102 // Promote the index.
1103 SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
1104 TLI.getVectorIdxTy(DAG.getDataLayout()));
1105 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1106 N->getOperand(1), Idx), 0);
1109 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
1110 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
1111 // the operand in place.
1112 return SDValue(DAG.UpdateNodeOperands(N,
1113 GetPromotedInteger(N->getOperand(0))), 0);
1116 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
1117 assert(OpNo == 0 && "Only know how to promote the condition!");
1118 SDValue Cond = N->getOperand(0);
1119 EVT OpTy = N->getOperand(1).getValueType();
1121 // Promote all the way up to the canonical SetCC type.
1122 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1123 Cond = PromoteTargetBoolean(Cond, OpVT);
1125 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
1126 N->getOperand(2)), 0);
1129 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1130 assert(OpNo == 0 && "Don't know how to promote this operand!");
1132 SDValue LHS = N->getOperand(0);
1133 SDValue RHS = N->getOperand(1);
1134 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1136 // The CC (#4) and the possible return values (#2 and #3) have legal types.
1137 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1138 N->getOperand(3), N->getOperand(4)), 0);
1141 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1142 assert(OpNo == 0 && "Don't know how to promote this operand!");
1144 SDValue LHS = N->getOperand(0);
1145 SDValue RHS = N->getOperand(1);
1146 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1148 // The CC (#2) is always legal.
1149 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1152 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1153 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1154 ZExtPromotedInteger(N->getOperand(1))), 0);
1157 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1158 SDValue Op = GetPromotedInteger(N->getOperand(0));
1160 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1161 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1162 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1165 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1166 return SDValue(DAG.UpdateNodeOperands(N,
1167 SExtPromotedInteger(N->getOperand(0))), 0);
1170 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1171 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1172 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1175 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1177 // Truncate the value and store the result.
1178 return DAG.getTruncStore(Ch, dl, Val, Ptr,
1179 N->getMemoryVT(), N->getMemOperand());
1182 SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N,
1185 SDValue DataOp = N->getValue();
1186 EVT DataVT = DataOp.getValueType();
1187 SDValue Mask = N->getMask();
1190 bool TruncateStore = false;
1192 // Mask comes before the data operand. If the data operand is legal, we just
1193 // promote the mask.
1194 // When the data operand has illegal type, we should legalize the data
1195 // operand first. The mask will be promoted/splitted/widened according to
1196 // the data operand type.
1197 if (TLI.isTypeLegal(DataVT))
1198 Mask = PromoteTargetBoolean(Mask, DataVT);
1200 if (getTypeAction(DataVT) == TargetLowering::TypePromoteInteger)
1201 return PromoteIntOp_MSTORE(N, 3);
1203 else if (getTypeAction(DataVT) == TargetLowering::TypeWidenVector)
1204 return WidenVecOp_MSTORE(N, 3);
1207 assert (getTypeAction(DataVT) == TargetLowering::TypeSplitVector);
1208 return SplitVecOp_MSTORE(N, 3);
1211 } else { // Data operand
1212 assert(OpNo == 3 && "Unexpected operand for promotion");
1213 DataOp = GetPromotedInteger(DataOp);
1214 Mask = PromoteTargetBoolean(Mask, DataOp.getValueType());
1215 TruncateStore = true;
1218 return DAG.getMaskedStore(N->getChain(), dl, DataOp, N->getBasePtr(), Mask,
1219 N->getMemoryVT(), N->getMemOperand(),
1223 SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N,
1225 assert(OpNo == 2 && "Only know how to promote the mask!");
1226 EVT DataVT = N->getValueType(0);
1227 SDValue Mask = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1228 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1229 NewOps[OpNo] = Mask;
1230 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1233 SDValue DAGTypeLegalizer::PromoteIntOp_MGATHER(MaskedGatherSDNode *N,
1236 SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
1239 EVT DataVT = N->getValueType(0);
1240 NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1242 NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
1243 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1246 SDValue DAGTypeLegalizer::PromoteIntOp_MSCATTER(MaskedScatterSDNode *N,
1248 SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
1251 EVT DataVT = N->getValue().getValueType();
1252 NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1254 NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
1255 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1258 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1259 SDValue Op = GetPromotedInteger(N->getOperand(0));
1260 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
1263 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1264 return SDValue(DAG.UpdateNodeOperands(N,
1265 ZExtPromotedInteger(N->getOperand(0))), 0);
1268 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1270 SDValue Op = GetPromotedInteger(N->getOperand(0));
1271 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1272 return DAG.getZeroExtendInReg(Op, dl,
1273 N->getOperand(0).getValueType().getScalarType());
1277 //===----------------------------------------------------------------------===//
1278 // Integer Result Expansion
1279 //===----------------------------------------------------------------------===//
1281 /// ExpandIntegerResult - This method is called when the specified result of the
1282 /// specified node is found to need expansion. At this point, the node may also
1283 /// have invalid operands or may have other results that need promotion, we just
1284 /// know that (at least) one result needs expansion.
1285 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1286 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
1288 Lo = Hi = SDValue();
1290 // See if the target wants to custom expand this node.
1291 if (CustomLowerNode(N, N->getValueType(ResNo), true))
1294 switch (N->getOpcode()) {
1297 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1298 N->dump(&DAG); dbgs() << "\n";
1300 llvm_unreachable("Do not know how to expand the result of this operator!");
1302 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1303 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1304 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1305 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1307 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1308 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1309 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1310 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1311 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1313 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1314 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1315 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1316 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break;
1317 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1318 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1319 case ISD::CTLZ_ZERO_UNDEF:
1320 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1321 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1322 case ISD::CTTZ_ZERO_UNDEF:
1323 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1324 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1325 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1326 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1327 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1328 case ISD::READCYCLECOUNTER: ExpandIntRes_READCYCLECOUNTER(N, Lo, Hi); break;
1329 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1330 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1331 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1332 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1333 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1334 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1335 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1336 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1337 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1339 case ISD::ATOMIC_LOAD_ADD:
1340 case ISD::ATOMIC_LOAD_SUB:
1341 case ISD::ATOMIC_LOAD_AND:
1342 case ISD::ATOMIC_LOAD_OR:
1343 case ISD::ATOMIC_LOAD_XOR:
1344 case ISD::ATOMIC_LOAD_NAND:
1345 case ISD::ATOMIC_LOAD_MIN:
1346 case ISD::ATOMIC_LOAD_MAX:
1347 case ISD::ATOMIC_LOAD_UMIN:
1348 case ISD::ATOMIC_LOAD_UMAX:
1349 case ISD::ATOMIC_SWAP:
1350 case ISD::ATOMIC_CMP_SWAP: {
1351 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1352 SplitInteger(Tmp.first, Lo, Hi);
1353 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1356 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
1357 AtomicSDNode *AN = cast<AtomicSDNode>(N);
1358 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::Other);
1359 SDValue Tmp = DAG.getAtomicCmpSwap(
1360 ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
1361 N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3),
1362 AN->getMemOperand(), AN->getSuccessOrdering(), AN->getFailureOrdering(),
1363 AN->getSynchScope());
1365 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
1366 // success simply by comparing the loaded value against the ingoing
1368 SDValue Success = DAG.getSetCC(SDLoc(N), N->getValueType(1), Tmp,
1369 N->getOperand(2), ISD::SETEQ);
1371 SplitInteger(Tmp, Lo, Hi);
1372 ReplaceValueWith(SDValue(N, 1), Success);
1373 ReplaceValueWith(SDValue(N, 2), Tmp.getValue(1));
1379 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1382 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1385 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1388 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1392 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1395 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1397 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1399 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1402 // If Lo/Hi is null, the sub-method took care of registering results etc.
1404 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1407 /// Lower an atomic node to the appropriate builtin call.
1408 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1409 unsigned Opc = Node->getOpcode();
1410 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1411 RTLIB::Libcall LC = RTLIB::getATOMIC(Opc, VT);
1412 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
1414 return ExpandChainLibCall(LC, Node, false);
1417 /// N is a shift by a value that needs to be expanded,
1418 /// and the shift amount is a constant 'Amt'. Expand the operation.
1419 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
1420 SDValue &Lo, SDValue &Hi) {
1422 // Expand the incoming operand to be shifted, so that we have its parts
1424 GetExpandedInteger(N->getOperand(0), InL, InH);
1426 // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
1427 // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
1434 EVT NVT = InL.getValueType();
1435 unsigned VTBits = N->getValueType(0).getSizeInBits();
1436 unsigned NVTBits = NVT.getSizeInBits();
1437 EVT ShTy = N->getOperand(1).getValueType();
1439 if (N->getOpcode() == ISD::SHL) {
1440 if (Amt.ugt(VTBits)) {
1441 Lo = Hi = DAG.getConstant(0, DL, NVT);
1442 } else if (Amt.ugt(NVTBits)) {
1443 Lo = DAG.getConstant(0, DL, NVT);
1444 Hi = DAG.getNode(ISD::SHL, DL,
1445 NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy));
1446 } else if (Amt == NVTBits) {
1447 Lo = DAG.getConstant(0, DL, NVT);
1449 } else if (Amt == 1 &&
1450 TLI.isOperationLegalOrCustom(ISD::ADDC,
1451 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1452 // Emit this X << 1 as X+X.
1453 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1454 SDValue LoOps[2] = { InL, InL };
1455 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps);
1456 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1457 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps);
1459 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy));
1460 Hi = DAG.getNode(ISD::OR, DL, NVT,
1461 DAG.getNode(ISD::SHL, DL, NVT, InH,
1462 DAG.getConstant(Amt, DL, ShTy)),
1463 DAG.getNode(ISD::SRL, DL, NVT, InL,
1464 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1469 if (N->getOpcode() == ISD::SRL) {
1470 if (Amt.ugt(VTBits)) {
1471 Lo = Hi = DAG.getConstant(0, DL, NVT);
1472 } else if (Amt.ugt(NVTBits)) {
1473 Lo = DAG.getNode(ISD::SRL, DL,
1474 NVT, InH, DAG.getConstant(Amt - NVTBits, DL, ShTy));
1475 Hi = DAG.getConstant(0, DL, NVT);
1476 } else if (Amt == NVTBits) {
1478 Hi = DAG.getConstant(0, DL, NVT);
1480 Lo = DAG.getNode(ISD::OR, DL, NVT,
1481 DAG.getNode(ISD::SRL, DL, NVT, InL,
1482 DAG.getConstant(Amt, DL, ShTy)),
1483 DAG.getNode(ISD::SHL, DL, NVT, InH,
1484 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1485 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
1490 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1491 if (Amt.ugt(VTBits)) {
1492 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1493 DAG.getConstant(NVTBits - 1, DL, ShTy));
1494 } else if (Amt.ugt(NVTBits)) {
1495 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1496 DAG.getConstant(Amt - NVTBits, DL, ShTy));
1497 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1498 DAG.getConstant(NVTBits - 1, DL, ShTy));
1499 } else if (Amt == NVTBits) {
1501 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1502 DAG.getConstant(NVTBits - 1, DL, ShTy));
1504 Lo = DAG.getNode(ISD::OR, DL, NVT,
1505 DAG.getNode(ISD::SRL, DL, NVT, InL,
1506 DAG.getConstant(Amt, DL, ShTy)),
1507 DAG.getNode(ISD::SHL, DL, NVT, InH,
1508 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1509 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
1513 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1514 /// this shift based on knowledge of the high bit of the shift amount. If we
1515 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1517 bool DAGTypeLegalizer::
1518 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1519 SDValue Amt = N->getOperand(1);
1520 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1521 EVT ShTy = Amt.getValueType();
1522 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1523 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1524 assert(isPowerOf2_32(NVTBits) &&
1525 "Expanded integer type size not a power of two!");
1528 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1529 APInt KnownZero, KnownOne;
1530 DAG.computeKnownBits(N->getOperand(1), KnownZero, KnownOne);
1532 // If we don't know anything about the high bits, exit.
1533 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1536 // Get the incoming operand to be shifted.
1538 GetExpandedInteger(N->getOperand(0), InL, InH);
1540 // If we know that any of the high bits of the shift amount are one, then we
1541 // can do this as a couple of simple shifts.
1542 if (KnownOne.intersects(HighBitMask)) {
1543 // Mask out the high bit, which we know is set.
1544 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1545 DAG.getConstant(~HighBitMask, dl, ShTy));
1547 switch (N->getOpcode()) {
1548 default: llvm_unreachable("Unknown shift");
1550 Lo = DAG.getConstant(0, dl, NVT); // Low part is zero.
1551 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1554 Hi = DAG.getConstant(0, dl, NVT); // Hi part is zero.
1555 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1558 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1559 DAG.getConstant(NVTBits - 1, dl, ShTy));
1560 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1565 // If we know that all of the high bits of the shift amount are zero, then we
1566 // can do this as a couple of simple shifts.
1567 if ((KnownZero & HighBitMask) == HighBitMask) {
1568 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
1569 // shift if x is zero. We can use XOR here because x is known to be smaller
1571 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
1572 DAG.getConstant(NVTBits - 1, dl, ShTy));
1575 switch (N->getOpcode()) {
1576 default: llvm_unreachable("Unknown shift");
1577 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1579 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1582 // When shifting right the arithmetic for Lo and Hi is swapped.
1583 if (N->getOpcode() != ISD::SHL)
1584 std::swap(InL, InH);
1586 // Use a little trick to get the bits that move from Lo to Hi. First
1587 // shift by one bit.
1588 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, dl, ShTy));
1589 // Then compute the remaining shift with amount-1.
1590 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
1592 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
1593 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
1595 if (N->getOpcode() != ISD::SHL)
1603 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1605 bool DAGTypeLegalizer::
1606 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1607 SDValue Amt = N->getOperand(1);
1608 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1609 EVT ShTy = Amt.getValueType();
1610 unsigned NVTBits = NVT.getSizeInBits();
1611 assert(isPowerOf2_32(NVTBits) &&
1612 "Expanded integer type size not a power of two!");
1615 // Get the incoming operand to be shifted.
1617 GetExpandedInteger(N->getOperand(0), InL, InH);
1619 SDValue NVBitsNode = DAG.getConstant(NVTBits, dl, ShTy);
1620 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1621 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1622 SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1623 Amt, NVBitsNode, ISD::SETULT);
1624 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1625 Amt, DAG.getConstant(0, dl, ShTy),
1628 SDValue LoS, HiS, LoL, HiL;
1629 switch (N->getOpcode()) {
1630 default: llvm_unreachable("Unknown shift");
1632 // Short: ShAmt < NVTBits
1633 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1634 HiS = DAG.getNode(ISD::OR, dl, NVT,
1635 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1636 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1638 // Long: ShAmt >= NVTBits
1639 LoL = DAG.getConstant(0, dl, NVT); // Lo part is zero.
1640 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1642 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1643 Hi = DAG.getSelect(dl, NVT, isZero, InH,
1644 DAG.getSelect(dl, NVT, isShort, HiS, HiL));
1647 // Short: ShAmt < NVTBits
1648 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1649 LoS = DAG.getNode(ISD::OR, dl, NVT,
1650 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1651 // FIXME: If Amt is zero, the following shift generates an undefined result
1652 // on some architectures.
1653 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1655 // Long: ShAmt >= NVTBits
1656 HiL = DAG.getConstant(0, dl, NVT); // Hi part is zero.
1657 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1659 Lo = DAG.getSelect(dl, NVT, isZero, InL,
1660 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
1661 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1664 // Short: ShAmt < NVTBits
1665 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1666 LoS = DAG.getNode(ISD::OR, dl, NVT,
1667 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1668 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1670 // Long: ShAmt >= NVTBits
1671 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1672 DAG.getConstant(NVTBits - 1, dl, ShTy));
1673 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1675 Lo = DAG.getSelect(dl, NVT, isZero, InL,
1676 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
1677 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1682 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1683 SDValue &Lo, SDValue &Hi) {
1685 // Expand the subcomponents.
1686 SDValue LHSL, LHSH, RHSL, RHSH;
1687 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1688 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1690 EVT NVT = LHSL.getValueType();
1691 SDValue LoOps[2] = { LHSL, RHSL };
1692 SDValue HiOps[3] = { LHSH, RHSH };
1694 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1695 // them. TODO: Teach operation legalization how to expand unsupported
1696 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1697 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1698 // generate a value of this type in the expanded code sequence.
1700 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1701 ISD::ADDC : ISD::SUBC,
1702 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1705 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1706 if (N->getOpcode() == ISD::ADD) {
1707 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1708 HiOps[2] = Lo.getValue(1);
1709 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1711 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1712 HiOps[2] = Lo.getValue(1);
1713 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1719 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1720 ISD::UADDO : ISD::USUBO,
1721 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1723 SDVTList VTList = DAG.getVTList(NVT, NVT);
1724 TargetLoweringBase::BooleanContent BoolType = TLI.getBooleanContents(NVT);
1726 if (N->getOpcode() == ISD::ADD) {
1728 Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
1729 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
1732 Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
1733 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
1735 SDValue OVF = Lo.getValue(1);
1738 case TargetLoweringBase::UndefinedBooleanContent:
1739 OVF = DAG.getNode(ISD::AND, dl, NVT, DAG.getConstant(1, dl, NVT), OVF);
1741 case TargetLoweringBase::ZeroOrOneBooleanContent:
1742 Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF);
1744 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
1745 Hi = DAG.getNode(RevOpc, dl, NVT, Hi, OVF);
1750 if (N->getOpcode() == ISD::ADD) {
1751 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
1752 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
1753 SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
1755 SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
1756 DAG.getConstant(1, dl, NVT),
1757 DAG.getConstant(0, dl, NVT));
1758 SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
1760 SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
1761 DAG.getConstant(1, dl, NVT), Carry1);
1762 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1764 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
1765 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
1767 DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
1768 LoOps[0], LoOps[1], ISD::SETULT);
1769 SDValue Borrow = DAG.getSelect(dl, NVT, Cmp,
1770 DAG.getConstant(1, dl, NVT),
1771 DAG.getConstant(0, dl, NVT));
1772 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1776 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1777 SDValue &Lo, SDValue &Hi) {
1778 // Expand the subcomponents.
1779 SDValue LHSL, LHSH, RHSL, RHSH;
1781 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1782 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1783 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1784 SDValue LoOps[2] = { LHSL, RHSL };
1785 SDValue HiOps[3] = { LHSH, RHSH };
1787 if (N->getOpcode() == ISD::ADDC) {
1788 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1789 HiOps[2] = Lo.getValue(1);
1790 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1792 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1793 HiOps[2] = Lo.getValue(1);
1794 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1797 // Legalized the flag result - switch anything that used the old flag to
1799 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1802 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1803 SDValue &Lo, SDValue &Hi) {
1804 // Expand the subcomponents.
1805 SDValue LHSL, LHSH, RHSL, RHSH;
1807 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1808 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1809 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1810 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1811 SDValue HiOps[3] = { LHSH, RHSH };
1813 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
1814 HiOps[2] = Lo.getValue(1);
1815 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
1817 // Legalized the flag result - switch anything that used the old flag to
1819 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1822 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1823 SDValue &Lo, SDValue &Hi) {
1824 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1826 SDValue Op = N->getOperand(0);
1827 if (Op.getValueType().bitsLE(NVT)) {
1828 // The low part is any extension of the input (which degenerates to a copy).
1829 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1830 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1832 // For example, extension of an i48 to an i64. The operand type necessarily
1833 // promotes to the result type, so will end up being expanded too.
1834 assert(getTypeAction(Op.getValueType()) ==
1835 TargetLowering::TypePromoteInteger &&
1836 "Only know how to promote this result!");
1837 SDValue Res = GetPromotedInteger(Op);
1838 assert(Res.getValueType() == N->getValueType(0) &&
1839 "Operand over promoted?");
1840 // Split the promoted operand. This will simplify when it is expanded.
1841 SplitInteger(Res, Lo, Hi);
1845 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1846 SDValue &Lo, SDValue &Hi) {
1848 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1849 EVT NVT = Lo.getValueType();
1850 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1851 unsigned NVTBits = NVT.getSizeInBits();
1852 unsigned EVTBits = EVT.getSizeInBits();
1854 if (NVTBits < EVTBits) {
1855 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1856 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1857 EVTBits - NVTBits)));
1859 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1860 // The high part replicates the sign bit of Lo, make it explicit.
1861 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1862 DAG.getConstant(NVTBits - 1, dl,
1863 TLI.getPointerTy(DAG.getDataLayout())));
1867 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1868 SDValue &Lo, SDValue &Hi) {
1870 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1871 EVT NVT = Lo.getValueType();
1872 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1873 unsigned NVTBits = NVT.getSizeInBits();
1874 unsigned EVTBits = EVT.getSizeInBits();
1876 if (NVTBits < EVTBits) {
1877 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1878 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1879 EVTBits - NVTBits)));
1881 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1882 // The high part must be zero, make it explicit.
1883 Hi = DAG.getConstant(0, dl, NVT);
1887 void DAGTypeLegalizer::ExpandIntRes_BITREVERSE(SDNode *N,
1888 SDValue &Lo, SDValue &Hi) {
1890 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1891 Lo = DAG.getNode(ISD::BITREVERSE, dl, Lo.getValueType(), Lo);
1892 Hi = DAG.getNode(ISD::BITREVERSE, dl, Hi.getValueType(), Hi);
1895 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1896 SDValue &Lo, SDValue &Hi) {
1898 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1899 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1900 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1903 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1904 SDValue &Lo, SDValue &Hi) {
1905 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1906 unsigned NBitWidth = NVT.getSizeInBits();
1907 auto Constant = cast<ConstantSDNode>(N);
1908 const APInt &Cst = Constant->getAPIntValue();
1909 bool IsTarget = Constant->isTargetOpcode();
1910 bool IsOpaque = Constant->isOpaque();
1912 Lo = DAG.getConstant(Cst.trunc(NBitWidth), dl, NVT, IsTarget, IsOpaque);
1913 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), dl, NVT, IsTarget,
1917 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1918 SDValue &Lo, SDValue &Hi) {
1920 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1921 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1922 EVT NVT = Lo.getValueType();
1924 SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
1925 DAG.getConstant(0, dl, NVT), ISD::SETNE);
1927 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
1928 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
1930 Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
1931 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1932 DAG.getConstant(NVT.getSizeInBits(), dl,
1934 Hi = DAG.getConstant(0, dl, NVT);
1937 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1938 SDValue &Lo, SDValue &Hi) {
1940 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1941 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1942 EVT NVT = Lo.getValueType();
1943 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1944 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1945 Hi = DAG.getConstant(0, dl, NVT);
1948 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1949 SDValue &Lo, SDValue &Hi) {
1951 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1952 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1953 EVT NVT = Lo.getValueType();
1955 SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
1956 DAG.getConstant(0, dl, NVT), ISD::SETNE);
1958 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
1959 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
1961 Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
1962 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1963 DAG.getConstant(NVT.getSizeInBits(), dl,
1965 Hi = DAG.getConstant(0, dl, NVT);
1968 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1971 EVT VT = N->getValueType(0);
1973 SDValue Op = N->getOperand(0);
1974 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
1975 Op = GetPromotedFloat(Op);
1977 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1978 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1979 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Op, true/*irrelevant*/, dl).first,
1983 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1986 EVT VT = N->getValueType(0);
1988 SDValue Op = N->getOperand(0);
1989 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
1990 Op = GetPromotedFloat(Op);
1992 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1993 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1994 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Op, false/*irrelevant*/, dl).first,
1998 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1999 SDValue &Lo, SDValue &Hi) {
2000 if (ISD::isNormalLoad(N)) {
2001 ExpandRes_NormalLoad(N, Lo, Hi);
2005 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
2007 EVT VT = N->getValueType(0);
2008 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2009 SDValue Ch = N->getChain();
2010 SDValue Ptr = N->getBasePtr();
2011 ISD::LoadExtType ExtType = N->getExtensionType();
2012 unsigned Alignment = N->getAlignment();
2013 bool isVolatile = N->isVolatile();
2014 bool isNonTemporal = N->isNonTemporal();
2015 bool isInvariant = N->isInvariant();
2016 AAMDNodes AAInfo = N->getAAInfo();
2019 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2021 if (N->getMemoryVT().bitsLE(NVT)) {
2022 EVT MemVT = N->getMemoryVT();
2024 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
2025 MemVT, isVolatile, isNonTemporal, isInvariant,
2028 // Remember the chain.
2029 Ch = Lo.getValue(1);
2031 if (ExtType == ISD::SEXTLOAD) {
2032 // The high part is obtained by SRA'ing all but one of the bits of the
2034 unsigned LoSize = Lo.getValueType().getSizeInBits();
2035 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2036 DAG.getConstant(LoSize - 1, dl,
2037 TLI.getPointerTy(DAG.getDataLayout())));
2038 } else if (ExtType == ISD::ZEXTLOAD) {
2039 // The high part is just a zero.
2040 Hi = DAG.getConstant(0, dl, NVT);
2042 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
2043 // The high part is undefined.
2044 Hi = DAG.getUNDEF(NVT);
2046 } else if (DAG.getDataLayout().isLittleEndian()) {
2047 // Little-endian - low bits are at low addresses.
2048 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
2049 isVolatile, isNonTemporal, isInvariant, Alignment,
2052 unsigned ExcessBits =
2053 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2054 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2056 // Increment the pointer to the other half.
2057 unsigned IncrementSize = NVT.getSizeInBits()/8;
2058 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2059 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2060 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
2061 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
2062 isVolatile, isNonTemporal, isInvariant,
2063 MinAlign(Alignment, IncrementSize), AAInfo);
2065 // Build a factor node to remember that this load is independent of the
2067 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2070 // Big-endian - high bits are at low addresses. Favor aligned loads at
2071 // the cost of some bit-fiddling.
2072 EVT MemVT = N->getMemoryVT();
2073 unsigned EBytes = MemVT.getStoreSize();
2074 unsigned IncrementSize = NVT.getSizeInBits()/8;
2075 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2077 // Load both the high bits and maybe some of the low bits.
2078 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
2079 EVT::getIntegerVT(*DAG.getContext(),
2080 MemVT.getSizeInBits() - ExcessBits),
2081 isVolatile, isNonTemporal, isInvariant, Alignment,
2084 // Increment the pointer to the other half.
2085 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2086 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2087 // Load the rest of the low bits.
2088 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
2089 N->getPointerInfo().getWithOffset(IncrementSize),
2090 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2091 isVolatile, isNonTemporal, isInvariant,
2092 MinAlign(Alignment, IncrementSize), AAInfo);
2094 // Build a factor node to remember that this load is independent of the
2096 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2099 if (ExcessBits < NVT.getSizeInBits()) {
2100 // Transfer low bits from the bottom of Hi to the top of Lo.
2102 ISD::OR, dl, NVT, Lo,
2103 DAG.getNode(ISD::SHL, dl, NVT, Hi,
2104 DAG.getConstant(ExcessBits, dl,
2105 TLI.getPointerTy(DAG.getDataLayout()))));
2106 // Move high bits to the right position in Hi.
2107 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT,
2109 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
2110 TLI.getPointerTy(DAG.getDataLayout())));
2114 // Legalize the chain result - switch anything that used the old chain to
2116 ReplaceValueWith(SDValue(N, 1), Ch);
2119 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
2120 SDValue &Lo, SDValue &Hi) {
2122 SDValue LL, LH, RL, RH;
2123 GetExpandedInteger(N->getOperand(0), LL, LH);
2124 GetExpandedInteger(N->getOperand(1), RL, RH);
2125 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
2126 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
2129 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
2130 SDValue &Lo, SDValue &Hi) {
2131 EVT VT = N->getValueType(0);
2132 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2135 SDValue LL, LH, RL, RH;
2136 GetExpandedInteger(N->getOperand(0), LL, LH);
2137 GetExpandedInteger(N->getOperand(1), RL, RH);
2139 if (TLI.expandMUL(N, Lo, Hi, NVT, DAG, LL, LH, RL, RH))
2142 // If nothing else, we can make a libcall.
2143 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2145 LC = RTLIB::MUL_I16;
2146 else if (VT == MVT::i32)
2147 LC = RTLIB::MUL_I32;
2148 else if (VT == MVT::i64)
2149 LC = RTLIB::MUL_I64;
2150 else if (VT == MVT::i128)
2151 LC = RTLIB::MUL_I128;
2152 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
2154 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2155 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, true/*irrelevant*/, dl).first,
2159 void DAGTypeLegalizer::ExpandIntRes_READCYCLECOUNTER(SDNode *N, SDValue &Lo,
2162 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2163 SDVTList VTs = DAG.getVTList(NVT, NVT, MVT::Other);
2164 SDValue R = DAG.getNode(N->getOpcode(), DL, VTs, N->getOperand(0));
2167 ReplaceValueWith(SDValue(N, 1), R.getValue(2));
2170 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
2171 SDValue &Lo, SDValue &Hi) {
2172 SDValue LHS = Node->getOperand(0);
2173 SDValue RHS = Node->getOperand(1);
2176 // Expand the result by simply replacing it with the equivalent
2177 // non-overflow-checking operation.
2178 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2179 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2181 SplitInteger(Sum, Lo, Hi);
2183 // Compute the overflow.
2185 // LHSSign -> LHS >= 0
2186 // RHSSign -> RHS >= 0
2187 // SumSign -> Sum >= 0
2190 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2192 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2194 EVT OType = Node->getValueType(1);
2195 SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
2197 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2198 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2199 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2200 Node->getOpcode() == ISD::SADDO ?
2201 ISD::SETEQ : ISD::SETNE);
2203 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2204 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2206 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2208 // Use the calculated overflow everywhere.
2209 ReplaceValueWith(SDValue(Node, 1), Cmp);
2212 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
2213 SDValue &Lo, SDValue &Hi) {
2214 EVT VT = N->getValueType(0);
2216 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2218 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
2219 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2220 SplitInteger(Res.getValue(0), Lo, Hi);
2224 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2226 LC = RTLIB::SDIV_I16;
2227 else if (VT == MVT::i32)
2228 LC = RTLIB::SDIV_I32;
2229 else if (VT == MVT::i64)
2230 LC = RTLIB::SDIV_I64;
2231 else if (VT == MVT::i128)
2232 LC = RTLIB::SDIV_I128;
2233 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
2235 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, true, dl).first, Lo, Hi);
2238 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
2239 SDValue &Lo, SDValue &Hi) {
2240 EVT VT = N->getValueType(0);
2243 // If we can emit an efficient shift operation, do so now. Check to see if
2244 // the RHS is a constant.
2245 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2246 return ExpandShiftByConstant(N, CN->getAPIntValue(), Lo, Hi);
2248 // If we can determine that the high bit of the shift is zero or one, even if
2249 // the low bits are variable, emit this shift in an optimized form.
2250 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
2253 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
2255 if (N->getOpcode() == ISD::SHL) {
2256 PartsOpc = ISD::SHL_PARTS;
2257 } else if (N->getOpcode() == ISD::SRL) {
2258 PartsOpc = ISD::SRL_PARTS;
2260 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2261 PartsOpc = ISD::SRA_PARTS;
2264 // Next check to see if the target supports this SHL_PARTS operation or if it
2265 // will custom expand it.
2266 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2267 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
2268 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
2269 Action == TargetLowering::Custom) {
2270 // Expand the subcomponents.
2272 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2273 EVT VT = LHSL.getValueType();
2275 // If the shift amount operand is coming from a vector legalization it may
2276 // have an illegal type. Fix that first by casting the operand, otherwise
2277 // the new SHL_PARTS operation would need further legalization.
2278 SDValue ShiftOp = N->getOperand(1);
2279 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2280 assert(ShiftTy.getScalarType().getSizeInBits() >=
2281 Log2_32_Ceil(VT.getScalarType().getSizeInBits()) &&
2282 "ShiftAmountTy is too small to cover the range of this type!");
2283 if (ShiftOp.getValueType() != ShiftTy)
2284 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
2286 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
2287 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops);
2288 Hi = Lo.getValue(1);
2292 // Otherwise, emit a libcall.
2293 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2295 if (N->getOpcode() == ISD::SHL) {
2296 isSigned = false; /*sign irrelevant*/
2298 LC = RTLIB::SHL_I16;
2299 else if (VT == MVT::i32)
2300 LC = RTLIB::SHL_I32;
2301 else if (VT == MVT::i64)
2302 LC = RTLIB::SHL_I64;
2303 else if (VT == MVT::i128)
2304 LC = RTLIB::SHL_I128;
2305 } else if (N->getOpcode() == ISD::SRL) {
2308 LC = RTLIB::SRL_I16;
2309 else if (VT == MVT::i32)
2310 LC = RTLIB::SRL_I32;
2311 else if (VT == MVT::i64)
2312 LC = RTLIB::SRL_I64;
2313 else if (VT == MVT::i128)
2314 LC = RTLIB::SRL_I128;
2316 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2319 LC = RTLIB::SRA_I16;
2320 else if (VT == MVT::i32)
2321 LC = RTLIB::SRA_I32;
2322 else if (VT == MVT::i64)
2323 LC = RTLIB::SRA_I64;
2324 else if (VT == MVT::i128)
2325 LC = RTLIB::SRA_I128;
2328 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2329 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2330 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, isSigned, dl).first, Lo, Hi);
2334 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2335 llvm_unreachable("Unsupported shift!");
2338 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2339 SDValue &Lo, SDValue &Hi) {
2340 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2342 SDValue Op = N->getOperand(0);
2343 if (Op.getValueType().bitsLE(NVT)) {
2344 // The low part is sign extension of the input (degenerates to a copy).
2345 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2346 // The high part is obtained by SRA'ing all but one of the bits of low part.
2347 unsigned LoSize = NVT.getSizeInBits();
2349 ISD::SRA, dl, NVT, Lo,
2350 DAG.getConstant(LoSize - 1, dl, TLI.getPointerTy(DAG.getDataLayout())));
2352 // For example, extension of an i48 to an i64. The operand type necessarily
2353 // promotes to the result type, so will end up being expanded too.
2354 assert(getTypeAction(Op.getValueType()) ==
2355 TargetLowering::TypePromoteInteger &&
2356 "Only know how to promote this result!");
2357 SDValue Res = GetPromotedInteger(Op);
2358 assert(Res.getValueType() == N->getValueType(0) &&
2359 "Operand over promoted?");
2360 // Split the promoted operand. This will simplify when it is expanded.
2361 SplitInteger(Res, Lo, Hi);
2362 unsigned ExcessBits =
2363 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2364 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2365 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2370 void DAGTypeLegalizer::
2371 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2373 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2374 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2376 if (EVT.bitsLE(Lo.getValueType())) {
2377 // sext_inreg the low part if needed.
2378 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2381 // The high part gets the sign extension from the lo-part. This handles
2382 // things like sextinreg V:i64 from i8.
2383 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2384 DAG.getConstant(Hi.getValueType().getSizeInBits() - 1, dl,
2385 TLI.getPointerTy(DAG.getDataLayout())));
2387 // For example, extension of an i48 to an i64. Leave the low part alone,
2388 // sext_inreg the high part.
2389 unsigned ExcessBits =
2390 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2391 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2392 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2397 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2398 SDValue &Lo, SDValue &Hi) {
2399 EVT VT = N->getValueType(0);
2401 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2403 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
2404 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2405 SplitInteger(Res.getValue(1), Lo, Hi);
2409 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2411 LC = RTLIB::SREM_I16;
2412 else if (VT == MVT::i32)
2413 LC = RTLIB::SREM_I32;
2414 else if (VT == MVT::i64)
2415 LC = RTLIB::SREM_I64;
2416 else if (VT == MVT::i128)
2417 LC = RTLIB::SREM_I128;
2418 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2420 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, true, dl).first, Lo, Hi);
2423 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2424 SDValue &Lo, SDValue &Hi) {
2425 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2427 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2428 Hi = DAG.getNode(ISD::SRL, dl, N->getOperand(0).getValueType(),
2430 DAG.getConstant(NVT.getSizeInBits(), dl,
2431 TLI.getPointerTy(DAG.getDataLayout())));
2432 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2435 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2436 SDValue &Lo, SDValue &Hi) {
2437 SDValue LHS = N->getOperand(0);
2438 SDValue RHS = N->getOperand(1);
2441 // Expand the result by simply replacing it with the equivalent
2442 // non-overflow-checking operation.
2443 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2444 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2446 SplitInteger(Sum, Lo, Hi);
2448 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2449 // overflows iff a - b > a.
2450 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2451 N->getOpcode () == ISD::UADDO ?
2452 ISD::SETULT : ISD::SETUGT);
2454 // Use the calculated overflow everywhere.
2455 ReplaceValueWith(SDValue(N, 1), Ofl);
2458 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
2459 SDValue &Lo, SDValue &Hi) {
2460 EVT VT = N->getValueType(0);
2463 // A divide for UMULO should be faster than a function call.
2464 if (N->getOpcode() == ISD::UMULO) {
2465 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
2467 SDValue MUL = DAG.getNode(ISD::MUL, dl, LHS.getValueType(), LHS, RHS);
2468 SplitInteger(MUL, Lo, Hi);
2470 // A divide for UMULO will be faster than a function call. Select to
2471 // make sure we aren't using 0.
2472 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(VT),
2473 RHS, DAG.getConstant(0, dl, VT), ISD::SETEQ);
2474 SDValue NotZero = DAG.getSelect(dl, VT, isZero,
2475 DAG.getConstant(1, dl, VT), RHS);
2476 SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero);
2477 SDValue Overflow = DAG.getSetCC(dl, N->getValueType(1), DIV, LHS,
2479 Overflow = DAG.getSelect(dl, N->getValueType(1), isZero,
2480 DAG.getConstant(0, dl, N->getValueType(1)),
2482 ReplaceValueWith(SDValue(N, 1), Overflow);
2486 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
2487 EVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2488 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
2490 // Replace this with a libcall that will check overflow.
2491 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2493 LC = RTLIB::MULO_I32;
2494 else if (VT == MVT::i64)
2495 LC = RTLIB::MULO_I64;
2496 else if (VT == MVT::i128)
2497 LC = RTLIB::MULO_I128;
2498 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!");
2500 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
2501 // Temporary for the overflow value, default it to zero.
2502 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
2503 DAG.getConstant(0, dl, PtrVT), Temp,
2504 MachinePointerInfo(), false, false, 0);
2506 TargetLowering::ArgListTy Args;
2507 TargetLowering::ArgListEntry Entry;
2508 for (const SDValue &Op : N->op_values()) {
2509 EVT ArgVT = Op.getValueType();
2510 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2513 Entry.isSExt = true;
2514 Entry.isZExt = false;
2515 Args.push_back(Entry);
2518 // Also pass the address of the overflow check.
2520 Entry.Ty = PtrTy->getPointerTo();
2521 Entry.isSExt = true;
2522 Entry.isZExt = false;
2523 Args.push_back(Entry);
2525 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
2527 TargetLowering::CallLoweringInfo CLI(DAG);
2528 CLI.setDebugLoc(dl).setChain(Chain)
2529 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Func, std::move(Args), 0)
2532 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2534 SplitInteger(CallInfo.first, Lo, Hi);
2535 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
2536 MachinePointerInfo(), false, false, false, 0);
2537 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
2538 DAG.getConstant(0, dl, PtrVT),
2540 // Use the overflow from the libcall everywhere.
2541 ReplaceValueWith(SDValue(N, 1), Ofl);
2544 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2545 SDValue &Lo, SDValue &Hi) {
2546 EVT VT = N->getValueType(0);
2548 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2550 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
2551 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2552 SplitInteger(Res.getValue(0), Lo, Hi);
2556 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2558 LC = RTLIB::UDIV_I16;
2559 else if (VT == MVT::i32)
2560 LC = RTLIB::UDIV_I32;
2561 else if (VT == MVT::i64)
2562 LC = RTLIB::UDIV_I64;
2563 else if (VT == MVT::i128)
2564 LC = RTLIB::UDIV_I128;
2565 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2567 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, false, dl).first, Lo, Hi);
2570 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2571 SDValue &Lo, SDValue &Hi) {
2572 EVT VT = N->getValueType(0);
2574 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2576 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
2577 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2578 SplitInteger(Res.getValue(1), Lo, Hi);
2582 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2584 LC = RTLIB::UREM_I16;
2585 else if (VT == MVT::i32)
2586 LC = RTLIB::UREM_I32;
2587 else if (VT == MVT::i64)
2588 LC = RTLIB::UREM_I64;
2589 else if (VT == MVT::i128)
2590 LC = RTLIB::UREM_I128;
2591 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2593 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, false, dl).first, Lo, Hi);
2596 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2597 SDValue &Lo, SDValue &Hi) {
2598 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2600 SDValue Op = N->getOperand(0);
2601 if (Op.getValueType().bitsLE(NVT)) {
2602 // The low part is zero extension of the input (degenerates to a copy).
2603 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2604 Hi = DAG.getConstant(0, dl, NVT); // The high part is just a zero.
2606 // For example, extension of an i48 to an i64. The operand type necessarily
2607 // promotes to the result type, so will end up being expanded too.
2608 assert(getTypeAction(Op.getValueType()) ==
2609 TargetLowering::TypePromoteInteger &&
2610 "Only know how to promote this result!");
2611 SDValue Res = GetPromotedInteger(Op);
2612 assert(Res.getValueType() == N->getValueType(0) &&
2613 "Operand over promoted?");
2614 // Split the promoted operand. This will simplify when it is expanded.
2615 SplitInteger(Res, Lo, Hi);
2616 unsigned ExcessBits =
2617 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2618 Hi = DAG.getZeroExtendInReg(Hi, dl,
2619 EVT::getIntegerVT(*DAG.getContext(),
2624 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
2625 SDValue &Lo, SDValue &Hi) {
2627 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
2628 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
2629 SDValue Zero = DAG.getConstant(0, dl, VT);
2630 SDValue Swap = DAG.getAtomicCmpSwap(
2631 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
2632 cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->getOperand(0),
2633 N->getOperand(1), Zero, Zero, cast<AtomicSDNode>(N)->getMemOperand(),
2634 cast<AtomicSDNode>(N)->getOrdering(),
2635 cast<AtomicSDNode>(N)->getOrdering(),
2636 cast<AtomicSDNode>(N)->getSynchScope());
2638 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
2639 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
2642 //===----------------------------------------------------------------------===//
2643 // Integer Operand Expansion
2644 //===----------------------------------------------------------------------===//
2646 /// ExpandIntegerOperand - This method is called when the specified operand of
2647 /// the specified node is found to need expansion. At this point, all of the
2648 /// result types of the node are known to be legal, but other operands of the
2649 /// node may need promotion or expansion as well as the specified one.
2650 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2651 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2652 SDValue Res = SDValue();
2654 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2657 switch (N->getOpcode()) {
2660 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2661 N->dump(&DAG); dbgs() << "\n";
2663 llvm_unreachable("Do not know how to expand this operator's operand!");
2665 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2666 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2667 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2668 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2669 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2670 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2671 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2672 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2673 case ISD::SETCCE: Res = ExpandIntOp_SETCCE(N); break;
2674 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2675 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2676 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2677 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2683 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2684 case ISD::RETURNADDR:
2685 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2687 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
2690 // If the result is null, the sub-method took care of registering results etc.
2691 if (!Res.getNode()) return false;
2693 // If the result is N, the sub-method updated N in place. Tell the legalizer
2695 if (Res.getNode() == N)
2698 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2699 "Invalid operand expansion");
2701 ReplaceValueWith(SDValue(N, 0), Res);
2705 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2706 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2707 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2709 ISD::CondCode &CCCode,
2711 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2712 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2713 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2715 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2716 if (RHSLo == RHSHi) {
2717 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2718 if (RHSCST->isAllOnesValue()) {
2719 // Equality comparison to -1.
2720 NewLHS = DAG.getNode(ISD::AND, dl,
2721 LHSLo.getValueType(), LHSLo, LHSHi);
2728 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2729 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2730 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2731 NewRHS = DAG.getConstant(0, dl, NewLHS.getValueType());
2735 // If this is a comparison of the sign bit, just look at the top part.
2737 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2738 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2739 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2745 // FIXME: This generated code sucks.
2746 ISD::CondCode LowCC;
2748 default: llvm_unreachable("Unknown integer setcc!");
2750 case ISD::SETULT: LowCC = ISD::SETULT; break;
2752 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2754 case ISD::SETULE: LowCC = ISD::SETULE; break;
2756 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2759 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2760 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2761 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2763 // NOTE: on targets without efficient SELECT of bools, we can always use
2764 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2765 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
2768 if (TLI.isTypeLegal(LHSLo.getValueType()) &&
2769 TLI.isTypeLegal(RHSLo.getValueType()))
2770 Tmp1 = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()),
2771 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2772 if (!Tmp1.getNode())
2773 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()),
2774 LHSLo, RHSLo, LowCC);
2775 if (TLI.isTypeLegal(LHSHi.getValueType()) &&
2776 TLI.isTypeLegal(RHSHi.getValueType()))
2777 Tmp2 = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2778 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2779 if (!Tmp2.getNode())
2780 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2781 getSetCCResultType(LHSHi.getValueType()),
2782 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2784 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2785 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2786 if ((Tmp1C && Tmp1C->isNullValue()) ||
2787 (Tmp2C && Tmp2C->isNullValue() &&
2788 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2789 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2790 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2791 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2792 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2793 // low part is known false, returns high part.
2794 // For LE / GE, if high part is known false, ignore the low part.
2795 // For LT / GT, if high part is known true, ignore the low part.
2801 if (LHSHi == RHSHi) {
2802 // Comparing the low bits is enough.
2808 // Lower with SETCCE if the target supports it.
2809 // FIXME: Make all targets support this, then remove the other lowering.
2810 if (TLI.getOperationAction(
2812 TLI.getTypeToExpandTo(*DAG.getContext(), LHSLo.getValueType())) ==
2813 TargetLowering::Custom) {
2814 // SETCCE can detect < and >= directly. For > and <=, flip operands and
2816 bool FlipOperands = false;
2818 case ISD::SETGT: CCCode = ISD::SETLT; FlipOperands = true; break;
2819 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break;
2820 case ISD::SETLE: CCCode = ISD::SETGE; FlipOperands = true; break;
2821 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break;
2825 std::swap(LHSLo, RHSLo);
2826 std::swap(LHSHi, RHSHi);
2828 // Perform a wide subtraction, feeding the carry from the low part into
2829 // SETCCE. The SETCCE operation is essentially looking at the high part of
2830 // the result of LHS - RHS. It is negative iff LHS < RHS. It is zero or
2831 // positive iff LHS >= RHS.
2832 SDVTList VTList = DAG.getVTList(LHSLo.getValueType(), MVT::Glue);
2833 SDValue LowCmp = DAG.getNode(ISD::SUBC, dl, VTList, LHSLo, RHSLo);
2835 DAG.getNode(ISD::SETCCE, dl, getSetCCResultType(LHSLo.getValueType()),
2836 LHSHi, RHSHi, LowCmp.getValue(1), DAG.getCondCode(CCCode));
2842 NewLHS = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2843 LHSHi, RHSHi, ISD::SETEQ, false,
2844 DagCombineInfo, dl);
2845 if (!NewLHS.getNode())
2846 NewLHS = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
2847 LHSHi, RHSHi, ISD::SETEQ);
2848 NewLHS = DAG.getSelect(dl, Tmp1.getValueType(),
2849 NewLHS, Tmp1, Tmp2);
2853 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2854 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2855 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2856 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2858 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2859 // against zero to select between true and false values.
2860 if (!NewRHS.getNode()) {
2861 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
2862 CCCode = ISD::SETNE;
2865 // Update N to have the operands specified.
2866 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2867 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2868 N->getOperand(4)), 0);
2871 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2872 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2873 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2874 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2876 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2877 // against zero to select between true and false values.
2878 if (!NewRHS.getNode()) {
2879 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
2880 CCCode = ISD::SETNE;
2883 // Update N to have the operands specified.
2884 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2885 N->getOperand(2), N->getOperand(3),
2886 DAG.getCondCode(CCCode)), 0);
2889 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2890 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2891 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2892 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2894 // If ExpandSetCCOperands returned a scalar, use it.
2895 if (!NewRHS.getNode()) {
2896 assert(NewLHS.getValueType() == N->getValueType(0) &&
2897 "Unexpected setcc expansion!");
2901 // Otherwise, update N to have the operands specified.
2902 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2903 DAG.getCondCode(CCCode)), 0);
2906 SDValue DAGTypeLegalizer::ExpandIntOp_SETCCE(SDNode *N) {
2907 SDValue LHS = N->getOperand(0);
2908 SDValue RHS = N->getOperand(1);
2909 SDValue Carry = N->getOperand(2);
2910 SDValue Cond = N->getOperand(3);
2911 SDLoc dl = SDLoc(N);
2913 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2914 GetExpandedInteger(LHS, LHSLo, LHSHi);
2915 GetExpandedInteger(RHS, RHSLo, RHSHi);
2917 // Expand to a SUBE for the low part and a smaller SETCCE for the high.
2918 SDVTList VTList = DAG.getVTList(LHSLo.getValueType(), MVT::Glue);
2919 SDValue LowCmp = DAG.getNode(ISD::SUBE, dl, VTList, LHSLo, RHSLo, Carry);
2920 return DAG.getNode(ISD::SETCCE, dl, N->getValueType(0), LHSHi, RHSHi,
2921 LowCmp.getValue(1), Cond);
2924 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2925 // The value being shifted is legal, but the shift amount is too big.
2926 // It follows that either the result of the shift is undefined, or the
2927 // upper half of the shift amount is zero. Just use the lower half.
2929 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2930 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2933 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2934 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2935 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2936 // constant to valid type.
2938 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2939 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2942 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2943 SDValue Op = N->getOperand(0);
2944 EVT DstVT = N->getValueType(0);
2945 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2946 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2947 "Don't know how to expand this SINT_TO_FP!");
2948 return TLI.makeLibCall(DAG, LC, DstVT, Op, true, SDLoc(N)).first;
2951 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2952 if (ISD::isNormalStore(N))
2953 return ExpandOp_NormalStore(N, OpNo);
2955 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2956 assert(OpNo == 1 && "Can only expand the stored value so far");
2958 EVT VT = N->getOperand(1).getValueType();
2959 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2960 SDValue Ch = N->getChain();
2961 SDValue Ptr = N->getBasePtr();
2962 unsigned Alignment = N->getAlignment();
2963 bool isVolatile = N->isVolatile();
2964 bool isNonTemporal = N->isNonTemporal();
2965 AAMDNodes AAInfo = N->getAAInfo();
2969 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2971 if (N->getMemoryVT().bitsLE(NVT)) {
2972 GetExpandedInteger(N->getValue(), Lo, Hi);
2973 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2974 N->getMemoryVT(), isVolatile, isNonTemporal,
2978 if (DAG.getDataLayout().isLittleEndian()) {
2979 // Little-endian - low bits are at low addresses.
2980 GetExpandedInteger(N->getValue(), Lo, Hi);
2982 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2983 isVolatile, isNonTemporal, Alignment, AAInfo);
2985 unsigned ExcessBits =
2986 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2987 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2989 // Increment the pointer to the other half.
2990 unsigned IncrementSize = NVT.getSizeInBits()/8;
2991 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2992 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2993 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2994 N->getPointerInfo().getWithOffset(IncrementSize),
2995 NEVT, isVolatile, isNonTemporal,
2996 MinAlign(Alignment, IncrementSize), AAInfo);
2997 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
3000 // Big-endian - high bits are at low addresses. Favor aligned stores at
3001 // the cost of some bit-fiddling.
3002 GetExpandedInteger(N->getValue(), Lo, Hi);
3004 EVT ExtVT = N->getMemoryVT();
3005 unsigned EBytes = ExtVT.getStoreSize();
3006 unsigned IncrementSize = NVT.getSizeInBits()/8;
3007 unsigned ExcessBits = (EBytes - IncrementSize)*8;
3008 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
3009 ExtVT.getSizeInBits() - ExcessBits);
3011 if (ExcessBits < NVT.getSizeInBits()) {
3012 // Transfer high bits from the top of Lo to the bottom of Hi.
3013 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
3014 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
3015 TLI.getPointerTy(DAG.getDataLayout())));
3017 ISD::OR, dl, NVT, Hi,
3018 DAG.getNode(ISD::SRL, dl, NVT, Lo,
3019 DAG.getConstant(ExcessBits, dl,
3020 TLI.getPointerTy(DAG.getDataLayout()))));
3023 // Store both the high bits and maybe some of the low bits.
3024 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
3025 HiVT, isVolatile, isNonTemporal, Alignment, AAInfo);
3027 // Increment the pointer to the other half.
3028 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
3029 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
3030 // Store the lowest ExcessBits bits in the second half.
3031 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
3032 N->getPointerInfo().getWithOffset(IncrementSize),
3033 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
3034 isVolatile, isNonTemporal,
3035 MinAlign(Alignment, IncrementSize), AAInfo);
3036 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
3039 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
3041 GetExpandedInteger(N->getOperand(0), InL, InH);
3042 // Just truncate the low part of the source.
3043 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL);
3046 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
3047 SDValue Op = N->getOperand(0);
3048 EVT SrcVT = Op.getValueType();
3049 EVT DstVT = N->getValueType(0);
3052 // The following optimization is valid only if every value in SrcVT (when
3053 // treated as signed) is representable in DstVT. Check that the mantissa
3054 // size of DstVT is >= than the number of bits in SrcVT -1.
3055 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT);
3056 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 &&
3057 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
3058 // Do a signed conversion then adjust the result.
3059 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
3060 SignedConv = TLI.LowerOperation(SignedConv, DAG);
3062 // The result of the signed conversion needs adjusting if the 'sign bit' of
3063 // the incoming integer was set. To handle this, we dynamically test to see
3064 // if it is set, and, if so, add a fudge factor.
3066 const uint64_t F32TwoE32 = 0x4F800000ULL;
3067 const uint64_t F32TwoE64 = 0x5F800000ULL;
3068 const uint64_t F32TwoE128 = 0x7F800000ULL;
3071 if (SrcVT == MVT::i32)
3072 FF = APInt(32, F32TwoE32);
3073 else if (SrcVT == MVT::i64)
3074 FF = APInt(32, F32TwoE64);
3075 else if (SrcVT == MVT::i128)
3076 FF = APInt(32, F32TwoE128);
3078 llvm_unreachable("Unsupported UINT_TO_FP!");
3080 // Check whether the sign bit is set.
3082 GetExpandedInteger(Op, Lo, Hi);
3083 SDValue SignSet = DAG.getSetCC(dl,
3084 getSetCCResultType(Hi.getValueType()),
3086 DAG.getConstant(0, dl, Hi.getValueType()),
3089 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
3091 DAG.getConstantPool(ConstantInt::get(*DAG.getContext(), FF.zext(64)),
3092 TLI.getPointerTy(DAG.getDataLayout()));
3094 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
3095 SDValue Zero = DAG.getIntPtrConstant(0, dl);
3096 SDValue Four = DAG.getIntPtrConstant(4, dl);
3097 if (DAG.getDataLayout().isBigEndian())
3098 std::swap(Zero, Four);
3099 SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet,
3101 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
3102 FudgePtr = DAG.getNode(ISD::ADD, dl, FudgePtr.getValueType(),
3104 Alignment = std::min(Alignment, 4u);
3106 // Load the value out, extending it from f32 to the destination float type.
3107 // FIXME: Avoid the extend by constructing the right constant pool?
3108 SDValue Fudge = DAG.getExtLoad(
3109 ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), FudgePtr,
3110 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
3111 false, false, false, Alignment);
3112 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
3115 // Otherwise, use a libcall.
3116 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
3117 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
3118 "Don't know how to expand this UINT_TO_FP!");
3119 return TLI.makeLibCall(DAG, LC, DstVT, Op, true, dl).first;
3122 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
3124 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
3125 cast<AtomicSDNode>(N)->getMemoryVT(),
3127 N->getOperand(1), N->getOperand(2),
3128 cast<AtomicSDNode>(N)->getMemOperand(),
3129 cast<AtomicSDNode>(N)->getOrdering(),
3130 cast<AtomicSDNode>(N)->getSynchScope());
3131 return Swap.getValue(1);
3135 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
3136 SDValue InOp0 = N->getOperand(0);
3137 EVT InVT = InOp0.getValueType();
3139 EVT OutVT = N->getValueType(0);
3140 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3141 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3142 unsigned OutNumElems = OutVT.getVectorNumElements();
3143 EVT NOutVTElem = NOutVT.getVectorElementType();
3146 SDValue BaseIdx = N->getOperand(1);
3148 SmallVector<SDValue, 8> Ops;
3149 Ops.reserve(OutNumElems);
3150 for (unsigned i = 0; i != OutNumElems; ++i) {
3152 // Extract the element from the original vector.
3153 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
3154 BaseIdx, DAG.getConstant(i, dl, BaseIdx.getValueType()));
3155 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3156 InVT.getVectorElementType(), N->getOperand(0), Index);
3158 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
3159 // Insert the converted element to the new vector.
3163 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3167 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
3168 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
3169 EVT VT = N->getValueType(0);
3172 ArrayRef<int> NewMask = SV->getMask().slice(0, VT.getVectorNumElements());
3174 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3175 SDValue V1 = GetPromotedInteger(N->getOperand(1));
3176 EVT OutVT = V0.getValueType();
3178 return DAG.getVectorShuffle(OutVT, dl, V0, V1, NewMask);
3182 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
3183 EVT OutVT = N->getValueType(0);
3184 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3185 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3186 unsigned NumElems = N->getNumOperands();
3187 EVT NOutVTElem = NOutVT.getVectorElementType();
3191 SmallVector<SDValue, 8> Ops;
3192 Ops.reserve(NumElems);
3193 for (unsigned i = 0; i != NumElems; ++i) {
3195 // BUILD_VECTOR integer operand types are allowed to be larger than the
3196 // result's element type. This may still be true after the promotion. For
3197 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
3198 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
3199 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
3200 Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
3202 Op = N->getOperand(i);
3206 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3209 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
3213 assert(!N->getOperand(0).getValueType().isVector() &&
3214 "Input must be a scalar");
3216 EVT OutVT = N->getValueType(0);
3217 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3218 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3219 EVT NOutVTElem = NOutVT.getVectorElementType();
3221 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
3223 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
3226 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
3229 EVT OutVT = N->getValueType(0);
3230 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3231 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3233 EVT InElemTy = OutVT.getVectorElementType();
3234 EVT OutElemTy = NOutVT.getVectorElementType();
3236 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
3237 unsigned NumOutElem = NOutVT.getVectorNumElements();
3238 unsigned NumOperands = N->getNumOperands();
3239 assert(NumElem * NumOperands == NumOutElem &&
3240 "Unexpected number of elements");
3242 // Take the elements from the first vector.
3243 SmallVector<SDValue, 8> Ops(NumOutElem);
3244 for (unsigned i = 0; i < NumOperands; ++i) {
3245 SDValue Op = N->getOperand(i);
3246 for (unsigned j = 0; j < NumElem; ++j) {
3247 SDValue Ext = DAG.getNode(
3248 ISD::EXTRACT_VECTOR_ELT, dl, InElemTy, Op,
3249 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3250 Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
3254 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3257 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
3258 EVT OutVT = N->getValueType(0);
3259 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3260 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3262 EVT NOutVTElem = NOutVT.getVectorElementType();
3265 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3267 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
3268 NOutVTElem, N->getOperand(1));
3269 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
3270 V0, ConvElem, N->getOperand(2));
3273 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3275 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3276 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl,
3277 TLI.getVectorIdxTy(DAG.getDataLayout()));
3278 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3279 V0->getValueType(0).getScalarType(), V0, V1);
3281 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
3282 // element types. If this is the case then we need to expand the outgoing
3283 // value and not truncate it.
3284 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
3287 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N) {
3289 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3290 MVT InVT = V0.getValueType().getSimpleVT();
3291 MVT OutVT = MVT::getVectorVT(InVT.getVectorElementType(),
3292 N->getValueType(0).getVectorNumElements());
3293 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1));
3294 return DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), Ext);
3297 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
3299 unsigned NumElems = N->getNumOperands();
3301 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
3303 SmallVector<SDValue, 8> NewOps;
3304 NewOps.reserve(NumElems);
3306 // For each incoming vector
3307 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
3308 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
3309 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
3310 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
3312 for (unsigned i=0; i<NumElem; ++i) {
3313 // Extract element from incoming vector
3314 SDValue Ex = DAG.getNode(
3315 ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Incoming,
3316 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3317 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
3318 NewOps.push_back(Tr);
3322 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0), NewOps);