1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "legalize-types"
31 //===----------------------------------------------------------------------===//
32 // Result Vector Scalarization: <1 x ty> -> ty.
33 //===----------------------------------------------------------------------===//
35 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
39 SDValue R = SDValue();
41 switch (N->getOpcode()) {
44 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
48 report_fatal_error("Do not know how to scalarize the result of this "
51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
54 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
57 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
58 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
60 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
61 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
62 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
64 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
65 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
66 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
67 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
68 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
73 case ISD::CTLZ_ZERO_UNDEF:
76 case ISD::CTTZ_ZERO_UNDEF:
96 case ISD::SIGN_EXTEND:
100 case ISD::ZERO_EXTEND:
101 R = ScalarizeVecRes_UnaryOp(N);
133 R = ScalarizeVecRes_BinOp(N);
136 R = ScalarizeVecRes_TernaryOp(N);
140 // If R is null, the sub-method took care of registering the result.
142 SetScalarizedVector(SDValue(N, ResNo), R);
145 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
146 SDValue LHS = GetScalarizedVector(N->getOperand(0));
147 SDValue RHS = GetScalarizedVector(N->getOperand(1));
148 return DAG.getNode(N->getOpcode(), SDLoc(N),
149 LHS.getValueType(), LHS, RHS, N->getFlags());
152 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
153 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
154 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
155 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
156 return DAG.getNode(N->getOpcode(), SDLoc(N),
157 Op0.getValueType(), Op0, Op1, Op2);
160 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
162 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
163 return GetScalarizedVector(Op);
166 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
167 EVT NewVT = N->getValueType(0).getVectorElementType();
168 return DAG.getNode(ISD::BITCAST, SDLoc(N),
169 NewVT, N->getOperand(0));
172 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
173 EVT EltVT = N->getValueType(0).getVectorElementType();
174 SDValue InOp = N->getOperand(0);
175 // The BUILD_VECTOR operands may be of wider element types and
176 // we may need to truncate them back to the requested return type.
177 if (EltVT.isInteger())
178 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
182 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
183 EVT NewVT = N->getValueType(0).getVectorElementType();
184 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
185 return DAG.getConvertRndSat(NewVT, SDLoc(N),
186 Op0, DAG.getValueType(NewVT),
187 DAG.getValueType(Op0.getValueType()),
190 cast<CvtRndSatSDNode>(N)->getCvtCode());
193 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
194 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
195 N->getValueType(0).getVectorElementType(),
196 N->getOperand(0), N->getOperand(1));
199 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
200 EVT NewVT = N->getValueType(0).getVectorElementType();
201 SDValue Op = GetScalarizedVector(N->getOperand(0));
202 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
203 NewVT, Op, N->getOperand(1));
206 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
207 SDValue Op = GetScalarizedVector(N->getOperand(0));
208 return DAG.getNode(ISD::FPOWI, SDLoc(N),
209 Op.getValueType(), Op, N->getOperand(1));
212 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
213 // The value to insert may have a wider type than the vector element type,
214 // so be sure to truncate it to the element type if necessary.
215 SDValue Op = N->getOperand(1);
216 EVT EltVT = N->getValueType(0).getVectorElementType();
217 if (Op.getValueType() != EltVT)
218 // FIXME: Can this happen for floating point types?
219 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
223 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
224 assert(N->isUnindexed() && "Indexed vector load?");
226 SDValue Result = DAG.getLoad(
227 ISD::UNINDEXED, N->getExtensionType(),
228 N->getValueType(0).getVectorElementType(), SDLoc(N), N->getChain(),
229 N->getBasePtr(), DAG.getUNDEF(N->getBasePtr().getValueType()),
230 N->getPointerInfo(), N->getMemoryVT().getVectorElementType(),
231 N->getOriginalAlignment(), N->getMemOperand()->getFlags(),
234 // Legalize the chain result - switch anything that used the old chain to
236 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
240 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
241 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
242 EVT DestVT = N->getValueType(0).getVectorElementType();
243 SDValue Op = N->getOperand(0);
244 EVT OpVT = Op.getValueType();
246 // The result needs scalarizing, but it's not a given that the source does.
247 // This is a workaround for targets where it's impossible to scalarize the
248 // result of a conversion, because the source type is legal.
249 // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
250 // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
251 // legal and was not scalarized.
252 // See the similar logic in ScalarizeVecRes_VSETCC
253 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
254 Op = GetScalarizedVector(Op);
256 EVT VT = OpVT.getVectorElementType();
258 ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
259 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
261 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
264 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
265 EVT EltVT = N->getValueType(0).getVectorElementType();
266 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
267 SDValue LHS = GetScalarizedVector(N->getOperand(0));
268 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
269 LHS, DAG.getValueType(ExtVT));
272 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
273 // If the operand is wider than the vector element type then it is implicitly
274 // truncated. Make that explicit here.
275 EVT EltVT = N->getValueType(0).getVectorElementType();
276 SDValue InOp = N->getOperand(0);
277 if (InOp.getValueType() != EltVT)
278 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
282 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
283 SDValue Cond = GetScalarizedVector(N->getOperand(0));
284 SDValue LHS = GetScalarizedVector(N->getOperand(1));
285 TargetLowering::BooleanContent ScalarBool =
286 TLI.getBooleanContents(false, false);
287 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
289 // If integer and float booleans have different contents then we can't
290 // reliably optimize in all cases. There is a full explanation for this in
291 // DAGCombiner::visitSELECT() where the same issue affects folding
292 // (select C, 0, 1) to (xor C, 1).
293 if (TLI.getBooleanContents(false, false) !=
294 TLI.getBooleanContents(false, true)) {
295 // At least try the common case where the boolean is generated by a
297 if (Cond->getOpcode() == ISD::SETCC) {
298 EVT OpVT = Cond->getOperand(0)->getValueType(0);
299 ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
300 VecBool = TLI.getBooleanContents(OpVT);
302 ScalarBool = TargetLowering::UndefinedBooleanContent;
305 if (ScalarBool != VecBool) {
306 EVT CondVT = Cond.getValueType();
307 switch (ScalarBool) {
308 case TargetLowering::UndefinedBooleanContent:
310 case TargetLowering::ZeroOrOneBooleanContent:
311 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
312 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
313 // Vector read from all ones, scalar expects a single 1 so mask.
314 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
315 Cond, DAG.getConstant(1, SDLoc(N), CondVT));
317 case TargetLowering::ZeroOrNegativeOneBooleanContent:
318 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
319 VecBool == TargetLowering::ZeroOrOneBooleanContent);
320 // Vector reads from a one, scalar from all ones so sign extend.
321 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
322 Cond, DAG.getValueType(MVT::i1));
327 return DAG.getSelect(SDLoc(N),
328 LHS.getValueType(), Cond, LHS,
329 GetScalarizedVector(N->getOperand(2)));
332 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
333 SDValue LHS = GetScalarizedVector(N->getOperand(1));
334 return DAG.getSelect(SDLoc(N),
335 LHS.getValueType(), N->getOperand(0), LHS,
336 GetScalarizedVector(N->getOperand(2)));
339 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
340 SDValue LHS = GetScalarizedVector(N->getOperand(2));
341 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
342 N->getOperand(0), N->getOperand(1),
343 LHS, GetScalarizedVector(N->getOperand(3)),
347 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
348 assert(N->getValueType(0).isVector() ==
349 N->getOperand(0).getValueType().isVector() &&
350 "Scalar/Vector type mismatch");
352 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
354 SDValue LHS = GetScalarizedVector(N->getOperand(0));
355 SDValue RHS = GetScalarizedVector(N->getOperand(1));
358 // Turn it into a scalar SETCC.
359 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
362 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
363 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
366 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
367 // Figure out if the scalar is the LHS or RHS and return it.
368 SDValue Arg = N->getOperand(2).getOperand(0);
370 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
371 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
372 return GetScalarizedVector(N->getOperand(Op));
375 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
376 assert(N->getValueType(0).isVector() &&
377 N->getOperand(0).getValueType().isVector() &&
378 "Operand types must be vectors");
379 SDValue LHS = N->getOperand(0);
380 SDValue RHS = N->getOperand(1);
381 EVT OpVT = LHS.getValueType();
382 EVT NVT = N->getValueType(0).getVectorElementType();
385 // The result needs scalarizing, but it's not a given that the source does.
386 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
387 LHS = GetScalarizedVector(LHS);
388 RHS = GetScalarizedVector(RHS);
390 EVT VT = OpVT.getVectorElementType();
392 ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
393 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
395 ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
396 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
399 // Turn it into a scalar SETCC.
400 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
402 // Vectors may have a different boolean contents to scalars. Promote the
403 // value appropriately.
404 ISD::NodeType ExtendCode =
405 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
406 return DAG.getNode(ExtendCode, DL, NVT, Res);
410 //===----------------------------------------------------------------------===//
411 // Operand Vector Scalarization <1 x ty> -> ty.
412 //===----------------------------------------------------------------------===//
414 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
415 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
418 SDValue Res = SDValue();
420 if (!Res.getNode()) {
421 switch (N->getOpcode()) {
424 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
428 llvm_unreachable("Do not know how to scalarize this operator's operand!");
430 Res = ScalarizeVecOp_BITCAST(N);
432 case ISD::ANY_EXTEND:
433 case ISD::ZERO_EXTEND:
434 case ISD::SIGN_EXTEND:
436 case ISD::FP_TO_SINT:
437 case ISD::FP_TO_UINT:
438 case ISD::SINT_TO_FP:
439 case ISD::UINT_TO_FP:
440 Res = ScalarizeVecOp_UnaryOp(N);
442 case ISD::CONCAT_VECTORS:
443 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
445 case ISD::EXTRACT_VECTOR_ELT:
446 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
449 Res = ScalarizeVecOp_VSELECT(N);
452 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
455 Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
460 // If the result is null, the sub-method took care of registering results etc.
461 if (!Res.getNode()) return false;
463 // If the result is N, the sub-method updated N in place. Tell the legalizer
465 if (Res.getNode() == N)
468 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
469 "Invalid operand expansion");
471 ReplaceValueWith(SDValue(N, 0), Res);
475 /// If the value to convert is a vector that needs to be scalarized, it must be
476 /// <1 x ty>. Convert the element instead.
477 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
478 SDValue Elt = GetScalarizedVector(N->getOperand(0));
479 return DAG.getNode(ISD::BITCAST, SDLoc(N),
480 N->getValueType(0), Elt);
483 /// If the input is a vector that needs to be scalarized, it must be <1 x ty>.
484 /// Do the operation on the element instead.
485 SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
486 assert(N->getValueType(0).getVectorNumElements() == 1 &&
487 "Unexpected vector type!");
488 SDValue Elt = GetScalarizedVector(N->getOperand(0));
489 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
490 N->getValueType(0).getScalarType(), Elt);
491 // Revectorize the result so the types line up with what the uses of this
492 // expression expect.
493 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op);
496 /// The vectors to concatenate have length one - use a BUILD_VECTOR instead.
497 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
498 SmallVector<SDValue, 8> Ops(N->getNumOperands());
499 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
500 Ops[i] = GetScalarizedVector(N->getOperand(i));
501 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Ops);
504 /// If the input is a vector that needs to be scalarized, it must be <1 x ty>,
505 /// so just return the element, ignoring the index.
506 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
507 SDValue Res = GetScalarizedVector(N->getOperand(0));
508 if (Res.getValueType() != N->getValueType(0))
509 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0),
515 /// If the input condition is a vector that needs to be scalarized, it must be
516 /// <1 x i1>, so just convert to a normal ISD::SELECT
517 /// (still with vector output type since that was acceptable if we got here).
518 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {
519 SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));
520 EVT VT = N->getValueType(0);
522 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
526 /// If the value to store is a vector that needs to be scalarized, it must be
527 /// <1 x ty>. Just store the element.
528 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
529 assert(N->isUnindexed() && "Indexed store of one-element vector?");
530 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
533 if (N->isTruncatingStore())
534 return DAG.getTruncStore(
535 N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
536 N->getBasePtr(), N->getPointerInfo(),
537 N->getMemoryVT().getVectorElementType(), N->getAlignment(),
538 N->getMemOperand()->getFlags(), N->getAAInfo());
540 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
541 N->getBasePtr(), N->getPointerInfo(),
542 N->getOriginalAlignment(), N->getMemOperand()->getFlags(),
546 /// If the value to round is a vector that needs to be scalarized, it must be
547 /// <1 x ty>. Convert the element instead.
548 SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
549 SDValue Elt = GetScalarizedVector(N->getOperand(0));
550 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
551 N->getValueType(0).getVectorElementType(), Elt,
553 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
556 //===----------------------------------------------------------------------===//
557 // Result Vector Splitting
558 //===----------------------------------------------------------------------===//
560 /// This method is called when the specified result of the specified node is
561 /// found to need vector splitting. At this point, the node may also have
562 /// invalid operands or may have other results that need legalization, we just
563 /// know that (at least) one result needs vector splitting.
564 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
565 DEBUG(dbgs() << "Split node result: ";
570 // See if the target wants to custom expand this node.
571 if (CustomLowerNode(N, N->getValueType(ResNo), true))
574 switch (N->getOpcode()) {
577 dbgs() << "SplitVectorResult #" << ResNo << ": ";
581 report_fatal_error("Do not know how to split the result of this "
584 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
586 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
587 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
588 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
589 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
590 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
591 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
592 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
593 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
594 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
595 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
596 case ISD::FCOPYSIGN: SplitVecRes_FCOPYSIGN(N, Lo, Hi); break;
597 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
598 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
599 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
601 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
604 SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
607 SplitVecRes_MGATHER(cast<MaskedGatherSDNode>(N), Lo, Hi);
610 SplitVecRes_SETCC(N, Lo, Hi);
612 case ISD::VECTOR_SHUFFLE:
613 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
616 case ISD::ANY_EXTEND_VECTOR_INREG:
617 case ISD::SIGN_EXTEND_VECTOR_INREG:
618 case ISD::ZERO_EXTEND_VECTOR_INREG:
619 SplitVecRes_ExtVecInRegOp(N, Lo, Hi);
622 case ISD::BITREVERSE:
624 case ISD::CONVERT_RNDSAT:
627 case ISD::CTLZ_ZERO_UNDEF:
628 case ISD::CTTZ_ZERO_UNDEF:
639 case ISD::FNEARBYINT:
643 case ISD::FP_TO_SINT:
644 case ISD::FP_TO_UINT:
650 case ISD::SINT_TO_FP:
652 case ISD::UINT_TO_FP:
653 SplitVecRes_UnaryOp(N, Lo, Hi);
656 case ISD::ANY_EXTEND:
657 case ISD::SIGN_EXTEND:
658 case ISD::ZERO_EXTEND:
659 SplitVecRes_ExtendOp(N, Lo, Hi);
691 SplitVecRes_BinOp(N, Lo, Hi);
694 SplitVecRes_TernaryOp(N, Lo, Hi);
698 // If Lo/Hi is null, the sub-method took care of registering results etc.
700 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
703 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
705 SDValue LHSLo, LHSHi;
706 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
707 SDValue RHSLo, RHSHi;
708 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
711 const SDNodeFlags *Flags = N->getFlags();
712 unsigned Opcode = N->getOpcode();
713 Lo = DAG.getNode(Opcode, dl, LHSLo.getValueType(), LHSLo, RHSLo, Flags);
714 Hi = DAG.getNode(Opcode, dl, LHSHi.getValueType(), LHSHi, RHSHi, Flags);
717 void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
719 SDValue Op0Lo, Op0Hi;
720 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
721 SDValue Op1Lo, Op1Hi;
722 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
723 SDValue Op2Lo, Op2Hi;
724 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
727 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
728 Op0Lo, Op1Lo, Op2Lo);
729 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
730 Op0Hi, Op1Hi, Op2Hi);
733 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
735 // We know the result is a vector. The input may be either a vector or a
738 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
741 SDValue InOp = N->getOperand(0);
742 EVT InVT = InOp.getValueType();
744 // Handle some special cases efficiently.
745 switch (getTypeAction(InVT)) {
746 case TargetLowering::TypeLegal:
747 case TargetLowering::TypePromoteInteger:
748 case TargetLowering::TypePromoteFloat:
749 case TargetLowering::TypeSoftenFloat:
750 case TargetLowering::TypeScalarizeVector:
751 case TargetLowering::TypeWidenVector:
753 case TargetLowering::TypeExpandInteger:
754 case TargetLowering::TypeExpandFloat:
755 // A scalar to vector conversion, where the scalar needs expansion.
756 // If the vector is being split in two then we can just convert the
759 GetExpandedOp(InOp, Lo, Hi);
760 if (DAG.getDataLayout().isBigEndian())
762 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
763 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
767 case TargetLowering::TypeSplitVector:
768 // If the input is a vector that needs to be split, convert each split
769 // piece of the input now.
770 GetSplitVector(InOp, Lo, Hi);
771 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
772 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
776 // In the general case, convert the input to an integer and split it by hand.
777 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
778 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
779 if (DAG.getDataLayout().isBigEndian())
780 std::swap(LoIntVT, HiIntVT);
782 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
784 if (DAG.getDataLayout().isBigEndian())
786 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
787 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
790 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
794 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
795 unsigned LoNumElts = LoVT.getVectorNumElements();
796 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
797 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, LoOps);
799 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
800 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, HiOps);
803 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
805 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
807 unsigned NumSubvectors = N->getNumOperands() / 2;
808 if (NumSubvectors == 1) {
809 Lo = N->getOperand(0);
810 Hi = N->getOperand(1);
815 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
817 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
818 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
820 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
821 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
824 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
826 SDValue Vec = N->getOperand(0);
827 SDValue Idx = N->getOperand(1);
831 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
833 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
834 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
835 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
836 DAG.getConstant(IdxVal + LoVT.getVectorNumElements(), dl,
837 TLI.getVectorIdxTy(DAG.getDataLayout())));
840 void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
842 SDValue Vec = N->getOperand(0);
843 SDValue SubVec = N->getOperand(1);
844 SDValue Idx = N->getOperand(2);
846 GetSplitVector(Vec, Lo, Hi);
848 EVT VecVT = Vec.getValueType();
849 EVT VecElemVT = VecVT.getVectorElementType();
850 unsigned VecElems = VecVT.getVectorNumElements();
851 unsigned SubElems = SubVec.getValueType().getVectorNumElements();
853 // If we know the index is 0, and we know the subvector doesn't cross the
854 // boundary between the halves, we can avoid spilling the vector, and insert
855 // into the lower half of the split vector directly.
856 // TODO: The IdxVal == 0 constraint is artificial, we could do this whenever
857 // the index is constant and there is no boundary crossing. But those cases
858 // don't seem to get hit in practice.
859 if (ConstantSDNode *ConstIdx = dyn_cast<ConstantSDNode>(Idx)) {
860 unsigned IdxVal = ConstIdx->getZExtValue();
861 if ((IdxVal == 0) && (IdxVal + SubElems <= VecElems / 2)) {
863 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
864 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx);
869 // Spill the vector to the stack.
870 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
872 DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, MachinePointerInfo());
874 // Store the new subvector into the specified index.
875 SDValue SubVecPtr = GetVectorElementPointer(StackPtr, VecElemVT, Idx);
876 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
877 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
878 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo());
880 // Load the Lo part from the stack slot.
882 DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo());
884 // Increment the pointer to the other part.
885 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
887 DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
888 DAG.getConstant(IncrementSize, dl, StackPtr.getValueType()));
890 // Load the Hi part from the stack slot.
891 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
892 MinAlign(Alignment, IncrementSize));
895 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
898 GetSplitVector(N->getOperand(0), Lo, Hi);
899 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
900 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
903 void DAGTypeLegalizer::SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo,
905 SDValue LHSLo, LHSHi;
906 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
909 SDValue RHSLo, RHSHi;
910 SDValue RHS = N->getOperand(1);
911 EVT RHSVT = RHS.getValueType();
912 if (getTypeAction(RHSVT) == TargetLowering::TypeSplitVector)
913 GetSplitVector(RHS, RHSLo, RHSHi);
915 std::tie(RHSLo, RHSHi) = DAG.SplitVector(RHS, SDLoc(RHS));
918 Lo = DAG.getNode(ISD::FCOPYSIGN, DL, LHSLo.getValueType(), LHSLo, RHSLo);
919 Hi = DAG.getNode(ISD::FCOPYSIGN, DL, LHSHi.getValueType(), LHSHi, RHSHi);
922 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
924 SDValue LHSLo, LHSHi;
925 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
929 std::tie(LoVT, HiVT) =
930 DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
932 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
933 DAG.getValueType(LoVT));
934 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
935 DAG.getValueType(HiVT));
938 void DAGTypeLegalizer::SplitVecRes_ExtVecInRegOp(SDNode *N, SDValue &Lo,
940 unsigned Opcode = N->getOpcode();
941 SDValue N0 = N->getOperand(0);
945 GetSplitVector(N0, InLo, InHi);
946 EVT InLoVT = InLo.getValueType();
947 unsigned InNumElements = InLoVT.getVectorNumElements();
949 EVT OutLoVT, OutHiVT;
950 std::tie(OutLoVT, OutHiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
951 unsigned OutNumElements = OutLoVT.getVectorNumElements();
952 assert((2 * OutNumElements) <= InNumElements &&
953 "Illegal extend vector in reg split");
955 // *_EXTEND_VECTOR_INREG instructions extend the lowest elements of the
956 // input vector (i.e. we only use InLo):
957 // OutLo will extend the first OutNumElements from InLo.
958 // OutHi will extend the next OutNumElements from InLo.
960 // Shuffle the elements from InLo for OutHi into the bottom elements to
961 // create a 'fake' InHi.
962 SmallVector<int, 8> SplitHi(InNumElements, -1);
963 for (unsigned i = 0; i != OutNumElements; ++i)
964 SplitHi[i] = i + OutNumElements;
965 InHi = DAG.getVectorShuffle(InLoVT, dl, InLo, DAG.getUNDEF(InLoVT), SplitHi);
967 Lo = DAG.getNode(Opcode, dl, OutLoVT, InLo);
968 Hi = DAG.getNode(Opcode, dl, OutHiVT, InHi);
971 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
973 SDValue Vec = N->getOperand(0);
974 SDValue Elt = N->getOperand(1);
975 SDValue Idx = N->getOperand(2);
977 GetSplitVector(Vec, Lo, Hi);
979 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
980 unsigned IdxVal = CIdx->getZExtValue();
981 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
982 if (IdxVal < LoNumElts)
983 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
984 Lo.getValueType(), Lo, Elt, Idx);
987 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
988 DAG.getConstant(IdxVal - LoNumElts, dl,
989 TLI.getVectorIdxTy(DAG.getDataLayout())));
993 // See if the target wants to custom expand this node.
994 if (CustomLowerNode(N, N->getValueType(0), true))
997 // Spill the vector to the stack.
998 EVT VecVT = Vec.getValueType();
999 EVT EltVT = VecVT.getVectorElementType();
1000 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1002 DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, MachinePointerInfo());
1004 // Store the new element. This may be larger than the vector element type,
1005 // so use a truncating store.
1006 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1007 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
1008 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
1010 DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT);
1012 // Load the Lo part from the stack slot.
1014 DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo());
1016 // Increment the pointer to the other part.
1017 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
1018 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
1019 DAG.getConstant(IncrementSize, dl,
1020 StackPtr.getValueType()));
1022 // Load the Hi part from the stack slot.
1023 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
1024 MinAlign(Alignment, IncrementSize));
1027 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
1031 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1032 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
1033 Hi = DAG.getUNDEF(HiVT);
1036 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
1038 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
1041 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
1043 ISD::LoadExtType ExtType = LD->getExtensionType();
1044 SDValue Ch = LD->getChain();
1045 SDValue Ptr = LD->getBasePtr();
1046 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
1047 EVT MemoryVT = LD->getMemoryVT();
1048 unsigned Alignment = LD->getOriginalAlignment();
1049 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
1050 AAMDNodes AAInfo = LD->getAAInfo();
1052 EVT LoMemVT, HiMemVT;
1053 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1055 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
1056 LD->getPointerInfo(), LoMemVT, Alignment, MMOFlags, AAInfo);
1058 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1059 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1060 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
1061 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
1062 LD->getPointerInfo().getWithOffset(IncrementSize), HiMemVT,
1063 Alignment, MMOFlags, AAInfo);
1065 // Build a factor node to remember that this load is independent of the
1067 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1070 // Legalize the chain result - switch anything that used the old chain to
1072 ReplaceValueWith(SDValue(LD, 1), Ch);
1075 void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
1076 SDValue &Lo, SDValue &Hi) {
1079 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
1081 SDValue Ch = MLD->getChain();
1082 SDValue Ptr = MLD->getBasePtr();
1083 SDValue Mask = MLD->getMask();
1084 SDValue Src0 = MLD->getSrc0();
1085 unsigned Alignment = MLD->getOriginalAlignment();
1086 ISD::LoadExtType ExtType = MLD->getExtensionType();
1088 // if Alignment is equal to the vector size,
1089 // take the half of it for the second part
1090 unsigned SecondHalfAlignment =
1091 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
1092 Alignment/2 : Alignment;
1094 // Split Mask operand
1095 SDValue MaskLo, MaskHi;
1096 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1097 GetSplitVector(Mask, MaskLo, MaskHi);
1099 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1101 EVT MemoryVT = MLD->getMemoryVT();
1102 EVT LoMemVT, HiMemVT;
1103 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1105 SDValue Src0Lo, Src0Hi;
1106 if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
1107 GetSplitVector(Src0, Src0Lo, Src0Hi);
1109 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1111 MachineMemOperand *MMO = DAG.getMachineFunction().
1112 getMachineMemOperand(MLD->getPointerInfo(),
1113 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1114 Alignment, MLD->getAAInfo(), MLD->getRanges());
1116 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, MaskLo, Src0Lo, LoMemVT, MMO,
1119 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1120 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1121 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
1123 MMO = DAG.getMachineFunction().
1124 getMachineMemOperand(MLD->getPointerInfo(),
1125 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1126 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
1128 Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, MaskHi, Src0Hi, HiMemVT, MMO,
1132 // Build a factor node to remember that this load is independent of the
1134 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1137 // Legalize the chain result - switch anything that used the old chain to
1139 ReplaceValueWith(SDValue(MLD, 1), Ch);
1143 void DAGTypeLegalizer::SplitVecRes_MGATHER(MaskedGatherSDNode *MGT,
1144 SDValue &Lo, SDValue &Hi) {
1147 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1149 SDValue Ch = MGT->getChain();
1150 SDValue Ptr = MGT->getBasePtr();
1151 SDValue Mask = MGT->getMask();
1152 SDValue Src0 = MGT->getValue();
1153 SDValue Index = MGT->getIndex();
1154 unsigned Alignment = MGT->getOriginalAlignment();
1156 // Split Mask operand
1157 SDValue MaskLo, MaskHi;
1158 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1159 GetSplitVector(Mask, MaskLo, MaskHi);
1161 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1163 EVT MemoryVT = MGT->getMemoryVT();
1164 EVT LoMemVT, HiMemVT;
1166 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1168 SDValue Src0Lo, Src0Hi;
1169 if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
1170 GetSplitVector(Src0, Src0Lo, Src0Hi);
1172 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1174 SDValue IndexHi, IndexLo;
1175 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1176 GetSplitVector(Index, IndexLo, IndexHi);
1178 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1180 MachineMemOperand *MMO = DAG.getMachineFunction().
1181 getMachineMemOperand(MGT->getPointerInfo(),
1182 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1183 Alignment, MGT->getAAInfo(), MGT->getRanges());
1185 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1186 Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl, OpsLo,
1189 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1190 Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl, OpsHi,
1193 // Build a factor node to remember that this load is independent of the
1195 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1198 // Legalize the chain result - switch anything that used the old chain to
1200 ReplaceValueWith(SDValue(MGT, 1), Ch);
1204 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
1205 assert(N->getValueType(0).isVector() &&
1206 N->getOperand(0).getValueType().isVector() &&
1207 "Operand types must be vectors");
1211 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1214 SDValue LL, LH, RL, RH;
1215 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
1216 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
1218 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
1219 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
1222 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
1224 // Get the dest types - they may not match the input types, e.g. int_to_fp.
1227 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1229 // If the input also splits, handle it directly for a compile time speedup.
1230 // Otherwise split it by hand.
1231 EVT InVT = N->getOperand(0).getValueType();
1232 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1233 GetSplitVector(N->getOperand(0), Lo, Hi);
1235 std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
1237 if (N->getOpcode() == ISD::FP_ROUND) {
1238 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
1239 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
1240 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
1241 SDValue DTyOpLo = DAG.getValueType(LoVT);
1242 SDValue DTyOpHi = DAG.getValueType(HiVT);
1243 SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
1244 SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
1245 SDValue RndOp = N->getOperand(3);
1246 SDValue SatOp = N->getOperand(4);
1247 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1248 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
1250 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
1253 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1254 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1258 void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
1261 EVT SrcVT = N->getOperand(0).getValueType();
1262 EVT DestVT = N->getValueType(0);
1264 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1266 // We can do better than a generic split operation if the extend is doing
1267 // more than just doubling the width of the elements and the following are
1269 // - The number of vector elements is even,
1270 // - the source type is legal,
1271 // - the type of a split source is illegal,
1272 // - the type of an extended (by doubling element size) source is legal, and
1273 // - the type of that extended source when split is legal.
1275 // This won't necessarily completely legalize the operation, but it will
1276 // more effectively move in the right direction and prevent falling down
1277 // to scalarization in many cases due to the input vector being split too
1279 unsigned NumElements = SrcVT.getVectorNumElements();
1280 if ((NumElements & 1) == 0 &&
1281 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
1282 LLVMContext &Ctx = *DAG.getContext();
1283 EVT NewSrcVT = EVT::getVectorVT(
1284 Ctx, EVT::getIntegerVT(
1285 Ctx, SrcVT.getVectorElementType().getSizeInBits() * 2),
1288 EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2);
1289 EVT SplitLoVT, SplitHiVT;
1290 std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
1291 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
1292 TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
1293 DEBUG(dbgs() << "Split vector extend via incremental extend:";
1294 N->dump(&DAG); dbgs() << "\n");
1295 // Extend the source vector by one step.
1297 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
1298 // Get the low and high halves of the new, extended one step, vector.
1299 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
1300 // Extend those vector halves the rest of the way.
1301 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1302 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1306 // Fall back to the generic unary operator splitting otherwise.
1307 SplitVecRes_UnaryOp(N, Lo, Hi);
1310 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
1311 SDValue &Lo, SDValue &Hi) {
1312 // The low and high parts of the original input give four input vectors.
1315 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
1316 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
1317 EVT NewVT = Inputs[0].getValueType();
1318 unsigned NewElts = NewVT.getVectorNumElements();
1320 // If Lo or Hi uses elements from at most two of the four input vectors, then
1321 // express it as a vector shuffle of those two inputs. Otherwise extract the
1322 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
1323 SmallVector<int, 16> Ops;
1324 for (unsigned High = 0; High < 2; ++High) {
1325 SDValue &Output = High ? Hi : Lo;
1327 // Build a shuffle mask for the output, discovering on the fly which
1328 // input vectors to use as shuffle operands (recorded in InputUsed).
1329 // If building a suitable shuffle vector proves too hard, then bail
1330 // out with useBuildVector set.
1331 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
1332 unsigned FirstMaskIdx = High * NewElts;
1333 bool useBuildVector = false;
1334 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1335 // The mask element. This indexes into the input.
1336 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1338 // The input vector this mask element indexes into.
1339 unsigned Input = (unsigned)Idx / NewElts;
1341 if (Input >= array_lengthof(Inputs)) {
1342 // The mask element does not index into any input vector.
1347 // Turn the index into an offset from the start of the input vector.
1348 Idx -= Input * NewElts;
1350 // Find or create a shuffle vector operand to hold this input.
1352 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
1353 if (InputUsed[OpNo] == Input) {
1354 // This input vector is already an operand.
1356 } else if (InputUsed[OpNo] == -1U) {
1357 // Create a new operand for this input vector.
1358 InputUsed[OpNo] = Input;
1363 if (OpNo >= array_lengthof(InputUsed)) {
1364 // More than two input vectors used! Give up on trying to create a
1365 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
1366 useBuildVector = true;
1370 // Add the mask index for the new shuffle vector.
1371 Ops.push_back(Idx + OpNo * NewElts);
1374 if (useBuildVector) {
1375 EVT EltVT = NewVT.getVectorElementType();
1376 SmallVector<SDValue, 16> SVOps;
1378 // Extract the input elements by hand.
1379 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1380 // The mask element. This indexes into the input.
1381 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1383 // The input vector this mask element indexes into.
1384 unsigned Input = (unsigned)Idx / NewElts;
1386 if (Input >= array_lengthof(Inputs)) {
1387 // The mask element is "undef" or indexes off the end of the input.
1388 SVOps.push_back(DAG.getUNDEF(EltVT));
1392 // Turn the index into an offset from the start of the input vector.
1393 Idx -= Input * NewElts;
1395 // Extract the vector element by hand.
1396 SVOps.push_back(DAG.getNode(
1397 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Inputs[Input],
1398 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
1401 // Construct the Lo/Hi output using a BUILD_VECTOR.
1402 Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, SVOps);
1403 } else if (InputUsed[0] == -1U) {
1404 // No input vectors were used! The result is undefined.
1405 Output = DAG.getUNDEF(NewVT);
1407 SDValue Op0 = Inputs[InputUsed[0]];
1408 // If only one input was used, use an undefined vector for the other.
1409 SDValue Op1 = InputUsed[1] == -1U ?
1410 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
1411 // At least one input vector was used. Create a new shuffle vector.
1412 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, Ops);
1420 //===----------------------------------------------------------------------===//
1421 // Operand Vector Splitting
1422 //===----------------------------------------------------------------------===//
1424 /// This method is called when the specified operand of the specified node is
1425 /// found to need vector splitting. At this point, all of the result types of
1426 /// the node are known to be legal, but other operands of the node may need
1427 /// legalization as well as the specified one.
1428 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
1429 DEBUG(dbgs() << "Split node operand: ";
1432 SDValue Res = SDValue();
1434 // See if the target wants to custom split this node.
1435 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1438 if (!Res.getNode()) {
1439 switch (N->getOpcode()) {
1442 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
1446 report_fatal_error("Do not know how to split this operator's "
1449 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1450 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1451 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1452 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1453 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1455 Res = SplitVecOp_TruncateHelper(N);
1457 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1458 case ISD::FCOPYSIGN: Res = SplitVecOp_FCOPYSIGN(N); break;
1460 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1463 Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
1466 Res = SplitVecOp_MSCATTER(cast<MaskedScatterSDNode>(N), OpNo);
1469 Res = SplitVecOp_MGATHER(cast<MaskedGatherSDNode>(N), OpNo);
1472 Res = SplitVecOp_VSELECT(N, OpNo);
1474 case ISD::FP_TO_SINT:
1475 case ISD::FP_TO_UINT:
1476 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1477 Res = SplitVecOp_TruncateHelper(N);
1479 Res = SplitVecOp_UnaryOp(N);
1481 case ISD::SINT_TO_FP:
1482 case ISD::UINT_TO_FP:
1483 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1484 Res = SplitVecOp_TruncateHelper(N);
1486 Res = SplitVecOp_UnaryOp(N);
1491 case ISD::FP_EXTEND:
1492 case ISD::SIGN_EXTEND:
1493 case ISD::ZERO_EXTEND:
1494 case ISD::ANY_EXTEND:
1496 Res = SplitVecOp_UnaryOp(N);
1501 // If the result is null, the sub-method took care of registering results etc.
1502 if (!Res.getNode()) return false;
1504 // If the result is N, the sub-method updated N in place. Tell the legalizer
1506 if (Res.getNode() == N)
1509 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1510 "Invalid operand expansion");
1512 ReplaceValueWith(SDValue(N, 0), Res);
1516 SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
1517 // The only possibility for an illegal operand is the mask, since result type
1518 // legalization would have handled this node already otherwise.
1519 assert(OpNo == 0 && "Illegal operand must be mask");
1521 SDValue Mask = N->getOperand(0);
1522 SDValue Src0 = N->getOperand(1);
1523 SDValue Src1 = N->getOperand(2);
1524 EVT Src0VT = Src0.getValueType();
1526 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");
1529 GetSplitVector(N->getOperand(0), Lo, Hi);
1530 assert(Lo.getValueType() == Hi.getValueType() &&
1531 "Lo and Hi have differing types");
1534 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
1535 assert(LoOpVT == HiOpVT && "Asymmetric vector split?");
1537 SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
1538 std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
1539 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
1540 std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
1543 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1545 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1547 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1550 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1551 // The result has a legal vector type, but the input needs splitting.
1552 EVT ResVT = N->getValueType(0);
1555 GetSplitVector(N->getOperand(0), Lo, Hi);
1556 EVT InVT = Lo.getValueType();
1558 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1559 InVT.getVectorNumElements());
1561 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1562 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1564 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1567 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1568 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1569 // end up being split all the way down to individual components. Convert the
1570 // split pieces into integers and reassemble.
1572 GetSplitVector(N->getOperand(0), Lo, Hi);
1573 Lo = BitConvertToInteger(Lo);
1574 Hi = BitConvertToInteger(Hi);
1576 if (DAG.getDataLayout().isBigEndian())
1579 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
1580 JoinIntegers(Lo, Hi));
1583 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1584 // We know that the extracted result type is legal.
1585 EVT SubVT = N->getValueType(0);
1586 SDValue Idx = N->getOperand(1);
1589 GetSplitVector(N->getOperand(0), Lo, Hi);
1591 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1592 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1594 if (IdxVal < LoElts) {
1595 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1596 "Extracted subvector crosses vector split!");
1597 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1599 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1600 DAG.getConstant(IdxVal - LoElts, dl,
1601 Idx.getValueType()));
1605 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1606 SDValue Vec = N->getOperand(0);
1607 SDValue Idx = N->getOperand(1);
1608 EVT VecVT = Vec.getValueType();
1610 if (isa<ConstantSDNode>(Idx)) {
1611 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1612 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1615 GetSplitVector(Vec, Lo, Hi);
1617 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1619 if (IdxVal < LoElts)
1620 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1621 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1622 DAG.getConstant(IdxVal - LoElts, SDLoc(N),
1623 Idx.getValueType())), 0);
1626 // See if the target wants to custom expand this node.
1627 if (CustomLowerNode(N, N->getValueType(0), true))
1630 // Make the vector elements byte-addressable if they aren't already.
1632 EVT EltVT = VecVT.getVectorElementType();
1633 if (EltVT.getSizeInBits() < 8) {
1634 SmallVector<SDValue, 4> ElementOps;
1635 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i) {
1636 ElementOps.push_back(DAG.getAnyExtOrTrunc(
1637 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vec,
1638 DAG.getConstant(i, dl, MVT::i8)),
1643 VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
1644 VecVT.getVectorNumElements());
1645 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, ElementOps);
1648 // Store the vector to the stack.
1649 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1651 DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, MachinePointerInfo());
1653 // Load back the required element.
1654 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1655 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1656 MachinePointerInfo(), EltVT);
1659 SDValue DAGTypeLegalizer::SplitVecOp_MGATHER(MaskedGatherSDNode *MGT,
1663 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1665 SDValue Ch = MGT->getChain();
1666 SDValue Ptr = MGT->getBasePtr();
1667 SDValue Index = MGT->getIndex();
1668 SDValue Mask = MGT->getMask();
1669 SDValue Src0 = MGT->getValue();
1670 unsigned Alignment = MGT->getOriginalAlignment();
1672 SDValue MaskLo, MaskHi;
1673 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1674 // Split Mask operand
1675 GetSplitVector(Mask, MaskLo, MaskHi);
1677 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1679 EVT MemoryVT = MGT->getMemoryVT();
1680 EVT LoMemVT, HiMemVT;
1681 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1683 SDValue Src0Lo, Src0Hi;
1684 if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
1685 GetSplitVector(Src0, Src0Lo, Src0Hi);
1687 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1689 SDValue IndexHi, IndexLo;
1690 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1691 GetSplitVector(Index, IndexLo, IndexHi);
1693 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1695 MachineMemOperand *MMO = DAG.getMachineFunction().
1696 getMachineMemOperand(MGT->getPointerInfo(),
1697 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1698 Alignment, MGT->getAAInfo(), MGT->getRanges());
1700 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1701 SDValue Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl,
1704 MMO = DAG.getMachineFunction().
1705 getMachineMemOperand(MGT->getPointerInfo(),
1706 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1707 Alignment, MGT->getAAInfo(),
1710 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1711 SDValue Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl,
1714 // Build a factor node to remember that this load is independent of the
1716 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1719 // Legalize the chain result - switch anything that used the old chain to
1721 ReplaceValueWith(SDValue(MGT, 1), Ch);
1723 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MGT->getValueType(0), Lo,
1725 ReplaceValueWith(SDValue(MGT, 0), Res);
1729 SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
1731 SDValue Ch = N->getChain();
1732 SDValue Ptr = N->getBasePtr();
1733 SDValue Mask = N->getMask();
1734 SDValue Data = N->getValue();
1735 EVT MemoryVT = N->getMemoryVT();
1736 unsigned Alignment = N->getOriginalAlignment();
1739 EVT LoMemVT, HiMemVT;
1740 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1742 SDValue DataLo, DataHi;
1743 if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
1744 // Split Data operand
1745 GetSplitVector(Data, DataLo, DataHi);
1747 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
1749 SDValue MaskLo, MaskHi;
1750 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1751 // Split Mask operand
1752 GetSplitVector(Mask, MaskLo, MaskHi);
1754 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
1756 MaskLo = PromoteTargetBoolean(MaskLo, DataLo.getValueType());
1757 MaskHi = PromoteTargetBoolean(MaskHi, DataHi.getValueType());
1759 // if Alignment is equal to the vector size,
1760 // take the half of it for the second part
1761 unsigned SecondHalfAlignment =
1762 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
1763 Alignment/2 : Alignment;
1766 MachineMemOperand *MMO = DAG.getMachineFunction().
1767 getMachineMemOperand(N->getPointerInfo(),
1768 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1769 Alignment, N->getAAInfo(), N->getRanges());
1771 Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, MaskLo, LoMemVT, MMO,
1772 N->isTruncatingStore());
1774 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1775 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1776 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
1778 MMO = DAG.getMachineFunction().
1779 getMachineMemOperand(N->getPointerInfo(),
1780 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1781 SecondHalfAlignment, N->getAAInfo(), N->getRanges());
1783 Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
1784 N->isTruncatingStore());
1786 // Build a factor node to remember that this store is independent of the
1788 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1791 SDValue DAGTypeLegalizer::SplitVecOp_MSCATTER(MaskedScatterSDNode *N,
1793 SDValue Ch = N->getChain();
1794 SDValue Ptr = N->getBasePtr();
1795 SDValue Mask = N->getMask();
1796 SDValue Index = N->getIndex();
1797 SDValue Data = N->getValue();
1798 EVT MemoryVT = N->getMemoryVT();
1799 unsigned Alignment = N->getOriginalAlignment();
1802 // Split all operands
1803 EVT LoMemVT, HiMemVT;
1804 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1806 SDValue DataLo, DataHi;
1807 if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
1808 // Split Data operand
1809 GetSplitVector(Data, DataLo, DataHi);
1811 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
1813 SDValue MaskLo, MaskHi;
1814 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1815 // Split Mask operand
1816 GetSplitVector(Mask, MaskLo, MaskHi);
1818 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
1820 SDValue IndexHi, IndexLo;
1821 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1822 GetSplitVector(Index, IndexLo, IndexHi);
1824 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, DL);
1827 MachineMemOperand *MMO = DAG.getMachineFunction().
1828 getMachineMemOperand(N->getPointerInfo(),
1829 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1830 Alignment, N->getAAInfo(), N->getRanges());
1832 SDValue OpsLo[] = {Ch, DataLo, MaskLo, Ptr, IndexLo};
1833 Lo = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataLo.getValueType(),
1836 MMO = DAG.getMachineFunction().
1837 getMachineMemOperand(N->getPointerInfo(),
1838 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1839 Alignment, N->getAAInfo(), N->getRanges());
1841 SDValue OpsHi[] = {Ch, DataHi, MaskHi, Ptr, IndexHi};
1842 Hi = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataHi.getValueType(),
1845 // Build a factor node to remember that this store is independent of the
1847 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1850 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1851 assert(N->isUnindexed() && "Indexed store of vector?");
1852 assert(OpNo == 1 && "Can only split the stored value");
1855 bool isTruncating = N->isTruncatingStore();
1856 SDValue Ch = N->getChain();
1857 SDValue Ptr = N->getBasePtr();
1858 EVT MemoryVT = N->getMemoryVT();
1859 unsigned Alignment = N->getOriginalAlignment();
1860 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
1861 AAMDNodes AAInfo = N->getAAInfo();
1863 GetSplitVector(N->getOperand(1), Lo, Hi);
1865 EVT LoMemVT, HiMemVT;
1866 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1868 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1871 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), LoMemVT,
1872 Alignment, MMOFlags, AAInfo);
1874 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), Alignment, MMOFlags,
1877 // Increment the pointer to the other half.
1878 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1879 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
1882 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1883 N->getPointerInfo().getWithOffset(IncrementSize),
1884 HiMemVT, Alignment, MMOFlags, AAInfo);
1886 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1887 N->getPointerInfo().getWithOffset(IncrementSize),
1888 Alignment, MMOFlags, AAInfo);
1890 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1893 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1896 // The input operands all must have the same type, and we know the result
1897 // type is valid. Convert this to a buildvector which extracts all the
1899 // TODO: If the input elements are power-two vectors, we could convert this to
1900 // a new CONCAT_VECTORS node with elements that are half-wide.
1901 SmallVector<SDValue, 32> Elts;
1902 EVT EltVT = N->getValueType(0).getVectorElementType();
1903 for (const SDValue &Op : N->op_values()) {
1904 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1906 Elts.push_back(DAG.getNode(
1907 ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Op,
1908 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
1912 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), Elts);
1915 SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
1916 // The result type is legal, but the input type is illegal. If splitting
1917 // ends up with the result type of each half still being legal, just
1918 // do that. If, however, that would result in an illegal result type,
1919 // we can try to get more clever with power-two vectors. Specifically,
1920 // split the input type, but also widen the result element size, then
1921 // concatenate the halves and truncate again. For example, consider a target
1922 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
1923 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
1924 // %inlo = v4i32 extract_subvector %in, 0
1925 // %inhi = v4i32 extract_subvector %in, 4
1926 // %lo16 = v4i16 trunc v4i32 %inlo
1927 // %hi16 = v4i16 trunc v4i32 %inhi
1928 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
1929 // %res = v8i8 trunc v8i16 %in16
1931 // Without this transform, the original truncate would end up being
1932 // scalarized, which is pretty much always a last resort.
1933 SDValue InVec = N->getOperand(0);
1934 EVT InVT = InVec->getValueType(0);
1935 EVT OutVT = N->getValueType(0);
1936 unsigned NumElements = OutVT.getVectorNumElements();
1937 bool IsFloat = OutVT.isFloatingPoint();
1939 // Widening should have already made sure this is a power-two vector
1940 // if we're trying to split it at all. assert() that's true, just in case.
1941 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
1943 unsigned InElementSize = InVT.getVectorElementType().getSizeInBits();
1944 unsigned OutElementSize = OutVT.getVectorElementType().getSizeInBits();
1946 // If the input elements are only 1/2 the width of the result elements,
1947 // just use the normal splitting. Our trick only work if there's room
1948 // to split more than once.
1949 if (InElementSize <= OutElementSize * 2)
1950 return SplitVecOp_UnaryOp(N);
1953 // Extract the halves of the input via extract_subvector.
1954 SDValue InLoVec, InHiVec;
1955 std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL);
1956 // Truncate them to 1/2 the element size.
1957 EVT HalfElementVT = IsFloat ?
1958 EVT::getFloatingPointVT(InElementSize/2) :
1959 EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
1960 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
1962 SDValue HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec);
1963 SDValue HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec);
1964 // Concatenate them to get the full intermediate truncation result.
1965 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
1966 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
1968 // Now finish up by truncating all the way down to the original result
1969 // type. This should normally be something that ends up being legal directly,
1970 // but in theory if a target has very wide vectors and an annoyingly
1971 // restricted set of legal types, this split can chain to build things up.
1973 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec,
1974 DAG.getTargetConstant(
1975 0, DL, TLI.getPointerTy(DAG.getDataLayout())))
1976 : DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
1979 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
1980 assert(N->getValueType(0).isVector() &&
1981 N->getOperand(0).getValueType().isVector() &&
1982 "Operand types must be vectors");
1983 // The result has a legal vector type, but the input needs splitting.
1984 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
1986 GetSplitVector(N->getOperand(0), Lo0, Hi0);
1987 GetSplitVector(N->getOperand(1), Lo1, Hi1);
1988 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
1989 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
1990 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
1992 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1993 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1994 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
1995 return PromoteTargetBoolean(Con, N->getValueType(0));
1999 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
2000 // The result has a legal vector type, but the input needs splitting.
2001 EVT ResVT = N->getValueType(0);
2004 GetSplitVector(N->getOperand(0), Lo, Hi);
2005 EVT InVT = Lo.getValueType();
2007 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
2008 InVT.getVectorNumElements());
2010 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
2011 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
2013 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
2016 SDValue DAGTypeLegalizer::SplitVecOp_FCOPYSIGN(SDNode *N) {
2017 // The result (and the first input) has a legal vector type, but the second
2018 // input needs splitting.
2019 return DAG.UnrollVectorOp(N, N->getValueType(0).getVectorNumElements());
2023 //===----------------------------------------------------------------------===//
2024 // Result Vector Widening
2025 //===----------------------------------------------------------------------===//
2027 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
2028 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
2032 // See if the target wants to custom widen this node.
2033 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
2036 SDValue Res = SDValue();
2037 switch (N->getOpcode()) {
2040 dbgs() << "WidenVectorResult #" << ResNo << ": ";
2044 llvm_unreachable("Do not know how to widen the result of this operator!");
2046 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
2047 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
2048 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
2049 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
2050 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
2051 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
2052 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
2053 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
2054 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
2055 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
2056 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
2058 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
2059 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
2060 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
2061 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
2062 case ISD::VECTOR_SHUFFLE:
2063 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
2066 Res = WidenVecRes_MLOAD(cast<MaskedLoadSDNode>(N));
2069 Res = WidenVecRes_MGATHER(cast<MaskedGatherSDNode>(N));
2088 Res = WidenVecRes_Binary(N);
2101 Res = WidenVecRes_BinaryCanTrap(N);
2104 case ISD::FCOPYSIGN:
2105 Res = WidenVecRes_FCOPYSIGN(N);
2109 Res = WidenVecRes_POWI(N);
2115 Res = WidenVecRes_Shift(N);
2118 case ISD::ANY_EXTEND_VECTOR_INREG:
2119 case ISD::SIGN_EXTEND_VECTOR_INREG:
2120 case ISD::ZERO_EXTEND_VECTOR_INREG:
2121 Res = WidenVecRes_EXTEND_VECTOR_INREG(N);
2124 case ISD::ANY_EXTEND:
2125 case ISD::FP_EXTEND:
2127 case ISD::FP_TO_SINT:
2128 case ISD::FP_TO_UINT:
2129 case ISD::SIGN_EXTEND:
2130 case ISD::SINT_TO_FP:
2132 case ISD::UINT_TO_FP:
2133 case ISD::ZERO_EXTEND:
2134 Res = WidenVecRes_Convert(N);
2137 case ISD::BITREVERSE:
2151 case ISD::FNEARBYINT:
2158 Res = WidenVecRes_Unary(N);
2161 Res = WidenVecRes_Ternary(N);
2165 // If Res is null, the sub-method took care of registering the result.
2167 SetWidenedVector(SDValue(N, ResNo), Res);
2170 SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
2171 // Ternary op widening.
2173 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2174 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2175 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2176 SDValue InOp3 = GetWidenedVector(N->getOperand(2));
2177 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
2180 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
2181 // Binary op widening.
2183 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2184 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2185 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2186 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, N->getFlags());
2189 SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
2190 // Binary op widening for operations that can trap.
2191 unsigned Opcode = N->getOpcode();
2193 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2194 EVT WidenEltVT = WidenVT.getVectorElementType();
2196 unsigned NumElts = VT.getVectorNumElements();
2197 const SDNodeFlags *Flags = N->getFlags();
2198 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
2199 NumElts = NumElts / 2;
2200 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2203 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
2204 // Operation doesn't trap so just widen as normal.
2205 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2206 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2207 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, Flags);
2210 // No legal vector version so unroll the vector operation and then widen.
2212 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2214 // Since the operation can trap, apply operation on the original vector.
2216 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2217 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2218 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
2220 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
2221 unsigned ConcatEnd = 0; // Current ConcatOps index.
2222 int Idx = 0; // Current Idx into input vectors.
2224 // NumElts := greatest legal vector size (at most WidenVT)
2225 // while (orig. vector has unhandled elements) {
2226 // take munches of size NumElts from the beginning and add to ConcatOps
2227 // NumElts := next smaller supported vector size or 1
2229 while (CurNumElts != 0) {
2230 while (CurNumElts >= NumElts) {
2231 SDValue EOp1 = DAG.getNode(
2232 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
2233 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2234 SDValue EOp2 = DAG.getNode(
2235 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
2236 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2237 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2, Flags);
2239 CurNumElts -= NumElts;
2242 NumElts = NumElts / 2;
2243 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2244 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
2247 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
2248 SDValue EOp1 = DAG.getNode(
2249 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp1,
2250 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2251 SDValue EOp2 = DAG.getNode(
2252 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp2,
2253 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2254 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
2261 // Check to see if we have a single operation with the widen type.
2262 if (ConcatEnd == 1) {
2263 VT = ConcatOps[0].getValueType();
2265 return ConcatOps[0];
2268 // while (Some element of ConcatOps is not of type MaxVT) {
2269 // From the end of ConcatOps, collect elements of the same type and put
2270 // them into an op of the next larger supported type
2272 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
2273 Idx = ConcatEnd - 1;
2274 VT = ConcatOps[Idx--].getValueType();
2275 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
2278 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
2282 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
2283 } while (!TLI.isTypeLegal(NextVT));
2285 if (!VT.isVector()) {
2286 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
2287 SDValue VecOp = DAG.getUNDEF(NextVT);
2288 unsigned NumToInsert = ConcatEnd - Idx - 1;
2289 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
2290 VecOp = DAG.getNode(
2291 ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, ConcatOps[OpIdx],
2292 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2294 ConcatOps[Idx+1] = VecOp;
2295 ConcatEnd = Idx + 2;
2297 // Vector type, create a CONCAT_VECTORS of type NextVT
2298 SDValue undefVec = DAG.getUNDEF(VT);
2299 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
2300 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
2301 unsigned RealVals = ConcatEnd - Idx - 1;
2302 unsigned SubConcatEnd = 0;
2303 unsigned SubConcatIdx = Idx + 1;
2304 while (SubConcatEnd < RealVals)
2305 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
2306 while (SubConcatEnd < OpsToConcat)
2307 SubConcatOps[SubConcatEnd++] = undefVec;
2308 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
2309 NextVT, SubConcatOps);
2310 ConcatEnd = SubConcatIdx + 1;
2314 // Check to see if we have a single operation with the widen type.
2315 if (ConcatEnd == 1) {
2316 VT = ConcatOps[0].getValueType();
2318 return ConcatOps[0];
2321 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
2322 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
2323 if (NumOps != ConcatEnd ) {
2324 SDValue UndefVal = DAG.getUNDEF(MaxVT);
2325 for (unsigned j = ConcatEnd; j < NumOps; ++j)
2326 ConcatOps[j] = UndefVal;
2328 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2329 makeArrayRef(ConcatOps.data(), NumOps));
2332 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
2333 SDValue InOp = N->getOperand(0);
2336 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2337 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2339 EVT InVT = InOp.getValueType();
2340 EVT InEltVT = InVT.getVectorElementType();
2341 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2343 unsigned Opcode = N->getOpcode();
2344 unsigned InVTNumElts = InVT.getVectorNumElements();
2345 const SDNodeFlags *Flags = N->getFlags();
2346 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2347 InOp = GetWidenedVector(N->getOperand(0));
2348 InVT = InOp.getValueType();
2349 InVTNumElts = InVT.getVectorNumElements();
2350 if (InVTNumElts == WidenNumElts) {
2351 if (N->getNumOperands() == 1)
2352 return DAG.getNode(Opcode, DL, WidenVT, InOp);
2353 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1), Flags);
2357 if (TLI.isTypeLegal(InWidenVT)) {
2358 // Because the result and the input are different vector types, widening
2359 // the result could create a legal type but widening the input might make
2360 // it an illegal type that might lead to repeatedly splitting the input
2361 // and then widening it. To avoid this, we widen the input only if
2362 // it results in a legal type.
2363 if (WidenNumElts % InVTNumElts == 0) {
2364 // Widen the input and call convert on the widened input vector.
2365 unsigned NumConcat = WidenNumElts/InVTNumElts;
2366 SmallVector<SDValue, 16> Ops(NumConcat);
2368 SDValue UndefVal = DAG.getUNDEF(InVT);
2369 for (unsigned i = 1; i != NumConcat; ++i)
2371 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
2372 if (N->getNumOperands() == 1)
2373 return DAG.getNode(Opcode, DL, WidenVT, InVec);
2374 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1), Flags);
2377 if (InVTNumElts % WidenNumElts == 0) {
2378 SDValue InVal = DAG.getNode(
2379 ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, InOp,
2380 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2381 // Extract the input and convert the shorten input vector.
2382 if (N->getNumOperands() == 1)
2383 return DAG.getNode(Opcode, DL, WidenVT, InVal);
2384 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1), Flags);
2388 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2389 SmallVector<SDValue, 16> Ops(WidenNumElts);
2390 EVT EltVT = WidenVT.getVectorElementType();
2391 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2393 for (i=0; i < MinElts; ++i) {
2394 SDValue Val = DAG.getNode(
2395 ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
2396 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2397 if (N->getNumOperands() == 1)
2398 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
2400 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1), Flags);
2403 SDValue UndefVal = DAG.getUNDEF(EltVT);
2404 for (; i < WidenNumElts; ++i)
2407 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, Ops);
2410 SDValue DAGTypeLegalizer::WidenVecRes_EXTEND_VECTOR_INREG(SDNode *N) {
2411 unsigned Opcode = N->getOpcode();
2412 SDValue InOp = N->getOperand(0);
2415 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2416 EVT WidenSVT = WidenVT.getVectorElementType();
2417 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2419 EVT InVT = InOp.getValueType();
2420 EVT InSVT = InVT.getVectorElementType();
2421 unsigned InVTNumElts = InVT.getVectorNumElements();
2423 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2424 InOp = GetWidenedVector(InOp);
2425 InVT = InOp.getValueType();
2426 if (InVT.getSizeInBits() == WidenVT.getSizeInBits()) {
2428 case ISD::ANY_EXTEND_VECTOR_INREG:
2429 return DAG.getAnyExtendVectorInReg(InOp, DL, WidenVT);
2430 case ISD::SIGN_EXTEND_VECTOR_INREG:
2431 return DAG.getSignExtendVectorInReg(InOp, DL, WidenVT);
2432 case ISD::ZERO_EXTEND_VECTOR_INREG:
2433 return DAG.getZeroExtendVectorInReg(InOp, DL, WidenVT);
2438 // Unroll, extend the scalars and rebuild the vector.
2439 SmallVector<SDValue, 16> Ops;
2440 for (unsigned i = 0, e = std::min(InVTNumElts, WidenNumElts); i != e; ++i) {
2441 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InSVT, InOp,
2442 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2444 case ISD::ANY_EXTEND_VECTOR_INREG:
2445 Val = DAG.getNode(ISD::ANY_EXTEND, DL, WidenSVT, Val);
2447 case ISD::SIGN_EXTEND_VECTOR_INREG:
2448 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, WidenSVT, Val);
2450 case ISD::ZERO_EXTEND_VECTOR_INREG:
2451 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenSVT, Val);
2454 llvm_unreachable("A *_EXTEND_VECTOR_INREG node was expected");
2459 while (Ops.size() != WidenNumElts)
2460 Ops.push_back(DAG.getUNDEF(WidenSVT));
2462 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, Ops);
2465 SDValue DAGTypeLegalizer::WidenVecRes_FCOPYSIGN(SDNode *N) {
2466 // If this is an FCOPYSIGN with same input types, we can treat it as a
2467 // normal (can trap) binary op.
2468 if (N->getOperand(0).getValueType() == N->getOperand(1).getValueType())
2469 return WidenVecRes_BinaryCanTrap(N);
2471 // If the types are different, fall back to unrolling.
2472 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2473 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2476 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
2477 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2478 SDValue InOp = GetWidenedVector(N->getOperand(0));
2479 SDValue ShOp = N->getOperand(1);
2480 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2483 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
2484 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2485 SDValue InOp = GetWidenedVector(N->getOperand(0));
2486 SDValue ShOp = N->getOperand(1);
2488 EVT ShVT = ShOp.getValueType();
2489 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
2490 ShOp = GetWidenedVector(ShOp);
2491 ShVT = ShOp.getValueType();
2493 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
2494 ShVT.getVectorElementType(),
2495 WidenVT.getVectorNumElements());
2496 if (ShVT != ShWidenVT)
2497 ShOp = ModifyToType(ShOp, ShWidenVT);
2499 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2502 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
2503 // Unary op widening.
2504 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2505 SDValue InOp = GetWidenedVector(N->getOperand(0));
2506 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
2509 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
2510 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2511 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
2512 cast<VTSDNode>(N->getOperand(1))->getVT()
2513 .getVectorElementType(),
2514 WidenVT.getVectorNumElements());
2515 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
2516 return DAG.getNode(N->getOpcode(), SDLoc(N),
2517 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
2520 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
2521 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
2522 return GetWidenedVector(WidenVec);
2525 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
2526 SDValue InOp = N->getOperand(0);
2527 EVT InVT = InOp.getValueType();
2528 EVT VT = N->getValueType(0);
2529 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2532 switch (getTypeAction(InVT)) {
2533 case TargetLowering::TypeLegal:
2535 case TargetLowering::TypePromoteInteger:
2536 // If the incoming type is a vector that is being promoted, then
2537 // we know that the elements are arranged differently and that we
2538 // must perform the conversion using a stack slot.
2539 if (InVT.isVector())
2542 // If the InOp is promoted to the same size, convert it. Otherwise,
2543 // fall out of the switch and widen the promoted input.
2544 InOp = GetPromotedInteger(InOp);
2545 InVT = InOp.getValueType();
2546 if (WidenVT.bitsEq(InVT))
2547 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2549 case TargetLowering::TypeSoftenFloat:
2550 case TargetLowering::TypePromoteFloat:
2551 case TargetLowering::TypeExpandInteger:
2552 case TargetLowering::TypeExpandFloat:
2553 case TargetLowering::TypeScalarizeVector:
2554 case TargetLowering::TypeSplitVector:
2556 case TargetLowering::TypeWidenVector:
2557 // If the InOp is widened to the same size, convert it. Otherwise, fall
2558 // out of the switch and widen the widened input.
2559 InOp = GetWidenedVector(InOp);
2560 InVT = InOp.getValueType();
2561 if (WidenVT.bitsEq(InVT))
2562 // The input widens to the same size. Convert to the widen value.
2563 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2567 unsigned WidenSize = WidenVT.getSizeInBits();
2568 unsigned InSize = InVT.getSizeInBits();
2569 // x86mmx is not an acceptable vector element type, so don't try.
2570 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
2571 // Determine new input vector type. The new input vector type will use
2572 // the same element type (if its a vector) or use the input type as a
2573 // vector. It is the same size as the type to widen to.
2575 unsigned NewNumElts = WidenSize / InSize;
2576 if (InVT.isVector()) {
2577 EVT InEltVT = InVT.getVectorElementType();
2578 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
2579 WidenSize / InEltVT.getSizeInBits());
2581 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
2584 if (TLI.isTypeLegal(NewInVT)) {
2585 // Because the result and the input are different vector types, widening
2586 // the result could create a legal type but widening the input might make
2587 // it an illegal type that might lead to repeatedly splitting the input
2588 // and then widening it. To avoid this, we widen the input only if
2589 // it results in a legal type.
2590 SmallVector<SDValue, 16> Ops(NewNumElts);
2591 SDValue UndefVal = DAG.getUNDEF(InVT);
2593 for (unsigned i = 1; i < NewNumElts; ++i)
2597 if (InVT.isVector())
2598 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
2600 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, Ops);
2601 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
2605 return CreateStackStoreLoad(InOp, WidenVT);
2608 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
2610 // Build a vector with undefined for the new nodes.
2611 EVT VT = N->getValueType(0);
2613 // Integer BUILD_VECTOR operands may be larger than the node's vector element
2614 // type. The UNDEFs need to have the same type as the existing operands.
2615 EVT EltVT = N->getOperand(0).getValueType();
2616 unsigned NumElts = VT.getVectorNumElements();
2618 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2619 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2621 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
2622 assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
2623 NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
2625 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, NewOps);
2628 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
2629 EVT InVT = N->getOperand(0).getValueType();
2630 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2632 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2633 unsigned NumInElts = InVT.getVectorNumElements();
2634 unsigned NumOperands = N->getNumOperands();
2636 bool InputWidened = false; // Indicates we need to widen the input.
2637 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
2638 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
2639 // Add undef vectors to widen to correct length.
2640 unsigned NumConcat = WidenVT.getVectorNumElements() /
2641 InVT.getVectorNumElements();
2642 SDValue UndefVal = DAG.getUNDEF(InVT);
2643 SmallVector<SDValue, 16> Ops(NumConcat);
2644 for (unsigned i=0; i < NumOperands; ++i)
2645 Ops[i] = N->getOperand(i);
2646 for (unsigned i = NumOperands; i != NumConcat; ++i)
2648 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
2651 InputWidened = true;
2652 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
2653 // The inputs and the result are widen to the same value.
2655 for (i=1; i < NumOperands; ++i)
2656 if (!N->getOperand(i).isUndef())
2659 if (i == NumOperands)
2660 // Everything but the first operand is an UNDEF so just return the
2661 // widened first operand.
2662 return GetWidenedVector(N->getOperand(0));
2664 if (NumOperands == 2) {
2665 // Replace concat of two operands with a shuffle.
2666 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
2667 for (unsigned i = 0; i < NumInElts; ++i) {
2669 MaskOps[i + NumInElts] = i + WidenNumElts;
2671 return DAG.getVectorShuffle(WidenVT, dl,
2672 GetWidenedVector(N->getOperand(0)),
2673 GetWidenedVector(N->getOperand(1)),
2679 // Fall back to use extracts and build vector.
2680 EVT EltVT = WidenVT.getVectorElementType();
2681 SmallVector<SDValue, 16> Ops(WidenNumElts);
2683 for (unsigned i=0; i < NumOperands; ++i) {
2684 SDValue InOp = N->getOperand(i);
2686 InOp = GetWidenedVector(InOp);
2687 for (unsigned j=0; j < NumInElts; ++j)
2688 Ops[Idx++] = DAG.getNode(
2689 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2690 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2692 SDValue UndefVal = DAG.getUNDEF(EltVT);
2693 for (; Idx < WidenNumElts; ++Idx)
2694 Ops[Idx] = UndefVal;
2695 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2698 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
2700 SDValue InOp = N->getOperand(0);
2701 SDValue RndOp = N->getOperand(3);
2702 SDValue SatOp = N->getOperand(4);
2704 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2705 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2707 EVT InVT = InOp.getValueType();
2708 EVT InEltVT = InVT.getVectorElementType();
2709 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2711 SDValue DTyOp = DAG.getValueType(WidenVT);
2712 SDValue STyOp = DAG.getValueType(InWidenVT);
2713 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
2715 unsigned InVTNumElts = InVT.getVectorNumElements();
2716 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2717 InOp = GetWidenedVector(InOp);
2718 InVT = InOp.getValueType();
2719 InVTNumElts = InVT.getVectorNumElements();
2720 if (InVTNumElts == WidenNumElts)
2721 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2725 if (TLI.isTypeLegal(InWidenVT)) {
2726 // Because the result and the input are different vector types, widening
2727 // the result could create a legal type but widening the input might make
2728 // it an illegal type that might lead to repeatedly splitting the input
2729 // and then widening it. To avoid this, we widen the input only if
2730 // it results in a legal type.
2731 if (WidenNumElts % InVTNumElts == 0) {
2732 // Widen the input and call convert on the widened input vector.
2733 unsigned NumConcat = WidenNumElts/InVTNumElts;
2734 SmallVector<SDValue, 16> Ops(NumConcat);
2736 SDValue UndefVal = DAG.getUNDEF(InVT);
2737 for (unsigned i = 1; i != NumConcat; ++i)
2740 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, Ops);
2741 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2745 if (InVTNumElts % WidenNumElts == 0) {
2746 // Extract the input and convert the shorten input vector.
2748 ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
2749 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2750 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2755 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2756 SmallVector<SDValue, 16> Ops(WidenNumElts);
2757 EVT EltVT = WidenVT.getVectorElementType();
2758 DTyOp = DAG.getValueType(EltVT);
2759 STyOp = DAG.getValueType(InEltVT);
2761 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2763 for (i=0; i < MinElts; ++i) {
2764 SDValue ExtVal = DAG.getNode(
2765 ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2766 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2767 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
2771 SDValue UndefVal = DAG.getUNDEF(EltVT);
2772 for (; i < WidenNumElts; ++i)
2775 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2778 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
2779 EVT VT = N->getValueType(0);
2780 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2781 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2782 SDValue InOp = N->getOperand(0);
2783 SDValue Idx = N->getOperand(1);
2786 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2787 InOp = GetWidenedVector(InOp);
2789 EVT InVT = InOp.getValueType();
2791 // Check if we can just return the input vector after widening.
2792 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2793 if (IdxVal == 0 && InVT == WidenVT)
2796 // Check if we can extract from the vector.
2797 unsigned InNumElts = InVT.getVectorNumElements();
2798 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
2799 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
2801 // We could try widening the input to the right length but for now, extract
2802 // the original elements, fill the rest with undefs and build a vector.
2803 SmallVector<SDValue, 16> Ops(WidenNumElts);
2804 EVT EltVT = VT.getVectorElementType();
2805 unsigned NumElts = VT.getVectorNumElements();
2807 for (i=0; i < NumElts; ++i)
2809 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2810 DAG.getConstant(IdxVal + i, dl,
2811 TLI.getVectorIdxTy(DAG.getDataLayout())));
2813 SDValue UndefVal = DAG.getUNDEF(EltVT);
2814 for (; i < WidenNumElts; ++i)
2816 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2819 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
2820 SDValue InOp = GetWidenedVector(N->getOperand(0));
2821 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
2822 InOp.getValueType(), InOp,
2823 N->getOperand(1), N->getOperand(2));
2826 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
2827 LoadSDNode *LD = cast<LoadSDNode>(N);
2828 ISD::LoadExtType ExtType = LD->getExtensionType();
2831 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
2832 if (ExtType != ISD::NON_EXTLOAD)
2833 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
2835 Result = GenWidenVectorLoads(LdChain, LD);
2837 // If we generate a single load, we can use that for the chain. Otherwise,
2838 // build a factor node to remember the multiple loads are independent and
2841 if (LdChain.size() == 1)
2842 NewChain = LdChain[0];
2844 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
2846 // Modified the chain - switch anything that used the old chain to use
2848 ReplaceValueWith(SDValue(N, 1), NewChain);
2853 SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {
2855 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),N->getValueType(0));
2856 SDValue Mask = N->getMask();
2857 EVT MaskVT = Mask.getValueType();
2858 SDValue Src0 = GetWidenedVector(N->getSrc0());
2859 ISD::LoadExtType ExtType = N->getExtensionType();
2862 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
2863 Mask = GetWidenedVector(Mask);
2865 EVT BoolVT = getSetCCResultType(WidenVT);
2867 // We can't use ModifyToType() because we should fill the mask with
2869 unsigned WidenNumElts = BoolVT.getVectorNumElements();
2870 unsigned MaskNumElts = MaskVT.getVectorNumElements();
2872 unsigned NumConcat = WidenNumElts / MaskNumElts;
2873 SmallVector<SDValue, 16> Ops(NumConcat);
2874 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
2876 for (unsigned i = 1; i != NumConcat; ++i)
2879 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
2882 SDValue Res = DAG.getMaskedLoad(WidenVT, dl, N->getChain(), N->getBasePtr(),
2883 Mask, Src0, N->getMemoryVT(),
2884 N->getMemOperand(), ExtType);
2885 // Legalize the chain result - switch anything that used the old chain to
2887 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2891 SDValue DAGTypeLegalizer::WidenVecRes_MGATHER(MaskedGatherSDNode *N) {
2893 EVT WideVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2894 SDValue Mask = N->getMask();
2895 SDValue Src0 = GetWidenedVector(N->getValue());
2896 unsigned NumElts = WideVT.getVectorNumElements();
2899 // The mask should be widened as well
2900 Mask = WidenTargetBoolean(Mask, WideVT, true);
2902 // Widen the Index operand
2903 SDValue Index = N->getIndex();
2904 EVT WideIndexVT = EVT::getVectorVT(*DAG.getContext(),
2905 Index.getValueType().getScalarType(),
2907 Index = ModifyToType(Index, WideIndexVT);
2908 SDValue Ops[] = { N->getChain(), Src0, Mask, N->getBasePtr(), Index };
2909 SDValue Res = DAG.getMaskedGather(DAG.getVTList(WideVT, MVT::Other),
2910 N->getMemoryVT(), dl, Ops,
2911 N->getMemOperand());
2913 // Legalize the chain result - switch anything that used the old chain to
2915 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2919 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
2920 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2921 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
2922 WidenVT, N->getOperand(0));
2925 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
2926 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2927 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2929 SDValue Cond1 = N->getOperand(0);
2930 EVT CondVT = Cond1.getValueType();
2931 if (CondVT.isVector()) {
2932 EVT CondEltVT = CondVT.getVectorElementType();
2933 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
2934 CondEltVT, WidenNumElts);
2935 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
2936 Cond1 = GetWidenedVector(Cond1);
2938 // If we have to split the condition there is no point in widening the
2939 // select. This would result in an cycle of widening the select ->
2940 // widening the condition operand -> splitting the condition operand ->
2941 // splitting the select -> widening the select. Instead split this select
2942 // further and widen the resulting type.
2943 if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
2944 SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
2945 SDValue Res = ModifyToType(SplitSelect, WidenVT);
2949 if (Cond1.getValueType() != CondWidenVT)
2950 Cond1 = ModifyToType(Cond1, CondWidenVT);
2953 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2954 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
2955 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
2956 return DAG.getNode(N->getOpcode(), SDLoc(N),
2957 WidenVT, Cond1, InOp1, InOp2);
2960 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
2961 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
2962 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
2963 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
2964 InOp1.getValueType(), N->getOperand(0),
2965 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
2968 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
2969 assert(N->getValueType(0).isVector() ==
2970 N->getOperand(0).getValueType().isVector() &&
2971 "Scalar/Vector type mismatch");
2972 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
2974 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2975 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2976 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2977 return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT,
2978 InOp1, InOp2, N->getOperand(2));
2981 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
2982 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2983 return DAG.getUNDEF(WidenVT);
2986 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
2987 EVT VT = N->getValueType(0);
2990 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2991 unsigned NumElts = VT.getVectorNumElements();
2992 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2994 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2995 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2997 // Adjust mask based on new input vector length.
2998 SmallVector<int, 16> NewMask;
2999 for (unsigned i = 0; i != NumElts; ++i) {
3000 int Idx = N->getMaskElt(i);
3001 if (Idx < (int)NumElts)
3002 NewMask.push_back(Idx);
3004 NewMask.push_back(Idx - NumElts + WidenNumElts);
3006 for (unsigned i = NumElts; i != WidenNumElts; ++i)
3007 NewMask.push_back(-1);
3008 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, NewMask);
3011 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
3012 assert(N->getValueType(0).isVector() &&
3013 N->getOperand(0).getValueType().isVector() &&
3014 "Operands must be vectors");
3015 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3016 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3018 SDValue InOp1 = N->getOperand(0);
3019 EVT InVT = InOp1.getValueType();
3020 assert(InVT.isVector() && "can not widen non-vector type");
3021 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
3022 InVT.getVectorElementType(), WidenNumElts);
3024 // The input and output types often differ here, and it could be that while
3025 // we'd prefer to widen the result type, the input operands have been split.
3026 // In this case, we also need to split the result of this node as well.
3027 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
3028 SDValue SplitVSetCC = SplitVecOp_VSETCC(N);
3029 SDValue Res = ModifyToType(SplitVSetCC, WidenVT);
3033 InOp1 = GetWidenedVector(InOp1);
3034 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
3036 // Assume that the input and output will be widen appropriately. If not,
3037 // we will have to unroll it at some point.
3038 assert(InOp1.getValueType() == WidenInVT &&
3039 InOp2.getValueType() == WidenInVT &&
3040 "Input not widened to expected type!");
3042 return DAG.getNode(ISD::SETCC, SDLoc(N),
3043 WidenVT, InOp1, InOp2, N->getOperand(2));
3047 //===----------------------------------------------------------------------===//
3048 // Widen Vector Operand
3049 //===----------------------------------------------------------------------===//
3050 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
3051 DEBUG(dbgs() << "Widen node operand " << OpNo << ": ";
3054 SDValue Res = SDValue();
3056 // See if the target wants to custom widen this node.
3057 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
3060 switch (N->getOpcode()) {
3063 dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
3067 llvm_unreachable("Do not know how to widen this operator's operand!");
3069 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
3070 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
3071 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
3072 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
3073 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
3074 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break;
3075 case ISD::MSCATTER: Res = WidenVecOp_MSCATTER(N, OpNo); break;
3076 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
3077 case ISD::FCOPYSIGN: Res = WidenVecOp_FCOPYSIGN(N); break;
3079 case ISD::ANY_EXTEND:
3080 case ISD::SIGN_EXTEND:
3081 case ISD::ZERO_EXTEND:
3082 Res = WidenVecOp_EXTEND(N);
3085 case ISD::FP_EXTEND:
3086 case ISD::FP_TO_SINT:
3087 case ISD::FP_TO_UINT:
3088 case ISD::SINT_TO_FP:
3089 case ISD::UINT_TO_FP:
3091 Res = WidenVecOp_Convert(N);
3095 // If Res is null, the sub-method took care of registering the result.
3096 if (!Res.getNode()) return false;
3098 // If the result is N, the sub-method updated N in place. Tell the legalizer
3100 if (Res.getNode() == N)
3104 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
3105 "Invalid operand expansion");
3107 ReplaceValueWith(SDValue(N, 0), Res);
3111 SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
3113 EVT VT = N->getValueType(0);
3115 SDValue InOp = N->getOperand(0);
3116 // If some legalization strategy other than widening is used on the operand,
3117 // we can't safely assume that just extending the low lanes is the correct
3119 if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
3120 return WidenVecOp_Convert(N);
3121 InOp = GetWidenedVector(InOp);
3122 assert(VT.getVectorNumElements() <
3123 InOp.getValueType().getVectorNumElements() &&
3124 "Input wasn't widened!");
3126 // We may need to further widen the operand until it has the same total
3127 // vector size as the result.
3128 EVT InVT = InOp.getValueType();
3129 if (InVT.getSizeInBits() != VT.getSizeInBits()) {
3130 EVT InEltVT = InVT.getVectorElementType();
3131 for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {
3132 EVT FixedVT = (MVT::SimpleValueType)i;
3133 EVT FixedEltVT = FixedVT.getVectorElementType();
3134 if (TLI.isTypeLegal(FixedVT) &&
3135 FixedVT.getSizeInBits() == VT.getSizeInBits() &&
3136 FixedEltVT == InEltVT) {
3137 assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&
3138 "Not enough elements in the fixed type for the operand!");
3139 assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&
3140 "We can't have the same type as we started with!");
3141 if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
3143 ISD::INSERT_SUBVECTOR, DL, FixedVT, DAG.getUNDEF(FixedVT), InOp,
3144 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3147 ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
3148 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3152 InVT = InOp.getValueType();
3153 if (InVT.getSizeInBits() != VT.getSizeInBits())
3154 // We couldn't find a legal vector type that was a widening of the input
3155 // and could be extended in-register to the result type, so we have to
3157 return WidenVecOp_Convert(N);
3160 // Use special DAG nodes to represent the operation of extending the
3162 switch (N->getOpcode()) {
3164 llvm_unreachable("Extend legalization on on extend operation!");
3165 case ISD::ANY_EXTEND:
3166 return DAG.getAnyExtendVectorInReg(InOp, DL, VT);
3167 case ISD::SIGN_EXTEND:
3168 return DAG.getSignExtendVectorInReg(InOp, DL, VT);
3169 case ISD::ZERO_EXTEND:
3170 return DAG.getZeroExtendVectorInReg(InOp, DL, VT);
3174 SDValue DAGTypeLegalizer::WidenVecOp_FCOPYSIGN(SDNode *N) {
3175 // The result (and first input) is legal, but the second input is illegal.
3176 // We can't do much to fix that, so just unroll and let the extracts off of
3177 // the second input be widened as needed later.
3178 return DAG.UnrollVectorOp(N);
3181 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
3182 // Since the result is legal and the input is illegal, it is unlikely that we
3183 // can fix the input to a legal type so unroll the convert into some scalar
3184 // code and create a nasty build vector.
3185 EVT VT = N->getValueType(0);
3186 EVT EltVT = VT.getVectorElementType();
3188 unsigned NumElts = VT.getVectorNumElements();
3189 SDValue InOp = N->getOperand(0);
3190 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
3191 InOp = GetWidenedVector(InOp);
3192 EVT InVT = InOp.getValueType();
3193 EVT InEltVT = InVT.getVectorElementType();
3195 unsigned Opcode = N->getOpcode();
3196 SmallVector<SDValue, 16> Ops(NumElts);
3197 for (unsigned i=0; i < NumElts; ++i)
3198 Ops[i] = DAG.getNode(
3201 ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
3202 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
3204 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3207 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
3208 EVT VT = N->getValueType(0);
3209 SDValue InOp = GetWidenedVector(N->getOperand(0));
3210 EVT InWidenVT = InOp.getValueType();
3213 // Check if we can convert between two legal vector types and extract.
3214 unsigned InWidenSize = InWidenVT.getSizeInBits();
3215 unsigned Size = VT.getSizeInBits();
3216 // x86mmx is not an acceptable vector element type, so don't try.
3217 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
3218 unsigned NewNumElts = InWidenSize / Size;
3219 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
3220 if (TLI.isTypeLegal(NewVT)) {
3221 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
3223 ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
3224 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3228 return CreateStackStoreLoad(InOp, VT);
3231 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
3232 // If the input vector is not legal, it is likely that we will not find a
3233 // legal vector of the same size. Replace the concatenate vector with a
3234 // nasty build vector.
3235 EVT VT = N->getValueType(0);
3236 EVT EltVT = VT.getVectorElementType();
3238 unsigned NumElts = VT.getVectorNumElements();
3239 SmallVector<SDValue, 16> Ops(NumElts);
3241 EVT InVT = N->getOperand(0).getValueType();
3242 unsigned NumInElts = InVT.getVectorNumElements();
3245 unsigned NumOperands = N->getNumOperands();
3246 for (unsigned i=0; i < NumOperands; ++i) {
3247 SDValue InOp = N->getOperand(i);
3248 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
3249 InOp = GetWidenedVector(InOp);
3250 for (unsigned j=0; j < NumInElts; ++j)
3251 Ops[Idx++] = DAG.getNode(
3252 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3253 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3255 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3258 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
3259 SDValue InOp = GetWidenedVector(N->getOperand(0));
3260 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
3261 N->getValueType(0), InOp, N->getOperand(1));
3264 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3265 SDValue InOp = GetWidenedVector(N->getOperand(0));
3266 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
3267 N->getValueType(0), InOp, N->getOperand(1));
3270 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
3271 // We have to widen the value, but we want only to store the original
3273 StoreSDNode *ST = cast<StoreSDNode>(N);
3275 SmallVector<SDValue, 16> StChain;
3276 if (ST->isTruncatingStore())
3277 GenWidenVectorTruncStores(StChain, ST);
3279 GenWidenVectorStores(StChain, ST);
3281 if (StChain.size() == 1)
3284 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
3287 SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
3288 MaskedStoreSDNode *MST = cast<MaskedStoreSDNode>(N);
3289 SDValue Mask = MST->getMask();
3290 EVT MaskVT = Mask.getValueType();
3291 SDValue StVal = MST->getValue();
3293 SDValue WideVal = GetWidenedVector(StVal);
3296 if (OpNo == 2 || getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
3297 Mask = GetWidenedVector(Mask);
3299 // The mask should be widened as well.
3300 EVT BoolVT = getSetCCResultType(WideVal.getValueType());
3301 // We can't use ModifyToType() because we should fill the mask with
3303 unsigned WidenNumElts = BoolVT.getVectorNumElements();
3304 unsigned MaskNumElts = MaskVT.getVectorNumElements();
3306 unsigned NumConcat = WidenNumElts / MaskNumElts;
3307 SmallVector<SDValue, 16> Ops(NumConcat);
3308 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
3310 for (unsigned i = 1; i != NumConcat; ++i)
3313 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
3315 assert(Mask.getValueType().getVectorNumElements() ==
3316 WideVal.getValueType().getVectorNumElements() &&
3317 "Mask and data vectors should have the same number of elements");
3318 return DAG.getMaskedStore(MST->getChain(), dl, WideVal, MST->getBasePtr(),
3319 Mask, MST->getMemoryVT(), MST->getMemOperand(),
3323 SDValue DAGTypeLegalizer::WidenVecOp_MSCATTER(SDNode *N, unsigned OpNo) {
3324 assert(OpNo == 1 && "Can widen only data operand of mscatter");
3325 MaskedScatterSDNode *MSC = cast<MaskedScatterSDNode>(N);
3326 SDValue DataOp = MSC->getValue();
3327 SDValue Mask = MSC->getMask();
3330 SDValue WideVal = GetWidenedVector(DataOp);
3331 EVT WideVT = WideVal.getValueType();
3332 unsigned NumElts = WideVal.getValueType().getVectorNumElements();
3335 // The mask should be widened as well.
3336 Mask = WidenTargetBoolean(Mask, WideVT, true);
3339 SDValue Index = MSC->getIndex();
3340 EVT WideIndexVT = EVT::getVectorVT(*DAG.getContext(),
3341 Index.getValueType().getScalarType(),
3343 Index = ModifyToType(Index, WideIndexVT);
3345 SDValue Ops[] = {MSC->getChain(), WideVal, Mask, MSC->getBasePtr(), Index};
3346 return DAG.getMaskedScatter(DAG.getVTList(MVT::Other),
3347 MSC->getMemoryVT(), dl, Ops,
3348 MSC->getMemOperand());
3351 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
3352 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
3353 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
3356 // WARNING: In this code we widen the compare instruction with garbage.
3357 // This garbage may contain denormal floats which may be slow. Is this a real
3358 // concern ? Should we zero the unused lanes if this is a float compare ?
3360 // Get a new SETCC node to compare the newly widened operands.
3361 // Only some of the compared elements are legal.
3362 EVT SVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
3363 InOp0.getValueType());
3364 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
3365 SVT, InOp0, InOp1, N->getOperand(2));
3367 // Extract the needed results from the result vector.
3368 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
3369 SVT.getVectorElementType(),
3370 N->getValueType(0).getVectorNumElements());
3371 SDValue CC = DAG.getNode(
3372 ISD::EXTRACT_SUBVECTOR, dl, ResVT, WideSETCC,
3373 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3375 return PromoteTargetBoolean(CC, N->getValueType(0));
3379 //===----------------------------------------------------------------------===//
3380 // Vector Widening Utilities
3381 //===----------------------------------------------------------------------===//
3383 // Utility function to find the type to chop up a widen vector for load/store
3384 // TLI: Target lowering used to determine legal types.
3385 // Width: Width left need to load/store.
3386 // WidenVT: The widen vector type to load to/store from
3387 // Align: If 0, don't allow use of a wider type
3388 // WidenEx: If Align is not 0, the amount additional we can load/store from.
3390 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
3391 unsigned Width, EVT WidenVT,
3392 unsigned Align = 0, unsigned WidenEx = 0) {
3393 EVT WidenEltVT = WidenVT.getVectorElementType();
3394 unsigned WidenWidth = WidenVT.getSizeInBits();
3395 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
3396 unsigned AlignInBits = Align*8;
3398 // If we have one element to load/store, return it.
3399 EVT RetVT = WidenEltVT;
3400 if (Width == WidenEltWidth)
3403 // See if there is larger legal integer than the element type to load/store.
3405 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
3406 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
3407 EVT MemVT((MVT::SimpleValueType) VT);
3408 unsigned MemVTWidth = MemVT.getSizeInBits();
3409 if (MemVT.getSizeInBits() <= WidenEltWidth)
3411 auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT);
3412 if ((Action == TargetLowering::TypeLegal ||
3413 Action == TargetLowering::TypePromoteInteger) &&
3414 (WidenWidth % MemVTWidth) == 0 &&
3415 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3416 (MemVTWidth <= Width ||
3417 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3423 // See if there is a larger vector type to load/store that has the same vector
3424 // element type and is evenly divisible with the WidenVT.
3425 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
3426 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
3427 EVT MemVT = (MVT::SimpleValueType) VT;
3428 unsigned MemVTWidth = MemVT.getSizeInBits();
3429 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
3430 (WidenWidth % MemVTWidth) == 0 &&
3431 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3432 (MemVTWidth <= Width ||
3433 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3434 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
3442 // Builds a vector type from scalar loads
3443 // VecTy: Resulting Vector type
3444 // LDOps: Load operators to build a vector type
3445 // [Start,End) the list of loads to use.
3446 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
3447 SmallVectorImpl<SDValue> &LdOps,
3448 unsigned Start, unsigned End) {
3449 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3450 SDLoc dl(LdOps[Start]);
3451 EVT LdTy = LdOps[Start].getValueType();
3452 unsigned Width = VecTy.getSizeInBits();
3453 unsigned NumElts = Width / LdTy.getSizeInBits();
3454 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
3457 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
3459 for (unsigned i = Start + 1; i != End; ++i) {
3460 EVT NewLdTy = LdOps[i].getValueType();
3461 if (NewLdTy != LdTy) {
3462 NumElts = Width / NewLdTy.getSizeInBits();
3463 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
3464 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
3465 // Readjust position and vector position based on new load type.
3466 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
3469 VecOp = DAG.getNode(
3470 ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
3471 DAG.getConstant(Idx++, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3473 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
3476 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
3478 // The strategy assumes that we can efficiently load power-of-two widths.
3479 // The routine chops the vector into the largest vector loads with the same
3480 // element type or scalar loads and then recombines it to the widen vector
3482 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3483 unsigned WidenWidth = WidenVT.getSizeInBits();
3484 EVT LdVT = LD->getMemoryVT();
3486 assert(LdVT.isVector() && WidenVT.isVector());
3487 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
3490 SDValue Chain = LD->getChain();
3491 SDValue BasePtr = LD->getBasePtr();
3492 unsigned Align = LD->getAlignment();
3493 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
3494 AAMDNodes AAInfo = LD->getAAInfo();
3496 int LdWidth = LdVT.getSizeInBits();
3497 int WidthDiff = WidenWidth - LdWidth;
3498 unsigned LdAlign = LD->isVolatile() ? 0 : Align; // Allow wider loads.
3500 // Find the vector type that can load from.
3501 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3502 int NewVTWidth = NewVT.getSizeInBits();
3503 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
3504 Align, MMOFlags, AAInfo);
3505 LdChain.push_back(LdOp.getValue(1));
3507 // Check if we can load the element with one instruction.
3508 if (LdWidth <= NewVTWidth) {
3509 if (!NewVT.isVector()) {
3510 unsigned NumElts = WidenWidth / NewVTWidth;
3511 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3512 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
3513 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
3515 if (NewVT == WidenVT)
3518 assert(WidenWidth % NewVTWidth == 0);
3519 unsigned NumConcat = WidenWidth / NewVTWidth;
3520 SmallVector<SDValue, 16> ConcatOps(NumConcat);
3521 SDValue UndefVal = DAG.getUNDEF(NewVT);
3522 ConcatOps[0] = LdOp;
3523 for (unsigned i = 1; i != NumConcat; ++i)
3524 ConcatOps[i] = UndefVal;
3525 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
3528 // Load vector by using multiple loads from largest vector to scalar.
3529 SmallVector<SDValue, 16> LdOps;
3530 LdOps.push_back(LdOp);
3532 LdWidth -= NewVTWidth;
3533 unsigned Offset = 0;
3535 while (LdWidth > 0) {
3536 unsigned Increment = NewVTWidth / 8;
3537 Offset += Increment;
3538 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3539 DAG.getConstant(Increment, dl, BasePtr.getValueType()));
3542 if (LdWidth < NewVTWidth) {
3543 // The current type we are using is too large. Find a better size.
3544 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3545 NewVTWidth = NewVT.getSizeInBits();
3546 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3547 LD->getPointerInfo().getWithOffset(Offset),
3548 MinAlign(Align, Increment), MMOFlags, AAInfo);
3549 LdChain.push_back(L.getValue(1));
3550 if (L->getValueType(0).isVector()) {
3551 SmallVector<SDValue, 16> Loads;
3553 unsigned size = L->getValueSizeInBits(0);
3554 while (size < LdOp->getValueSizeInBits(0)) {
3555 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
3556 size += L->getValueSizeInBits(0);
3558 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
3561 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3562 LD->getPointerInfo().getWithOffset(Offset),
3563 MinAlign(Align, Increment), MMOFlags, AAInfo);
3564 LdChain.push_back(L.getValue(1));
3570 LdWidth -= NewVTWidth;
3573 // Build the vector from the load operations.
3574 unsigned End = LdOps.size();
3575 if (!LdOps[0].getValueType().isVector())
3576 // All the loads are scalar loads.
3577 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
3579 // If the load contains vectors, build the vector using concat vector.
3580 // All of the vectors used to load are power-of-2, and the scalar loads can be
3581 // combined to make a power-of-2 vector.
3582 SmallVector<SDValue, 16> ConcatOps(End);
3585 EVT LdTy = LdOps[i].getValueType();
3586 // First, combine the scalar loads to a vector.
3587 if (!LdTy.isVector()) {
3588 for (--i; i >= 0; --i) {
3589 LdTy = LdOps[i].getValueType();
3590 if (LdTy.isVector())
3593 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i + 1, End);
3595 ConcatOps[--Idx] = LdOps[i];
3596 for (--i; i >= 0; --i) {
3597 EVT NewLdTy = LdOps[i].getValueType();
3598 if (NewLdTy != LdTy) {
3599 // Create a larger vector.
3600 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
3601 makeArrayRef(&ConcatOps[Idx], End - Idx));
3605 ConcatOps[--Idx] = LdOps[i];
3608 if (WidenWidth == LdTy.getSizeInBits() * (End - Idx))
3609 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
3610 makeArrayRef(&ConcatOps[Idx], End - Idx));
3612 // We need to fill the rest with undefs to build the vector.
3613 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
3614 SmallVector<SDValue, 16> WidenOps(NumOps);
3615 SDValue UndefVal = DAG.getUNDEF(LdTy);
3618 for (; i != End-Idx; ++i)
3619 WidenOps[i] = ConcatOps[Idx+i];
3620 for (; i != NumOps; ++i)
3621 WidenOps[i] = UndefVal;
3623 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
3627 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
3629 ISD::LoadExtType ExtType) {
3630 // For extension loads, it may not be more efficient to chop up the vector
3631 // and then extend it. Instead, we unroll the load and build a new vector.
3632 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3633 EVT LdVT = LD->getMemoryVT();
3635 assert(LdVT.isVector() && WidenVT.isVector());
3638 SDValue Chain = LD->getChain();
3639 SDValue BasePtr = LD->getBasePtr();
3640 unsigned Align = LD->getAlignment();
3641 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
3642 AAMDNodes AAInfo = LD->getAAInfo();
3644 EVT EltVT = WidenVT.getVectorElementType();
3645 EVT LdEltVT = LdVT.getVectorElementType();
3646 unsigned NumElts = LdVT.getVectorNumElements();
3648 // Load each element and widen.
3649 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3650 SmallVector<SDValue, 16> Ops(WidenNumElts);
3651 unsigned Increment = LdEltVT.getSizeInBits() / 8;
3653 DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, LD->getPointerInfo(),
3654 LdEltVT, Align, MMOFlags, AAInfo);
3655 LdChain.push_back(Ops[0].getValue(1));
3656 unsigned i = 0, Offset = Increment;
3657 for (i=1; i < NumElts; ++i, Offset += Increment) {
3658 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3660 DAG.getConstant(Offset, dl,
3661 BasePtr.getValueType()));
3662 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
3663 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
3664 Align, MMOFlags, AAInfo);
3665 LdChain.push_back(Ops[i].getValue(1));
3668 // Fill the rest with undefs.
3669 SDValue UndefVal = DAG.getUNDEF(EltVT);
3670 for (; i != WidenNumElts; ++i)
3673 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
3677 void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
3679 // The strategy assumes that we can efficiently store power-of-two widths.
3680 // The routine chops the vector into the largest vector stores with the same
3681 // element type or scalar stores.
3682 SDValue Chain = ST->getChain();
3683 SDValue BasePtr = ST->getBasePtr();
3684 unsigned Align = ST->getAlignment();
3685 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
3686 AAMDNodes AAInfo = ST->getAAInfo();
3687 SDValue ValOp = GetWidenedVector(ST->getValue());
3690 EVT StVT = ST->getMemoryVT();
3691 unsigned StWidth = StVT.getSizeInBits();
3692 EVT ValVT = ValOp.getValueType();
3693 unsigned ValWidth = ValVT.getSizeInBits();
3694 EVT ValEltVT = ValVT.getVectorElementType();
3695 unsigned ValEltWidth = ValEltVT.getSizeInBits();
3696 assert(StVT.getVectorElementType() == ValEltVT);
3698 int Idx = 0; // current index to store
3699 unsigned Offset = 0; // offset from base to store
3700 while (StWidth != 0) {
3701 // Find the largest vector type we can store with.
3702 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
3703 unsigned NewVTWidth = NewVT.getSizeInBits();
3704 unsigned Increment = NewVTWidth / 8;
3705 if (NewVT.isVector()) {
3706 unsigned NumVTElts = NewVT.getVectorNumElements();
3708 SDValue EOp = DAG.getNode(
3709 ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
3710 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3711 StChain.push_back(DAG.getStore(
3712 Chain, dl, EOp, BasePtr, ST->getPointerInfo().getWithOffset(Offset),
3713 MinAlign(Align, Offset), MMOFlags, AAInfo));
3714 StWidth -= NewVTWidth;
3715 Offset += Increment;
3717 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3718 DAG.getConstant(Increment, dl,
3719 BasePtr.getValueType()));
3720 } while (StWidth != 0 && StWidth >= NewVTWidth);
3722 // Cast the vector to the scalar type we can store.
3723 unsigned NumElts = ValWidth / NewVTWidth;
3724 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3725 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
3726 // Readjust index position based on new vector type.
3727 Idx = Idx * ValEltWidth / NewVTWidth;
3729 SDValue EOp = DAG.getNode(
3730 ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
3731 DAG.getConstant(Idx++, dl,
3732 TLI.getVectorIdxTy(DAG.getDataLayout())));
3733 StChain.push_back(DAG.getStore(
3734 Chain, dl, EOp, BasePtr, ST->getPointerInfo().getWithOffset(Offset),
3735 MinAlign(Align, Offset), MMOFlags, AAInfo));
3736 StWidth -= NewVTWidth;
3737 Offset += Increment;
3738 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3739 DAG.getConstant(Increment, dl,
3740 BasePtr.getValueType()));
3741 } while (StWidth != 0 && StWidth >= NewVTWidth);
3742 // Restore index back to be relative to the original widen element type.
3743 Idx = Idx * NewVTWidth / ValEltWidth;
3749 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
3751 // For extension loads, it may not be more efficient to truncate the vector
3752 // and then store it. Instead, we extract each element and then store it.
3753 SDValue Chain = ST->getChain();
3754 SDValue BasePtr = ST->getBasePtr();
3755 unsigned Align = ST->getAlignment();
3756 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
3757 AAMDNodes AAInfo = ST->getAAInfo();
3758 SDValue ValOp = GetWidenedVector(ST->getValue());
3761 EVT StVT = ST->getMemoryVT();
3762 EVT ValVT = ValOp.getValueType();
3764 // It must be true that the wide vector type is bigger than where we need to
3766 assert(StVT.isVector() && ValOp.getValueType().isVector());
3767 assert(StVT.bitsLT(ValOp.getValueType()));
3769 // For truncating stores, we can not play the tricks of chopping legal vector
3770 // types and bitcast it to the right type. Instead, we unroll the store.
3771 EVT StEltVT = StVT.getVectorElementType();
3772 EVT ValEltVT = ValVT.getVectorElementType();
3773 unsigned Increment = ValEltVT.getSizeInBits() / 8;
3774 unsigned NumElts = StVT.getVectorNumElements();
3775 SDValue EOp = DAG.getNode(
3776 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3777 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3778 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
3779 ST->getPointerInfo(), StEltVT, Align,
3781 unsigned Offset = Increment;
3782 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
3783 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3785 DAG.getConstant(Offset, dl,
3786 BasePtr.getValueType()));
3787 SDValue EOp = DAG.getNode(
3788 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3789 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3790 StChain.push_back(DAG.getTruncStore(
3791 Chain, dl, EOp, NewBasePtr, ST->getPointerInfo().getWithOffset(Offset),
3792 StEltVT, MinAlign(Align, Offset), MMOFlags, AAInfo));
3796 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
3797 /// input vector must have the same element type as NVT.
3798 /// FillWithZeroes specifies that the vector should be widened with zeroes.
3799 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT,
3800 bool FillWithZeroes) {
3801 // Note that InOp might have been widened so it might already have
3802 // the right width or it might need be narrowed.
3803 EVT InVT = InOp.getValueType();
3804 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
3805 "input and widen element type must match");
3808 // Check if InOp already has the right width.
3812 unsigned InNumElts = InVT.getVectorNumElements();
3813 unsigned WidenNumElts = NVT.getVectorNumElements();
3814 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
3815 unsigned NumConcat = WidenNumElts / InNumElts;
3816 SmallVector<SDValue, 16> Ops(NumConcat);
3817 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, InVT) :
3820 for (unsigned i = 1; i != NumConcat; ++i)
3823 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
3826 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
3828 ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
3829 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3831 // Fall back to extract and build.
3832 SmallVector<SDValue, 16> Ops(WidenNumElts);
3833 EVT EltVT = NVT.getVectorElementType();
3834 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
3836 for (Idx = 0; Idx < MinNumElts; ++Idx)
3837 Ops[Idx] = DAG.getNode(
3838 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3839 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3841 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, EltVT) :
3842 DAG.getUNDEF(EltVT);
3843 for ( ; Idx < WidenNumElts; ++Idx)
3845 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);