1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "legalize-types"
31 //===----------------------------------------------------------------------===//
32 // Result Vector Scalarization: <1 x ty> -> ty.
33 //===----------------------------------------------------------------------===//
35 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
39 SDValue R = SDValue();
41 switch (N->getOpcode()) {
44 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
48 report_fatal_error("Do not know how to scalarize the result of this "
51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
54 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
55 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
56 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
57 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
58 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
59 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
60 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
61 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
62 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
63 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
64 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
65 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
66 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
67 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
68 case ISD::ANY_EXTEND_VECTOR_INREG:
69 case ISD::SIGN_EXTEND_VECTOR_INREG:
70 case ISD::ZERO_EXTEND_VECTOR_INREG:
71 R = ScalarizeVecRes_VecInregOp(N);
77 case ISD::CTLZ_ZERO_UNDEF:
80 case ISD::CTTZ_ZERO_UNDEF:
100 case ISD::SIGN_EXTEND:
101 case ISD::SINT_TO_FP:
103 case ISD::UINT_TO_FP:
104 case ISD::ZERO_EXTEND:
105 case ISD::FCANONICALIZE:
106 R = ScalarizeVecRes_UnaryOp(N);
138 R = ScalarizeVecRes_BinOp(N);
141 R = ScalarizeVecRes_TernaryOp(N);
145 // If R is null, the sub-method took care of registering the result.
147 SetScalarizedVector(SDValue(N, ResNo), R);
150 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
151 SDValue LHS = GetScalarizedVector(N->getOperand(0));
152 SDValue RHS = GetScalarizedVector(N->getOperand(1));
153 return DAG.getNode(N->getOpcode(), SDLoc(N),
154 LHS.getValueType(), LHS, RHS, N->getFlags());
157 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
158 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
159 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
160 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
161 return DAG.getNode(N->getOpcode(), SDLoc(N),
162 Op0.getValueType(), Op0, Op1, Op2);
165 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
167 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
168 return GetScalarizedVector(Op);
171 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
172 EVT NewVT = N->getValueType(0).getVectorElementType();
173 return DAG.getNode(ISD::BITCAST, SDLoc(N),
174 NewVT, N->getOperand(0));
177 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
178 EVT EltVT = N->getValueType(0).getVectorElementType();
179 SDValue InOp = N->getOperand(0);
180 // The BUILD_VECTOR operands may be of wider element types and
181 // we may need to truncate them back to the requested return type.
182 if (EltVT.isInteger())
183 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
187 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
188 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
189 N->getValueType(0).getVectorElementType(),
190 N->getOperand(0), N->getOperand(1));
193 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
194 EVT NewVT = N->getValueType(0).getVectorElementType();
195 SDValue Op = GetScalarizedVector(N->getOperand(0));
196 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
197 NewVT, Op, N->getOperand(1));
200 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
201 SDValue Op = GetScalarizedVector(N->getOperand(0));
202 return DAG.getNode(ISD::FPOWI, SDLoc(N),
203 Op.getValueType(), Op, N->getOperand(1));
206 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
207 // The value to insert may have a wider type than the vector element type,
208 // so be sure to truncate it to the element type if necessary.
209 SDValue Op = N->getOperand(1);
210 EVT EltVT = N->getValueType(0).getVectorElementType();
211 if (Op.getValueType() != EltVT)
212 // FIXME: Can this happen for floating point types?
213 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
217 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
218 assert(N->isUnindexed() && "Indexed vector load?");
220 SDValue Result = DAG.getLoad(
221 ISD::UNINDEXED, N->getExtensionType(),
222 N->getValueType(0).getVectorElementType(), SDLoc(N), N->getChain(),
223 N->getBasePtr(), DAG.getUNDEF(N->getBasePtr().getValueType()),
224 N->getPointerInfo(), N->getMemoryVT().getVectorElementType(),
225 N->getOriginalAlignment(), N->getMemOperand()->getFlags(),
228 // Legalize the chain result - switch anything that used the old chain to
230 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
234 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
235 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
236 EVT DestVT = N->getValueType(0).getVectorElementType();
237 SDValue Op = N->getOperand(0);
238 EVT OpVT = Op.getValueType();
240 // The result needs scalarizing, but it's not a given that the source does.
241 // This is a workaround for targets where it's impossible to scalarize the
242 // result of a conversion, because the source type is legal.
243 // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
244 // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
245 // legal and was not scalarized.
246 // See the similar logic in ScalarizeVecRes_VSETCC
247 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
248 Op = GetScalarizedVector(Op);
250 EVT VT = OpVT.getVectorElementType();
252 ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
253 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
255 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
258 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
259 EVT EltVT = N->getValueType(0).getVectorElementType();
260 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
261 SDValue LHS = GetScalarizedVector(N->getOperand(0));
262 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
263 LHS, DAG.getValueType(ExtVT));
266 SDValue DAGTypeLegalizer::ScalarizeVecRes_VecInregOp(SDNode *N) {
268 SDValue Op = N->getOperand(0);
270 EVT OpVT = Op.getValueType();
271 EVT OpEltVT = OpVT.getVectorElementType();
272 EVT EltVT = N->getValueType(0).getVectorElementType();
274 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
275 Op = GetScalarizedVector(Op);
278 ISD::EXTRACT_VECTOR_ELT, DL, OpEltVT, Op,
279 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
282 switch (N->getOpcode()) {
283 case ISD::ANY_EXTEND_VECTOR_INREG:
284 return DAG.getNode(ISD::ANY_EXTEND, DL, EltVT, Op);
285 case ISD::SIGN_EXTEND_VECTOR_INREG:
286 return DAG.getNode(ISD::SIGN_EXTEND, DL, EltVT, Op);
287 case ISD::ZERO_EXTEND_VECTOR_INREG:
288 return DAG.getNode(ISD::ZERO_EXTEND, DL, EltVT, Op);
291 llvm_unreachable("Illegal extend_vector_inreg opcode");
294 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
295 // If the operand is wider than the vector element type then it is implicitly
296 // truncated. Make that explicit here.
297 EVT EltVT = N->getValueType(0).getVectorElementType();
298 SDValue InOp = N->getOperand(0);
299 if (InOp.getValueType() != EltVT)
300 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
304 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
305 SDValue Cond = GetScalarizedVector(N->getOperand(0));
306 SDValue LHS = GetScalarizedVector(N->getOperand(1));
307 TargetLowering::BooleanContent ScalarBool =
308 TLI.getBooleanContents(false, false);
309 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
311 // If integer and float booleans have different contents then we can't
312 // reliably optimize in all cases. There is a full explanation for this in
313 // DAGCombiner::visitSELECT() where the same issue affects folding
314 // (select C, 0, 1) to (xor C, 1).
315 if (TLI.getBooleanContents(false, false) !=
316 TLI.getBooleanContents(false, true)) {
317 // At least try the common case where the boolean is generated by a
319 if (Cond->getOpcode() == ISD::SETCC) {
320 EVT OpVT = Cond->getOperand(0)->getValueType(0);
321 ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
322 VecBool = TLI.getBooleanContents(OpVT);
324 ScalarBool = TargetLowering::UndefinedBooleanContent;
327 if (ScalarBool != VecBool) {
328 EVT CondVT = Cond.getValueType();
329 switch (ScalarBool) {
330 case TargetLowering::UndefinedBooleanContent:
332 case TargetLowering::ZeroOrOneBooleanContent:
333 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
334 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
335 // Vector read from all ones, scalar expects a single 1 so mask.
336 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
337 Cond, DAG.getConstant(1, SDLoc(N), CondVT));
339 case TargetLowering::ZeroOrNegativeOneBooleanContent:
340 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
341 VecBool == TargetLowering::ZeroOrOneBooleanContent);
342 // Vector reads from a one, scalar from all ones so sign extend.
343 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
344 Cond, DAG.getValueType(MVT::i1));
349 return DAG.getSelect(SDLoc(N),
350 LHS.getValueType(), Cond, LHS,
351 GetScalarizedVector(N->getOperand(2)));
354 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
355 SDValue LHS = GetScalarizedVector(N->getOperand(1));
356 return DAG.getSelect(SDLoc(N),
357 LHS.getValueType(), N->getOperand(0), LHS,
358 GetScalarizedVector(N->getOperand(2)));
361 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
362 SDValue LHS = GetScalarizedVector(N->getOperand(2));
363 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
364 N->getOperand(0), N->getOperand(1),
365 LHS, GetScalarizedVector(N->getOperand(3)),
369 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
370 assert(N->getValueType(0).isVector() ==
371 N->getOperand(0).getValueType().isVector() &&
372 "Scalar/Vector type mismatch");
374 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
376 SDValue LHS = GetScalarizedVector(N->getOperand(0));
377 SDValue RHS = GetScalarizedVector(N->getOperand(1));
380 // Turn it into a scalar SETCC.
381 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
384 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
385 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
388 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
389 // Figure out if the scalar is the LHS or RHS and return it.
390 SDValue Arg = N->getOperand(2).getOperand(0);
392 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
393 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
394 return GetScalarizedVector(N->getOperand(Op));
397 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
398 assert(N->getValueType(0).isVector() &&
399 N->getOperand(0).getValueType().isVector() &&
400 "Operand types must be vectors");
401 SDValue LHS = N->getOperand(0);
402 SDValue RHS = N->getOperand(1);
403 EVT OpVT = LHS.getValueType();
404 EVT NVT = N->getValueType(0).getVectorElementType();
407 // The result needs scalarizing, but it's not a given that the source does.
408 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
409 LHS = GetScalarizedVector(LHS);
410 RHS = GetScalarizedVector(RHS);
412 EVT VT = OpVT.getVectorElementType();
414 ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
415 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
417 ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
418 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
421 // Turn it into a scalar SETCC.
422 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
424 // Vectors may have a different boolean contents to scalars. Promote the
425 // value appropriately.
426 ISD::NodeType ExtendCode =
427 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
428 return DAG.getNode(ExtendCode, DL, NVT, Res);
432 //===----------------------------------------------------------------------===//
433 // Operand Vector Scalarization <1 x ty> -> ty.
434 //===----------------------------------------------------------------------===//
436 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
437 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
440 SDValue Res = SDValue();
442 if (!Res.getNode()) {
443 switch (N->getOpcode()) {
446 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
450 llvm_unreachable("Do not know how to scalarize this operator's operand!");
452 Res = ScalarizeVecOp_BITCAST(N);
454 case ISD::ANY_EXTEND:
455 case ISD::ZERO_EXTEND:
456 case ISD::SIGN_EXTEND:
458 case ISD::FP_TO_SINT:
459 case ISD::FP_TO_UINT:
460 case ISD::SINT_TO_FP:
461 case ISD::UINT_TO_FP:
462 Res = ScalarizeVecOp_UnaryOp(N);
464 case ISD::CONCAT_VECTORS:
465 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
467 case ISD::EXTRACT_VECTOR_ELT:
468 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
471 Res = ScalarizeVecOp_VSELECT(N);
474 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
477 Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
482 // If the result is null, the sub-method took care of registering results etc.
483 if (!Res.getNode()) return false;
485 // If the result is N, the sub-method updated N in place. Tell the legalizer
487 if (Res.getNode() == N)
490 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
491 "Invalid operand expansion");
493 ReplaceValueWith(SDValue(N, 0), Res);
497 /// If the value to convert is a vector that needs to be scalarized, it must be
498 /// <1 x ty>. Convert the element instead.
499 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
500 SDValue Elt = GetScalarizedVector(N->getOperand(0));
501 return DAG.getNode(ISD::BITCAST, SDLoc(N),
502 N->getValueType(0), Elt);
505 /// If the input is a vector that needs to be scalarized, it must be <1 x ty>.
506 /// Do the operation on the element instead.
507 SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
508 assert(N->getValueType(0).getVectorNumElements() == 1 &&
509 "Unexpected vector type!");
510 SDValue Elt = GetScalarizedVector(N->getOperand(0));
511 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
512 N->getValueType(0).getScalarType(), Elt);
513 // Revectorize the result so the types line up with what the uses of this
514 // expression expect.
515 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op);
518 /// The vectors to concatenate have length one - use a BUILD_VECTOR instead.
519 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
520 SmallVector<SDValue, 8> Ops(N->getNumOperands());
521 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
522 Ops[i] = GetScalarizedVector(N->getOperand(i));
523 return DAG.getBuildVector(N->getValueType(0), SDLoc(N), Ops);
526 /// If the input is a vector that needs to be scalarized, it must be <1 x ty>,
527 /// so just return the element, ignoring the index.
528 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
529 SDValue Res = GetScalarizedVector(N->getOperand(0));
530 if (Res.getValueType() != N->getValueType(0))
531 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0),
537 /// If the input condition is a vector that needs to be scalarized, it must be
538 /// <1 x i1>, so just convert to a normal ISD::SELECT
539 /// (still with vector output type since that was acceptable if we got here).
540 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {
541 SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));
542 EVT VT = N->getValueType(0);
544 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
548 /// If the value to store is a vector that needs to be scalarized, it must be
549 /// <1 x ty>. Just store the element.
550 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
551 assert(N->isUnindexed() && "Indexed store of one-element vector?");
552 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
555 if (N->isTruncatingStore())
556 return DAG.getTruncStore(
557 N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
558 N->getBasePtr(), N->getPointerInfo(),
559 N->getMemoryVT().getVectorElementType(), N->getAlignment(),
560 N->getMemOperand()->getFlags(), N->getAAInfo());
562 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
563 N->getBasePtr(), N->getPointerInfo(),
564 N->getOriginalAlignment(), N->getMemOperand()->getFlags(),
568 /// If the value to round is a vector that needs to be scalarized, it must be
569 /// <1 x ty>. Convert the element instead.
570 SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
571 SDValue Elt = GetScalarizedVector(N->getOperand(0));
572 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
573 N->getValueType(0).getVectorElementType(), Elt,
575 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
578 //===----------------------------------------------------------------------===//
579 // Result Vector Splitting
580 //===----------------------------------------------------------------------===//
582 /// This method is called when the specified result of the specified node is
583 /// found to need vector splitting. At this point, the node may also have
584 /// invalid operands or may have other results that need legalization, we just
585 /// know that (at least) one result needs vector splitting.
586 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
587 DEBUG(dbgs() << "Split node result: ";
592 // See if the target wants to custom expand this node.
593 if (CustomLowerNode(N, N->getValueType(ResNo), true))
596 switch (N->getOpcode()) {
599 dbgs() << "SplitVectorResult #" << ResNo << ": ";
603 report_fatal_error("Do not know how to split the result of this "
606 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
608 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
609 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
610 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
611 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
612 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
613 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
614 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
615 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
616 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
617 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
618 case ISD::FCOPYSIGN: SplitVecRes_FCOPYSIGN(N, Lo, Hi); break;
619 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
620 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
621 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
623 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
626 SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
629 SplitVecRes_MGATHER(cast<MaskedGatherSDNode>(N), Lo, Hi);
632 SplitVecRes_SETCC(N, Lo, Hi);
634 case ISD::VECTOR_SHUFFLE:
635 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
638 case ISD::ANY_EXTEND_VECTOR_INREG:
639 case ISD::SIGN_EXTEND_VECTOR_INREG:
640 case ISD::ZERO_EXTEND_VECTOR_INREG:
641 SplitVecRes_ExtVecInRegOp(N, Lo, Hi);
644 case ISD::BITREVERSE:
648 case ISD::CTLZ_ZERO_UNDEF:
649 case ISD::CTTZ_ZERO_UNDEF:
660 case ISD::FNEARBYINT:
664 case ISD::FP_TO_SINT:
665 case ISD::FP_TO_UINT:
671 case ISD::SINT_TO_FP:
673 case ISD::UINT_TO_FP:
674 case ISD::FCANONICALIZE:
675 SplitVecRes_UnaryOp(N, Lo, Hi);
678 case ISD::ANY_EXTEND:
679 case ISD::SIGN_EXTEND:
680 case ISD::ZERO_EXTEND:
681 SplitVecRes_ExtendOp(N, Lo, Hi);
713 SplitVecRes_BinOp(N, Lo, Hi);
716 SplitVecRes_TernaryOp(N, Lo, Hi);
720 // If Lo/Hi is null, the sub-method took care of registering results etc.
722 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
725 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
727 SDValue LHSLo, LHSHi;
728 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
729 SDValue RHSLo, RHSHi;
730 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
733 const SDNodeFlags *Flags = N->getFlags();
734 unsigned Opcode = N->getOpcode();
735 Lo = DAG.getNode(Opcode, dl, LHSLo.getValueType(), LHSLo, RHSLo, Flags);
736 Hi = DAG.getNode(Opcode, dl, LHSHi.getValueType(), LHSHi, RHSHi, Flags);
739 void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
741 SDValue Op0Lo, Op0Hi;
742 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
743 SDValue Op1Lo, Op1Hi;
744 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
745 SDValue Op2Lo, Op2Hi;
746 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
749 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
750 Op0Lo, Op1Lo, Op2Lo);
751 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
752 Op0Hi, Op1Hi, Op2Hi);
755 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
757 // We know the result is a vector. The input may be either a vector or a
760 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
763 SDValue InOp = N->getOperand(0);
764 EVT InVT = InOp.getValueType();
766 // Handle some special cases efficiently.
767 switch (getTypeAction(InVT)) {
768 case TargetLowering::TypeLegal:
769 case TargetLowering::TypePromoteInteger:
770 case TargetLowering::TypePromoteFloat:
771 case TargetLowering::TypeSoftenFloat:
772 case TargetLowering::TypeScalarizeVector:
773 case TargetLowering::TypeWidenVector:
775 case TargetLowering::TypeExpandInteger:
776 case TargetLowering::TypeExpandFloat:
777 // A scalar to vector conversion, where the scalar needs expansion.
778 // If the vector is being split in two then we can just convert the
781 GetExpandedOp(InOp, Lo, Hi);
782 if (DAG.getDataLayout().isBigEndian())
784 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
785 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
789 case TargetLowering::TypeSplitVector:
790 // If the input is a vector that needs to be split, convert each split
791 // piece of the input now.
792 GetSplitVector(InOp, Lo, Hi);
793 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
794 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
798 // In the general case, convert the input to an integer and split it by hand.
799 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
800 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
801 if (DAG.getDataLayout().isBigEndian())
802 std::swap(LoIntVT, HiIntVT);
804 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
806 if (DAG.getDataLayout().isBigEndian())
808 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
809 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
812 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
816 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
817 unsigned LoNumElts = LoVT.getVectorNumElements();
818 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
819 Lo = DAG.getBuildVector(LoVT, dl, LoOps);
821 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
822 Hi = DAG.getBuildVector(HiVT, dl, HiOps);
825 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
827 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
829 unsigned NumSubvectors = N->getNumOperands() / 2;
830 if (NumSubvectors == 1) {
831 Lo = N->getOperand(0);
832 Hi = N->getOperand(1);
837 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
839 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
840 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
842 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
843 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
846 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
848 SDValue Vec = N->getOperand(0);
849 SDValue Idx = N->getOperand(1);
853 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
855 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
856 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
857 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
858 DAG.getConstant(IdxVal + LoVT.getVectorNumElements(), dl,
859 TLI.getVectorIdxTy(DAG.getDataLayout())));
862 void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
864 SDValue Vec = N->getOperand(0);
865 SDValue SubVec = N->getOperand(1);
866 SDValue Idx = N->getOperand(2);
868 GetSplitVector(Vec, Lo, Hi);
870 EVT VecVT = Vec.getValueType();
871 unsigned VecElems = VecVT.getVectorNumElements();
872 unsigned SubElems = SubVec.getValueType().getVectorNumElements();
874 // If we know the index is 0, and we know the subvector doesn't cross the
875 // boundary between the halves, we can avoid spilling the vector, and insert
876 // into the lower half of the split vector directly.
877 // TODO: The IdxVal == 0 constraint is artificial, we could do this whenever
878 // the index is constant and there is no boundary crossing. But those cases
879 // don't seem to get hit in practice.
880 if (ConstantSDNode *ConstIdx = dyn_cast<ConstantSDNode>(Idx)) {
881 unsigned IdxVal = ConstIdx->getZExtValue();
882 if ((IdxVal == 0) && (IdxVal + SubElems <= VecElems / 2)) {
884 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
885 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx);
890 // Spill the vector to the stack.
891 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
893 DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, MachinePointerInfo());
895 // Store the new subvector into the specified index.
896 SDValue SubVecPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
897 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
898 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
899 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo());
901 // Load the Lo part from the stack slot.
903 DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo());
905 // Increment the pointer to the other part.
906 unsigned IncrementSize = Lo.getValueSizeInBits() / 8;
908 DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
909 DAG.getConstant(IncrementSize, dl, StackPtr.getValueType()));
911 // Load the Hi part from the stack slot.
912 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
913 MinAlign(Alignment, IncrementSize));
916 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
919 GetSplitVector(N->getOperand(0), Lo, Hi);
920 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
921 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
924 void DAGTypeLegalizer::SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo,
926 SDValue LHSLo, LHSHi;
927 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
930 SDValue RHSLo, RHSHi;
931 SDValue RHS = N->getOperand(1);
932 EVT RHSVT = RHS.getValueType();
933 if (getTypeAction(RHSVT) == TargetLowering::TypeSplitVector)
934 GetSplitVector(RHS, RHSLo, RHSHi);
936 std::tie(RHSLo, RHSHi) = DAG.SplitVector(RHS, SDLoc(RHS));
939 Lo = DAG.getNode(ISD::FCOPYSIGN, DL, LHSLo.getValueType(), LHSLo, RHSLo);
940 Hi = DAG.getNode(ISD::FCOPYSIGN, DL, LHSHi.getValueType(), LHSHi, RHSHi);
943 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
945 SDValue LHSLo, LHSHi;
946 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
950 std::tie(LoVT, HiVT) =
951 DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
953 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
954 DAG.getValueType(LoVT));
955 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
956 DAG.getValueType(HiVT));
959 void DAGTypeLegalizer::SplitVecRes_ExtVecInRegOp(SDNode *N, SDValue &Lo,
961 unsigned Opcode = N->getOpcode();
962 SDValue N0 = N->getOperand(0);
967 if (getTypeAction(N0.getValueType()) == TargetLowering::TypeSplitVector)
968 GetSplitVector(N0, InLo, InHi);
970 std::tie(InLo, InHi) = DAG.SplitVectorOperand(N, 0);
972 EVT InLoVT = InLo.getValueType();
973 unsigned InNumElements = InLoVT.getVectorNumElements();
975 EVT OutLoVT, OutHiVT;
976 std::tie(OutLoVT, OutHiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
977 unsigned OutNumElements = OutLoVT.getVectorNumElements();
978 assert((2 * OutNumElements) <= InNumElements &&
979 "Illegal extend vector in reg split");
981 // *_EXTEND_VECTOR_INREG instructions extend the lowest elements of the
982 // input vector (i.e. we only use InLo):
983 // OutLo will extend the first OutNumElements from InLo.
984 // OutHi will extend the next OutNumElements from InLo.
986 // Shuffle the elements from InLo for OutHi into the bottom elements to
987 // create a 'fake' InHi.
988 SmallVector<int, 8> SplitHi(InNumElements, -1);
989 for (unsigned i = 0; i != OutNumElements; ++i)
990 SplitHi[i] = i + OutNumElements;
991 InHi = DAG.getVectorShuffle(InLoVT, dl, InLo, DAG.getUNDEF(InLoVT), SplitHi);
993 Lo = DAG.getNode(Opcode, dl, OutLoVT, InLo);
994 Hi = DAG.getNode(Opcode, dl, OutHiVT, InHi);
997 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
999 SDValue Vec = N->getOperand(0);
1000 SDValue Elt = N->getOperand(1);
1001 SDValue Idx = N->getOperand(2);
1003 GetSplitVector(Vec, Lo, Hi);
1005 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
1006 unsigned IdxVal = CIdx->getZExtValue();
1007 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
1008 if (IdxVal < LoNumElts)
1009 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
1010 Lo.getValueType(), Lo, Elt, Idx);
1013 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
1014 DAG.getConstant(IdxVal - LoNumElts, dl,
1015 TLI.getVectorIdxTy(DAG.getDataLayout())));
1019 // See if the target wants to custom expand this node.
1020 if (CustomLowerNode(N, N->getValueType(0), true))
1023 // Spill the vector to the stack.
1024 EVT VecVT = Vec.getValueType();
1025 EVT EltVT = VecVT.getVectorElementType();
1026 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1028 DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, MachinePointerInfo());
1030 // Store the new element. This may be larger than the vector element type,
1031 // so use a truncating store.
1032 SDValue EltPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1033 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
1034 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
1036 DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT);
1038 // Load the Lo part from the stack slot.
1040 DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo());
1042 // Increment the pointer to the other part.
1043 unsigned IncrementSize = Lo.getValueSizeInBits() / 8;
1044 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
1045 DAG.getConstant(IncrementSize, dl,
1046 StackPtr.getValueType()));
1048 // Load the Hi part from the stack slot.
1049 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
1050 MinAlign(Alignment, IncrementSize));
1053 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
1057 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1058 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
1059 Hi = DAG.getUNDEF(HiVT);
1062 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
1064 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
1067 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
1069 ISD::LoadExtType ExtType = LD->getExtensionType();
1070 SDValue Ch = LD->getChain();
1071 SDValue Ptr = LD->getBasePtr();
1072 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
1073 EVT MemoryVT = LD->getMemoryVT();
1074 unsigned Alignment = LD->getOriginalAlignment();
1075 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
1076 AAMDNodes AAInfo = LD->getAAInfo();
1078 EVT LoMemVT, HiMemVT;
1079 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1081 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
1082 LD->getPointerInfo(), LoMemVT, Alignment, MMOFlags, AAInfo);
1084 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1085 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1086 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
1087 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
1088 LD->getPointerInfo().getWithOffset(IncrementSize), HiMemVT,
1089 Alignment, MMOFlags, AAInfo);
1091 // Build a factor node to remember that this load is independent of the
1093 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1096 // Legalize the chain result - switch anything that used the old chain to
1098 ReplaceValueWith(SDValue(LD, 1), Ch);
1101 void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
1102 SDValue &Lo, SDValue &Hi) {
1105 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
1107 SDValue Ch = MLD->getChain();
1108 SDValue Ptr = MLD->getBasePtr();
1109 SDValue Mask = MLD->getMask();
1110 SDValue Src0 = MLD->getSrc0();
1111 unsigned Alignment = MLD->getOriginalAlignment();
1112 ISD::LoadExtType ExtType = MLD->getExtensionType();
1114 // if Alignment is equal to the vector size,
1115 // take the half of it for the second part
1116 unsigned SecondHalfAlignment =
1117 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
1118 Alignment/2 : Alignment;
1120 // Split Mask operand
1121 SDValue MaskLo, MaskHi;
1122 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1123 GetSplitVector(Mask, MaskLo, MaskHi);
1125 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1127 EVT MemoryVT = MLD->getMemoryVT();
1128 EVT LoMemVT, HiMemVT;
1129 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1131 SDValue Src0Lo, Src0Hi;
1132 if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
1133 GetSplitVector(Src0, Src0Lo, Src0Hi);
1135 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1137 MachineMemOperand *MMO = DAG.getMachineFunction().
1138 getMachineMemOperand(MLD->getPointerInfo(),
1139 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1140 Alignment, MLD->getAAInfo(), MLD->getRanges());
1142 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, MaskLo, Src0Lo, LoMemVT, MMO,
1143 ExtType, MLD->isExpandingLoad());
1145 Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, dl, LoMemVT, DAG,
1146 MLD->isExpandingLoad());
1148 MMO = DAG.getMachineFunction().
1149 getMachineMemOperand(MLD->getPointerInfo(),
1150 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1151 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
1153 Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, MaskHi, Src0Hi, HiMemVT, MMO,
1154 ExtType, MLD->isExpandingLoad());
1157 // Build a factor node to remember that this load is independent of the
1159 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1162 // Legalize the chain result - switch anything that used the old chain to
1164 ReplaceValueWith(SDValue(MLD, 1), Ch);
1168 void DAGTypeLegalizer::SplitVecRes_MGATHER(MaskedGatherSDNode *MGT,
1169 SDValue &Lo, SDValue &Hi) {
1172 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1174 SDValue Ch = MGT->getChain();
1175 SDValue Ptr = MGT->getBasePtr();
1176 SDValue Mask = MGT->getMask();
1177 SDValue Src0 = MGT->getValue();
1178 SDValue Index = MGT->getIndex();
1179 unsigned Alignment = MGT->getOriginalAlignment();
1181 // Split Mask operand
1182 SDValue MaskLo, MaskHi;
1183 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1184 GetSplitVector(Mask, MaskLo, MaskHi);
1186 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1188 EVT MemoryVT = MGT->getMemoryVT();
1189 EVT LoMemVT, HiMemVT;
1191 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1193 SDValue Src0Lo, Src0Hi;
1194 if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
1195 GetSplitVector(Src0, Src0Lo, Src0Hi);
1197 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1199 SDValue IndexHi, IndexLo;
1200 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1201 GetSplitVector(Index, IndexLo, IndexHi);
1203 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1205 MachineMemOperand *MMO = DAG.getMachineFunction().
1206 getMachineMemOperand(MGT->getPointerInfo(),
1207 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1208 Alignment, MGT->getAAInfo(), MGT->getRanges());
1210 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1211 Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl, OpsLo,
1214 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1215 Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl, OpsHi,
1218 // Build a factor node to remember that this load is independent of the
1220 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1223 // Legalize the chain result - switch anything that used the old chain to
1225 ReplaceValueWith(SDValue(MGT, 1), Ch);
1229 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
1230 assert(N->getValueType(0).isVector() &&
1231 N->getOperand(0).getValueType().isVector() &&
1232 "Operand types must be vectors");
1236 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1239 SDValue LL, LH, RL, RH;
1240 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
1241 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
1243 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
1244 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
1247 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
1249 // Get the dest types - they may not match the input types, e.g. int_to_fp.
1252 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1254 // If the input also splits, handle it directly for a compile time speedup.
1255 // Otherwise split it by hand.
1256 EVT InVT = N->getOperand(0).getValueType();
1257 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1258 GetSplitVector(N->getOperand(0), Lo, Hi);
1260 std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
1262 if (N->getOpcode() == ISD::FP_ROUND) {
1263 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
1264 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
1266 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1267 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1271 void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
1274 EVT SrcVT = N->getOperand(0).getValueType();
1275 EVT DestVT = N->getValueType(0);
1277 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1279 // We can do better than a generic split operation if the extend is doing
1280 // more than just doubling the width of the elements and the following are
1282 // - The number of vector elements is even,
1283 // - the source type is legal,
1284 // - the type of a split source is illegal,
1285 // - the type of an extended (by doubling element size) source is legal, and
1286 // - the type of that extended source when split is legal.
1288 // This won't necessarily completely legalize the operation, but it will
1289 // more effectively move in the right direction and prevent falling down
1290 // to scalarization in many cases due to the input vector being split too
1292 unsigned NumElements = SrcVT.getVectorNumElements();
1293 if ((NumElements & 1) == 0 &&
1294 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
1295 LLVMContext &Ctx = *DAG.getContext();
1296 EVT NewSrcVT = EVT::getVectorVT(
1297 Ctx, EVT::getIntegerVT(
1298 Ctx, SrcVT.getScalarSizeInBits() * 2),
1301 EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2);
1302 EVT SplitLoVT, SplitHiVT;
1303 std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
1304 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
1305 TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
1306 DEBUG(dbgs() << "Split vector extend via incremental extend:";
1307 N->dump(&DAG); dbgs() << "\n");
1308 // Extend the source vector by one step.
1310 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
1311 // Get the low and high halves of the new, extended one step, vector.
1312 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
1313 // Extend those vector halves the rest of the way.
1314 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1315 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1319 // Fall back to the generic unary operator splitting otherwise.
1320 SplitVecRes_UnaryOp(N, Lo, Hi);
1323 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
1324 SDValue &Lo, SDValue &Hi) {
1325 // The low and high parts of the original input give four input vectors.
1328 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
1329 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
1330 EVT NewVT = Inputs[0].getValueType();
1331 unsigned NewElts = NewVT.getVectorNumElements();
1333 // If Lo or Hi uses elements from at most two of the four input vectors, then
1334 // express it as a vector shuffle of those two inputs. Otherwise extract the
1335 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
1336 SmallVector<int, 16> Ops;
1337 for (unsigned High = 0; High < 2; ++High) {
1338 SDValue &Output = High ? Hi : Lo;
1340 // Build a shuffle mask for the output, discovering on the fly which
1341 // input vectors to use as shuffle operands (recorded in InputUsed).
1342 // If building a suitable shuffle vector proves too hard, then bail
1343 // out with useBuildVector set.
1344 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
1345 unsigned FirstMaskIdx = High * NewElts;
1346 bool useBuildVector = false;
1347 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1348 // The mask element. This indexes into the input.
1349 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1351 // The input vector this mask element indexes into.
1352 unsigned Input = (unsigned)Idx / NewElts;
1354 if (Input >= array_lengthof(Inputs)) {
1355 // The mask element does not index into any input vector.
1360 // Turn the index into an offset from the start of the input vector.
1361 Idx -= Input * NewElts;
1363 // Find or create a shuffle vector operand to hold this input.
1365 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
1366 if (InputUsed[OpNo] == Input) {
1367 // This input vector is already an operand.
1369 } else if (InputUsed[OpNo] == -1U) {
1370 // Create a new operand for this input vector.
1371 InputUsed[OpNo] = Input;
1376 if (OpNo >= array_lengthof(InputUsed)) {
1377 // More than two input vectors used! Give up on trying to create a
1378 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
1379 useBuildVector = true;
1383 // Add the mask index for the new shuffle vector.
1384 Ops.push_back(Idx + OpNo * NewElts);
1387 if (useBuildVector) {
1388 EVT EltVT = NewVT.getVectorElementType();
1389 SmallVector<SDValue, 16> SVOps;
1391 // Extract the input elements by hand.
1392 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1393 // The mask element. This indexes into the input.
1394 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1396 // The input vector this mask element indexes into.
1397 unsigned Input = (unsigned)Idx / NewElts;
1399 if (Input >= array_lengthof(Inputs)) {
1400 // The mask element is "undef" or indexes off the end of the input.
1401 SVOps.push_back(DAG.getUNDEF(EltVT));
1405 // Turn the index into an offset from the start of the input vector.
1406 Idx -= Input * NewElts;
1408 // Extract the vector element by hand.
1409 SVOps.push_back(DAG.getNode(
1410 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Inputs[Input],
1411 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
1414 // Construct the Lo/Hi output using a BUILD_VECTOR.
1415 Output = DAG.getBuildVector(NewVT, dl, SVOps);
1416 } else if (InputUsed[0] == -1U) {
1417 // No input vectors were used! The result is undefined.
1418 Output = DAG.getUNDEF(NewVT);
1420 SDValue Op0 = Inputs[InputUsed[0]];
1421 // If only one input was used, use an undefined vector for the other.
1422 SDValue Op1 = InputUsed[1] == -1U ?
1423 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
1424 // At least one input vector was used. Create a new shuffle vector.
1425 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, Ops);
1433 //===----------------------------------------------------------------------===//
1434 // Operand Vector Splitting
1435 //===----------------------------------------------------------------------===//
1437 /// This method is called when the specified operand of the specified node is
1438 /// found to need vector splitting. At this point, all of the result types of
1439 /// the node are known to be legal, but other operands of the node may need
1440 /// legalization as well as the specified one.
1441 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
1442 DEBUG(dbgs() << "Split node operand: ";
1445 SDValue Res = SDValue();
1447 // See if the target wants to custom split this node.
1448 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1451 if (!Res.getNode()) {
1452 switch (N->getOpcode()) {
1455 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
1459 report_fatal_error("Do not know how to split this operator's "
1462 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1463 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1464 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1465 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1466 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1468 Res = SplitVecOp_TruncateHelper(N);
1470 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1471 case ISD::FCOPYSIGN: Res = SplitVecOp_FCOPYSIGN(N); break;
1473 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1476 Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
1479 Res = SplitVecOp_MSCATTER(cast<MaskedScatterSDNode>(N), OpNo);
1482 Res = SplitVecOp_MGATHER(cast<MaskedGatherSDNode>(N), OpNo);
1485 Res = SplitVecOp_VSELECT(N, OpNo);
1487 case ISD::FP_TO_SINT:
1488 case ISD::FP_TO_UINT:
1489 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1490 Res = SplitVecOp_TruncateHelper(N);
1492 Res = SplitVecOp_UnaryOp(N);
1494 case ISD::SINT_TO_FP:
1495 case ISD::UINT_TO_FP:
1496 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1497 Res = SplitVecOp_TruncateHelper(N);
1499 Res = SplitVecOp_UnaryOp(N);
1504 case ISD::FP_EXTEND:
1505 case ISD::SIGN_EXTEND:
1506 case ISD::ZERO_EXTEND:
1507 case ISD::ANY_EXTEND:
1509 case ISD::FCANONICALIZE:
1510 Res = SplitVecOp_UnaryOp(N);
1513 case ISD::ANY_EXTEND_VECTOR_INREG:
1514 case ISD::SIGN_EXTEND_VECTOR_INREG:
1515 case ISD::ZERO_EXTEND_VECTOR_INREG:
1516 Res = SplitVecOp_ExtVecInRegOp(N);
1521 // If the result is null, the sub-method took care of registering results etc.
1522 if (!Res.getNode()) return false;
1524 // If the result is N, the sub-method updated N in place. Tell the legalizer
1526 if (Res.getNode() == N)
1529 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1530 "Invalid operand expansion");
1532 ReplaceValueWith(SDValue(N, 0), Res);
1536 SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
1537 // The only possibility for an illegal operand is the mask, since result type
1538 // legalization would have handled this node already otherwise.
1539 assert(OpNo == 0 && "Illegal operand must be mask");
1541 SDValue Mask = N->getOperand(0);
1542 SDValue Src0 = N->getOperand(1);
1543 SDValue Src1 = N->getOperand(2);
1544 EVT Src0VT = Src0.getValueType();
1546 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");
1549 GetSplitVector(N->getOperand(0), Lo, Hi);
1550 assert(Lo.getValueType() == Hi.getValueType() &&
1551 "Lo and Hi have differing types");
1554 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
1555 assert(LoOpVT == HiOpVT && "Asymmetric vector split?");
1557 SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
1558 std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
1559 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
1560 std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
1563 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1565 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1567 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1570 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1571 // The result has a legal vector type, but the input needs splitting.
1572 EVT ResVT = N->getValueType(0);
1575 GetSplitVector(N->getOperand(0), Lo, Hi);
1576 EVT InVT = Lo.getValueType();
1578 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1579 InVT.getVectorNumElements());
1581 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1582 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1584 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1587 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1588 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1589 // end up being split all the way down to individual components. Convert the
1590 // split pieces into integers and reassemble.
1592 GetSplitVector(N->getOperand(0), Lo, Hi);
1593 Lo = BitConvertToInteger(Lo);
1594 Hi = BitConvertToInteger(Hi);
1596 if (DAG.getDataLayout().isBigEndian())
1599 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
1600 JoinIntegers(Lo, Hi));
1603 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1604 // We know that the extracted result type is legal.
1605 EVT SubVT = N->getValueType(0);
1606 SDValue Idx = N->getOperand(1);
1609 GetSplitVector(N->getOperand(0), Lo, Hi);
1611 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1612 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1614 if (IdxVal < LoElts) {
1615 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1616 "Extracted subvector crosses vector split!");
1617 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1619 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1620 DAG.getConstant(IdxVal - LoElts, dl,
1621 Idx.getValueType()));
1625 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1626 SDValue Vec = N->getOperand(0);
1627 SDValue Idx = N->getOperand(1);
1628 EVT VecVT = Vec.getValueType();
1630 if (isa<ConstantSDNode>(Idx)) {
1631 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1632 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1635 GetSplitVector(Vec, Lo, Hi);
1637 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1639 if (IdxVal < LoElts)
1640 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1641 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1642 DAG.getConstant(IdxVal - LoElts, SDLoc(N),
1643 Idx.getValueType())), 0);
1646 // See if the target wants to custom expand this node.
1647 if (CustomLowerNode(N, N->getValueType(0), true))
1650 // Make the vector elements byte-addressable if they aren't already.
1652 EVT EltVT = VecVT.getVectorElementType();
1653 if (EltVT.getSizeInBits() < 8) {
1654 SmallVector<SDValue, 4> ElementOps;
1655 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i) {
1656 ElementOps.push_back(DAG.getAnyExtOrTrunc(
1657 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vec,
1658 DAG.getConstant(i, dl, MVT::i8)),
1663 VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
1664 VecVT.getVectorNumElements());
1665 Vec = DAG.getBuildVector(VecVT, dl, ElementOps);
1668 // Store the vector to the stack.
1669 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1671 DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, MachinePointerInfo());
1673 // Load back the required element.
1674 StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1675 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1676 MachinePointerInfo(), EltVT);
1679 SDValue DAGTypeLegalizer::SplitVecOp_ExtVecInRegOp(SDNode *N) {
1682 // *_EXTEND_VECTOR_INREG only reference the lower half of the input, so
1683 // splitting the result has the same effect as splitting the input operand.
1684 SplitVecRes_ExtVecInRegOp(N, Lo, Hi);
1686 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), N->getValueType(0), Lo, Hi);
1689 SDValue DAGTypeLegalizer::SplitVecOp_MGATHER(MaskedGatherSDNode *MGT,
1693 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1695 SDValue Ch = MGT->getChain();
1696 SDValue Ptr = MGT->getBasePtr();
1697 SDValue Index = MGT->getIndex();
1698 SDValue Mask = MGT->getMask();
1699 SDValue Src0 = MGT->getValue();
1700 unsigned Alignment = MGT->getOriginalAlignment();
1702 SDValue MaskLo, MaskHi;
1703 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1704 // Split Mask operand
1705 GetSplitVector(Mask, MaskLo, MaskHi);
1707 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1709 EVT MemoryVT = MGT->getMemoryVT();
1710 EVT LoMemVT, HiMemVT;
1711 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1713 SDValue Src0Lo, Src0Hi;
1714 if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
1715 GetSplitVector(Src0, Src0Lo, Src0Hi);
1717 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1719 SDValue IndexHi, IndexLo;
1720 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1721 GetSplitVector(Index, IndexLo, IndexHi);
1723 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1725 MachineMemOperand *MMO = DAG.getMachineFunction().
1726 getMachineMemOperand(MGT->getPointerInfo(),
1727 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1728 Alignment, MGT->getAAInfo(), MGT->getRanges());
1730 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1731 SDValue Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl,
1734 MMO = DAG.getMachineFunction().
1735 getMachineMemOperand(MGT->getPointerInfo(),
1736 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1737 Alignment, MGT->getAAInfo(),
1740 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1741 SDValue Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl,
1744 // Build a factor node to remember that this load is independent of the
1746 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1749 // Legalize the chain result - switch anything that used the old chain to
1751 ReplaceValueWith(SDValue(MGT, 1), Ch);
1753 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MGT->getValueType(0), Lo,
1755 ReplaceValueWith(SDValue(MGT, 0), Res);
1759 SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
1761 SDValue Ch = N->getChain();
1762 SDValue Ptr = N->getBasePtr();
1763 SDValue Mask = N->getMask();
1764 SDValue Data = N->getValue();
1765 EVT MemoryVT = N->getMemoryVT();
1766 unsigned Alignment = N->getOriginalAlignment();
1769 EVT LoMemVT, HiMemVT;
1770 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1772 SDValue DataLo, DataHi;
1773 if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
1774 // Split Data operand
1775 GetSplitVector(Data, DataLo, DataHi);
1777 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
1779 SDValue MaskLo, MaskHi;
1780 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1781 // Split Mask operand
1782 GetSplitVector(Mask, MaskLo, MaskHi);
1784 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
1786 MaskLo = PromoteTargetBoolean(MaskLo, DataLo.getValueType());
1787 MaskHi = PromoteTargetBoolean(MaskHi, DataHi.getValueType());
1789 // if Alignment is equal to the vector size,
1790 // take the half of it for the second part
1791 unsigned SecondHalfAlignment =
1792 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
1793 Alignment/2 : Alignment;
1796 MachineMemOperand *MMO = DAG.getMachineFunction().
1797 getMachineMemOperand(N->getPointerInfo(),
1798 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1799 Alignment, N->getAAInfo(), N->getRanges());
1801 Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, MaskLo, LoMemVT, MMO,
1802 N->isTruncatingStore(),
1803 N->isCompressingStore());
1805 Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, DL, LoMemVT, DAG,
1806 N->isCompressingStore());
1807 MMO = DAG.getMachineFunction().
1808 getMachineMemOperand(N->getPointerInfo(),
1809 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1810 SecondHalfAlignment, N->getAAInfo(), N->getRanges());
1812 Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
1813 N->isTruncatingStore(), N->isCompressingStore());
1815 // Build a factor node to remember that this store is independent of the
1817 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1820 SDValue DAGTypeLegalizer::SplitVecOp_MSCATTER(MaskedScatterSDNode *N,
1822 SDValue Ch = N->getChain();
1823 SDValue Ptr = N->getBasePtr();
1824 SDValue Mask = N->getMask();
1825 SDValue Index = N->getIndex();
1826 SDValue Data = N->getValue();
1827 EVT MemoryVT = N->getMemoryVT();
1828 unsigned Alignment = N->getOriginalAlignment();
1831 // Split all operands
1832 EVT LoMemVT, HiMemVT;
1833 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1835 SDValue DataLo, DataHi;
1836 if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
1837 // Split Data operand
1838 GetSplitVector(Data, DataLo, DataHi);
1840 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
1842 SDValue MaskLo, MaskHi;
1843 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1844 // Split Mask operand
1845 GetSplitVector(Mask, MaskLo, MaskHi);
1847 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
1849 SDValue IndexHi, IndexLo;
1850 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1851 GetSplitVector(Index, IndexLo, IndexHi);
1853 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, DL);
1856 MachineMemOperand *MMO = DAG.getMachineFunction().
1857 getMachineMemOperand(N->getPointerInfo(),
1858 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1859 Alignment, N->getAAInfo(), N->getRanges());
1861 SDValue OpsLo[] = {Ch, DataLo, MaskLo, Ptr, IndexLo};
1862 Lo = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataLo.getValueType(),
1865 MMO = DAG.getMachineFunction().
1866 getMachineMemOperand(N->getPointerInfo(),
1867 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1868 Alignment, N->getAAInfo(), N->getRanges());
1870 SDValue OpsHi[] = {Ch, DataHi, MaskHi, Ptr, IndexHi};
1871 Hi = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataHi.getValueType(),
1874 // Build a factor node to remember that this store is independent of the
1876 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1879 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1880 assert(N->isUnindexed() && "Indexed store of vector?");
1881 assert(OpNo == 1 && "Can only split the stored value");
1884 bool isTruncating = N->isTruncatingStore();
1885 SDValue Ch = N->getChain();
1886 SDValue Ptr = N->getBasePtr();
1887 EVT MemoryVT = N->getMemoryVT();
1888 unsigned Alignment = N->getOriginalAlignment();
1889 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
1890 AAMDNodes AAInfo = N->getAAInfo();
1892 GetSplitVector(N->getOperand(1), Lo, Hi);
1894 EVT LoMemVT, HiMemVT;
1895 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1897 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1900 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), LoMemVT,
1901 Alignment, MMOFlags, AAInfo);
1903 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), Alignment, MMOFlags,
1906 // Increment the pointer to the other half.
1907 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1908 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
1911 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1912 N->getPointerInfo().getWithOffset(IncrementSize),
1913 HiMemVT, Alignment, MMOFlags, AAInfo);
1915 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1916 N->getPointerInfo().getWithOffset(IncrementSize),
1917 Alignment, MMOFlags, AAInfo);
1919 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1922 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1925 // The input operands all must have the same type, and we know the result
1926 // type is valid. Convert this to a buildvector which extracts all the
1928 // TODO: If the input elements are power-two vectors, we could convert this to
1929 // a new CONCAT_VECTORS node with elements that are half-wide.
1930 SmallVector<SDValue, 32> Elts;
1931 EVT EltVT = N->getValueType(0).getVectorElementType();
1932 for (const SDValue &Op : N->op_values()) {
1933 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1935 Elts.push_back(DAG.getNode(
1936 ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Op,
1937 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
1941 return DAG.getBuildVector(N->getValueType(0), DL, Elts);
1944 SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
1945 // The result type is legal, but the input type is illegal. If splitting
1946 // ends up with the result type of each half still being legal, just
1947 // do that. If, however, that would result in an illegal result type,
1948 // we can try to get more clever with power-two vectors. Specifically,
1949 // split the input type, but also widen the result element size, then
1950 // concatenate the halves and truncate again. For example, consider a target
1951 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
1952 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
1953 // %inlo = v4i32 extract_subvector %in, 0
1954 // %inhi = v4i32 extract_subvector %in, 4
1955 // %lo16 = v4i16 trunc v4i32 %inlo
1956 // %hi16 = v4i16 trunc v4i32 %inhi
1957 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
1958 // %res = v8i8 trunc v8i16 %in16
1960 // Without this transform, the original truncate would end up being
1961 // scalarized, which is pretty much always a last resort.
1962 SDValue InVec = N->getOperand(0);
1963 EVT InVT = InVec->getValueType(0);
1964 EVT OutVT = N->getValueType(0);
1965 unsigned NumElements = OutVT.getVectorNumElements();
1966 bool IsFloat = OutVT.isFloatingPoint();
1968 // Widening should have already made sure this is a power-two vector
1969 // if we're trying to split it at all. assert() that's true, just in case.
1970 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
1972 unsigned InElementSize = InVT.getScalarSizeInBits();
1973 unsigned OutElementSize = OutVT.getScalarSizeInBits();
1975 // If the input elements are only 1/2 the width of the result elements,
1976 // just use the normal splitting. Our trick only work if there's room
1977 // to split more than once.
1978 if (InElementSize <= OutElementSize * 2)
1979 return SplitVecOp_UnaryOp(N);
1982 // Extract the halves of the input via extract_subvector.
1983 SDValue InLoVec, InHiVec;
1984 std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL);
1985 // Truncate them to 1/2 the element size.
1986 EVT HalfElementVT = IsFloat ?
1987 EVT::getFloatingPointVT(InElementSize/2) :
1988 EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
1989 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
1991 SDValue HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec);
1992 SDValue HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec);
1993 // Concatenate them to get the full intermediate truncation result.
1994 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
1995 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
1997 // Now finish up by truncating all the way down to the original result
1998 // type. This should normally be something that ends up being legal directly,
1999 // but in theory if a target has very wide vectors and an annoyingly
2000 // restricted set of legal types, this split can chain to build things up.
2002 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec,
2003 DAG.getTargetConstant(
2004 0, DL, TLI.getPointerTy(DAG.getDataLayout())))
2005 : DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
2008 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
2009 assert(N->getValueType(0).isVector() &&
2010 N->getOperand(0).getValueType().isVector() &&
2011 "Operand types must be vectors");
2012 // The result has a legal vector type, but the input needs splitting.
2013 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
2015 GetSplitVector(N->getOperand(0), Lo0, Hi0);
2016 GetSplitVector(N->getOperand(1), Lo1, Hi1);
2017 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
2018 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
2019 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
2021 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
2022 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
2023 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
2024 return PromoteTargetBoolean(Con, N->getValueType(0));
2028 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
2029 // The result has a legal vector type, but the input needs splitting.
2030 EVT ResVT = N->getValueType(0);
2033 GetSplitVector(N->getOperand(0), Lo, Hi);
2034 EVT InVT = Lo.getValueType();
2036 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
2037 InVT.getVectorNumElements());
2039 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
2040 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
2042 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
2045 SDValue DAGTypeLegalizer::SplitVecOp_FCOPYSIGN(SDNode *N) {
2046 // The result (and the first input) has a legal vector type, but the second
2047 // input needs splitting.
2048 return DAG.UnrollVectorOp(N, N->getValueType(0).getVectorNumElements());
2052 //===----------------------------------------------------------------------===//
2053 // Result Vector Widening
2054 //===----------------------------------------------------------------------===//
2056 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
2057 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
2061 // See if the target wants to custom widen this node.
2062 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
2065 SDValue Res = SDValue();
2066 switch (N->getOpcode()) {
2069 dbgs() << "WidenVectorResult #" << ResNo << ": ";
2073 llvm_unreachable("Do not know how to widen the result of this operator!");
2075 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
2076 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
2077 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
2078 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
2079 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
2080 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
2081 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
2082 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
2083 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
2084 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
2086 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
2087 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
2088 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
2089 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
2090 case ISD::VECTOR_SHUFFLE:
2091 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
2094 Res = WidenVecRes_MLOAD(cast<MaskedLoadSDNode>(N));
2097 Res = WidenVecRes_MGATHER(cast<MaskedGatherSDNode>(N));
2116 Res = WidenVecRes_Binary(N);
2129 Res = WidenVecRes_BinaryCanTrap(N);
2132 case ISD::FCOPYSIGN:
2133 Res = WidenVecRes_FCOPYSIGN(N);
2137 Res = WidenVecRes_POWI(N);
2143 Res = WidenVecRes_Shift(N);
2146 case ISD::ANY_EXTEND_VECTOR_INREG:
2147 case ISD::SIGN_EXTEND_VECTOR_INREG:
2148 case ISD::ZERO_EXTEND_VECTOR_INREG:
2149 Res = WidenVecRes_EXTEND_VECTOR_INREG(N);
2152 case ISD::ANY_EXTEND:
2153 case ISD::FP_EXTEND:
2155 case ISD::FP_TO_SINT:
2156 case ISD::FP_TO_UINT:
2157 case ISD::SIGN_EXTEND:
2158 case ISD::SINT_TO_FP:
2160 case ISD::UINT_TO_FP:
2161 case ISD::ZERO_EXTEND:
2162 Res = WidenVecRes_Convert(N);
2165 case ISD::BITREVERSE:
2179 case ISD::FNEARBYINT:
2186 Res = WidenVecRes_Unary(N);
2189 Res = WidenVecRes_Ternary(N);
2193 // If Res is null, the sub-method took care of registering the result.
2195 SetWidenedVector(SDValue(N, ResNo), Res);
2198 SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
2199 // Ternary op widening.
2201 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2202 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2203 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2204 SDValue InOp3 = GetWidenedVector(N->getOperand(2));
2205 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
2208 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
2209 // Binary op widening.
2211 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2212 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2213 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2214 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, N->getFlags());
2217 SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
2218 // Binary op widening for operations that can trap.
2219 unsigned Opcode = N->getOpcode();
2221 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2222 EVT WidenEltVT = WidenVT.getVectorElementType();
2224 unsigned NumElts = VT.getVectorNumElements();
2225 const SDNodeFlags *Flags = N->getFlags();
2226 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
2227 NumElts = NumElts / 2;
2228 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2231 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
2232 // Operation doesn't trap so just widen as normal.
2233 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2234 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2235 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, Flags);
2238 // No legal vector version so unroll the vector operation and then widen.
2240 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2242 // Since the operation can trap, apply operation on the original vector.
2244 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2245 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2246 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
2248 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
2249 unsigned ConcatEnd = 0; // Current ConcatOps index.
2250 int Idx = 0; // Current Idx into input vectors.
2252 // NumElts := greatest legal vector size (at most WidenVT)
2253 // while (orig. vector has unhandled elements) {
2254 // take munches of size NumElts from the beginning and add to ConcatOps
2255 // NumElts := next smaller supported vector size or 1
2257 while (CurNumElts != 0) {
2258 while (CurNumElts >= NumElts) {
2259 SDValue EOp1 = DAG.getNode(
2260 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
2261 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2262 SDValue EOp2 = DAG.getNode(
2263 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
2264 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2265 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2, Flags);
2267 CurNumElts -= NumElts;
2270 NumElts = NumElts / 2;
2271 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2272 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
2275 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
2276 SDValue EOp1 = DAG.getNode(
2277 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp1,
2278 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2279 SDValue EOp2 = DAG.getNode(
2280 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp2,
2281 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2282 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
2289 // Check to see if we have a single operation with the widen type.
2290 if (ConcatEnd == 1) {
2291 VT = ConcatOps[0].getValueType();
2293 return ConcatOps[0];
2296 // while (Some element of ConcatOps is not of type MaxVT) {
2297 // From the end of ConcatOps, collect elements of the same type and put
2298 // them into an op of the next larger supported type
2300 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
2301 Idx = ConcatEnd - 1;
2302 VT = ConcatOps[Idx--].getValueType();
2303 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
2306 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
2310 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
2311 } while (!TLI.isTypeLegal(NextVT));
2313 if (!VT.isVector()) {
2314 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
2315 SDValue VecOp = DAG.getUNDEF(NextVT);
2316 unsigned NumToInsert = ConcatEnd - Idx - 1;
2317 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
2318 VecOp = DAG.getNode(
2319 ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, ConcatOps[OpIdx],
2320 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2322 ConcatOps[Idx+1] = VecOp;
2323 ConcatEnd = Idx + 2;
2325 // Vector type, create a CONCAT_VECTORS of type NextVT
2326 SDValue undefVec = DAG.getUNDEF(VT);
2327 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
2328 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
2329 unsigned RealVals = ConcatEnd - Idx - 1;
2330 unsigned SubConcatEnd = 0;
2331 unsigned SubConcatIdx = Idx + 1;
2332 while (SubConcatEnd < RealVals)
2333 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
2334 while (SubConcatEnd < OpsToConcat)
2335 SubConcatOps[SubConcatEnd++] = undefVec;
2336 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
2337 NextVT, SubConcatOps);
2338 ConcatEnd = SubConcatIdx + 1;
2342 // Check to see if we have a single operation with the widen type.
2343 if (ConcatEnd == 1) {
2344 VT = ConcatOps[0].getValueType();
2346 return ConcatOps[0];
2349 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
2350 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
2351 if (NumOps != ConcatEnd ) {
2352 SDValue UndefVal = DAG.getUNDEF(MaxVT);
2353 for (unsigned j = ConcatEnd; j < NumOps; ++j)
2354 ConcatOps[j] = UndefVal;
2356 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2357 makeArrayRef(ConcatOps.data(), NumOps));
2360 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
2361 SDValue InOp = N->getOperand(0);
2364 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2365 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2367 EVT InVT = InOp.getValueType();
2368 EVT InEltVT = InVT.getVectorElementType();
2369 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2371 unsigned Opcode = N->getOpcode();
2372 unsigned InVTNumElts = InVT.getVectorNumElements();
2373 const SDNodeFlags *Flags = N->getFlags();
2374 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2375 InOp = GetWidenedVector(N->getOperand(0));
2376 InVT = InOp.getValueType();
2377 InVTNumElts = InVT.getVectorNumElements();
2378 if (InVTNumElts == WidenNumElts) {
2379 if (N->getNumOperands() == 1)
2380 return DAG.getNode(Opcode, DL, WidenVT, InOp);
2381 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1), Flags);
2383 if (WidenVT.getSizeInBits() == InVT.getSizeInBits()) {
2384 // If both input and result vector types are of same width, extend
2385 // operations should be done with SIGN/ZERO_EXTEND_VECTOR_INREG, which
2386 // accepts fewer elements in the result than in the input.
2387 if (Opcode == ISD::SIGN_EXTEND)
2388 return DAG.getSignExtendVectorInReg(InOp, DL, WidenVT);
2389 if (Opcode == ISD::ZERO_EXTEND)
2390 return DAG.getZeroExtendVectorInReg(InOp, DL, WidenVT);
2394 if (TLI.isTypeLegal(InWidenVT)) {
2395 // Because the result and the input are different vector types, widening
2396 // the result could create a legal type but widening the input might make
2397 // it an illegal type that might lead to repeatedly splitting the input
2398 // and then widening it. To avoid this, we widen the input only if
2399 // it results in a legal type.
2400 if (WidenNumElts % InVTNumElts == 0) {
2401 // Widen the input and call convert on the widened input vector.
2402 unsigned NumConcat = WidenNumElts/InVTNumElts;
2403 SmallVector<SDValue, 16> Ops(NumConcat);
2405 SDValue UndefVal = DAG.getUNDEF(InVT);
2406 for (unsigned i = 1; i != NumConcat; ++i)
2408 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
2409 if (N->getNumOperands() == 1)
2410 return DAG.getNode(Opcode, DL, WidenVT, InVec);
2411 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1), Flags);
2414 if (InVTNumElts % WidenNumElts == 0) {
2415 SDValue InVal = DAG.getNode(
2416 ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, InOp,
2417 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2418 // Extract the input and convert the shorten input vector.
2419 if (N->getNumOperands() == 1)
2420 return DAG.getNode(Opcode, DL, WidenVT, InVal);
2421 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1), Flags);
2425 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2426 SmallVector<SDValue, 16> Ops(WidenNumElts);
2427 EVT EltVT = WidenVT.getVectorElementType();
2428 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2430 for (i=0; i < MinElts; ++i) {
2431 SDValue Val = DAG.getNode(
2432 ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
2433 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2434 if (N->getNumOperands() == 1)
2435 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
2437 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1), Flags);
2440 SDValue UndefVal = DAG.getUNDEF(EltVT);
2441 for (; i < WidenNumElts; ++i)
2444 return DAG.getBuildVector(WidenVT, DL, Ops);
2447 SDValue DAGTypeLegalizer::WidenVecRes_EXTEND_VECTOR_INREG(SDNode *N) {
2448 unsigned Opcode = N->getOpcode();
2449 SDValue InOp = N->getOperand(0);
2452 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2453 EVT WidenSVT = WidenVT.getVectorElementType();
2454 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2456 EVT InVT = InOp.getValueType();
2457 EVT InSVT = InVT.getVectorElementType();
2458 unsigned InVTNumElts = InVT.getVectorNumElements();
2460 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2461 InOp = GetWidenedVector(InOp);
2462 InVT = InOp.getValueType();
2463 if (InVT.getSizeInBits() == WidenVT.getSizeInBits()) {
2465 case ISD::ANY_EXTEND_VECTOR_INREG:
2466 return DAG.getAnyExtendVectorInReg(InOp, DL, WidenVT);
2467 case ISD::SIGN_EXTEND_VECTOR_INREG:
2468 return DAG.getSignExtendVectorInReg(InOp, DL, WidenVT);
2469 case ISD::ZERO_EXTEND_VECTOR_INREG:
2470 return DAG.getZeroExtendVectorInReg(InOp, DL, WidenVT);
2475 // Unroll, extend the scalars and rebuild the vector.
2476 SmallVector<SDValue, 16> Ops;
2477 for (unsigned i = 0, e = std::min(InVTNumElts, WidenNumElts); i != e; ++i) {
2478 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InSVT, InOp,
2479 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2481 case ISD::ANY_EXTEND_VECTOR_INREG:
2482 Val = DAG.getNode(ISD::ANY_EXTEND, DL, WidenSVT, Val);
2484 case ISD::SIGN_EXTEND_VECTOR_INREG:
2485 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, WidenSVT, Val);
2487 case ISD::ZERO_EXTEND_VECTOR_INREG:
2488 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenSVT, Val);
2491 llvm_unreachable("A *_EXTEND_VECTOR_INREG node was expected");
2496 while (Ops.size() != WidenNumElts)
2497 Ops.push_back(DAG.getUNDEF(WidenSVT));
2499 return DAG.getBuildVector(WidenVT, DL, Ops);
2502 SDValue DAGTypeLegalizer::WidenVecRes_FCOPYSIGN(SDNode *N) {
2503 // If this is an FCOPYSIGN with same input types, we can treat it as a
2504 // normal (can trap) binary op.
2505 if (N->getOperand(0).getValueType() == N->getOperand(1).getValueType())
2506 return WidenVecRes_BinaryCanTrap(N);
2508 // If the types are different, fall back to unrolling.
2509 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2510 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2513 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
2514 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2515 SDValue InOp = GetWidenedVector(N->getOperand(0));
2516 SDValue ShOp = N->getOperand(1);
2517 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2520 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
2521 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2522 SDValue InOp = GetWidenedVector(N->getOperand(0));
2523 SDValue ShOp = N->getOperand(1);
2525 EVT ShVT = ShOp.getValueType();
2526 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
2527 ShOp = GetWidenedVector(ShOp);
2528 ShVT = ShOp.getValueType();
2530 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
2531 ShVT.getVectorElementType(),
2532 WidenVT.getVectorNumElements());
2533 if (ShVT != ShWidenVT)
2534 ShOp = ModifyToType(ShOp, ShWidenVT);
2536 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2539 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
2540 // Unary op widening.
2541 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2542 SDValue InOp = GetWidenedVector(N->getOperand(0));
2543 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
2546 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
2547 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2548 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
2549 cast<VTSDNode>(N->getOperand(1))->getVT()
2550 .getVectorElementType(),
2551 WidenVT.getVectorNumElements());
2552 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
2553 return DAG.getNode(N->getOpcode(), SDLoc(N),
2554 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
2557 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
2558 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
2559 return GetWidenedVector(WidenVec);
2562 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
2563 SDValue InOp = N->getOperand(0);
2564 EVT InVT = InOp.getValueType();
2565 EVT VT = N->getValueType(0);
2566 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2569 switch (getTypeAction(InVT)) {
2570 case TargetLowering::TypeLegal:
2572 case TargetLowering::TypePromoteInteger:
2573 // If the incoming type is a vector that is being promoted, then
2574 // we know that the elements are arranged differently and that we
2575 // must perform the conversion using a stack slot.
2576 if (InVT.isVector())
2579 // If the InOp is promoted to the same size, convert it. Otherwise,
2580 // fall out of the switch and widen the promoted input.
2581 InOp = GetPromotedInteger(InOp);
2582 InVT = InOp.getValueType();
2583 if (WidenVT.bitsEq(InVT))
2584 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2586 case TargetLowering::TypeSoftenFloat:
2587 case TargetLowering::TypePromoteFloat:
2588 case TargetLowering::TypeExpandInteger:
2589 case TargetLowering::TypeExpandFloat:
2590 case TargetLowering::TypeScalarizeVector:
2591 case TargetLowering::TypeSplitVector:
2593 case TargetLowering::TypeWidenVector:
2594 // If the InOp is widened to the same size, convert it. Otherwise, fall
2595 // out of the switch and widen the widened input.
2596 InOp = GetWidenedVector(InOp);
2597 InVT = InOp.getValueType();
2598 if (WidenVT.bitsEq(InVT))
2599 // The input widens to the same size. Convert to the widen value.
2600 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2604 unsigned WidenSize = WidenVT.getSizeInBits();
2605 unsigned InSize = InVT.getSizeInBits();
2606 // x86mmx is not an acceptable vector element type, so don't try.
2607 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
2608 // Determine new input vector type. The new input vector type will use
2609 // the same element type (if its a vector) or use the input type as a
2610 // vector. It is the same size as the type to widen to.
2612 unsigned NewNumElts = WidenSize / InSize;
2613 if (InVT.isVector()) {
2614 EVT InEltVT = InVT.getVectorElementType();
2615 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
2616 WidenSize / InEltVT.getSizeInBits());
2618 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
2621 if (TLI.isTypeLegal(NewInVT)) {
2622 // Because the result and the input are different vector types, widening
2623 // the result could create a legal type but widening the input might make
2624 // it an illegal type that might lead to repeatedly splitting the input
2625 // and then widening it. To avoid this, we widen the input only if
2626 // it results in a legal type.
2627 SmallVector<SDValue, 16> Ops(NewNumElts);
2628 SDValue UndefVal = DAG.getUNDEF(InVT);
2630 for (unsigned i = 1; i < NewNumElts; ++i)
2634 if (InVT.isVector())
2635 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
2637 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, Ops);
2638 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
2642 return CreateStackStoreLoad(InOp, WidenVT);
2645 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
2647 // Build a vector with undefined for the new nodes.
2648 EVT VT = N->getValueType(0);
2650 // Integer BUILD_VECTOR operands may be larger than the node's vector element
2651 // type. The UNDEFs need to have the same type as the existing operands.
2652 EVT EltVT = N->getOperand(0).getValueType();
2653 unsigned NumElts = VT.getVectorNumElements();
2655 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2656 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2658 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
2659 assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
2660 NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
2662 return DAG.getBuildVector(WidenVT, dl, NewOps);
2665 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
2666 EVT InVT = N->getOperand(0).getValueType();
2667 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2669 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2670 unsigned NumInElts = InVT.getVectorNumElements();
2671 unsigned NumOperands = N->getNumOperands();
2673 bool InputWidened = false; // Indicates we need to widen the input.
2674 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
2675 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
2676 // Add undef vectors to widen to correct length.
2677 unsigned NumConcat = WidenVT.getVectorNumElements() /
2678 InVT.getVectorNumElements();
2679 SDValue UndefVal = DAG.getUNDEF(InVT);
2680 SmallVector<SDValue, 16> Ops(NumConcat);
2681 for (unsigned i=0; i < NumOperands; ++i)
2682 Ops[i] = N->getOperand(i);
2683 for (unsigned i = NumOperands; i != NumConcat; ++i)
2685 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
2688 InputWidened = true;
2689 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
2690 // The inputs and the result are widen to the same value.
2692 for (i=1; i < NumOperands; ++i)
2693 if (!N->getOperand(i).isUndef())
2696 if (i == NumOperands)
2697 // Everything but the first operand is an UNDEF so just return the
2698 // widened first operand.
2699 return GetWidenedVector(N->getOperand(0));
2701 if (NumOperands == 2) {
2702 // Replace concat of two operands with a shuffle.
2703 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
2704 for (unsigned i = 0; i < NumInElts; ++i) {
2706 MaskOps[i + NumInElts] = i + WidenNumElts;
2708 return DAG.getVectorShuffle(WidenVT, dl,
2709 GetWidenedVector(N->getOperand(0)),
2710 GetWidenedVector(N->getOperand(1)),
2716 // Fall back to use extracts and build vector.
2717 EVT EltVT = WidenVT.getVectorElementType();
2718 SmallVector<SDValue, 16> Ops(WidenNumElts);
2720 for (unsigned i=0; i < NumOperands; ++i) {
2721 SDValue InOp = N->getOperand(i);
2723 InOp = GetWidenedVector(InOp);
2724 for (unsigned j=0; j < NumInElts; ++j)
2725 Ops[Idx++] = DAG.getNode(
2726 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2727 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2729 SDValue UndefVal = DAG.getUNDEF(EltVT);
2730 for (; Idx < WidenNumElts; ++Idx)
2731 Ops[Idx] = UndefVal;
2732 return DAG.getBuildVector(WidenVT, dl, Ops);
2735 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
2736 EVT VT = N->getValueType(0);
2737 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2738 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2739 SDValue InOp = N->getOperand(0);
2740 SDValue Idx = N->getOperand(1);
2743 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2744 InOp = GetWidenedVector(InOp);
2746 EVT InVT = InOp.getValueType();
2748 // Check if we can just return the input vector after widening.
2749 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2750 if (IdxVal == 0 && InVT == WidenVT)
2753 // Check if we can extract from the vector.
2754 unsigned InNumElts = InVT.getVectorNumElements();
2755 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
2756 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
2758 // We could try widening the input to the right length but for now, extract
2759 // the original elements, fill the rest with undefs and build a vector.
2760 SmallVector<SDValue, 16> Ops(WidenNumElts);
2761 EVT EltVT = VT.getVectorElementType();
2762 unsigned NumElts = VT.getVectorNumElements();
2764 for (i=0; i < NumElts; ++i)
2766 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2767 DAG.getConstant(IdxVal + i, dl,
2768 TLI.getVectorIdxTy(DAG.getDataLayout())));
2770 SDValue UndefVal = DAG.getUNDEF(EltVT);
2771 for (; i < WidenNumElts; ++i)
2773 return DAG.getBuildVector(WidenVT, dl, Ops);
2776 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
2777 SDValue InOp = GetWidenedVector(N->getOperand(0));
2778 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
2779 InOp.getValueType(), InOp,
2780 N->getOperand(1), N->getOperand(2));
2783 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
2784 LoadSDNode *LD = cast<LoadSDNode>(N);
2785 ISD::LoadExtType ExtType = LD->getExtensionType();
2788 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
2789 if (ExtType != ISD::NON_EXTLOAD)
2790 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
2792 Result = GenWidenVectorLoads(LdChain, LD);
2794 // If we generate a single load, we can use that for the chain. Otherwise,
2795 // build a factor node to remember the multiple loads are independent and
2798 if (LdChain.size() == 1)
2799 NewChain = LdChain[0];
2801 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
2803 // Modified the chain - switch anything that used the old chain to use
2805 ReplaceValueWith(SDValue(N, 1), NewChain);
2810 SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {
2812 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),N->getValueType(0));
2813 SDValue Mask = N->getMask();
2814 EVT MaskVT = Mask.getValueType();
2815 SDValue Src0 = GetWidenedVector(N->getSrc0());
2816 ISD::LoadExtType ExtType = N->getExtensionType();
2819 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
2820 Mask = GetWidenedVector(Mask);
2822 EVT BoolVT = getSetCCResultType(WidenVT);
2824 // We can't use ModifyToType() because we should fill the mask with
2826 unsigned WidenNumElts = BoolVT.getVectorNumElements();
2827 unsigned MaskNumElts = MaskVT.getVectorNumElements();
2829 unsigned NumConcat = WidenNumElts / MaskNumElts;
2830 SmallVector<SDValue, 16> Ops(NumConcat);
2831 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
2833 for (unsigned i = 1; i != NumConcat; ++i)
2836 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
2839 SDValue Res = DAG.getMaskedLoad(WidenVT, dl, N->getChain(), N->getBasePtr(),
2840 Mask, Src0, N->getMemoryVT(),
2841 N->getMemOperand(), ExtType,
2842 N->isExpandingLoad());
2843 // Legalize the chain result - switch anything that used the old chain to
2845 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2849 SDValue DAGTypeLegalizer::WidenVecRes_MGATHER(MaskedGatherSDNode *N) {
2851 EVT WideVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2852 SDValue Mask = N->getMask();
2853 SDValue Src0 = GetWidenedVector(N->getValue());
2854 unsigned NumElts = WideVT.getVectorNumElements();
2857 // The mask should be widened as well
2858 Mask = WidenTargetBoolean(Mask, WideVT, true);
2860 // Widen the Index operand
2861 SDValue Index = N->getIndex();
2862 EVT WideIndexVT = EVT::getVectorVT(*DAG.getContext(),
2863 Index.getValueType().getScalarType(),
2865 Index = ModifyToType(Index, WideIndexVT);
2866 SDValue Ops[] = { N->getChain(), Src0, Mask, N->getBasePtr(), Index };
2867 SDValue Res = DAG.getMaskedGather(DAG.getVTList(WideVT, MVT::Other),
2868 N->getMemoryVT(), dl, Ops,
2869 N->getMemOperand());
2871 // Legalize the chain result - switch anything that used the old chain to
2873 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2877 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
2878 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2879 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
2880 WidenVT, N->getOperand(0));
2883 // Return true if this is a node that could have two SETCCs as operands.
2884 static inline bool isLogicalMaskOp(unsigned Opcode) {
2894 // This is used just for the assert in convertMask(). Check that this either
2895 // a SETCC or a previously handled SETCC by convertMask().
2897 static inline bool isSETCCorConvertedSETCC(SDValue N) {
2898 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
2899 N = N.getOperand(0);
2900 else if (N.getOpcode() == ISD::CONCAT_VECTORS) {
2901 for (unsigned i = 1; i < N->getNumOperands(); ++i)
2902 if (!N->getOperand(i)->isUndef())
2904 N = N.getOperand(0);
2907 if (N.getOpcode() == ISD::TRUNCATE)
2908 N = N.getOperand(0);
2909 else if (N.getOpcode() == ISD::SIGN_EXTEND)
2910 N = N.getOperand(0);
2912 return (N.getOpcode() == ISD::SETCC);
2916 // Return a mask of vector type MaskVT to replace InMask. Also adjust MaskVT
2917 // to ToMaskVT if needed with vector extension or truncation.
2918 SDValue DAGTypeLegalizer::convertMask(SDValue InMask, EVT MaskVT,
2920 LLVMContext &Ctx = *DAG.getContext();
2922 // Currently a SETCC or a AND/OR/XOR with two SETCCs are handled.
2923 unsigned InMaskOpc = InMask->getOpcode();
2924 assert((InMaskOpc == ISD::SETCC ||
2925 (isLogicalMaskOp(InMaskOpc) &&
2926 isSETCCorConvertedSETCC(InMask->getOperand(0)) &&
2927 isSETCCorConvertedSETCC(InMask->getOperand(1)))) &&
2928 "Unexpected mask argument.");
2930 // Make a new Mask node, with a legal result VT.
2931 SmallVector<SDValue, 4> Ops;
2932 for (unsigned i = 0; i < InMask->getNumOperands(); ++i)
2933 Ops.push_back(InMask->getOperand(i));
2934 SDValue Mask = DAG.getNode(InMaskOpc, SDLoc(InMask), MaskVT, Ops);
2936 // If MaskVT has smaller or bigger elements than ToMaskVT, a vector sign
2937 // extend or truncate is needed.
2938 unsigned MaskScalarBits = MaskVT.getScalarSizeInBits();
2939 unsigned ToMaskScalBits = ToMaskVT.getScalarSizeInBits();
2940 if (MaskScalarBits < ToMaskScalBits) {
2941 EVT ExtVT = EVT::getVectorVT(Ctx, ToMaskVT.getVectorElementType(),
2942 MaskVT.getVectorNumElements());
2943 Mask = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Mask), ExtVT, Mask);
2944 } else if (MaskScalarBits > ToMaskScalBits) {
2945 EVT TruncVT = EVT::getVectorVT(Ctx, ToMaskVT.getVectorElementType(),
2946 MaskVT.getVectorNumElements());
2947 Mask = DAG.getNode(ISD::TRUNCATE, SDLoc(Mask), TruncVT, Mask);
2950 assert(Mask->getValueType(0).getScalarSizeInBits() ==
2951 ToMaskVT.getScalarSizeInBits() &&
2952 "Mask should have the right element size by now.");
2954 // Adjust Mask to the right number of elements.
2955 unsigned CurrMaskNumEls = Mask->getValueType(0).getVectorNumElements();
2956 if (CurrMaskNumEls > ToMaskVT.getVectorNumElements()) {
2957 MVT IdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
2958 SDValue ZeroIdx = DAG.getConstant(0, SDLoc(Mask), IdxTy);
2959 Mask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(Mask), ToMaskVT, Mask,
2961 } else if (CurrMaskNumEls < ToMaskVT.getVectorNumElements()) {
2962 unsigned NumSubVecs = (ToMaskVT.getVectorNumElements() / CurrMaskNumEls);
2963 EVT SubVT = Mask->getValueType(0);
2964 SmallVector<SDValue, 16> SubConcatOps(NumSubVecs);
2965 SubConcatOps[0] = Mask;
2966 for (unsigned i = 1; i < NumSubVecs; ++i)
2967 SubConcatOps[i] = DAG.getUNDEF(SubVT);
2969 DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Mask), ToMaskVT, SubConcatOps);
2972 assert((Mask->getValueType(0) == ToMaskVT) &&
2973 "A mask of ToMaskVT should have been produced by now.");
2978 // Get the target mask VT, and widen if needed.
2979 EVT DAGTypeLegalizer::getSETCCWidenedResultTy(SDValue SetCC) {
2980 assert(SetCC->getOpcode() == ISD::SETCC);
2981 LLVMContext &Ctx = *DAG.getContext();
2982 EVT MaskVT = getSetCCResultType(SetCC->getOperand(0).getValueType());
2983 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
2984 MaskVT = TLI.getTypeToTransformTo(Ctx, MaskVT);
2988 // This method tries to handle VSELECT and its mask by legalizing operands
2989 // (which may require widening) and if needed adjusting the mask vector type
2990 // to match that of the VSELECT. Without it, many cases end up with
2991 // scalarization of the SETCC, with many unnecessary instructions.
2992 SDValue DAGTypeLegalizer::WidenVSELECTAndMask(SDNode *N) {
2993 LLVMContext &Ctx = *DAG.getContext();
2994 SDValue Cond = N->getOperand(0);
2996 if (N->getOpcode() != ISD::VSELECT)
2999 if (Cond->getOpcode() != ISD::SETCC && !isLogicalMaskOp(Cond->getOpcode()))
3002 // If this is a splitted VSELECT that was previously already handled, do
3004 if (Cond->getValueType(0).getScalarSizeInBits() != 1)
3007 EVT VSelVT = N->getValueType(0);
3008 // Only handle vector types which are a power of 2.
3009 if (!isPowerOf2_64(VSelVT.getSizeInBits()))
3012 // Don't touch if this will be scalarized.
3013 EVT FinalVT = VSelVT;
3014 while (getTypeAction(FinalVT) == TargetLowering::TypeSplitVector)
3015 FinalVT = EVT::getVectorVT(Ctx, FinalVT.getVectorElementType(),
3016 FinalVT.getVectorNumElements() / 2);
3017 if (FinalVT.getVectorNumElements() == 1)
3020 // If there is support for an i1 vector mask, don't touch.
3021 if (Cond.getOpcode() == ISD::SETCC) {
3022 EVT SetCCOpVT = Cond->getOperand(0).getValueType();
3023 while (TLI.getTypeAction(Ctx, SetCCOpVT) != TargetLowering::TypeLegal)
3024 SetCCOpVT = TLI.getTypeToTransformTo(Ctx, SetCCOpVT);
3025 EVT SetCCResVT = getSetCCResultType(SetCCOpVT);
3026 if (SetCCResVT.getScalarSizeInBits() == 1)
3030 // Get the VT and operands for VSELECT, and widen if needed.
3031 SDValue VSelOp1 = N->getOperand(1);
3032 SDValue VSelOp2 = N->getOperand(2);
3033 if (getTypeAction(VSelVT) == TargetLowering::TypeWidenVector) {
3034 VSelVT = TLI.getTypeToTransformTo(Ctx, VSelVT);
3035 VSelOp1 = GetWidenedVector(VSelOp1);
3036 VSelOp2 = GetWidenedVector(VSelOp2);
3039 // The mask of the VSELECT should have integer elements.
3040 EVT ToMaskVT = VSelVT;
3041 if (!ToMaskVT.getScalarType().isInteger())
3042 ToMaskVT = ToMaskVT.changeVectorElementTypeToInteger();
3045 if (Cond->getOpcode() == ISD::SETCC) {
3046 EVT MaskVT = getSETCCWidenedResultTy(Cond);
3047 Mask = convertMask(Cond, MaskVT, ToMaskVT);
3048 } else if (isLogicalMaskOp(Cond->getOpcode()) &&
3049 Cond->getOperand(0).getOpcode() == ISD::SETCC &&
3050 Cond->getOperand(1).getOpcode() == ISD::SETCC) {
3051 // Cond is (AND/OR/XOR (SETCC, SETCC))
3052 SDValue SETCC0 = Cond->getOperand(0);
3053 SDValue SETCC1 = Cond->getOperand(1);
3054 EVT VT0 = getSETCCWidenedResultTy(SETCC0);
3055 EVT VT1 = getSETCCWidenedResultTy(SETCC1);
3056 unsigned ScalarBits0 = VT0.getScalarSizeInBits();
3057 unsigned ScalarBits1 = VT1.getScalarSizeInBits();
3058 unsigned ScalarBits_ToMask = ToMaskVT.getScalarSizeInBits();
3060 // If the two SETCCs have different VTs, either extend/truncate one of
3061 // them to the other "towards" ToMaskVT, or truncate one and extend the
3062 // other to ToMaskVT.
3063 if (ScalarBits0 != ScalarBits1) {
3064 EVT NarrowVT = ((ScalarBits0 < ScalarBits1) ? VT0 : VT1);
3065 EVT WideVT = ((NarrowVT == VT0) ? VT1 : VT0);
3066 if (ScalarBits_ToMask >= WideVT.getScalarSizeInBits())
3068 else if (ScalarBits_ToMask <= NarrowVT.getScalarSizeInBits())
3073 // If the two SETCCs have the same VT, don't change it.
3076 // Make new SETCCs and logical nodes.
3077 SETCC0 = convertMask(SETCC0, VT0, MaskVT);
3078 SETCC1 = convertMask(SETCC1, VT1, MaskVT);
3079 Cond = DAG.getNode(Cond->getOpcode(), SDLoc(Cond), MaskVT, SETCC0, SETCC1);
3081 // Convert the logical op for VSELECT if needed.
3082 Mask = convertMask(Cond, MaskVT, ToMaskVT);
3086 return DAG.getNode(ISD::VSELECT, SDLoc(N), VSelVT, Mask, VSelOp1, VSelOp2);
3089 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
3090 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3091 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3093 SDValue Cond1 = N->getOperand(0);
3094 EVT CondVT = Cond1.getValueType();
3095 if (CondVT.isVector()) {
3096 if (SDValue Res = WidenVSELECTAndMask(N))
3099 EVT CondEltVT = CondVT.getVectorElementType();
3100 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
3101 CondEltVT, WidenNumElts);
3102 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
3103 Cond1 = GetWidenedVector(Cond1);
3105 // If we have to split the condition there is no point in widening the
3106 // select. This would result in an cycle of widening the select ->
3107 // widening the condition operand -> splitting the condition operand ->
3108 // splitting the select -> widening the select. Instead split this select
3109 // further and widen the resulting type.
3110 if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
3111 SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
3112 SDValue Res = ModifyToType(SplitSelect, WidenVT);
3116 if (Cond1.getValueType() != CondWidenVT)
3117 Cond1 = ModifyToType(Cond1, CondWidenVT);
3120 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
3121 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
3122 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
3123 return DAG.getNode(N->getOpcode(), SDLoc(N),
3124 WidenVT, Cond1, InOp1, InOp2);
3127 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
3128 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
3129 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
3130 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
3131 InOp1.getValueType(), N->getOperand(0),
3132 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
3135 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
3136 assert(N->getValueType(0).isVector() ==
3137 N->getOperand(0).getValueType().isVector() &&
3138 "Scalar/Vector type mismatch");
3139 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
3141 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3142 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
3143 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
3144 return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT,
3145 InOp1, InOp2, N->getOperand(2));
3148 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
3149 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3150 return DAG.getUNDEF(WidenVT);
3153 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
3154 EVT VT = N->getValueType(0);
3157 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3158 unsigned NumElts = VT.getVectorNumElements();
3159 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3161 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
3162 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
3164 // Adjust mask based on new input vector length.
3165 SmallVector<int, 16> NewMask;
3166 for (unsigned i = 0; i != NumElts; ++i) {
3167 int Idx = N->getMaskElt(i);
3168 if (Idx < (int)NumElts)
3169 NewMask.push_back(Idx);
3171 NewMask.push_back(Idx - NumElts + WidenNumElts);
3173 for (unsigned i = NumElts; i != WidenNumElts; ++i)
3174 NewMask.push_back(-1);
3175 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, NewMask);
3178 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
3179 assert(N->getValueType(0).isVector() &&
3180 N->getOperand(0).getValueType().isVector() &&
3181 "Operands must be vectors");
3182 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3183 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3185 SDValue InOp1 = N->getOperand(0);
3186 EVT InVT = InOp1.getValueType();
3187 assert(InVT.isVector() && "can not widen non-vector type");
3188 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
3189 InVT.getVectorElementType(), WidenNumElts);
3191 // The input and output types often differ here, and it could be that while
3192 // we'd prefer to widen the result type, the input operands have been split.
3193 // In this case, we also need to split the result of this node as well.
3194 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
3195 SDValue SplitVSetCC = SplitVecOp_VSETCC(N);
3196 SDValue Res = ModifyToType(SplitVSetCC, WidenVT);
3200 InOp1 = GetWidenedVector(InOp1);
3201 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
3203 // Assume that the input and output will be widen appropriately. If not,
3204 // we will have to unroll it at some point.
3205 assert(InOp1.getValueType() == WidenInVT &&
3206 InOp2.getValueType() == WidenInVT &&
3207 "Input not widened to expected type!");
3209 return DAG.getNode(ISD::SETCC, SDLoc(N),
3210 WidenVT, InOp1, InOp2, N->getOperand(2));
3214 //===----------------------------------------------------------------------===//
3215 // Widen Vector Operand
3216 //===----------------------------------------------------------------------===//
3217 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
3218 DEBUG(dbgs() << "Widen node operand " << OpNo << ": ";
3221 SDValue Res = SDValue();
3223 // See if the target wants to custom widen this node.
3224 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
3227 switch (N->getOpcode()) {
3230 dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
3234 llvm_unreachable("Do not know how to widen this operator's operand!");
3236 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
3237 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
3238 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
3239 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
3240 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
3241 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break;
3242 case ISD::MSCATTER: Res = WidenVecOp_MSCATTER(N, OpNo); break;
3243 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
3244 case ISD::FCOPYSIGN: Res = WidenVecOp_FCOPYSIGN(N); break;
3246 case ISD::ANY_EXTEND:
3247 case ISD::SIGN_EXTEND:
3248 case ISD::ZERO_EXTEND:
3249 Res = WidenVecOp_EXTEND(N);
3252 case ISD::FP_EXTEND:
3253 case ISD::FP_TO_SINT:
3254 case ISD::FP_TO_UINT:
3255 case ISD::SINT_TO_FP:
3256 case ISD::UINT_TO_FP:
3258 Res = WidenVecOp_Convert(N);
3262 // If Res is null, the sub-method took care of registering the result.
3263 if (!Res.getNode()) return false;
3265 // If the result is N, the sub-method updated N in place. Tell the legalizer
3267 if (Res.getNode() == N)
3271 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
3272 "Invalid operand expansion");
3274 ReplaceValueWith(SDValue(N, 0), Res);
3278 SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
3280 EVT VT = N->getValueType(0);
3282 SDValue InOp = N->getOperand(0);
3283 // If some legalization strategy other than widening is used on the operand,
3284 // we can't safely assume that just extending the low lanes is the correct
3286 if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
3287 return WidenVecOp_Convert(N);
3288 InOp = GetWidenedVector(InOp);
3289 assert(VT.getVectorNumElements() <
3290 InOp.getValueType().getVectorNumElements() &&
3291 "Input wasn't widened!");
3293 // We may need to further widen the operand until it has the same total
3294 // vector size as the result.
3295 EVT InVT = InOp.getValueType();
3296 if (InVT.getSizeInBits() != VT.getSizeInBits()) {
3297 EVT InEltVT = InVT.getVectorElementType();
3298 for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {
3299 EVT FixedVT = (MVT::SimpleValueType)i;
3300 EVT FixedEltVT = FixedVT.getVectorElementType();
3301 if (TLI.isTypeLegal(FixedVT) &&
3302 FixedVT.getSizeInBits() == VT.getSizeInBits() &&
3303 FixedEltVT == InEltVT) {
3304 assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&
3305 "Not enough elements in the fixed type for the operand!");
3306 assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&
3307 "We can't have the same type as we started with!");
3308 if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
3310 ISD::INSERT_SUBVECTOR, DL, FixedVT, DAG.getUNDEF(FixedVT), InOp,
3311 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3314 ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
3315 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3319 InVT = InOp.getValueType();
3320 if (InVT.getSizeInBits() != VT.getSizeInBits())
3321 // We couldn't find a legal vector type that was a widening of the input
3322 // and could be extended in-register to the result type, so we have to
3324 return WidenVecOp_Convert(N);
3327 // Use special DAG nodes to represent the operation of extending the
3329 switch (N->getOpcode()) {
3331 llvm_unreachable("Extend legalization on on extend operation!");
3332 case ISD::ANY_EXTEND:
3333 return DAG.getAnyExtendVectorInReg(InOp, DL, VT);
3334 case ISD::SIGN_EXTEND:
3335 return DAG.getSignExtendVectorInReg(InOp, DL, VT);
3336 case ISD::ZERO_EXTEND:
3337 return DAG.getZeroExtendVectorInReg(InOp, DL, VT);
3341 SDValue DAGTypeLegalizer::WidenVecOp_FCOPYSIGN(SDNode *N) {
3342 // The result (and first input) is legal, but the second input is illegal.
3343 // We can't do much to fix that, so just unroll and let the extracts off of
3344 // the second input be widened as needed later.
3345 return DAG.UnrollVectorOp(N);
3348 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
3349 // Since the result is legal and the input is illegal, it is unlikely that we
3350 // can fix the input to a legal type so unroll the convert into some scalar
3351 // code and create a nasty build vector.
3352 EVT VT = N->getValueType(0);
3353 EVT EltVT = VT.getVectorElementType();
3355 unsigned NumElts = VT.getVectorNumElements();
3356 SDValue InOp = N->getOperand(0);
3357 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
3358 InOp = GetWidenedVector(InOp);
3359 EVT InVT = InOp.getValueType();
3360 EVT InEltVT = InVT.getVectorElementType();
3362 unsigned Opcode = N->getOpcode();
3363 SmallVector<SDValue, 16> Ops(NumElts);
3364 for (unsigned i=0; i < NumElts; ++i)
3365 Ops[i] = DAG.getNode(
3368 ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
3369 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
3371 return DAG.getBuildVector(VT, dl, Ops);
3374 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
3375 EVT VT = N->getValueType(0);
3376 SDValue InOp = GetWidenedVector(N->getOperand(0));
3377 EVT InWidenVT = InOp.getValueType();
3380 // Check if we can convert between two legal vector types and extract.
3381 unsigned InWidenSize = InWidenVT.getSizeInBits();
3382 unsigned Size = VT.getSizeInBits();
3383 // x86mmx is not an acceptable vector element type, so don't try.
3384 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
3385 unsigned NewNumElts = InWidenSize / Size;
3386 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
3387 if (TLI.isTypeLegal(NewVT)) {
3388 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
3390 ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
3391 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3395 return CreateStackStoreLoad(InOp, VT);
3398 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
3399 // If the input vector is not legal, it is likely that we will not find a
3400 // legal vector of the same size. Replace the concatenate vector with a
3401 // nasty build vector.
3402 EVT VT = N->getValueType(0);
3403 EVT EltVT = VT.getVectorElementType();
3405 unsigned NumElts = VT.getVectorNumElements();
3406 SmallVector<SDValue, 16> Ops(NumElts);
3408 EVT InVT = N->getOperand(0).getValueType();
3409 unsigned NumInElts = InVT.getVectorNumElements();
3412 unsigned NumOperands = N->getNumOperands();
3413 for (unsigned i=0; i < NumOperands; ++i) {
3414 SDValue InOp = N->getOperand(i);
3415 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
3416 InOp = GetWidenedVector(InOp);
3417 for (unsigned j=0; j < NumInElts; ++j)
3418 Ops[Idx++] = DAG.getNode(
3419 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3420 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3422 return DAG.getBuildVector(VT, dl, Ops);
3425 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
3426 SDValue InOp = GetWidenedVector(N->getOperand(0));
3427 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
3428 N->getValueType(0), InOp, N->getOperand(1));
3431 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3432 SDValue InOp = GetWidenedVector(N->getOperand(0));
3433 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
3434 N->getValueType(0), InOp, N->getOperand(1));
3437 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
3438 // We have to widen the value, but we want only to store the original
3440 StoreSDNode *ST = cast<StoreSDNode>(N);
3442 SmallVector<SDValue, 16> StChain;
3443 if (ST->isTruncatingStore())
3444 GenWidenVectorTruncStores(StChain, ST);
3446 GenWidenVectorStores(StChain, ST);
3448 if (StChain.size() == 1)
3451 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
3454 SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
3455 MaskedStoreSDNode *MST = cast<MaskedStoreSDNode>(N);
3456 SDValue Mask = MST->getMask();
3457 EVT MaskVT = Mask.getValueType();
3458 SDValue StVal = MST->getValue();
3460 SDValue WideVal = GetWidenedVector(StVal);
3463 if (OpNo == 2 || getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
3464 Mask = GetWidenedVector(Mask);
3466 // The mask should be widened as well.
3467 EVT BoolVT = getSetCCResultType(WideVal.getValueType());
3468 // We can't use ModifyToType() because we should fill the mask with
3470 unsigned WidenNumElts = BoolVT.getVectorNumElements();
3471 unsigned MaskNumElts = MaskVT.getVectorNumElements();
3473 unsigned NumConcat = WidenNumElts / MaskNumElts;
3474 SmallVector<SDValue, 16> Ops(NumConcat);
3475 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
3477 for (unsigned i = 1; i != NumConcat; ++i)
3480 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
3482 assert(Mask.getValueType().getVectorNumElements() ==
3483 WideVal.getValueType().getVectorNumElements() &&
3484 "Mask and data vectors should have the same number of elements");
3485 return DAG.getMaskedStore(MST->getChain(), dl, WideVal, MST->getBasePtr(),
3486 Mask, MST->getMemoryVT(), MST->getMemOperand(),
3487 false, MST->isCompressingStore());
3490 SDValue DAGTypeLegalizer::WidenVecOp_MSCATTER(SDNode *N, unsigned OpNo) {
3491 assert(OpNo == 1 && "Can widen only data operand of mscatter");
3492 MaskedScatterSDNode *MSC = cast<MaskedScatterSDNode>(N);
3493 SDValue DataOp = MSC->getValue();
3494 SDValue Mask = MSC->getMask();
3497 SDValue WideVal = GetWidenedVector(DataOp);
3498 EVT WideVT = WideVal.getValueType();
3499 unsigned NumElts = WideVal.getValueType().getVectorNumElements();
3502 // The mask should be widened as well.
3503 Mask = WidenTargetBoolean(Mask, WideVT, true);
3506 SDValue Index = MSC->getIndex();
3507 EVT WideIndexVT = EVT::getVectorVT(*DAG.getContext(),
3508 Index.getValueType().getScalarType(),
3510 Index = ModifyToType(Index, WideIndexVT);
3512 SDValue Ops[] = {MSC->getChain(), WideVal, Mask, MSC->getBasePtr(), Index};
3513 return DAG.getMaskedScatter(DAG.getVTList(MVT::Other),
3514 MSC->getMemoryVT(), dl, Ops,
3515 MSC->getMemOperand());
3518 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
3519 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
3520 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
3523 // WARNING: In this code we widen the compare instruction with garbage.
3524 // This garbage may contain denormal floats which may be slow. Is this a real
3525 // concern ? Should we zero the unused lanes if this is a float compare ?
3527 // Get a new SETCC node to compare the newly widened operands.
3528 // Only some of the compared elements are legal.
3529 EVT SVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
3530 InOp0.getValueType());
3531 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
3532 SVT, InOp0, InOp1, N->getOperand(2));
3534 // Extract the needed results from the result vector.
3535 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
3536 SVT.getVectorElementType(),
3537 N->getValueType(0).getVectorNumElements());
3538 SDValue CC = DAG.getNode(
3539 ISD::EXTRACT_SUBVECTOR, dl, ResVT, WideSETCC,
3540 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3542 return PromoteTargetBoolean(CC, N->getValueType(0));
3546 //===----------------------------------------------------------------------===//
3547 // Vector Widening Utilities
3548 //===----------------------------------------------------------------------===//
3550 // Utility function to find the type to chop up a widen vector for load/store
3551 // TLI: Target lowering used to determine legal types.
3552 // Width: Width left need to load/store.
3553 // WidenVT: The widen vector type to load to/store from
3554 // Align: If 0, don't allow use of a wider type
3555 // WidenEx: If Align is not 0, the amount additional we can load/store from.
3557 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
3558 unsigned Width, EVT WidenVT,
3559 unsigned Align = 0, unsigned WidenEx = 0) {
3560 EVT WidenEltVT = WidenVT.getVectorElementType();
3561 unsigned WidenWidth = WidenVT.getSizeInBits();
3562 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
3563 unsigned AlignInBits = Align*8;
3565 // If we have one element to load/store, return it.
3566 EVT RetVT = WidenEltVT;
3567 if (Width == WidenEltWidth)
3570 // See if there is larger legal integer than the element type to load/store.
3572 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
3573 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
3574 EVT MemVT((MVT::SimpleValueType) VT);
3575 unsigned MemVTWidth = MemVT.getSizeInBits();
3576 if (MemVT.getSizeInBits() <= WidenEltWidth)
3578 auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT);
3579 if ((Action == TargetLowering::TypeLegal ||
3580 Action == TargetLowering::TypePromoteInteger) &&
3581 (WidenWidth % MemVTWidth) == 0 &&
3582 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3583 (MemVTWidth <= Width ||
3584 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3590 // See if there is a larger vector type to load/store that has the same vector
3591 // element type and is evenly divisible with the WidenVT.
3592 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
3593 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
3594 EVT MemVT = (MVT::SimpleValueType) VT;
3595 unsigned MemVTWidth = MemVT.getSizeInBits();
3596 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
3597 (WidenWidth % MemVTWidth) == 0 &&
3598 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3599 (MemVTWidth <= Width ||
3600 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3601 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
3609 // Builds a vector type from scalar loads
3610 // VecTy: Resulting Vector type
3611 // LDOps: Load operators to build a vector type
3612 // [Start,End) the list of loads to use.
3613 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
3614 SmallVectorImpl<SDValue> &LdOps,
3615 unsigned Start, unsigned End) {
3616 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3617 SDLoc dl(LdOps[Start]);
3618 EVT LdTy = LdOps[Start].getValueType();
3619 unsigned Width = VecTy.getSizeInBits();
3620 unsigned NumElts = Width / LdTy.getSizeInBits();
3621 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
3624 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
3626 for (unsigned i = Start + 1; i != End; ++i) {
3627 EVT NewLdTy = LdOps[i].getValueType();
3628 if (NewLdTy != LdTy) {
3629 NumElts = Width / NewLdTy.getSizeInBits();
3630 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
3631 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
3632 // Readjust position and vector position based on new load type.
3633 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
3636 VecOp = DAG.getNode(
3637 ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
3638 DAG.getConstant(Idx++, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3640 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
3643 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
3645 // The strategy assumes that we can efficiently load power-of-two widths.
3646 // The routine chops the vector into the largest vector loads with the same
3647 // element type or scalar loads and then recombines it to the widen vector
3649 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3650 unsigned WidenWidth = WidenVT.getSizeInBits();
3651 EVT LdVT = LD->getMemoryVT();
3653 assert(LdVT.isVector() && WidenVT.isVector());
3654 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
3657 SDValue Chain = LD->getChain();
3658 SDValue BasePtr = LD->getBasePtr();
3659 unsigned Align = LD->getAlignment();
3660 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
3661 AAMDNodes AAInfo = LD->getAAInfo();
3663 int LdWidth = LdVT.getSizeInBits();
3664 int WidthDiff = WidenWidth - LdWidth;
3665 unsigned LdAlign = LD->isVolatile() ? 0 : Align; // Allow wider loads.
3667 // Find the vector type that can load from.
3668 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3669 int NewVTWidth = NewVT.getSizeInBits();
3670 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
3671 Align, MMOFlags, AAInfo);
3672 LdChain.push_back(LdOp.getValue(1));
3674 // Check if we can load the element with one instruction.
3675 if (LdWidth <= NewVTWidth) {
3676 if (!NewVT.isVector()) {
3677 unsigned NumElts = WidenWidth / NewVTWidth;
3678 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3679 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
3680 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
3682 if (NewVT == WidenVT)
3685 assert(WidenWidth % NewVTWidth == 0);
3686 unsigned NumConcat = WidenWidth / NewVTWidth;
3687 SmallVector<SDValue, 16> ConcatOps(NumConcat);
3688 SDValue UndefVal = DAG.getUNDEF(NewVT);
3689 ConcatOps[0] = LdOp;
3690 for (unsigned i = 1; i != NumConcat; ++i)
3691 ConcatOps[i] = UndefVal;
3692 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
3695 // Load vector by using multiple loads from largest vector to scalar.
3696 SmallVector<SDValue, 16> LdOps;
3697 LdOps.push_back(LdOp);
3699 LdWidth -= NewVTWidth;
3700 unsigned Offset = 0;
3702 while (LdWidth > 0) {
3703 unsigned Increment = NewVTWidth / 8;
3704 Offset += Increment;
3705 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3706 DAG.getConstant(Increment, dl, BasePtr.getValueType()));
3709 if (LdWidth < NewVTWidth) {
3710 // The current type we are using is too large. Find a better size.
3711 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3712 NewVTWidth = NewVT.getSizeInBits();
3713 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3714 LD->getPointerInfo().getWithOffset(Offset),
3715 MinAlign(Align, Increment), MMOFlags, AAInfo);
3716 LdChain.push_back(L.getValue(1));
3717 if (L->getValueType(0).isVector() && NewVTWidth >= LdWidth) {
3718 // Later code assumes the vector loads produced will be mergeable, so we
3719 // must pad the final entry up to the previous width. Scalars are
3720 // combined separately.
3721 SmallVector<SDValue, 16> Loads;
3723 unsigned size = L->getValueSizeInBits(0);
3724 while (size < LdOp->getValueSizeInBits(0)) {
3725 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
3726 size += L->getValueSizeInBits(0);
3728 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
3731 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3732 LD->getPointerInfo().getWithOffset(Offset),
3733 MinAlign(Align, Increment), MMOFlags, AAInfo);
3734 LdChain.push_back(L.getValue(1));
3740 LdWidth -= NewVTWidth;
3743 // Build the vector from the load operations.
3744 unsigned End = LdOps.size();
3745 if (!LdOps[0].getValueType().isVector())
3746 // All the loads are scalar loads.
3747 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
3749 // If the load contains vectors, build the vector using concat vector.
3750 // All of the vectors used to load are power-of-2, and the scalar loads can be
3751 // combined to make a power-of-2 vector.
3752 SmallVector<SDValue, 16> ConcatOps(End);
3755 EVT LdTy = LdOps[i].getValueType();
3756 // First, combine the scalar loads to a vector.
3757 if (!LdTy.isVector()) {
3758 for (--i; i >= 0; --i) {
3759 LdTy = LdOps[i].getValueType();
3760 if (LdTy.isVector())
3763 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i + 1, End);
3765 ConcatOps[--Idx] = LdOps[i];
3766 for (--i; i >= 0; --i) {
3767 EVT NewLdTy = LdOps[i].getValueType();
3768 if (NewLdTy != LdTy) {
3769 // Create a larger vector.
3770 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
3771 makeArrayRef(&ConcatOps[Idx], End - Idx));
3775 ConcatOps[--Idx] = LdOps[i];
3778 if (WidenWidth == LdTy.getSizeInBits() * (End - Idx))
3779 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
3780 makeArrayRef(&ConcatOps[Idx], End - Idx));
3782 // We need to fill the rest with undefs to build the vector.
3783 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
3784 SmallVector<SDValue, 16> WidenOps(NumOps);
3785 SDValue UndefVal = DAG.getUNDEF(LdTy);
3788 for (; i != End-Idx; ++i)
3789 WidenOps[i] = ConcatOps[Idx+i];
3790 for (; i != NumOps; ++i)
3791 WidenOps[i] = UndefVal;
3793 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
3797 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
3799 ISD::LoadExtType ExtType) {
3800 // For extension loads, it may not be more efficient to chop up the vector
3801 // and then extend it. Instead, we unroll the load and build a new vector.
3802 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3803 EVT LdVT = LD->getMemoryVT();
3805 assert(LdVT.isVector() && WidenVT.isVector());
3808 SDValue Chain = LD->getChain();
3809 SDValue BasePtr = LD->getBasePtr();
3810 unsigned Align = LD->getAlignment();
3811 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
3812 AAMDNodes AAInfo = LD->getAAInfo();
3814 EVT EltVT = WidenVT.getVectorElementType();
3815 EVT LdEltVT = LdVT.getVectorElementType();
3816 unsigned NumElts = LdVT.getVectorNumElements();
3818 // Load each element and widen.
3819 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3820 SmallVector<SDValue, 16> Ops(WidenNumElts);
3821 unsigned Increment = LdEltVT.getSizeInBits() / 8;
3823 DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, LD->getPointerInfo(),
3824 LdEltVT, Align, MMOFlags, AAInfo);
3825 LdChain.push_back(Ops[0].getValue(1));
3826 unsigned i = 0, Offset = Increment;
3827 for (i=1; i < NumElts; ++i, Offset += Increment) {
3828 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3830 DAG.getConstant(Offset, dl,
3831 BasePtr.getValueType()));
3832 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
3833 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
3834 Align, MMOFlags, AAInfo);
3835 LdChain.push_back(Ops[i].getValue(1));
3838 // Fill the rest with undefs.
3839 SDValue UndefVal = DAG.getUNDEF(EltVT);
3840 for (; i != WidenNumElts; ++i)
3843 return DAG.getBuildVector(WidenVT, dl, Ops);
3846 void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
3848 // The strategy assumes that we can efficiently store power-of-two widths.
3849 // The routine chops the vector into the largest vector stores with the same
3850 // element type or scalar stores.
3851 SDValue Chain = ST->getChain();
3852 SDValue BasePtr = ST->getBasePtr();
3853 unsigned Align = ST->getAlignment();
3854 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
3855 AAMDNodes AAInfo = ST->getAAInfo();
3856 SDValue ValOp = GetWidenedVector(ST->getValue());
3859 EVT StVT = ST->getMemoryVT();
3860 unsigned StWidth = StVT.getSizeInBits();
3861 EVT ValVT = ValOp.getValueType();
3862 unsigned ValWidth = ValVT.getSizeInBits();
3863 EVT ValEltVT = ValVT.getVectorElementType();
3864 unsigned ValEltWidth = ValEltVT.getSizeInBits();
3865 assert(StVT.getVectorElementType() == ValEltVT);
3867 int Idx = 0; // current index to store
3868 unsigned Offset = 0; // offset from base to store
3869 while (StWidth != 0) {
3870 // Find the largest vector type we can store with.
3871 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
3872 unsigned NewVTWidth = NewVT.getSizeInBits();
3873 unsigned Increment = NewVTWidth / 8;
3874 if (NewVT.isVector()) {
3875 unsigned NumVTElts = NewVT.getVectorNumElements();
3877 SDValue EOp = DAG.getNode(
3878 ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
3879 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3880 StChain.push_back(DAG.getStore(
3881 Chain, dl, EOp, BasePtr, ST->getPointerInfo().getWithOffset(Offset),
3882 MinAlign(Align, Offset), MMOFlags, AAInfo));
3883 StWidth -= NewVTWidth;
3884 Offset += Increment;
3886 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3887 DAG.getConstant(Increment, dl,
3888 BasePtr.getValueType()));
3889 } while (StWidth != 0 && StWidth >= NewVTWidth);
3891 // Cast the vector to the scalar type we can store.
3892 unsigned NumElts = ValWidth / NewVTWidth;
3893 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3894 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
3895 // Readjust index position based on new vector type.
3896 Idx = Idx * ValEltWidth / NewVTWidth;
3898 SDValue EOp = DAG.getNode(
3899 ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
3900 DAG.getConstant(Idx++, dl,
3901 TLI.getVectorIdxTy(DAG.getDataLayout())));
3902 StChain.push_back(DAG.getStore(
3903 Chain, dl, EOp, BasePtr, ST->getPointerInfo().getWithOffset(Offset),
3904 MinAlign(Align, Offset), MMOFlags, AAInfo));
3905 StWidth -= NewVTWidth;
3906 Offset += Increment;
3907 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3908 DAG.getConstant(Increment, dl,
3909 BasePtr.getValueType()));
3910 } while (StWidth != 0 && StWidth >= NewVTWidth);
3911 // Restore index back to be relative to the original widen element type.
3912 Idx = Idx * NewVTWidth / ValEltWidth;
3918 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
3920 // For extension loads, it may not be more efficient to truncate the vector
3921 // and then store it. Instead, we extract each element and then store it.
3922 SDValue Chain = ST->getChain();
3923 SDValue BasePtr = ST->getBasePtr();
3924 unsigned Align = ST->getAlignment();
3925 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
3926 AAMDNodes AAInfo = ST->getAAInfo();
3927 SDValue ValOp = GetWidenedVector(ST->getValue());
3930 EVT StVT = ST->getMemoryVT();
3931 EVT ValVT = ValOp.getValueType();
3933 // It must be true that the wide vector type is bigger than where we need to
3935 assert(StVT.isVector() && ValOp.getValueType().isVector());
3936 assert(StVT.bitsLT(ValOp.getValueType()));
3938 // For truncating stores, we can not play the tricks of chopping legal vector
3939 // types and bitcast it to the right type. Instead, we unroll the store.
3940 EVT StEltVT = StVT.getVectorElementType();
3941 EVT ValEltVT = ValVT.getVectorElementType();
3942 unsigned Increment = ValEltVT.getSizeInBits() / 8;
3943 unsigned NumElts = StVT.getVectorNumElements();
3944 SDValue EOp = DAG.getNode(
3945 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3946 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3947 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
3948 ST->getPointerInfo(), StEltVT, Align,
3950 unsigned Offset = Increment;
3951 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
3952 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3954 DAG.getConstant(Offset, dl,
3955 BasePtr.getValueType()));
3956 SDValue EOp = DAG.getNode(
3957 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3958 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3959 StChain.push_back(DAG.getTruncStore(
3960 Chain, dl, EOp, NewBasePtr, ST->getPointerInfo().getWithOffset(Offset),
3961 StEltVT, MinAlign(Align, Offset), MMOFlags, AAInfo));
3965 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
3966 /// input vector must have the same element type as NVT.
3967 /// FillWithZeroes specifies that the vector should be widened with zeroes.
3968 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT,
3969 bool FillWithZeroes) {
3970 // Note that InOp might have been widened so it might already have
3971 // the right width or it might need be narrowed.
3972 EVT InVT = InOp.getValueType();
3973 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
3974 "input and widen element type must match");
3977 // Check if InOp already has the right width.
3981 unsigned InNumElts = InVT.getVectorNumElements();
3982 unsigned WidenNumElts = NVT.getVectorNumElements();
3983 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
3984 unsigned NumConcat = WidenNumElts / InNumElts;
3985 SmallVector<SDValue, 16> Ops(NumConcat);
3986 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, InVT) :
3989 for (unsigned i = 1; i != NumConcat; ++i)
3992 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
3995 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
3997 ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
3998 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4000 // Fall back to extract and build.
4001 SmallVector<SDValue, 16> Ops(WidenNumElts);
4002 EVT EltVT = NVT.getVectorElementType();
4003 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
4005 for (Idx = 0; Idx < MinNumElts; ++Idx)
4006 Ops[Idx] = DAG.getNode(
4007 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
4008 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4010 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, EltVT) :
4011 DAG.getUNDEF(EltVT);
4012 for ( ; Idx < WidenNumElts; ++Idx)
4014 return DAG.getBuildVector(NVT, dl, Ops);